| Project Settings |
|---|
| Project Name | AHB_Bus_Matrix_syn | Implementation Name | synthesis |
| Top Module | work.AHB_Bus_Matrix | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
40 |
93 |
0 |
- |
0m:01s |
- |
17-02-2016
AM 10:28:23 |
| (premap) | Complete |
78 |
3 |
0 |
0m:00s |
0m:00s |
137MB |
17-02-2016
AM 10:28:25 |
| (fpga_mapper) | Complete |
15 |
6 |
0 |
0m:02s |
0m:02s |
151MB |
17-02-2016
AM 10:28:27 |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 17-02-2016
AM 10:28:24 |
| Area Summary |
|---|
| |
| Carry Cells | 320 |
Sequential Cells | 365 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 2 |
| Global Clock Buffers | 5 |
LUTs
(total_luts) | 663 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 112.1 MHz | 1.080 |
| AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock | 100.0 MHz | 147.8 MHz | 3.234 |
| System | 100.0 MHz | 895.2 MHz | 8.883 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 0 |
| |
|