----------------------------------------------------------------------
-- Created by SmartDesign Wed Feb 17 10:28:07 2016
-- Version: v11.7 11.7.0.119
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
-- AHB_Bus_Matrix entity declaration
----------------------------------------------------------------------
entity AHB_Bus_Matrix is
    -- Port list
    port(
        -- Inputs
        DEVRST_N     : in  std_logic;
        MMUART_0_RXD : in  std_logic;
        -- Outputs
        MMUART_0_TXD : out std_logic
        );
end AHB_Bus_Matrix;
----------------------------------------------------------------------
-- AHB_Bus_Matrix architecture body
----------------------------------------------------------------------
architecture RTL of AHB_Bus_Matrix is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- AHB_Bus_Matrix_sb
component AHB_Bus_Matrix_sb
    -- Port list
    port(
        -- Inputs
        DEVRST_N              : in  std_logic;
        FAB_RESET_N           : in  std_logic;
        FIC_0_AHB_S_HADDR     : in  std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HMASTLOCK : in  std_logic;
        FIC_0_AHB_S_HREADY    : in  std_logic;
        FIC_0_AHB_S_HSEL      : in  std_logic;
        FIC_0_AHB_S_HSIZE     : in  std_logic_vector(1 downto 0);
        FIC_0_AHB_S_HTRANS    : in  std_logic_vector(1 downto 0);
        FIC_0_AHB_S_HWDATA    : in  std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HWRITE    : in  std_logic;
        FIC_1_AHB_S_HADDR     : in  std_logic_vector(31 downto 0);
        FIC_1_AHB_S_HMASTLOCK : in  std_logic;
        FIC_1_AHB_S_HREADY    : in  std_logic;
        FIC_1_AHB_S_HSEL      : in  std_logic;
        FIC_1_AHB_S_HSIZE     : in  std_logic_vector(1 downto 0);
        FIC_1_AHB_S_HTRANS    : in  std_logic_vector(1 downto 0);
        FIC_1_AHB_S_HWDATA    : in  std_logic_vector(31 downto 0);
        FIC_1_AHB_S_HWRITE    : in  std_logic;
        MMUART_0_RXD          : in  std_logic;
        MSS_INT_F2M           : in  std_logic;
        -- Outputs
        FIC_0_AHB_S_HRDATA    : out std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HREADYOUT : out std_logic;
        FIC_0_AHB_S_HRESP     : out std_logic;
        FIC_0_CLK             : out std_logic;
        FIC_0_LOCK            : out std_logic;
        FIC_1_AHB_S_HRDATA    : out std_logic_vector(31 downto 0);
        FIC_1_AHB_S_HREADYOUT : out std_logic;
        FIC_1_AHB_S_HRESP     : out std_logic;
        FIC_1_CLK             : out std_logic;
        FIC_1_LOCK            : out std_logic;
        GPIO_0_M2F            : out std_logic;
        GPIO_2_M2F            : out std_logic;
        INIT_DONE             : out std_logic;
        MMUART_0_TXD          : out std_logic;
        MSS_READY             : out std_logic;
        POWER_ON_RESET_N      : out std_logic
        );
end component;
-- AND2
component AND2
    -- Port list
    port(
        -- Inputs
        A : in  std_logic;
        B : in  std_logic;
        -- Outputs
        Y : out std_logic
        );
end component;
-- Fabric_Master1
-- using entity instantiation for component Fabric_Master1
-- Fabric_Master2
-- using entity instantiation for component Fabric_Master2
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal AHB_Bus_Matrix_sb_0_FIC_0_CLK    : std_logic;
signal AHB_Bus_Matrix_sb_0_FIC_1_CLK    : std_logic;
signal AHB_Bus_Matrix_sb_0_GPIO_0_M2F   : std_logic;
signal AHB_Bus_Matrix_sb_0_GPIO_2_M2F   : std_logic;
signal AHB_Bus_Matrix_sb_0_MSS_READY    : std_logic;
signal AND2_0_Y                         : std_logic;
signal Fabric_Master1_0_BIF_1_HADDR     : std_logic_vector(31 downto 0);
signal Fabric_Master1_0_BIF_1_HMASTLOCK : std_logic;
signal Fabric_Master1_0_BIF_1_HRDATA    : std_logic_vector(31 downto 0);
signal Fabric_Master1_0_BIF_1_HREADY    : std_logic;
signal Fabric_Master1_0_BIF_1_HREADYOUT : std_logic;
signal Fabric_Master1_0_BIF_1_HRESP     : std_logic;
signal Fabric_Master1_0_BIF_1_HSELx     : std_logic;
signal Fabric_Master1_0_BIF_1_HSIZE     : std_logic_vector(1 downto 0);
signal Fabric_Master1_0_BIF_1_HTRANS    : std_logic_vector(1 downto 0);
signal Fabric_Master1_0_BIF_1_HWDATA    : std_logic_vector(31 downto 0);
signal Fabric_Master1_0_BIF_1_HWRITE    : std_logic;
signal Fabric_Master1_0_INT1            : std_logic;
signal Fabric_Master2_0_BIF_1_HADDR     : std_logic_vector(31 downto 0);
signal Fabric_Master2_0_BIF_1_HMASTLOCK : std_logic;
signal Fabric_Master2_0_BIF_1_HRDATA    : std_logic_vector(31 downto 0);
signal Fabric_Master2_0_BIF_1_HREADY    : std_logic;
signal Fabric_Master2_0_BIF_1_HREADYOUT : std_logic;
signal Fabric_Master2_0_BIF_1_HRESP     : std_logic;
signal Fabric_Master2_0_BIF_1_HSELx     : std_logic;
signal Fabric_Master2_0_BIF_1_HSIZE     : std_logic_vector(1 downto 0);
signal Fabric_Master2_0_BIF_1_HTRANS    : std_logic_vector(1 downto 0);
signal Fabric_Master2_0_BIF_1_HWDATA    : std_logic_vector(31 downto 0);
signal Fabric_Master2_0_BIF_1_HWRITE    : std_logic;
signal Fabric_Master2_0_INT2            : std_logic;
signal MMUART_0_TXD_net_0               : std_logic;
signal MMUART_0_TXD_net_1               : std_logic;
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal VCC_net                          : std_logic;

begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
 VCC_net <= '1';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 MMUART_0_TXD_net_1 <= MMUART_0_TXD_net_0;
 MMUART_0_TXD       <= MMUART_0_TXD_net_1;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- AHB_Bus_Matrix_sb_0
AHB_Bus_Matrix_sb_0 : AHB_Bus_Matrix_sb
    port map( 
        -- Inputs
        MMUART_0_RXD          => MMUART_0_RXD,
        FAB_RESET_N           => VCC_net,
        DEVRST_N              => DEVRST_N,
        FIC_1_AHB_S_HWRITE    => Fabric_Master2_0_BIF_1_HWRITE,
        FIC_1_AHB_S_HSEL      => Fabric_Master2_0_BIF_1_HSELx,
        FIC_1_AHB_S_HMASTLOCK => Fabric_Master2_0_BIF_1_HMASTLOCK,
        FIC_1_AHB_S_HREADY    => Fabric_Master2_0_BIF_1_HREADY,
        FIC_0_AHB_S_HWRITE    => Fabric_Master1_0_BIF_1_HWRITE,
        FIC_0_AHB_S_HSEL      => Fabric_Master1_0_BIF_1_HSELx,
        FIC_0_AHB_S_HMASTLOCK => Fabric_Master1_0_BIF_1_HMASTLOCK,
        FIC_0_AHB_S_HREADY    => Fabric_Master1_0_BIF_1_HREADY,
        MSS_INT_F2M           => AND2_0_Y,
        FIC_1_AHB_S_HADDR     => Fabric_Master2_0_BIF_1_HADDR,
        FIC_1_AHB_S_HTRANS    => Fabric_Master2_0_BIF_1_HTRANS,
        FIC_1_AHB_S_HSIZE     => Fabric_Master2_0_BIF_1_HSIZE,
        FIC_1_AHB_S_HWDATA    => Fabric_Master2_0_BIF_1_HWDATA,
        FIC_0_AHB_S_HADDR     => Fabric_Master1_0_BIF_1_HADDR,
        FIC_0_AHB_S_HTRANS    => Fabric_Master1_0_BIF_1_HTRANS,
        FIC_0_AHB_S_HSIZE     => Fabric_Master1_0_BIF_1_HSIZE,
        FIC_0_AHB_S_HWDATA    => Fabric_Master1_0_BIF_1_HWDATA,
        -- Outputs
        MMUART_0_TXD          => MMUART_0_TXD_net_0,
        POWER_ON_RESET_N      => OPEN,
        INIT_DONE             => OPEN,
        FIC_0_CLK             => AHB_Bus_Matrix_sb_0_FIC_0_CLK,
        FIC_0_LOCK            => OPEN,
        FIC_1_CLK             => AHB_Bus_Matrix_sb_0_FIC_1_CLK,
        FIC_1_LOCK            => OPEN,
        MSS_READY             => AHB_Bus_Matrix_sb_0_MSS_READY,
        GPIO_0_M2F            => AHB_Bus_Matrix_sb_0_GPIO_0_M2F,
        GPIO_2_M2F            => AHB_Bus_Matrix_sb_0_GPIO_2_M2F,
        FIC_1_AHB_S_HREADYOUT => Fabric_Master2_0_BIF_1_HREADYOUT,
        FIC_1_AHB_S_HRESP     => Fabric_Master2_0_BIF_1_HRESP,
        FIC_0_AHB_S_HREADYOUT => Fabric_Master1_0_BIF_1_HREADYOUT,
        FIC_0_AHB_S_HRESP     => Fabric_Master1_0_BIF_1_HRESP,
        FIC_1_AHB_S_HRDATA    => Fabric_Master2_0_BIF_1_HRDATA,
        FIC_0_AHB_S_HRDATA    => Fabric_Master1_0_BIF_1_HRDATA 
        );
-- AND2_0
AND2_0 : AND2
    port map( 
        -- Inputs
        A => Fabric_Master1_0_INT1,
        B => Fabric_Master2_0_INT2,
        -- Outputs
        Y => AND2_0_Y 
        );
-- Fabric_Master1_0
Fabric_Master1_0 : entity work.Fabric_Master1
    port map( 
        -- Inputs
        RESET_N       => AHB_Bus_Matrix_sb_0_MSS_READY,
        HCLK          => AHB_Bus_Matrix_sb_0_FIC_0_CLK,
        HREADYOUT     => Fabric_Master1_0_BIF_1_HREADYOUT,
        HRESP         => Fabric_Master1_0_BIF_1_HRESP,
        MASTER1_START => AHB_Bus_Matrix_sb_0_GPIO_0_M2F,
        MASTER1_STOP  => AHB_Bus_Matrix_sb_0_GPIO_2_M2F,
        HRDATA        => Fabric_Master1_0_BIF_1_HRDATA,
        -- Outputs
        HWRITE        => Fabric_Master1_0_BIF_1_HWRITE,
        HMASTLOCK     => Fabric_Master1_0_BIF_1_HMASTLOCK,
        HREADY        => Fabric_Master1_0_BIF_1_HREADY,
        HSEL          => Fabric_Master1_0_BIF_1_HSELx,
        INT1          => Fabric_Master1_0_INT1,
        HTRANS        => Fabric_Master1_0_BIF_1_HTRANS,
        HSIZE         => Fabric_Master1_0_BIF_1_HSIZE,
        HWDATA        => Fabric_Master1_0_BIF_1_HWDATA,
        HADDR         => Fabric_Master1_0_BIF_1_HADDR 
        );
-- Fabric_Master2_0
Fabric_Master2_0 : entity work.Fabric_Master2
    port map( 
        -- Inputs
        RESET_N       => AHB_Bus_Matrix_sb_0_MSS_READY,
        HCLK          => AHB_Bus_Matrix_sb_0_FIC_1_CLK,
        HREADYOUT     => Fabric_Master2_0_BIF_1_HREADYOUT,
        HRESP         => Fabric_Master2_0_BIF_1_HRESP,
        MASTER2_START => AHB_Bus_Matrix_sb_0_GPIO_0_M2F,
        MASTER2_STOP  => AHB_Bus_Matrix_sb_0_GPIO_2_M2F,
        HRDATA        => Fabric_Master2_0_BIF_1_HRDATA,
        -- Outputs
        HWRITE        => Fabric_Master2_0_BIF_1_HWRITE,
        HMASTLOCK     => Fabric_Master2_0_BIF_1_HMASTLOCK,
        HREADY        => Fabric_Master2_0_BIF_1_HREADY,
        HSEL          => Fabric_Master2_0_BIF_1_HSELx,
        INT2          => Fabric_Master2_0_INT2,
        HTRANS        => Fabric_Master2_0_BIF_1_HTRANS,
        HSIZE         => Fabric_Master2_0_BIF_1_HSIZE,
        HWDATA        => Fabric_Master2_0_BIF_1_HWDATA,
        HADDR         => Fabric_Master2_0_BIF_1_HADDR 
        );

end RTL;
