#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\synthesis\run_options.txt
#--  Written on Wed Feb 17 10:28:22 2016


#project files
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix_sb/CCC_0/AHB_Bus_Matrix_sb_CCC_0_FCCC.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/Actel/SgCore/OSC/2.0.101/osc_comps.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix_sb/FABOSC_0/AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix_sb_MSS/AHB_Bus_Matrix_sb_MSS_syn.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix_sb_MSS/AHB_Bus_Matrix_sb_MSS.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vhdl/core/coreresetp_pcie_hotreset.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vhdl/core/coreresetp.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix_sb/AHB_Bus_Matrix_sb.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/hdl/Fabric_Master1.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/hdl/Fabric_Master2.vhd"
add_file -vhdl -lib work "D:/Libero11.7/AC388/M2S_AC388_DF/AHB_Bus_Matrix/component/work/AHB_Bus_Matrix/AHB_Bus_Matrix.vhd"



#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology SmartFusion2
set_option -part M2S150T
set_option -package FC1152
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.AHB_Bus_Matrix"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./AHB_Bus_Matrix.edn"
impl -active "synthesis"
