-- Version: v11.7 11.7.0.119

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity AHB_Bus_Matrix_sb_FABOSC_0_OSC is

    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );

end AHB_Bus_Matrix_sb_FABOSC_0_OSC;

architecture DEF_ARCH of AHB_Bus_Matrix_sb_FABOSC_0_OSC is 

  component RCOSC_25_50MHZ
    generic (FREQUENCY:real := 50.0);

    port( CLKOUT : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

begin 


    I_RCOSC_25_50MHZ : RCOSC_25_50MHZ
      generic map(FREQUENCY => 50.0)

      port map(CLKOUT => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity CoreResetP is

    port( AHB_Bus_Matrix_sb_0_MSS_READY                    : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK                    : in    std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N : in    std_logic;
          POWER_ON_RESET_N                                 : in    std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F      : in    std_logic
        );

end CoreResetP;

architecture DEF_ARCH of CoreResetP is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \MSS_HPMS_READY_int\, \mss_ready_select\, VCC_net_1, 
        \POWER_ON_RESET_N_clk_base\, 
        \un6_fic_2_apb_m_preset_n_clk_base\, GND_net_1, 
        \mss_ready_state\, \RESET_N_M2F_clk_base\, 
        \FIC_2_APB_M_PRESET_N_q1\, \POWER_ON_RESET_N_q1\, 
        \RESET_N_M2F_q1\, \FIC_2_APB_M_PRESET_N_clk_base\, 
        \MSS_HPMS_READY_int_3\ : std_logic;

begin 


    RESET_N_M2F_clk_base : SLE
      port map(D => \RESET_N_M2F_q1\, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \RESET_N_M2F_clk_base\);
    
    POWER_ON_RESET_N_clk_base : SLE
      port map(D => \POWER_ON_RESET_N_q1\, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        POWER_ON_RESET_N, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \POWER_ON_RESET_N_clk_base\);
    
    mss_ready_select : SLE
      port map(D => VCC_net_1, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => 
        \un6_fic_2_apb_m_preset_n_clk_base\, ALn => 
        \POWER_ON_RESET_N_clk_base\, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mss_ready_select\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    mss_ready_state : SLE
      port map(D => VCC_net_1, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => 
        \RESET_N_M2F_clk_base\, ALn => 
        \POWER_ON_RESET_N_clk_base\, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mss_ready_state\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    un6_fic_2_apb_m_preset_n_clk_base : CFG2
      generic map(INIT => x"8")

      port map(A => \FIC_2_APB_M_PRESET_N_clk_base\, B => 
        \mss_ready_state\, Y => 
        \un6_fic_2_apb_m_preset_n_clk_base\);
    
    RESET_N_M2F_q1 : SLE
      port map(D => VCC_net_1, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \RESET_N_M2F_q1\);
    
    MSS_HPMS_READY_int_RNIQ6H4 : CLKINT
      port map(A => \MSS_HPMS_READY_int\, Y => 
        AHB_Bus_Matrix_sb_0_MSS_READY);
    
    FIC_2_APB_M_PRESET_N_clk_base : SLE
      port map(D => \FIC_2_APB_M_PRESET_N_q1\, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \FIC_2_APB_M_PRESET_N_clk_base\);
    
    POWER_ON_RESET_N_q1 : SLE
      port map(D => VCC_net_1, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        POWER_ON_RESET_N, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \POWER_ON_RESET_N_q1\);
    
    FIC_2_APB_M_PRESET_N_q1 : SLE
      port map(D => VCC_net_1, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \FIC_2_APB_M_PRESET_N_q1\);
    
    MSS_HPMS_READY_int_3 : CFG3
      generic map(INIT => x"E0")

      port map(A => \RESET_N_M2F_clk_base\, B => 
        \mss_ready_select\, C => \FIC_2_APB_M_PRESET_N_clk_base\, 
        Y => \MSS_HPMS_READY_int_3\);
    
    MSS_HPMS_READY_int : SLE
      port map(D => \MSS_HPMS_READY_int_3\, CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, EN => VCC_net_1, ALn => 
        \POWER_ON_RESET_N_clk_base\, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \MSS_HPMS_READY_int\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity AHB_Bus_Matrix_sb_MSS is

    port( Fabric_Master1_0_BIF_1_HADDR                     : in    std_logic_vector(31 downto 0);
          Fabric_Master1_0_BIF_1_HSIZE                     : in    std_logic_vector(1 downto 0);
          Fabric_Master1_0_BIF_1_HTRANS                    : in    std_logic_vector(1 to 1);
          Fabric_Master1_0_BIF_1_HWDATA                    : in    std_logic_vector(31 downto 0);
          Fabric_Master2_0_BIF_1_HADDR                     : in    std_logic_vector(31 downto 0);
          Fabric_Master2_0_BIF_1_HSIZE                     : in    std_logic_vector(1 downto 0);
          Fabric_Master2_0_BIF_1_HTRANS                    : in    std_logic_vector(1 to 1);
          Fabric_Master2_0_BIF_1_HWDATA                    : in    std_logic_vector(31 downto 0);
          MMUART_0_TXD                                     : out   std_logic;
          MMUART_0_RXD                                     : in    std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_2_M2F                   : out   std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N : out   std_logic;
          Fabric_Master1_0_BIF_1_HREADYOUT                 : out   std_logic;
          Fabric_Master2_0_BIF_1_HREADYOUT                 : out   std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F      : out   std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_0_M2F                   : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK                    : in    std_logic;
          AND2_0_Y                                         : in    std_logic;
          Fabric_Master1_0_BIF_1_HSELx                     : in    std_logic;
          Fabric_Master1_0_BIF_1_HWRITE                    : in    std_logic;
          Fabric_Master2_0_BIF_1_HSELx                     : in    std_logic;
          Fabric_Master2_0_BIF_1_HWRITE                    : in    std_logic;
          FIC_1_LOCK                                       : in    std_logic
        );

end AHB_Bus_Matrix_sb_MSS;

architecture DEF_ARCH of AHB_Bus_Matrix_sb_MSS is 

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MSS_120

            generic (INIT:std_logic_vector(1437 downto 0) := "00" & x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; 
        ACT_UBITS:std_logic_vector(55 downto 0) := x"FFFFFFFFFFFFFF"; 
        MEMORYFILE:string := ""; RTC_MAIN_XTL_FREQ:real := 0.0; 
        RTC_MAIN_XTL_MODE:string := "1"; DDR_CLK_FREQ:real := 0.0
        );

    port( CAN_RXBUS_MGPIO3A_H2F_A                 : out   std_logic;
          CAN_RXBUS_MGPIO3A_H2F_B                 : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_A                : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_B                : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_A                 : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_B                 : out   std_logic;
          CLK_CONFIG_APB                          : out   std_logic;
          COMMS_INT                               : out   std_logic;
          CONFIG_PRESET_N                         : out   std_logic;
          EDAC_ERROR                              : out   std_logic_vector(7 downto 0);
          F_FM0_RDATA                             : out   std_logic_vector(31 downto 0);
          F_FM0_READYOUT                          : out   std_logic;
          F_FM0_RESP                              : out   std_logic;
          F_FM1_RDATA                             : out   std_logic_vector(31 downto 0);
          F_FM1_READYOUT                          : out   std_logic;
          F_FM1_RESP                              : out   std_logic;
          F_HM0_ADDR                              : out   std_logic_vector(31 downto 0);
          F_HM0_ENABLE                            : out   std_logic;
          F_HM0_SEL                               : out   std_logic;
          F_HM0_SIZE                              : out   std_logic_vector(1 downto 0);
          F_HM0_TRANS1                            : out   std_logic;
          F_HM0_WDATA                             : out   std_logic_vector(31 downto 0);
          F_HM0_WRITE                             : out   std_logic;
          F_HM1_ADDR                              : out   std_logic_vector(31 downto 0);
          F_HM1_ENABLE                            : out   std_logic;
          F_HM1_SEL                               : out   std_logic;
          F_HM1_SIZE                              : out   std_logic_vector(1 downto 0);
          F_HM1_TRANS1                            : out   std_logic;
          F_HM1_WDATA                             : out   std_logic_vector(31 downto 0);
          F_HM1_WRITE                             : out   std_logic;
          FAB_CHRGVBUS                            : out   std_logic;
          FAB_DISCHRGVBUS                         : out   std_logic;
          FAB_DMPULLDOWN                          : out   std_logic;
          FAB_DPPULLDOWN                          : out   std_logic;
          FAB_DRVVBUS                             : out   std_logic;
          FAB_IDPULLUP                            : out   std_logic;
          FAB_OPMODE                              : out   std_logic_vector(1 downto 0);
          FAB_SUSPENDM                            : out   std_logic;
          FAB_TERMSEL                             : out   std_logic;
          FAB_TXVALID                             : out   std_logic;
          FAB_VCONTROL                            : out   std_logic_vector(3 downto 0);
          FAB_VCONTROLLOADM                       : out   std_logic;
          FAB_XCVRSEL                             : out   std_logic_vector(1 downto 0);
          FAB_XDATAOUT                            : out   std_logic_vector(7 downto 0);
          FACC_GLMUX_SEL                          : out   std_logic;
          FIC32_0_MASTER                          : out   std_logic_vector(1 downto 0);
          FIC32_1_MASTER                          : out   std_logic_vector(1 downto 0);
          FPGA_RESET_N                            : out   std_logic;
          GTX_CLK                                 : out   std_logic;
          H2F_INTERRUPT                           : out   std_logic_vector(15 downto 0);
          H2F_NMI                                 : out   std_logic;
          H2FCALIB                                : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_A                 : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_B                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_A                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_B                 : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_A                  : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_B                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_A                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_B                  : out   std_logic;
          MDCF                                    : out   std_logic;
          MDOENF                                  : out   std_logic;
          MDOF                                    : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_A              : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_B              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_A              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_B              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_A              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_B              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_A              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_B              : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_A               : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_B               : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_A              : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_B              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_A              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_B              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_A              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_B              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_A              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_B              : out   std_logic;
          MMUART1_DTR_MGPIO12B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_B              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_A              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_B              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_A              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_B              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_A              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_B              : out   std_logic;
          MPLL_LOCK                               : out   std_logic;
          PER2_FABRIC_PADDR                       : out   std_logic_vector(16 downto 2);
          PER2_FABRIC_PENABLE                     : out   std_logic;
          PER2_FABRIC_PSEL                        : out   std_logic;
          PER2_FABRIC_PWDATA                      : out   std_logic_vector(31 downto 0);
          PER2_FABRIC_PWRITE                      : out   std_logic;
          RTC_MATCH                               : out   std_logic;
          SLEEPDEEP                               : out   std_logic;
          SLEEPHOLDACK                            : out   std_logic;
          SLEEPING                                : out   std_logic;
          SMBALERT_NO0                            : out   std_logic;
          SMBALERT_NO1                            : out   std_logic;
          SMBSUS_NO0                              : out   std_logic;
          SMBSUS_NO1                              : out   std_logic;
          SPI0_CLK_OUT                            : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_A                  : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_B                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_A                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_B                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_A                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_B                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_A                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_B                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_A                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_B                  : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_A                 : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_B                 : out   std_logic;
          SPI0_SS4_MGPIO19A_H2F_A                 : out   std_logic;
          SPI0_SS5_MGPIO20A_H2F_A                 : out   std_logic;
          SPI0_SS6_MGPIO21A_H2F_A                 : out   std_logic;
          SPI0_SS7_MGPIO22A_H2F_A                 : out   std_logic;
          SPI1_CLK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_A                 : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_B                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_A                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_B                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_A                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_B                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_A                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_B                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_A                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_B                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_A                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_B                 : out   std_logic;
          SPI1_SS4_MGPIO17A_H2F_A                 : out   std_logic;
          SPI1_SS5_MGPIO18A_H2F_A                 : out   std_logic;
          SPI1_SS6_MGPIO23A_H2F_A                 : out   std_logic;
          SPI1_SS7_MGPIO24A_H2F_A                 : out   std_logic;
          TCGF                                    : out   std_logic_vector(9 downto 0);
          TRACECLK                                : out   std_logic;
          TRACEDATA                               : out   std_logic_vector(3 downto 0);
          TX_CLK                                  : out   std_logic;
          TX_ENF                                  : out   std_logic;
          TX_ERRF                                 : out   std_logic;
          TXCTL_EN_RIF                            : out   std_logic;
          TXD_RIF                                 : out   std_logic_vector(3 downto 0);
          TXDF                                    : out   std_logic_vector(7 downto 0);
          TXEV                                    : out   std_logic;
          WDOGTIMEOUT                             : out   std_logic;
          F_ARREADY_HREADYOUT1                    : out   std_logic;
          F_AWREADY_HREADYOUT0                    : out   std_logic;
          F_BID                                   : out   std_logic_vector(3 downto 0);
          F_BRESP_HRESP0                          : out   std_logic_vector(1 downto 0);
          F_BVALID                                : out   std_logic;
          F_RDATA_HRDATA01                        : out   std_logic_vector(63 downto 0);
          F_RID                                   : out   std_logic_vector(3 downto 0);
          F_RLAST                                 : out   std_logic;
          F_RRESP_HRESP1                          : out   std_logic_vector(1 downto 0);
          F_RVALID                                : out   std_logic;
          F_WREADY                                : out   std_logic;
          MDDR_FABRIC_PRDATA                      : out   std_logic_vector(15 downto 0);
          MDDR_FABRIC_PREADY                      : out   std_logic;
          MDDR_FABRIC_PSLVERR                     : out   std_logic;
          REV_ARADDR                              : out   std_logic_vector(31 downto 0);
          REV_ARBURST                             : out   std_logic_vector(1 downto 0);
          REV_ARID                                : out   std_logic_vector(3 downto 0);
          REV_ARLEN                               : out   std_logic_vector(3 downto 0);
          REV_ARLOCK                              : out   std_logic_vector(1 downto 0);
          REV_ARSIZE                              : out   std_logic_vector(1 downto 0);
          REV_AWADDR                              : out   std_logic_vector(31 downto 0);
          REV_AWLOCK                              : out   std_logic_vector(1 downto 0);
          REV_AWSIZE                              : out   std_logic_vector(1 downto 0);
          REV_RREADY                              : out   std_logic;
          REV_WID                                 : out   std_logic_vector(3 downto 0);
          REV_WSTRB                               : out   std_logic_vector(7 downto 0);
          CAN_RXBUS_F2H_SCP                       : in    std_logic := 'U';
          CAN_TX_EBL_F2H_SCP                      : in    std_logic := 'U';
          CAN_TXBUS_F2H_SCP                       : in    std_logic := 'U';
          CLK_BASE                                : in    std_logic := 'U';
          COLF                                    : in    std_logic := 'U';
          CRSF                                    : in    std_logic := 'U';
          F2_DMAREADY                             : in    std_logic_vector(1 downto 0) := (others => 'U');
          F2H_INTERRUPT                           : in    std_logic_vector(15 downto 0) := (others => 'U');
          F2HCALIB                                : in    std_logic := 'U';
          F_DMAREADY                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_ADDR                              : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_ENABLE                            : in    std_logic := 'U';
          F_FM0_MASTLOCK                          : in    std_logic := 'U';
          F_FM0_READY                             : in    std_logic := 'U';
          F_FM0_SEL                               : in    std_logic := 'U';
          F_FM0_SIZE                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_TRANS1                            : in    std_logic := 'U';
          F_FM0_WDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_WRITE                             : in    std_logic := 'U';
          F_FM1_ADDR                              : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM1_ENABLE                            : in    std_logic := 'U';
          F_FM1_MASTLOCK                          : in    std_logic := 'U';
          F_FM1_READY                             : in    std_logic := 'U';
          F_FM1_SEL                               : in    std_logic := 'U';
          F_FM1_SIZE                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM1_TRANS1                            : in    std_logic := 'U';
          F_FM1_WDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM1_WRITE                             : in    std_logic := 'U';
          F_HM0_RDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_HM0_READY                             : in    std_logic := 'U';
          F_HM0_RESP                              : in    std_logic := 'U';
          F_HM1_RDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_HM1_READY                             : in    std_logic := 'U';
          F_HM1_RESP                              : in    std_logic := 'U';
          FAB_AVALID                              : in    std_logic := 'U';
          FAB_HOSTDISCON                          : in    std_logic := 'U';
          FAB_IDDIG                               : in    std_logic := 'U';
          FAB_LINESTATE                           : in    std_logic_vector(1 downto 0) := (others => 'U');
          FAB_M3_RESET_N                          : in    std_logic := 'U';
          FAB_PLL_LOCK                            : in    std_logic := 'U';
          FAB_RXACTIVE                            : in    std_logic := 'U';
          FAB_RXERROR                             : in    std_logic := 'U';
          FAB_RXVALID                             : in    std_logic := 'U';
          FAB_RXVALIDH                            : in    std_logic := 'U';
          FAB_SESSEND                             : in    std_logic := 'U';
          FAB_TXREADY                             : in    std_logic := 'U';
          FAB_VBUSVALID                           : in    std_logic := 'U';
          FAB_VSTATUS                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          FAB_XDATAIN                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          GTX_CLKPF                               : in    std_logic := 'U';
          I2C0_BCLK                               : in    std_logic := 'U';
          I2C0_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C0_SDA_F2H_SCP                        : in    std_logic := 'U';
          I2C1_BCLK                               : in    std_logic := 'U';
          I2C1_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C1_SDA_F2H_SCP                        : in    std_logic := 'U';
          MDIF                                    : in    std_logic := 'U';
          MGPIO0A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO10A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO12A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO13A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO14A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO15A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO16A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO17B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO18B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO19B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO1A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO20B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO21B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO22B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO24B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO25B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO26B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO27B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO28B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO29B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO2A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO30B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO31B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO3A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO4A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO5A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO6A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO7A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO8A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO9A_F2H_GPIN                        : in    std_logic := 'U';
          MMUART0_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DTR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART0_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_TXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART1_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_TXD_F2H_SCP                     : in    std_logic := 'U';
          PER2_FABRIC_PRDATA                      : in    std_logic_vector(31 downto 0) := (others => 'U');
          PER2_FABRIC_PREADY                      : in    std_logic := 'U';
          PER2_FABRIC_PSLVERR                     : in    std_logic := 'U';
          RCGF                                    : in    std_logic_vector(9 downto 0) := (others => 'U');
          RX_CLKPF                                : in    std_logic := 'U';
          RX_DVF                                  : in    std_logic := 'U';
          RX_ERRF                                 : in    std_logic := 'U';
          RX_EV                                   : in    std_logic := 'U';
          RXDF                                    : in    std_logic_vector(7 downto 0) := (others => 'U');
          SLEEPHOLDREQ                            : in    std_logic := 'U';
          SMBALERT_NI0                            : in    std_logic := 'U';
          SMBALERT_NI1                            : in    std_logic := 'U';
          SMBSUS_NI0                              : in    std_logic := 'U';
          SMBSUS_NI1                              : in    std_logic := 'U';
          SPI0_CLK_IN                             : in    std_logic := 'U';
          SPI0_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS3_F2H_SCP                        : in    std_logic := 'U';
          SPI1_CLK_IN                             : in    std_logic := 'U';
          SPI1_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS3_F2H_SCP                        : in    std_logic := 'U';
          TX_CLKPF                                : in    std_logic := 'U';
          USER_MSS_GPIO_RESET_N                   : in    std_logic := 'U';
          USER_MSS_RESET_N                        : in    std_logic := 'U';
          XCLK_FAB                                : in    std_logic := 'U';
          CLK_MDDR_APB                            : in    std_logic := 'U';
          F_ARADDR_HADDR1                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_ARBURST_HTRANS1                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARID_HSEL1                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLEN_HBURST1                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLOCK_HMASTLOCK1                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARSIZE_HSIZE1                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARVALID_HWRITE1                       : in    std_logic := 'U';
          F_AWADDR_HADDR0                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_AWBURST_HTRANS0                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWID_HSEL0                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLEN_HBURST0                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLOCK_HMASTLOCK0                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWSIZE_HSIZE0                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWVALID_HWRITE0                       : in    std_logic := 'U';
          F_BREADY                                : in    std_logic := 'U';
          F_RMW_AXI                               : in    std_logic := 'U';
          F_RREADY                                : in    std_logic := 'U';
          F_WDATA_HWDATA01                        : in    std_logic_vector(63 downto 0) := (others => 'U');
          F_WID_HREADY01                          : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_WLAST                                 : in    std_logic := 'U';
          F_WSTRB                                 : in    std_logic_vector(7 downto 0) := (others => 'U');
          F_WVALID                                : in    std_logic := 'U';
          FPGA_MDDR_ARESET_N                      : in    std_logic := 'U';
          MDDR_FABRIC_PADDR                       : in    std_logic_vector(10 downto 2) := (others => 'U');
          MDDR_FABRIC_PENABLE                     : in    std_logic := 'U';
          MDDR_FABRIC_PSEL                        : in    std_logic := 'U';
          MDDR_FABRIC_PWDATA                      : in    std_logic_vector(15 downto 0) := (others => 'U');
          MDDR_FABRIC_PWRITE                      : in    std_logic := 'U';
          PRESET_N                                : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_IN         : in    std_logic := 'U';
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN        : in    std_logic := 'U';
          CAN_TXBUS_USBA_DATA0_MGPIO2A_IN         : in    std_logic := 'U';
          DM_IN                                   : in    std_logic_vector(4 downto 0) := (others => 'U');
          DRAM_DQ_IN                              : in    std_logic_vector(35 downto 0) := (others => 'U');
          DRAM_DQS_IN                             : in    std_logic_vector(4 downto 0) := (others => 'U');
          DRAM_FIFO_WE_IN                         : in    std_logic_vector(2 downto 0) := (others => 'U');
          I2C0_SCL_USBC_DATA1_MGPIO31B_IN         : in    std_logic := 'U';
          I2C0_SDA_USBC_DATA0_MGPIO30B_IN         : in    std_logic := 'U';
          I2C1_SCL_USBA_DATA4_MGPIO1A_IN          : in    std_logic := 'U';
          I2C1_SDA_USBA_DATA3_MGPIO0A_IN          : in    std_logic := 'U';
          MGPIO0B_IN                              : in    std_logic := 'U';
          MGPIO10B_IN                             : in    std_logic := 'U';
          MGPIO1B_IN                              : in    std_logic := 'U';
          MGPIO25A_IN                             : in    std_logic := 'U';
          MGPIO26A_IN                             : in    std_logic := 'U';
          MGPIO27A_IN                             : in    std_logic := 'U';
          MGPIO28A_IN                             : in    std_logic := 'U';
          MGPIO29A_IN                             : in    std_logic := 'U';
          MGPIO2B_IN                              : in    std_logic := 'U';
          MGPIO30A_IN                             : in    std_logic := 'U';
          MGPIO31A_IN                             : in    std_logic := 'U';
          MGPIO3B_IN                              : in    std_logic := 'U';
          MGPIO4B_IN                              : in    std_logic := 'U';
          MGPIO5B_IN                              : in    std_logic := 'U';
          MGPIO6B_IN                              : in    std_logic := 'U';
          MGPIO7B_IN                              : in    std_logic := 'U';
          MGPIO8B_IN                              : in    std_logic := 'U';
          MGPIO9B_IN                              : in    std_logic := 'U';
          MMUART0_CTS_USBC_DATA7_MGPIO19B_IN      : in    std_logic := 'U';
          MMUART0_DCD_MGPIO22B_IN                 : in    std_logic := 'U';
          MMUART0_DSR_MGPIO20B_IN                 : in    std_logic := 'U';
          MMUART0_DTR_USBC_DATA6_MGPIO18B_IN      : in    std_logic := 'U';
          MMUART0_RI_MGPIO21B_IN                  : in    std_logic := 'U';
          MMUART0_RTS_USBC_DATA5_MGPIO17B_IN      : in    std_logic := 'U';
          MMUART0_RXD_USBC_STP_MGPIO28B_IN        : in    std_logic := 'U';
          MMUART0_SCK_USBC_NXT_MGPIO29B_IN        : in    std_logic := 'U';
          MMUART0_TXD_USBC_DIR_MGPIO27B_IN        : in    std_logic := 'U';
          MMUART1_CTS_MGPIO13B_IN                 : in    std_logic := 'U';
          MMUART1_DCD_MGPIO16B_IN                 : in    std_logic := 'U';
          MMUART1_DSR_MGPIO14B_IN                 : in    std_logic := 'U';
          MMUART1_DTR_MGPIO12B_IN                 : in    std_logic := 'U';
          MMUART1_RI_MGPIO15B_IN                  : in    std_logic := 'U';
          MMUART1_RTS_MGPIO11B_IN                 : in    std_logic := 'U';
          MMUART1_RXD_USBC_DATA3_MGPIO26B_IN      : in    std_logic := 'U';
          MMUART1_SCK_USBC_DATA4_MGPIO25B_IN      : in    std_logic := 'U';
          MMUART1_TXD_USBC_DATA2_MGPIO24B_IN      : in    std_logic := 'U';
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN     : in    std_logic := 'U';
          RGMII_MDC_RMII_MDC_IN                   : in    std_logic := 'U';
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN      : in    std_logic := 'U';
          RGMII_RX_CLK_IN                         : in    std_logic := 'U';
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN  : in    std_logic := 'U';
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN      : in    std_logic := 'U';
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN      : in    std_logic := 'U';
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN     : in    std_logic := 'U';
          RGMII_RXD3_USBB_DATA4_IN                : in    std_logic := 'U';
          RGMII_TX_CLK_IN                         : in    std_logic := 'U';
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN     : in    std_logic := 'U';
          RGMII_TXD0_RMII_TXD0_USBB_DIR_IN        : in    std_logic := 'U';
          RGMII_TXD1_RMII_TXD1_USBB_STP_IN        : in    std_logic := 'U';
          RGMII_TXD2_USBB_DATA5_IN                : in    std_logic := 'U';
          RGMII_TXD3_USBB_DATA6_IN                : in    std_logic := 'U';
          SPI0_SCK_USBA_XCLK_IN                   : in    std_logic := 'U';
          SPI0_SDI_USBA_DIR_MGPIO5A_IN            : in    std_logic := 'U';
          SPI0_SDO_USBA_STP_MGPIO6A_IN            : in    std_logic := 'U';
          SPI0_SS0_USBA_NXT_MGPIO7A_IN            : in    std_logic := 'U';
          SPI0_SS1_USBA_DATA5_MGPIO8A_IN          : in    std_logic := 'U';
          SPI0_SS2_USBA_DATA6_MGPIO9A_IN          : in    std_logic := 'U';
          SPI0_SS3_USBA_DATA7_MGPIO10A_IN         : in    std_logic := 'U';
          SPI0_SS4_MGPIO19A_IN                    : in    std_logic := 'U';
          SPI0_SS5_MGPIO20A_IN                    : in    std_logic := 'U';
          SPI0_SS6_MGPIO21A_IN                    : in    std_logic := 'U';
          SPI0_SS7_MGPIO22A_IN                    : in    std_logic := 'U';
          SPI1_SCK_IN                             : in    std_logic := 'U';
          SPI1_SDI_MGPIO11A_IN                    : in    std_logic := 'U';
          SPI1_SDO_MGPIO12A_IN                    : in    std_logic := 'U';
          SPI1_SS0_MGPIO13A_IN                    : in    std_logic := 'U';
          SPI1_SS1_MGPIO14A_IN                    : in    std_logic := 'U';
          SPI1_SS2_MGPIO15A_IN                    : in    std_logic := 'U';
          SPI1_SS3_MGPIO16A_IN                    : in    std_logic := 'U';
          SPI1_SS4_MGPIO17A_IN                    : in    std_logic := 'U';
          SPI1_SS5_MGPIO18A_IN                    : in    std_logic := 'U';
          SPI1_SS6_MGPIO23A_IN                    : in    std_logic := 'U';
          SPI1_SS7_MGPIO24A_IN                    : in    std_logic := 'U';
          USBC_XCLK_IN                            : in    std_logic := 'U';
          USBD_DATA0_IN                           : in    std_logic := 'U';
          USBD_DATA1_IN                           : in    std_logic := 'U';
          USBD_DATA2_IN                           : in    std_logic := 'U';
          USBD_DATA3_IN                           : in    std_logic := 'U';
          USBD_DATA4_IN                           : in    std_logic := 'U';
          USBD_DATA5_IN                           : in    std_logic := 'U';
          USBD_DATA6_IN                           : in    std_logic := 'U';
          USBD_DATA7_MGPIO23B_IN                  : in    std_logic := 'U';
          USBD_DIR_IN                             : in    std_logic := 'U';
          USBD_NXT_IN                             : in    std_logic := 'U';
          USBD_STP_IN                             : in    std_logic := 'U';
          USBD_XCLK_IN                            : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT        : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT       : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT        : out   std_logic;
          DRAM_ADDR                               : out   std_logic_vector(15 downto 0);
          DRAM_BA                                 : out   std_logic_vector(2 downto 0);
          DRAM_CASN                               : out   std_logic;
          DRAM_CKE                                : out   std_logic;
          DRAM_CLK                                : out   std_logic;
          DRAM_CSN                                : out   std_logic;
          DRAM_DM_RDQS_OUT                        : out   std_logic_vector(4 downto 0);
          DRAM_DQ_OUT                             : out   std_logic_vector(35 downto 0);
          DRAM_DQS_OUT                            : out   std_logic_vector(4 downto 0);
          DRAM_FIFO_WE_OUT                        : out   std_logic_vector(2 downto 0);
          DRAM_ODT                                : out   std_logic;
          DRAM_RASN                               : out   std_logic;
          DRAM_RSTN                               : out   std_logic;
          DRAM_WEN                                : out   std_logic;
          I2C0_SCL_USBC_DATA1_MGPIO31B_OUT        : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OUT        : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OUT         : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OUT         : out   std_logic;
          MGPIO0B_OUT                             : out   std_logic;
          MGPIO10B_OUT                            : out   std_logic;
          MGPIO1B_OUT                             : out   std_logic;
          MGPIO25A_OUT                            : out   std_logic;
          MGPIO26A_OUT                            : out   std_logic;
          MGPIO27A_OUT                            : out   std_logic;
          MGPIO28A_OUT                            : out   std_logic;
          MGPIO29A_OUT                            : out   std_logic;
          MGPIO2B_OUT                             : out   std_logic;
          MGPIO30A_OUT                            : out   std_logic;
          MGPIO31A_OUT                            : out   std_logic;
          MGPIO3B_OUT                             : out   std_logic;
          MGPIO4B_OUT                             : out   std_logic;
          MGPIO5B_OUT                             : out   std_logic;
          MGPIO6B_OUT                             : out   std_logic;
          MGPIO7B_OUT                             : out   std_logic;
          MGPIO8B_OUT                             : out   std_logic;
          MGPIO9B_OUT                             : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT     : out   std_logic;
          MMUART0_DCD_MGPIO22B_OUT                : out   std_logic;
          MMUART0_DSR_MGPIO20B_OUT                : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT     : out   std_logic;
          MMUART0_RI_MGPIO21B_OUT                 : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT     : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OUT       : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OUT       : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OUT       : out   std_logic;
          MMUART1_CTS_MGPIO13B_OUT                : out   std_logic;
          MMUART1_DCD_MGPIO16B_OUT                : out   std_logic;
          MMUART1_DSR_MGPIO14B_OUT                : out   std_logic;
          MMUART1_DTR_MGPIO12B_OUT                : out   std_logic;
          MMUART1_RI_MGPIO15B_OUT                 : out   std_logic;
          MMUART1_RTS_MGPIO11B_OUT                : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT     : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT     : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT     : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT    : out   std_logic;
          RGMII_MDC_RMII_MDC_OUT                  : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT     : out   std_logic;
          RGMII_RX_CLK_OUT                        : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT     : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT     : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT    : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OUT               : out   std_logic;
          RGMII_TX_CLK_OUT                        : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT    : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT       : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OUT       : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OUT               : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OUT               : out   std_logic;
          SPI0_SCK_USBA_XCLK_OUT                  : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OUT           : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OUT           : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OUT           : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OUT         : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OUT         : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OUT        : out   std_logic;
          SPI0_SS4_MGPIO19A_OUT                   : out   std_logic;
          SPI0_SS5_MGPIO20A_OUT                   : out   std_logic;
          SPI0_SS6_MGPIO21A_OUT                   : out   std_logic;
          SPI0_SS7_MGPIO22A_OUT                   : out   std_logic;
          SPI1_SCK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_OUT                   : out   std_logic;
          SPI1_SDO_MGPIO12A_OUT                   : out   std_logic;
          SPI1_SS0_MGPIO13A_OUT                   : out   std_logic;
          SPI1_SS1_MGPIO14A_OUT                   : out   std_logic;
          SPI1_SS2_MGPIO15A_OUT                   : out   std_logic;
          SPI1_SS3_MGPIO16A_OUT                   : out   std_logic;
          SPI1_SS4_MGPIO17A_OUT                   : out   std_logic;
          SPI1_SS5_MGPIO18A_OUT                   : out   std_logic;
          SPI1_SS6_MGPIO23A_OUT                   : out   std_logic;
          SPI1_SS7_MGPIO24A_OUT                   : out   std_logic;
          USBC_XCLK_OUT                           : out   std_logic;
          USBD_DATA0_OUT                          : out   std_logic;
          USBD_DATA1_OUT                          : out   std_logic;
          USBD_DATA2_OUT                          : out   std_logic;
          USBD_DATA3_OUT                          : out   std_logic;
          USBD_DATA4_OUT                          : out   std_logic;
          USBD_DATA5_OUT                          : out   std_logic;
          USBD_DATA6_OUT                          : out   std_logic;
          USBD_DATA7_MGPIO23B_OUT                 : out   std_logic;
          USBD_DIR_OUT                            : out   std_logic;
          USBD_NXT_OUT                            : out   std_logic;
          USBD_STP_OUT                            : out   std_logic;
          USBD_XCLK_OUT                           : out   std_logic;
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OE         : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE        : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OE         : out   std_logic;
          DM_OE                                   : out   std_logic_vector(4 downto 0);
          DRAM_DQ_OE                              : out   std_logic_vector(35 downto 0);
          DRAM_DQS_OE                             : out   std_logic_vector(4 downto 0);
          I2C0_SCL_USBC_DATA1_MGPIO31B_OE         : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OE         : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OE          : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OE          : out   std_logic;
          MGPIO0B_OE                              : out   std_logic;
          MGPIO10B_OE                             : out   std_logic;
          MGPIO1B_OE                              : out   std_logic;
          MGPIO25A_OE                             : out   std_logic;
          MGPIO26A_OE                             : out   std_logic;
          MGPIO27A_OE                             : out   std_logic;
          MGPIO28A_OE                             : out   std_logic;
          MGPIO29A_OE                             : out   std_logic;
          MGPIO2B_OE                              : out   std_logic;
          MGPIO30A_OE                             : out   std_logic;
          MGPIO31A_OE                             : out   std_logic;
          MGPIO3B_OE                              : out   std_logic;
          MGPIO4B_OE                              : out   std_logic;
          MGPIO5B_OE                              : out   std_logic;
          MGPIO6B_OE                              : out   std_logic;
          MGPIO7B_OE                              : out   std_logic;
          MGPIO8B_OE                              : out   std_logic;
          MGPIO9B_OE                              : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OE      : out   std_logic;
          MMUART0_DCD_MGPIO22B_OE                 : out   std_logic;
          MMUART0_DSR_MGPIO20B_OE                 : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OE      : out   std_logic;
          MMUART0_RI_MGPIO21B_OE                  : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OE      : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OE        : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OE        : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OE        : out   std_logic;
          MMUART1_CTS_MGPIO13B_OE                 : out   std_logic;
          MMUART1_DCD_MGPIO16B_OE                 : out   std_logic;
          MMUART1_DSR_MGPIO14B_OE                 : out   std_logic;
          MMUART1_DTR_MGPIO12B_OE                 : out   std_logic;
          MMUART1_RI_MGPIO15B_OE                  : out   std_logic;
          MMUART1_RTS_MGPIO11B_OE                 : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OE      : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OE      : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OE      : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE     : out   std_logic;
          RGMII_MDC_RMII_MDC_OE                   : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE      : out   std_logic;
          RGMII_RX_CLK_OE                         : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE  : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE      : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE      : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE     : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OE                : out   std_logic;
          RGMII_TX_CLK_OE                         : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE     : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OE        : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OE        : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OE                : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OE                : out   std_logic;
          SPI0_SCK_USBA_XCLK_OE                   : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OE            : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OE            : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OE            : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OE          : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OE          : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OE         : out   std_logic;
          SPI0_SS4_MGPIO19A_OE                    : out   std_logic;
          SPI0_SS5_MGPIO20A_OE                    : out   std_logic;
          SPI0_SS6_MGPIO21A_OE                    : out   std_logic;
          SPI0_SS7_MGPIO22A_OE                    : out   std_logic;
          SPI1_SCK_OE                             : out   std_logic;
          SPI1_SDI_MGPIO11A_OE                    : out   std_logic;
          SPI1_SDO_MGPIO12A_OE                    : out   std_logic;
          SPI1_SS0_MGPIO13A_OE                    : out   std_logic;
          SPI1_SS1_MGPIO14A_OE                    : out   std_logic;
          SPI1_SS2_MGPIO15A_OE                    : out   std_logic;
          SPI1_SS3_MGPIO16A_OE                    : out   std_logic;
          SPI1_SS4_MGPIO17A_OE                    : out   std_logic;
          SPI1_SS5_MGPIO18A_OE                    : out   std_logic;
          SPI1_SS6_MGPIO23A_OE                    : out   std_logic;
          SPI1_SS7_MGPIO24A_OE                    : out   std_logic;
          USBC_XCLK_OE                            : out   std_logic;
          USBD_DATA0_OE                           : out   std_logic;
          USBD_DATA1_OE                           : out   std_logic;
          USBD_DATA2_OE                           : out   std_logic;
          USBD_DATA3_OE                           : out   std_logic;
          USBD_DATA4_OE                           : out   std_logic;
          USBD_DATA5_OE                           : out   std_logic;
          USBD_DATA6_OE                           : out   std_logic;
          USBD_DATA7_MGPIO23B_OE                  : out   std_logic;
          USBD_DIR_OE                             : out   std_logic;
          USBD_NXT_OE                             : out   std_logic;
          USBD_STP_OE                             : out   std_logic;
          USBD_XCLK_OE                            : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component TRIBUFF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

    signal MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART_0_RXD_PAD_Y, VCC_net_1, GND_net_1 : std_logic;
    signal nc488, nc74, nc54, nc302, nc406, nc312, nc416, nc461, 
        nc599, nc309, nc458, nc32, nc402, nc319, nc228, nc325, 
        nc8, nc148, nc327, nc346, nc412, nc98, nc60, nc196, nc224, 
        nc29, nc601, nc102, nc120, nc61, nc611, nc525, nc95, 
        nc328, nc273, nc374, nc580, nc112, nc10, nc42, nc341, 
        nc602, nc79, nc231, nc135, nc59, nc11, nc444, nc330, 
        nc550, nc612, nc562, nc427, nc579, nc588, nc86, nc604, 
        nc460, nc198, nc322, nc426, nc441, nc280, nc396, nc103, 
        nc586, nc329, nc558, nc113, nc176, nc33, nc27, nc238, 
        nc335, nc383, nc485, nc422, nc250, nc337, nc408, nc567, 
        nc556, nc234, nc418, nc391, nc62, nc353, nc455, nc130, 
        nc77, nc57, nc535, nc122, nc494, nc583, nc338, nc90, 
        nc169, nc43, nc12, nc542, nc553, nc491, nc91, nc178, 
        nc581, nc376, nc437, nc84, nc440, nc500, nc332, nc436, 
        nc510, nc184, nc551, nc483, nc123, nc339, nc584, nc286, 
        nc371, nc432, nc287, nc547, nc154, nc508, nc453, nc474, 
        nc428, nc554, nc200, nc256, nc518, nc3, nc489, nc63, 
        nc257, nc506, nc210, nc592, nc132, nc471, nc303, nc405, 
        nc516, nc149, nc603, nc89, nc459, nc490, nc261, nc165, 
        nc313, nc415, nc13, nc92, nc613, nc360, nc285, nc503, nc4, 
        nc520, nc255, nc513, nc597, nc282, nc133, nc605, nc36, 
        nc365, nc268, nc501, nc367, nc252, nc572, nc511, nc528, 
        nc438, nc264, nc199, nc104, nc160, nc220, nc403, nc87, 
        nc608, nc470, nc565, nc114, nc368, nc504, nc206, nc526, 
        nc413, nc207, nc241, nc145, nc514, nc323, nc425, nc216, 
        nc46, nc6, nc606, nc340, nc217, nc181, nc93, nc187, nc600, 
        nc409, nc289, nc577, nc467, nc610, nc419, nc151, nc523, 
        nc1, nc157, nc362, nc466, nc530, nc259, nc34, nc369, 
        nc345, nc248, nc205, nc179, nc347, nc462, nc215, nc521, 
        nc244, nc538, nc291, nc195, nc66, nc140, nc202, nc545, 
        nc390, nc230, nc124, nc348, nc162, nc423, nc212, nc283, 
        nc384, nc536, nc524, nc226, nc44, nc333, nc435, nc227, 
        nc16, nc253, nc354, nc447, nc429, nc589, nc39, nc395, 
        nc298, nc342, nc446, nc397, nc533, nc9, nc349, nc294, 
        nc559, nc163, nc101, nc107, nc186, nc190, nc28, nc271, 
        nc442, nc175, nc209, nc595, nc225, nc111, nc117, nc398, 
        nc370, nc531, nc219, nc468, nc49, nc64, nc156, nc25, 
        nc142, nc78, nc58, nc222, nc134, nc433, nc497, nc534, 
        nc236, nc14, nc37, nc237, nc375, nc75, nc278, nc392, 
        nc496, nc55, nc96, nc377, nc188, nc607, nc386, nc399, 
        nc439, nc274, nc203, nc304, nc492, nc170, nc560, nc158, 
        nc213, nc575, nc314, nc356, nc378, nc143, nc69, nc121, 
        nc47, nc127, nc381, nc235, nc192, nc509, nc229, nc448, 
        nc484, nc519, nc568, nc477, nc19, nc351, nc260, nc232, 
        nc372, nc476, nc106, nc454, nc20, nc566, nc481, nc116, 
        nc363, nc465, nc379, nc21, nc94, nc472, nc451, nc193, 
        nc70, nc50, nc67, nc540, nc563, nc71, nc223, nc51, nc324, 
        nc172, nc498, nc108, nc131, nc306, nc137, nc17, nc118, 
        nc561, nc239, nc529, nc609, nc582, nc548, nc316, nc240, 
        nc99, nc88, nc480, nc164, nc463, nc546, nc552, nc301, 
        nc564, nc126, nc266, nc343, nc445, nc22, nc173, nc267, 
        nc85, nc404, nc450, nc311, nc590, nc414, nc587, nc469, 
        nc478, nc72, nc52, nc543, nc401, nc233, nc334, nc557, 
        nc411, nc598, nc290, nc189, nc265, nc128, nc541, nc97, 
        nc326, nc596, nc539, nc393, nc495, nc159, nc144, nc443, 
        nc262, nc570, nc544, nc246, nc136, nc23, nc247, nc321, 
        nc593, nc502, nc424, nc512, nc449, nc80, nc400, nc578, 
        nc73, nc81, nc53, nc410, nc270, nc591, nc421, nc576, 
        nc245, nc161, nc373, nc475, nc167, nc281, nc194, nc507, 
        nc185, nc493, nc138, nc269, nc380, nc336, nc517, nc594, 
        nc296, nc297, nc251, nc155, nc242, nc573, nc350, nc109, 
        nc499, nc119, nc331, nc38, nc385, nc288, nc522, nc434, 
        nc387, nc571, nc2, nc82, nc284, nc420, nc35, nc295, nc355, 
        nc258, nc263, nc180, nc364, nc357, nc174, nc585, nc431, 
        nc473, nc388, nc254, nc574, nc141, nc276, nc147, nc48, 
        nc7, nc5, nc150, nc277, nc292, nc249, nc555, nc527, nc358, 
        nc569, nc487, nc479, nc45, nc382, nc486, nc201, nc105, 
        nc457, nc166, nc26, nc129, nc300, nc389, nc211, nc115, 
        nc275, nc352, nc456, nc310, nc482, nc532, nc359, nc191, 
        nc83, nc197, nc430, nc76, nc56, nc243, nc68, nc344, nc452, 
        nc299, nc272, nc182, nc30, nc305, nc208, nc307, nc31, 
        nc65, nc315, nc218, nc168, nc18, nc317, nc549, nc366, 
        nc152, nc204, nc537, nc100, nc214, nc505, nc308, nc15, 
        nc110, nc515, nc318, nc40, nc146, nc24, nc221, nc125, 
        nc183, nc139, nc361, nc41, nc293, nc171, nc320, nc394, 
        nc177, nc407, nc464, nc279, nc417, nc153 : std_logic;

begin 


    MMUART_0_RXD_PAD : INBUF
      port map(PAD => MMUART_0_RXD, Y => MMUART_0_RXD_PAD_Y);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    MSS_ADLIB_INST : MSS_120

              generic map(INIT => "00" & x"0000000003612000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE4000000000000100000000F0E3DC00000180DFDC010842108421000001FE34001FF8000000400000000000891007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
         ACT_UBITS => x"FFFFFFFFFFFFFF",
         MEMORYFILE => "ENVM_init.mem", RTC_MAIN_XTL_FREQ => 0.0,
         DDR_CLK_FREQ => 0.0)

      port map(CAN_RXBUS_MGPIO3A_H2F_A => OPEN, 
        CAN_RXBUS_MGPIO3A_H2F_B => OPEN, CAN_TX_EBL_MGPIO4A_H2F_A
         => OPEN, CAN_TX_EBL_MGPIO4A_H2F_B => OPEN, 
        CAN_TXBUS_MGPIO2A_H2F_A => OPEN, CAN_TXBUS_MGPIO2A_H2F_B
         => AHB_Bus_Matrix_sb_0_GPIO_2_M2F, CLK_CONFIG_APB => 
        OPEN, COMMS_INT => OPEN, CONFIG_PRESET_N => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, 
        EDAC_ERROR(7) => nc488, EDAC_ERROR(6) => nc74, 
        EDAC_ERROR(5) => nc54, EDAC_ERROR(4) => nc302, 
        EDAC_ERROR(3) => nc406, EDAC_ERROR(2) => nc312, 
        EDAC_ERROR(1) => nc416, EDAC_ERROR(0) => nc461, 
        F_FM0_RDATA(31) => nc599, F_FM0_RDATA(30) => nc309, 
        F_FM0_RDATA(29) => nc458, F_FM0_RDATA(28) => nc32, 
        F_FM0_RDATA(27) => nc402, F_FM0_RDATA(26) => nc319, 
        F_FM0_RDATA(25) => nc228, F_FM0_RDATA(24) => nc325, 
        F_FM0_RDATA(23) => nc8, F_FM0_RDATA(22) => nc148, 
        F_FM0_RDATA(21) => nc327, F_FM0_RDATA(20) => nc346, 
        F_FM0_RDATA(19) => nc412, F_FM0_RDATA(18) => nc98, 
        F_FM0_RDATA(17) => nc60, F_FM0_RDATA(16) => nc196, 
        F_FM0_RDATA(15) => nc224, F_FM0_RDATA(14) => nc29, 
        F_FM0_RDATA(13) => nc601, F_FM0_RDATA(12) => nc102, 
        F_FM0_RDATA(11) => nc120, F_FM0_RDATA(10) => nc61, 
        F_FM0_RDATA(9) => nc611, F_FM0_RDATA(8) => nc525, 
        F_FM0_RDATA(7) => nc95, F_FM0_RDATA(6) => nc328, 
        F_FM0_RDATA(5) => nc273, F_FM0_RDATA(4) => nc374, 
        F_FM0_RDATA(3) => nc580, F_FM0_RDATA(2) => nc112, 
        F_FM0_RDATA(1) => nc10, F_FM0_RDATA(0) => nc42, 
        F_FM0_READYOUT => Fabric_Master1_0_BIF_1_HREADYOUT, 
        F_FM0_RESP => OPEN, F_FM1_RDATA(31) => nc341, 
        F_FM1_RDATA(30) => nc602, F_FM1_RDATA(29) => nc79, 
        F_FM1_RDATA(28) => nc231, F_FM1_RDATA(27) => nc135, 
        F_FM1_RDATA(26) => nc59, F_FM1_RDATA(25) => nc11, 
        F_FM1_RDATA(24) => nc444, F_FM1_RDATA(23) => nc330, 
        F_FM1_RDATA(22) => nc550, F_FM1_RDATA(21) => nc612, 
        F_FM1_RDATA(20) => nc562, F_FM1_RDATA(19) => nc427, 
        F_FM1_RDATA(18) => nc579, F_FM1_RDATA(17) => nc588, 
        F_FM1_RDATA(16) => nc86, F_FM1_RDATA(15) => nc604, 
        F_FM1_RDATA(14) => nc460, F_FM1_RDATA(13) => nc198, 
        F_FM1_RDATA(12) => nc322, F_FM1_RDATA(11) => nc426, 
        F_FM1_RDATA(10) => nc441, F_FM1_RDATA(9) => nc280, 
        F_FM1_RDATA(8) => nc396, F_FM1_RDATA(7) => nc103, 
        F_FM1_RDATA(6) => nc586, F_FM1_RDATA(5) => nc329, 
        F_FM1_RDATA(4) => nc558, F_FM1_RDATA(3) => nc113, 
        F_FM1_RDATA(2) => nc176, F_FM1_RDATA(1) => nc33, 
        F_FM1_RDATA(0) => nc27, F_FM1_READYOUT => 
        Fabric_Master2_0_BIF_1_HREADYOUT, F_FM1_RESP => OPEN, 
        F_HM0_ADDR(31) => nc238, F_HM0_ADDR(30) => nc335, 
        F_HM0_ADDR(29) => nc383, F_HM0_ADDR(28) => nc485, 
        F_HM0_ADDR(27) => nc422, F_HM0_ADDR(26) => nc250, 
        F_HM0_ADDR(25) => nc337, F_HM0_ADDR(24) => nc408, 
        F_HM0_ADDR(23) => nc567, F_HM0_ADDR(22) => nc556, 
        F_HM0_ADDR(21) => nc234, F_HM0_ADDR(20) => nc418, 
        F_HM0_ADDR(19) => nc391, F_HM0_ADDR(18) => nc62, 
        F_HM0_ADDR(17) => nc353, F_HM0_ADDR(16) => nc455, 
        F_HM0_ADDR(15) => nc130, F_HM0_ADDR(14) => nc77, 
        F_HM0_ADDR(13) => nc57, F_HM0_ADDR(12) => nc535, 
        F_HM0_ADDR(11) => nc122, F_HM0_ADDR(10) => nc494, 
        F_HM0_ADDR(9) => nc583, F_HM0_ADDR(8) => nc338, 
        F_HM0_ADDR(7) => nc90, F_HM0_ADDR(6) => nc169, 
        F_HM0_ADDR(5) => nc43, F_HM0_ADDR(4) => nc12, 
        F_HM0_ADDR(3) => nc542, F_HM0_ADDR(2) => nc553, 
        F_HM0_ADDR(1) => nc491, F_HM0_ADDR(0) => nc91, 
        F_HM0_ENABLE => OPEN, F_HM0_SEL => OPEN, F_HM0_SIZE(1)
         => nc178, F_HM0_SIZE(0) => nc581, F_HM0_TRANS1 => OPEN, 
        F_HM0_WDATA(31) => nc376, F_HM0_WDATA(30) => nc437, 
        F_HM0_WDATA(29) => nc84, F_HM0_WDATA(28) => nc440, 
        F_HM0_WDATA(27) => nc500, F_HM0_WDATA(26) => nc332, 
        F_HM0_WDATA(25) => nc436, F_HM0_WDATA(24) => nc510, 
        F_HM0_WDATA(23) => nc184, F_HM0_WDATA(22) => nc551, 
        F_HM0_WDATA(21) => nc483, F_HM0_WDATA(20) => nc123, 
        F_HM0_WDATA(19) => nc339, F_HM0_WDATA(18) => nc584, 
        F_HM0_WDATA(17) => nc286, F_HM0_WDATA(16) => nc371, 
        F_HM0_WDATA(15) => nc432, F_HM0_WDATA(14) => nc287, 
        F_HM0_WDATA(13) => nc547, F_HM0_WDATA(12) => nc154, 
        F_HM0_WDATA(11) => nc508, F_HM0_WDATA(10) => nc453, 
        F_HM0_WDATA(9) => nc474, F_HM0_WDATA(8) => nc428, 
        F_HM0_WDATA(7) => nc554, F_HM0_WDATA(6) => nc200, 
        F_HM0_WDATA(5) => nc256, F_HM0_WDATA(4) => nc518, 
        F_HM0_WDATA(3) => nc3, F_HM0_WDATA(2) => nc489, 
        F_HM0_WDATA(1) => nc63, F_HM0_WDATA(0) => nc257, 
        F_HM0_WRITE => OPEN, F_HM1_ADDR(31) => nc506, 
        F_HM1_ADDR(30) => nc210, F_HM1_ADDR(29) => nc592, 
        F_HM1_ADDR(28) => nc132, F_HM1_ADDR(27) => nc471, 
        F_HM1_ADDR(26) => nc303, F_HM1_ADDR(25) => nc405, 
        F_HM1_ADDR(24) => nc516, F_HM1_ADDR(23) => nc149, 
        F_HM1_ADDR(22) => nc603, F_HM1_ADDR(21) => nc89, 
        F_HM1_ADDR(20) => nc459, F_HM1_ADDR(19) => nc490, 
        F_HM1_ADDR(18) => nc261, F_HM1_ADDR(17) => nc165, 
        F_HM1_ADDR(16) => nc313, F_HM1_ADDR(15) => nc415, 
        F_HM1_ADDR(14) => nc13, F_HM1_ADDR(13) => nc92, 
        F_HM1_ADDR(12) => nc613, F_HM1_ADDR(11) => nc360, 
        F_HM1_ADDR(10) => nc285, F_HM1_ADDR(9) => nc503, 
        F_HM1_ADDR(8) => nc4, F_HM1_ADDR(7) => nc520, 
        F_HM1_ADDR(6) => nc255, F_HM1_ADDR(5) => nc513, 
        F_HM1_ADDR(4) => nc597, F_HM1_ADDR(3) => nc282, 
        F_HM1_ADDR(2) => nc133, F_HM1_ADDR(1) => nc605, 
        F_HM1_ADDR(0) => nc36, F_HM1_ENABLE => OPEN, F_HM1_SEL
         => OPEN, F_HM1_SIZE(1) => nc365, F_HM1_SIZE(0) => nc268, 
        F_HM1_TRANS1 => OPEN, F_HM1_WDATA(31) => nc501, 
        F_HM1_WDATA(30) => nc367, F_HM1_WDATA(29) => nc252, 
        F_HM1_WDATA(28) => nc572, F_HM1_WDATA(27) => nc511, 
        F_HM1_WDATA(26) => nc528, F_HM1_WDATA(25) => nc438, 
        F_HM1_WDATA(24) => nc264, F_HM1_WDATA(23) => nc199, 
        F_HM1_WDATA(22) => nc104, F_HM1_WDATA(21) => nc160, 
        F_HM1_WDATA(20) => nc220, F_HM1_WDATA(19) => nc403, 
        F_HM1_WDATA(18) => nc87, F_HM1_WDATA(17) => nc608, 
        F_HM1_WDATA(16) => nc470, F_HM1_WDATA(15) => nc565, 
        F_HM1_WDATA(14) => nc114, F_HM1_WDATA(13) => nc368, 
        F_HM1_WDATA(12) => nc504, F_HM1_WDATA(11) => nc206, 
        F_HM1_WDATA(10) => nc526, F_HM1_WDATA(9) => nc413, 
        F_HM1_WDATA(8) => nc207, F_HM1_WDATA(7) => nc241, 
        F_HM1_WDATA(6) => nc145, F_HM1_WDATA(5) => nc514, 
        F_HM1_WDATA(4) => nc323, F_HM1_WDATA(3) => nc425, 
        F_HM1_WDATA(2) => nc216, F_HM1_WDATA(1) => nc46, 
        F_HM1_WDATA(0) => nc6, F_HM1_WRITE => OPEN, FAB_CHRGVBUS
         => OPEN, FAB_DISCHRGVBUS => OPEN, FAB_DMPULLDOWN => OPEN, 
        FAB_DPPULLDOWN => OPEN, FAB_DRVVBUS => OPEN, FAB_IDPULLUP
         => OPEN, FAB_OPMODE(1) => nc606, FAB_OPMODE(0) => nc340, 
        FAB_SUSPENDM => OPEN, FAB_TERMSEL => OPEN, FAB_TXVALID
         => OPEN, FAB_VCONTROL(3) => nc217, FAB_VCONTROL(2) => 
        nc181, FAB_VCONTROL(1) => nc93, FAB_VCONTROL(0) => nc187, 
        FAB_VCONTROLLOADM => OPEN, FAB_XCVRSEL(1) => nc600, 
        FAB_XCVRSEL(0) => nc409, FAB_XDATAOUT(7) => nc289, 
        FAB_XDATAOUT(6) => nc577, FAB_XDATAOUT(5) => nc467, 
        FAB_XDATAOUT(4) => nc610, FAB_XDATAOUT(3) => nc419, 
        FAB_XDATAOUT(2) => nc151, FAB_XDATAOUT(1) => nc523, 
        FAB_XDATAOUT(0) => nc1, FACC_GLMUX_SEL => OPEN, 
        FIC32_0_MASTER(1) => nc157, FIC32_0_MASTER(0) => nc362, 
        FIC32_1_MASTER(1) => nc466, FIC32_1_MASTER(0) => nc530, 
        FPGA_RESET_N => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F, GTX_CLK => 
        OPEN, H2F_INTERRUPT(15) => nc259, H2F_INTERRUPT(14) => 
        nc34, H2F_INTERRUPT(13) => nc369, H2F_INTERRUPT(12) => 
        nc345, H2F_INTERRUPT(11) => nc248, H2F_INTERRUPT(10) => 
        nc205, H2F_INTERRUPT(9) => nc179, H2F_INTERRUPT(8) => 
        nc347, H2F_INTERRUPT(7) => nc462, H2F_INTERRUPT(6) => 
        nc215, H2F_INTERRUPT(5) => nc521, H2F_INTERRUPT(4) => 
        nc244, H2F_INTERRUPT(3) => nc538, H2F_INTERRUPT(2) => 
        nc291, H2F_INTERRUPT(1) => nc195, H2F_INTERRUPT(0) => 
        nc66, H2F_NMI => OPEN, H2FCALIB => OPEN, 
        I2C0_SCL_MGPIO31B_H2F_A => OPEN, I2C0_SCL_MGPIO31B_H2F_B
         => OPEN, I2C0_SDA_MGPIO30B_H2F_A => OPEN, 
        I2C0_SDA_MGPIO30B_H2F_B => OPEN, I2C1_SCL_MGPIO1A_H2F_A
         => OPEN, I2C1_SCL_MGPIO1A_H2F_B => OPEN, 
        I2C1_SDA_MGPIO0A_H2F_A => OPEN, I2C1_SDA_MGPIO0A_H2F_B
         => AHB_Bus_Matrix_sb_0_GPIO_0_M2F, MDCF => OPEN, MDOENF
         => OPEN, MDOF => OPEN, MMUART0_CTS_MGPIO19B_H2F_A => 
        OPEN, MMUART0_CTS_MGPIO19B_H2F_B => OPEN, 
        MMUART0_DCD_MGPIO22B_H2F_A => OPEN, 
        MMUART0_DCD_MGPIO22B_H2F_B => OPEN, 
        MMUART0_DSR_MGPIO20B_H2F_A => OPEN, 
        MMUART0_DSR_MGPIO20B_H2F_B => OPEN, 
        MMUART0_DTR_MGPIO18B_H2F_A => OPEN, 
        MMUART0_DTR_MGPIO18B_H2F_B => OPEN, 
        MMUART0_RI_MGPIO21B_H2F_A => OPEN, 
        MMUART0_RI_MGPIO21B_H2F_B => OPEN, 
        MMUART0_RTS_MGPIO17B_H2F_A => OPEN, 
        MMUART0_RTS_MGPIO17B_H2F_B => OPEN, 
        MMUART0_RXD_MGPIO28B_H2F_A => OPEN, 
        MMUART0_RXD_MGPIO28B_H2F_B => OPEN, 
        MMUART0_SCK_MGPIO29B_H2F_A => OPEN, 
        MMUART0_SCK_MGPIO29B_H2F_B => OPEN, 
        MMUART0_TXD_MGPIO27B_H2F_A => OPEN, 
        MMUART0_TXD_MGPIO27B_H2F_B => OPEN, 
        MMUART1_DTR_MGPIO12B_H2F_A => OPEN, 
        MMUART1_RTS_MGPIO11B_H2F_A => OPEN, 
        MMUART1_RTS_MGPIO11B_H2F_B => OPEN, 
        MMUART1_RXD_MGPIO26B_H2F_A => OPEN, 
        MMUART1_RXD_MGPIO26B_H2F_B => OPEN, 
        MMUART1_SCK_MGPIO25B_H2F_A => OPEN, 
        MMUART1_SCK_MGPIO25B_H2F_B => OPEN, 
        MMUART1_TXD_MGPIO24B_H2F_A => OPEN, 
        MMUART1_TXD_MGPIO24B_H2F_B => OPEN, MPLL_LOCK => OPEN, 
        PER2_FABRIC_PADDR(16) => nc140, PER2_FABRIC_PADDR(15) => 
        nc202, PER2_FABRIC_PADDR(14) => nc545, 
        PER2_FABRIC_PADDR(13) => nc390, PER2_FABRIC_PADDR(12) => 
        nc230, PER2_FABRIC_PADDR(11) => nc124, 
        PER2_FABRIC_PADDR(10) => nc348, PER2_FABRIC_PADDR(9) => 
        nc162, PER2_FABRIC_PADDR(8) => nc423, 
        PER2_FABRIC_PADDR(7) => nc212, PER2_FABRIC_PADDR(6) => 
        nc283, PER2_FABRIC_PADDR(5) => nc384, 
        PER2_FABRIC_PADDR(4) => nc536, PER2_FABRIC_PADDR(3) => 
        nc524, PER2_FABRIC_PADDR(2) => nc226, PER2_FABRIC_PENABLE
         => OPEN, PER2_FABRIC_PSEL => OPEN, 
        PER2_FABRIC_PWDATA(31) => nc44, PER2_FABRIC_PWDATA(30)
         => nc333, PER2_FABRIC_PWDATA(29) => nc435, 
        PER2_FABRIC_PWDATA(28) => nc227, PER2_FABRIC_PWDATA(27)
         => nc16, PER2_FABRIC_PWDATA(26) => nc253, 
        PER2_FABRIC_PWDATA(25) => nc354, PER2_FABRIC_PWDATA(24)
         => nc447, PER2_FABRIC_PWDATA(23) => nc429, 
        PER2_FABRIC_PWDATA(22) => nc589, PER2_FABRIC_PWDATA(21)
         => nc39, PER2_FABRIC_PWDATA(20) => nc395, 
        PER2_FABRIC_PWDATA(19) => nc298, PER2_FABRIC_PWDATA(18)
         => nc342, PER2_FABRIC_PWDATA(17) => nc446, 
        PER2_FABRIC_PWDATA(16) => nc397, PER2_FABRIC_PWDATA(15)
         => nc533, PER2_FABRIC_PWDATA(14) => nc9, 
        PER2_FABRIC_PWDATA(13) => nc349, PER2_FABRIC_PWDATA(12)
         => nc294, PER2_FABRIC_PWDATA(11) => nc559, 
        PER2_FABRIC_PWDATA(10) => nc163, PER2_FABRIC_PWDATA(9)
         => nc101, PER2_FABRIC_PWDATA(8) => nc107, 
        PER2_FABRIC_PWDATA(7) => nc186, PER2_FABRIC_PWDATA(6) => 
        nc190, PER2_FABRIC_PWDATA(5) => nc28, 
        PER2_FABRIC_PWDATA(4) => nc271, PER2_FABRIC_PWDATA(3) => 
        nc442, PER2_FABRIC_PWDATA(2) => nc175, 
        PER2_FABRIC_PWDATA(1) => nc209, PER2_FABRIC_PWDATA(0) => 
        nc595, PER2_FABRIC_PWRITE => OPEN, RTC_MATCH => OPEN, 
        SLEEPDEEP => OPEN, SLEEPHOLDACK => OPEN, SLEEPING => OPEN, 
        SMBALERT_NO0 => OPEN, SMBALERT_NO1 => OPEN, SMBSUS_NO0
         => OPEN, SMBSUS_NO1 => OPEN, SPI0_CLK_OUT => OPEN, 
        SPI0_SDI_MGPIO5A_H2F_A => OPEN, SPI0_SDI_MGPIO5A_H2F_B
         => OPEN, SPI0_SDO_MGPIO6A_H2F_A => OPEN, 
        SPI0_SDO_MGPIO6A_H2F_B => OPEN, SPI0_SS0_MGPIO7A_H2F_A
         => OPEN, SPI0_SS0_MGPIO7A_H2F_B => OPEN, 
        SPI0_SS1_MGPIO8A_H2F_A => OPEN, SPI0_SS1_MGPIO8A_H2F_B
         => OPEN, SPI0_SS2_MGPIO9A_H2F_A => OPEN, 
        SPI0_SS2_MGPIO9A_H2F_B => OPEN, SPI0_SS3_MGPIO10A_H2F_A
         => OPEN, SPI0_SS3_MGPIO10A_H2F_B => OPEN, 
        SPI0_SS4_MGPIO19A_H2F_A => OPEN, SPI0_SS5_MGPIO20A_H2F_A
         => OPEN, SPI0_SS6_MGPIO21A_H2F_A => OPEN, 
        SPI0_SS7_MGPIO22A_H2F_A => OPEN, SPI1_CLK_OUT => OPEN, 
        SPI1_SDI_MGPIO11A_H2F_A => OPEN, SPI1_SDI_MGPIO11A_H2F_B
         => OPEN, SPI1_SDO_MGPIO12A_H2F_A => OPEN, 
        SPI1_SDO_MGPIO12A_H2F_B => OPEN, SPI1_SS0_MGPIO13A_H2F_A
         => OPEN, SPI1_SS0_MGPIO13A_H2F_B => OPEN, 
        SPI1_SS1_MGPIO14A_H2F_A => OPEN, SPI1_SS1_MGPIO14A_H2F_B
         => OPEN, SPI1_SS2_MGPIO15A_H2F_A => OPEN, 
        SPI1_SS2_MGPIO15A_H2F_B => OPEN, SPI1_SS3_MGPIO16A_H2F_A
         => OPEN, SPI1_SS3_MGPIO16A_H2F_B => OPEN, 
        SPI1_SS4_MGPIO17A_H2F_A => OPEN, SPI1_SS5_MGPIO18A_H2F_A
         => OPEN, SPI1_SS6_MGPIO23A_H2F_A => OPEN, 
        SPI1_SS7_MGPIO24A_H2F_A => OPEN, TCGF(9) => nc225, 
        TCGF(8) => nc111, TCGF(7) => nc117, TCGF(6) => nc398, 
        TCGF(5) => nc370, TCGF(4) => nc531, TCGF(3) => nc219, 
        TCGF(2) => nc468, TCGF(1) => nc49, TCGF(0) => nc64, 
        TRACECLK => OPEN, TRACEDATA(3) => nc156, TRACEDATA(2) => 
        nc25, TRACEDATA(1) => nc142, TRACEDATA(0) => nc78, TX_CLK
         => OPEN, TX_ENF => OPEN, TX_ERRF => OPEN, TXCTL_EN_RIF
         => OPEN, TXD_RIF(3) => nc58, TXD_RIF(2) => nc222, 
        TXD_RIF(1) => nc134, TXD_RIF(0) => nc433, TXDF(7) => 
        nc497, TXDF(6) => nc534, TXDF(5) => nc236, TXDF(4) => 
        nc14, TXDF(3) => nc37, TXDF(2) => nc237, TXDF(1) => nc375, 
        TXDF(0) => nc75, TXEV => OPEN, WDOGTIMEOUT => OPEN, 
        F_ARREADY_HREADYOUT1 => OPEN, F_AWREADY_HREADYOUT0 => 
        OPEN, F_BID(3) => nc278, F_BID(2) => nc392, F_BID(1) => 
        nc496, F_BID(0) => nc55, F_BRESP_HRESP0(1) => nc96, 
        F_BRESP_HRESP0(0) => nc377, F_BVALID => OPEN, 
        F_RDATA_HRDATA01(63) => nc188, F_RDATA_HRDATA01(62) => 
        nc607, F_RDATA_HRDATA01(61) => nc386, 
        F_RDATA_HRDATA01(60) => nc399, F_RDATA_HRDATA01(59) => 
        nc439, F_RDATA_HRDATA01(58) => nc274, 
        F_RDATA_HRDATA01(57) => nc203, F_RDATA_HRDATA01(56) => 
        nc304, F_RDATA_HRDATA01(55) => nc492, 
        F_RDATA_HRDATA01(54) => nc170, F_RDATA_HRDATA01(53) => 
        nc560, F_RDATA_HRDATA01(52) => nc158, 
        F_RDATA_HRDATA01(51) => nc213, F_RDATA_HRDATA01(50) => 
        nc575, F_RDATA_HRDATA01(49) => nc314, 
        F_RDATA_HRDATA01(48) => nc356, F_RDATA_HRDATA01(47) => 
        nc378, F_RDATA_HRDATA01(46) => nc143, 
        F_RDATA_HRDATA01(45) => nc69, F_RDATA_HRDATA01(44) => 
        nc121, F_RDATA_HRDATA01(43) => nc47, F_RDATA_HRDATA01(42)
         => nc127, F_RDATA_HRDATA01(41) => nc381, 
        F_RDATA_HRDATA01(40) => nc235, F_RDATA_HRDATA01(39) => 
        nc192, F_RDATA_HRDATA01(38) => nc509, 
        F_RDATA_HRDATA01(37) => nc229, F_RDATA_HRDATA01(36) => 
        nc448, F_RDATA_HRDATA01(35) => nc484, 
        F_RDATA_HRDATA01(34) => nc519, F_RDATA_HRDATA01(33) => 
        nc568, F_RDATA_HRDATA01(32) => nc477, 
        F_RDATA_HRDATA01(31) => nc19, F_RDATA_HRDATA01(30) => 
        nc351, F_RDATA_HRDATA01(29) => nc260, 
        F_RDATA_HRDATA01(28) => nc232, F_RDATA_HRDATA01(27) => 
        nc372, F_RDATA_HRDATA01(26) => nc476, 
        F_RDATA_HRDATA01(25) => nc106, F_RDATA_HRDATA01(24) => 
        nc454, F_RDATA_HRDATA01(23) => nc20, F_RDATA_HRDATA01(22)
         => nc566, F_RDATA_HRDATA01(21) => nc481, 
        F_RDATA_HRDATA01(20) => nc116, F_RDATA_HRDATA01(19) => 
        nc363, F_RDATA_HRDATA01(18) => nc465, 
        F_RDATA_HRDATA01(17) => nc379, F_RDATA_HRDATA01(16) => 
        nc21, F_RDATA_HRDATA01(15) => nc94, F_RDATA_HRDATA01(14)
         => nc472, F_RDATA_HRDATA01(13) => nc451, 
        F_RDATA_HRDATA01(12) => nc193, F_RDATA_HRDATA01(11) => 
        nc70, F_RDATA_HRDATA01(10) => nc50, F_RDATA_HRDATA01(9)
         => nc67, F_RDATA_HRDATA01(8) => nc540, 
        F_RDATA_HRDATA01(7) => nc563, F_RDATA_HRDATA01(6) => nc71, 
        F_RDATA_HRDATA01(5) => nc223, F_RDATA_HRDATA01(4) => nc51, 
        F_RDATA_HRDATA01(3) => nc324, F_RDATA_HRDATA01(2) => 
        nc172, F_RDATA_HRDATA01(1) => nc498, F_RDATA_HRDATA01(0)
         => nc108, F_RID(3) => nc131, F_RID(2) => nc306, F_RID(1)
         => nc137, F_RID(0) => nc17, F_RLAST => OPEN, 
        F_RRESP_HRESP1(1) => nc118, F_RRESP_HRESP1(0) => nc561, 
        F_RVALID => OPEN, F_WREADY => OPEN, 
        MDDR_FABRIC_PRDATA(15) => nc239, MDDR_FABRIC_PRDATA(14)
         => nc529, MDDR_FABRIC_PRDATA(13) => nc609, 
        MDDR_FABRIC_PRDATA(12) => nc582, MDDR_FABRIC_PRDATA(11)
         => nc548, MDDR_FABRIC_PRDATA(10) => nc316, 
        MDDR_FABRIC_PRDATA(9) => nc240, MDDR_FABRIC_PRDATA(8) => 
        nc99, MDDR_FABRIC_PRDATA(7) => nc88, 
        MDDR_FABRIC_PRDATA(6) => nc480, MDDR_FABRIC_PRDATA(5) => 
        nc164, MDDR_FABRIC_PRDATA(4) => nc463, 
        MDDR_FABRIC_PRDATA(3) => nc546, MDDR_FABRIC_PRDATA(2) => 
        nc552, MDDR_FABRIC_PRDATA(1) => nc301, 
        MDDR_FABRIC_PRDATA(0) => nc564, MDDR_FABRIC_PREADY => 
        OPEN, MDDR_FABRIC_PSLVERR => OPEN, REV_ARADDR(31) => 
        nc126, REV_ARADDR(30) => nc266, REV_ARADDR(29) => nc343, 
        REV_ARADDR(28) => nc445, REV_ARADDR(27) => nc22, 
        REV_ARADDR(26) => nc173, REV_ARADDR(25) => nc267, 
        REV_ARADDR(24) => nc85, REV_ARADDR(23) => nc404, 
        REV_ARADDR(22) => nc450, REV_ARADDR(21) => nc311, 
        REV_ARADDR(20) => nc590, REV_ARADDR(19) => nc414, 
        REV_ARADDR(18) => nc587, REV_ARADDR(17) => nc469, 
        REV_ARADDR(16) => nc478, REV_ARADDR(15) => nc72, 
        REV_ARADDR(14) => nc52, REV_ARADDR(13) => nc543, 
        REV_ARADDR(12) => nc401, REV_ARADDR(11) => nc233, 
        REV_ARADDR(10) => nc334, REV_ARADDR(9) => nc557, 
        REV_ARADDR(8) => nc411, REV_ARADDR(7) => nc598, 
        REV_ARADDR(6) => nc290, REV_ARADDR(5) => nc189, 
        REV_ARADDR(4) => nc265, REV_ARADDR(3) => nc128, 
        REV_ARADDR(2) => nc541, REV_ARADDR(1) => nc97, 
        REV_ARADDR(0) => nc326, REV_ARBURST(1) => nc596, 
        REV_ARBURST(0) => nc539, REV_ARID(3) => nc393, 
        REV_ARID(2) => nc495, REV_ARID(1) => nc159, REV_ARID(0)
         => nc144, REV_ARLEN(3) => nc443, REV_ARLEN(2) => nc262, 
        REV_ARLEN(1) => nc570, REV_ARLEN(0) => nc544, 
        REV_ARLOCK(1) => nc246, REV_ARLOCK(0) => nc136, 
        REV_ARSIZE(1) => nc23, REV_ARSIZE(0) => nc247, 
        REV_AWADDR(31) => nc321, REV_AWADDR(30) => nc593, 
        REV_AWADDR(29) => nc502, REV_AWADDR(28) => nc424, 
        REV_AWADDR(27) => nc512, REV_AWADDR(26) => nc449, 
        REV_AWADDR(25) => nc80, REV_AWADDR(24) => nc400, 
        REV_AWADDR(23) => nc578, REV_AWADDR(22) => nc73, 
        REV_AWADDR(21) => nc81, REV_AWADDR(20) => nc53, 
        REV_AWADDR(19) => nc410, REV_AWADDR(18) => nc270, 
        REV_AWADDR(17) => nc591, REV_AWADDR(16) => nc421, 
        REV_AWADDR(15) => nc576, REV_AWADDR(14) => nc245, 
        REV_AWADDR(13) => nc161, REV_AWADDR(12) => nc373, 
        REV_AWADDR(11) => nc475, REV_AWADDR(10) => nc167, 
        REV_AWADDR(9) => nc281, REV_AWADDR(8) => nc194, 
        REV_AWADDR(7) => nc507, REV_AWADDR(6) => nc185, 
        REV_AWADDR(5) => nc493, REV_AWADDR(4) => nc138, 
        REV_AWADDR(3) => nc269, REV_AWADDR(2) => nc380, 
        REV_AWADDR(1) => nc336, REV_AWADDR(0) => nc517, 
        REV_AWLOCK(1) => nc594, REV_AWLOCK(0) => nc296, 
        REV_AWSIZE(1) => nc297, REV_AWSIZE(0) => nc251, 
        REV_RREADY => OPEN, REV_WID(3) => nc155, REV_WID(2) => 
        nc242, REV_WID(1) => nc573, REV_WID(0) => nc350, 
        REV_WSTRB(7) => nc109, REV_WSTRB(6) => nc499, 
        REV_WSTRB(5) => nc119, REV_WSTRB(4) => nc331, 
        REV_WSTRB(3) => nc38, REV_WSTRB(2) => nc385, REV_WSTRB(1)
         => nc288, REV_WSTRB(0) => nc522, CAN_RXBUS_F2H_SCP => 
        VCC_net_1, CAN_TX_EBL_F2H_SCP => VCC_net_1, 
        CAN_TXBUS_F2H_SCP => VCC_net_1, CLK_BASE => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, COLF => VCC_net_1, CRSF
         => VCC_net_1, F2_DMAREADY(1) => VCC_net_1, 
        F2_DMAREADY(0) => VCC_net_1, F2H_INTERRUPT(15) => 
        GND_net_1, F2H_INTERRUPT(14) => GND_net_1, 
        F2H_INTERRUPT(13) => GND_net_1, F2H_INTERRUPT(12) => 
        GND_net_1, F2H_INTERRUPT(11) => GND_net_1, 
        F2H_INTERRUPT(10) => GND_net_1, F2H_INTERRUPT(9) => 
        GND_net_1, F2H_INTERRUPT(8) => GND_net_1, 
        F2H_INTERRUPT(7) => GND_net_1, F2H_INTERRUPT(6) => 
        GND_net_1, F2H_INTERRUPT(5) => GND_net_1, 
        F2H_INTERRUPT(4) => GND_net_1, F2H_INTERRUPT(3) => 
        GND_net_1, F2H_INTERRUPT(2) => GND_net_1, 
        F2H_INTERRUPT(1) => GND_net_1, F2H_INTERRUPT(0) => 
        AND2_0_Y, F2HCALIB => VCC_net_1, F_DMAREADY(1) => 
        VCC_net_1, F_DMAREADY(0) => VCC_net_1, F_FM0_ADDR(31) => 
        Fabric_Master1_0_BIF_1_HADDR(31), F_FM0_ADDR(30) => 
        Fabric_Master1_0_BIF_1_HADDR(30), F_FM0_ADDR(29) => 
        Fabric_Master1_0_BIF_1_HADDR(29), F_FM0_ADDR(28) => 
        Fabric_Master1_0_BIF_1_HADDR(28), F_FM0_ADDR(27) => 
        Fabric_Master1_0_BIF_1_HADDR(27), F_FM0_ADDR(26) => 
        Fabric_Master1_0_BIF_1_HADDR(26), F_FM0_ADDR(25) => 
        Fabric_Master1_0_BIF_1_HADDR(25), F_FM0_ADDR(24) => 
        Fabric_Master1_0_BIF_1_HADDR(24), F_FM0_ADDR(23) => 
        Fabric_Master1_0_BIF_1_HADDR(23), F_FM0_ADDR(22) => 
        Fabric_Master1_0_BIF_1_HADDR(22), F_FM0_ADDR(21) => 
        Fabric_Master1_0_BIF_1_HADDR(21), F_FM0_ADDR(20) => 
        Fabric_Master1_0_BIF_1_HADDR(20), F_FM0_ADDR(19) => 
        Fabric_Master1_0_BIF_1_HADDR(19), F_FM0_ADDR(18) => 
        Fabric_Master1_0_BIF_1_HADDR(18), F_FM0_ADDR(17) => 
        Fabric_Master1_0_BIF_1_HADDR(17), F_FM0_ADDR(16) => 
        Fabric_Master1_0_BIF_1_HADDR(16), F_FM0_ADDR(15) => 
        Fabric_Master1_0_BIF_1_HADDR(15), F_FM0_ADDR(14) => 
        Fabric_Master1_0_BIF_1_HADDR(14), F_FM0_ADDR(13) => 
        Fabric_Master1_0_BIF_1_HADDR(13), F_FM0_ADDR(12) => 
        Fabric_Master1_0_BIF_1_HADDR(12), F_FM0_ADDR(11) => 
        Fabric_Master1_0_BIF_1_HADDR(11), F_FM0_ADDR(10) => 
        Fabric_Master1_0_BIF_1_HADDR(10), F_FM0_ADDR(9) => 
        Fabric_Master1_0_BIF_1_HADDR(9), F_FM0_ADDR(8) => 
        Fabric_Master1_0_BIF_1_HADDR(8), F_FM0_ADDR(7) => 
        Fabric_Master1_0_BIF_1_HADDR(7), F_FM0_ADDR(6) => 
        Fabric_Master1_0_BIF_1_HADDR(6), F_FM0_ADDR(5) => 
        Fabric_Master1_0_BIF_1_HADDR(5), F_FM0_ADDR(4) => 
        Fabric_Master1_0_BIF_1_HADDR(4), F_FM0_ADDR(3) => 
        Fabric_Master1_0_BIF_1_HADDR(3), F_FM0_ADDR(2) => 
        Fabric_Master1_0_BIF_1_HADDR(2), F_FM0_ADDR(1) => 
        Fabric_Master1_0_BIF_1_HADDR(1), F_FM0_ADDR(0) => 
        Fabric_Master1_0_BIF_1_HADDR(0), F_FM0_ENABLE => 
        GND_net_1, F_FM0_MASTLOCK => GND_net_1, F_FM0_READY => 
        VCC_net_1, F_FM0_SEL => Fabric_Master1_0_BIF_1_HSELx, 
        F_FM0_SIZE(1) => Fabric_Master1_0_BIF_1_HSIZE(1), 
        F_FM0_SIZE(0) => Fabric_Master1_0_BIF_1_HSIZE(0), 
        F_FM0_TRANS1 => Fabric_Master1_0_BIF_1_HTRANS(1), 
        F_FM0_WDATA(31) => Fabric_Master1_0_BIF_1_HWDATA(31), 
        F_FM0_WDATA(30) => Fabric_Master1_0_BIF_1_HWDATA(30), 
        F_FM0_WDATA(29) => Fabric_Master1_0_BIF_1_HWDATA(29), 
        F_FM0_WDATA(28) => Fabric_Master1_0_BIF_1_HWDATA(28), 
        F_FM0_WDATA(27) => Fabric_Master1_0_BIF_1_HWDATA(27), 
        F_FM0_WDATA(26) => Fabric_Master1_0_BIF_1_HWDATA(26), 
        F_FM0_WDATA(25) => Fabric_Master1_0_BIF_1_HWDATA(25), 
        F_FM0_WDATA(24) => Fabric_Master1_0_BIF_1_HWDATA(24), 
        F_FM0_WDATA(23) => Fabric_Master1_0_BIF_1_HWDATA(23), 
        F_FM0_WDATA(22) => Fabric_Master1_0_BIF_1_HWDATA(22), 
        F_FM0_WDATA(21) => Fabric_Master1_0_BIF_1_HWDATA(21), 
        F_FM0_WDATA(20) => Fabric_Master1_0_BIF_1_HWDATA(20), 
        F_FM0_WDATA(19) => Fabric_Master1_0_BIF_1_HWDATA(19), 
        F_FM0_WDATA(18) => Fabric_Master1_0_BIF_1_HWDATA(18), 
        F_FM0_WDATA(17) => Fabric_Master1_0_BIF_1_HWDATA(17), 
        F_FM0_WDATA(16) => Fabric_Master1_0_BIF_1_HWDATA(16), 
        F_FM0_WDATA(15) => Fabric_Master1_0_BIF_1_HWDATA(15), 
        F_FM0_WDATA(14) => Fabric_Master1_0_BIF_1_HWDATA(14), 
        F_FM0_WDATA(13) => Fabric_Master1_0_BIF_1_HWDATA(13), 
        F_FM0_WDATA(12) => Fabric_Master1_0_BIF_1_HWDATA(12), 
        F_FM0_WDATA(11) => Fabric_Master1_0_BIF_1_HWDATA(11), 
        F_FM0_WDATA(10) => Fabric_Master1_0_BIF_1_HWDATA(10), 
        F_FM0_WDATA(9) => Fabric_Master1_0_BIF_1_HWDATA(9), 
        F_FM0_WDATA(8) => Fabric_Master1_0_BIF_1_HWDATA(8), 
        F_FM0_WDATA(7) => Fabric_Master1_0_BIF_1_HWDATA(7), 
        F_FM0_WDATA(6) => Fabric_Master1_0_BIF_1_HWDATA(6), 
        F_FM0_WDATA(5) => Fabric_Master1_0_BIF_1_HWDATA(5), 
        F_FM0_WDATA(4) => Fabric_Master1_0_BIF_1_HWDATA(4), 
        F_FM0_WDATA(3) => Fabric_Master1_0_BIF_1_HWDATA(3), 
        F_FM0_WDATA(2) => Fabric_Master1_0_BIF_1_HWDATA(2), 
        F_FM0_WDATA(1) => Fabric_Master1_0_BIF_1_HWDATA(1), 
        F_FM0_WDATA(0) => Fabric_Master1_0_BIF_1_HWDATA(0), 
        F_FM0_WRITE => Fabric_Master1_0_BIF_1_HWRITE, 
        F_FM1_ADDR(31) => Fabric_Master2_0_BIF_1_HADDR(31), 
        F_FM1_ADDR(30) => Fabric_Master2_0_BIF_1_HADDR(30), 
        F_FM1_ADDR(29) => Fabric_Master2_0_BIF_1_HADDR(29), 
        F_FM1_ADDR(28) => Fabric_Master2_0_BIF_1_HADDR(28), 
        F_FM1_ADDR(27) => Fabric_Master2_0_BIF_1_HADDR(27), 
        F_FM1_ADDR(26) => Fabric_Master2_0_BIF_1_HADDR(26), 
        F_FM1_ADDR(25) => Fabric_Master2_0_BIF_1_HADDR(25), 
        F_FM1_ADDR(24) => Fabric_Master2_0_BIF_1_HADDR(24), 
        F_FM1_ADDR(23) => Fabric_Master2_0_BIF_1_HADDR(23), 
        F_FM1_ADDR(22) => Fabric_Master2_0_BIF_1_HADDR(22), 
        F_FM1_ADDR(21) => Fabric_Master2_0_BIF_1_HADDR(21), 
        F_FM1_ADDR(20) => Fabric_Master2_0_BIF_1_HADDR(20), 
        F_FM1_ADDR(19) => Fabric_Master2_0_BIF_1_HADDR(19), 
        F_FM1_ADDR(18) => Fabric_Master2_0_BIF_1_HADDR(18), 
        F_FM1_ADDR(17) => Fabric_Master2_0_BIF_1_HADDR(17), 
        F_FM1_ADDR(16) => Fabric_Master2_0_BIF_1_HADDR(16), 
        F_FM1_ADDR(15) => Fabric_Master2_0_BIF_1_HADDR(15), 
        F_FM1_ADDR(14) => Fabric_Master2_0_BIF_1_HADDR(14), 
        F_FM1_ADDR(13) => Fabric_Master2_0_BIF_1_HADDR(13), 
        F_FM1_ADDR(12) => Fabric_Master2_0_BIF_1_HADDR(12), 
        F_FM1_ADDR(11) => Fabric_Master2_0_BIF_1_HADDR(11), 
        F_FM1_ADDR(10) => Fabric_Master2_0_BIF_1_HADDR(10), 
        F_FM1_ADDR(9) => Fabric_Master2_0_BIF_1_HADDR(9), 
        F_FM1_ADDR(8) => Fabric_Master2_0_BIF_1_HADDR(8), 
        F_FM1_ADDR(7) => Fabric_Master2_0_BIF_1_HADDR(7), 
        F_FM1_ADDR(6) => Fabric_Master2_0_BIF_1_HADDR(6), 
        F_FM1_ADDR(5) => Fabric_Master2_0_BIF_1_HADDR(5), 
        F_FM1_ADDR(4) => Fabric_Master2_0_BIF_1_HADDR(4), 
        F_FM1_ADDR(3) => Fabric_Master2_0_BIF_1_HADDR(3), 
        F_FM1_ADDR(2) => Fabric_Master2_0_BIF_1_HADDR(2), 
        F_FM1_ADDR(1) => Fabric_Master2_0_BIF_1_HADDR(1), 
        F_FM1_ADDR(0) => Fabric_Master2_0_BIF_1_HADDR(0), 
        F_FM1_ENABLE => GND_net_1, F_FM1_MASTLOCK => GND_net_1, 
        F_FM1_READY => VCC_net_1, F_FM1_SEL => 
        Fabric_Master2_0_BIF_1_HSELx, F_FM1_SIZE(1) => 
        Fabric_Master2_0_BIF_1_HSIZE(1), F_FM1_SIZE(0) => 
        Fabric_Master2_0_BIF_1_HSIZE(0), F_FM1_TRANS1 => 
        Fabric_Master2_0_BIF_1_HTRANS(1), F_FM1_WDATA(31) => 
        Fabric_Master2_0_BIF_1_HWDATA(31), F_FM1_WDATA(30) => 
        Fabric_Master2_0_BIF_1_HWDATA(30), F_FM1_WDATA(29) => 
        Fabric_Master2_0_BIF_1_HWDATA(29), F_FM1_WDATA(28) => 
        Fabric_Master2_0_BIF_1_HWDATA(28), F_FM1_WDATA(27) => 
        Fabric_Master2_0_BIF_1_HWDATA(27), F_FM1_WDATA(26) => 
        Fabric_Master2_0_BIF_1_HWDATA(26), F_FM1_WDATA(25) => 
        Fabric_Master2_0_BIF_1_HWDATA(25), F_FM1_WDATA(24) => 
        Fabric_Master2_0_BIF_1_HWDATA(24), F_FM1_WDATA(23) => 
        Fabric_Master2_0_BIF_1_HWDATA(23), F_FM1_WDATA(22) => 
        Fabric_Master2_0_BIF_1_HWDATA(22), F_FM1_WDATA(21) => 
        Fabric_Master2_0_BIF_1_HWDATA(21), F_FM1_WDATA(20) => 
        Fabric_Master2_0_BIF_1_HWDATA(20), F_FM1_WDATA(19) => 
        Fabric_Master2_0_BIF_1_HWDATA(19), F_FM1_WDATA(18) => 
        Fabric_Master2_0_BIF_1_HWDATA(18), F_FM1_WDATA(17) => 
        Fabric_Master2_0_BIF_1_HWDATA(17), F_FM1_WDATA(16) => 
        Fabric_Master2_0_BIF_1_HWDATA(16), F_FM1_WDATA(15) => 
        Fabric_Master2_0_BIF_1_HWDATA(15), F_FM1_WDATA(14) => 
        Fabric_Master2_0_BIF_1_HWDATA(14), F_FM1_WDATA(13) => 
        Fabric_Master2_0_BIF_1_HWDATA(13), F_FM1_WDATA(12) => 
        Fabric_Master2_0_BIF_1_HWDATA(12), F_FM1_WDATA(11) => 
        Fabric_Master2_0_BIF_1_HWDATA(11), F_FM1_WDATA(10) => 
        Fabric_Master2_0_BIF_1_HWDATA(10), F_FM1_WDATA(9) => 
        Fabric_Master2_0_BIF_1_HWDATA(9), F_FM1_WDATA(8) => 
        Fabric_Master2_0_BIF_1_HWDATA(8), F_FM1_WDATA(7) => 
        Fabric_Master2_0_BIF_1_HWDATA(7), F_FM1_WDATA(6) => 
        Fabric_Master2_0_BIF_1_HWDATA(6), F_FM1_WDATA(5) => 
        Fabric_Master2_0_BIF_1_HWDATA(5), F_FM1_WDATA(4) => 
        Fabric_Master2_0_BIF_1_HWDATA(4), F_FM1_WDATA(3) => 
        Fabric_Master2_0_BIF_1_HWDATA(3), F_FM1_WDATA(2) => 
        Fabric_Master2_0_BIF_1_HWDATA(2), F_FM1_WDATA(1) => 
        Fabric_Master2_0_BIF_1_HWDATA(1), F_FM1_WDATA(0) => 
        Fabric_Master2_0_BIF_1_HWDATA(0), F_FM1_WRITE => 
        Fabric_Master2_0_BIF_1_HWRITE, F_HM0_RDATA(31) => 
        GND_net_1, F_HM0_RDATA(30) => GND_net_1, F_HM0_RDATA(29)
         => GND_net_1, F_HM0_RDATA(28) => GND_net_1, 
        F_HM0_RDATA(27) => GND_net_1, F_HM0_RDATA(26) => 
        GND_net_1, F_HM0_RDATA(25) => GND_net_1, F_HM0_RDATA(24)
         => GND_net_1, F_HM0_RDATA(23) => GND_net_1, 
        F_HM0_RDATA(22) => GND_net_1, F_HM0_RDATA(21) => 
        GND_net_1, F_HM0_RDATA(20) => GND_net_1, F_HM0_RDATA(19)
         => GND_net_1, F_HM0_RDATA(18) => GND_net_1, 
        F_HM0_RDATA(17) => GND_net_1, F_HM0_RDATA(16) => 
        GND_net_1, F_HM0_RDATA(15) => GND_net_1, F_HM0_RDATA(14)
         => GND_net_1, F_HM0_RDATA(13) => GND_net_1, 
        F_HM0_RDATA(12) => GND_net_1, F_HM0_RDATA(11) => 
        GND_net_1, F_HM0_RDATA(10) => GND_net_1, F_HM0_RDATA(9)
         => GND_net_1, F_HM0_RDATA(8) => GND_net_1, 
        F_HM0_RDATA(7) => GND_net_1, F_HM0_RDATA(6) => GND_net_1, 
        F_HM0_RDATA(5) => GND_net_1, F_HM0_RDATA(4) => GND_net_1, 
        F_HM0_RDATA(3) => GND_net_1, F_HM0_RDATA(2) => GND_net_1, 
        F_HM0_RDATA(1) => GND_net_1, F_HM0_RDATA(0) => GND_net_1, 
        F_HM0_READY => VCC_net_1, F_HM0_RESP => GND_net_1, 
        F_HM1_RDATA(31) => GND_net_1, F_HM1_RDATA(30) => 
        GND_net_1, F_HM1_RDATA(29) => GND_net_1, F_HM1_RDATA(28)
         => GND_net_1, F_HM1_RDATA(27) => GND_net_1, 
        F_HM1_RDATA(26) => GND_net_1, F_HM1_RDATA(25) => 
        GND_net_1, F_HM1_RDATA(24) => GND_net_1, F_HM1_RDATA(23)
         => GND_net_1, F_HM1_RDATA(22) => GND_net_1, 
        F_HM1_RDATA(21) => GND_net_1, F_HM1_RDATA(20) => 
        GND_net_1, F_HM1_RDATA(19) => GND_net_1, F_HM1_RDATA(18)
         => GND_net_1, F_HM1_RDATA(17) => GND_net_1, 
        F_HM1_RDATA(16) => GND_net_1, F_HM1_RDATA(15) => 
        GND_net_1, F_HM1_RDATA(14) => GND_net_1, F_HM1_RDATA(13)
         => GND_net_1, F_HM1_RDATA(12) => GND_net_1, 
        F_HM1_RDATA(11) => GND_net_1, F_HM1_RDATA(10) => 
        GND_net_1, F_HM1_RDATA(9) => GND_net_1, F_HM1_RDATA(8)
         => GND_net_1, F_HM1_RDATA(7) => GND_net_1, 
        F_HM1_RDATA(6) => GND_net_1, F_HM1_RDATA(5) => GND_net_1, 
        F_HM1_RDATA(4) => GND_net_1, F_HM1_RDATA(3) => GND_net_1, 
        F_HM1_RDATA(2) => GND_net_1, F_HM1_RDATA(1) => GND_net_1, 
        F_HM1_RDATA(0) => GND_net_1, F_HM1_READY => VCC_net_1, 
        F_HM1_RESP => GND_net_1, FAB_AVALID => VCC_net_1, 
        FAB_HOSTDISCON => VCC_net_1, FAB_IDDIG => VCC_net_1, 
        FAB_LINESTATE(1) => VCC_net_1, FAB_LINESTATE(0) => 
        VCC_net_1, FAB_M3_RESET_N => VCC_net_1, FAB_PLL_LOCK => 
        FIC_1_LOCK, FAB_RXACTIVE => VCC_net_1, FAB_RXERROR => 
        VCC_net_1, FAB_RXVALID => VCC_net_1, FAB_RXVALIDH => 
        GND_net_1, FAB_SESSEND => VCC_net_1, FAB_TXREADY => 
        VCC_net_1, FAB_VBUSVALID => VCC_net_1, FAB_VSTATUS(7) => 
        VCC_net_1, FAB_VSTATUS(6) => VCC_net_1, FAB_VSTATUS(5)
         => VCC_net_1, FAB_VSTATUS(4) => VCC_net_1, 
        FAB_VSTATUS(3) => VCC_net_1, FAB_VSTATUS(2) => VCC_net_1, 
        FAB_VSTATUS(1) => VCC_net_1, FAB_VSTATUS(0) => VCC_net_1, 
        FAB_XDATAIN(7) => VCC_net_1, FAB_XDATAIN(6) => VCC_net_1, 
        FAB_XDATAIN(5) => VCC_net_1, FAB_XDATAIN(4) => VCC_net_1, 
        FAB_XDATAIN(3) => VCC_net_1, FAB_XDATAIN(2) => VCC_net_1, 
        FAB_XDATAIN(1) => VCC_net_1, FAB_XDATAIN(0) => VCC_net_1, 
        GTX_CLKPF => VCC_net_1, I2C0_BCLK => VCC_net_1, 
        I2C0_SCL_F2H_SCP => VCC_net_1, I2C0_SDA_F2H_SCP => 
        VCC_net_1, I2C1_BCLK => VCC_net_1, I2C1_SCL_F2H_SCP => 
        VCC_net_1, I2C1_SDA_F2H_SCP => VCC_net_1, MDIF => 
        VCC_net_1, MGPIO0A_F2H_GPIN => VCC_net_1, 
        MGPIO10A_F2H_GPIN => VCC_net_1, MGPIO11A_F2H_GPIN => 
        VCC_net_1, MGPIO11B_F2H_GPIN => VCC_net_1, 
        MGPIO12A_F2H_GPIN => VCC_net_1, MGPIO13A_F2H_GPIN => 
        VCC_net_1, MGPIO14A_F2H_GPIN => VCC_net_1, 
        MGPIO15A_F2H_GPIN => VCC_net_1, MGPIO16A_F2H_GPIN => 
        VCC_net_1, MGPIO17B_F2H_GPIN => VCC_net_1, 
        MGPIO18B_F2H_GPIN => VCC_net_1, MGPIO19B_F2H_GPIN => 
        VCC_net_1, MGPIO1A_F2H_GPIN => VCC_net_1, 
        MGPIO20B_F2H_GPIN => VCC_net_1, MGPIO21B_F2H_GPIN => 
        VCC_net_1, MGPIO22B_F2H_GPIN => VCC_net_1, 
        MGPIO24B_F2H_GPIN => VCC_net_1, MGPIO25B_F2H_GPIN => 
        VCC_net_1, MGPIO26B_F2H_GPIN => VCC_net_1, 
        MGPIO27B_F2H_GPIN => VCC_net_1, MGPIO28B_F2H_GPIN => 
        VCC_net_1, MGPIO29B_F2H_GPIN => VCC_net_1, 
        MGPIO2A_F2H_GPIN => VCC_net_1, MGPIO30B_F2H_GPIN => 
        VCC_net_1, MGPIO31B_F2H_GPIN => VCC_net_1, 
        MGPIO3A_F2H_GPIN => VCC_net_1, MGPIO4A_F2H_GPIN => 
        VCC_net_1, MGPIO5A_F2H_GPIN => VCC_net_1, 
        MGPIO6A_F2H_GPIN => VCC_net_1, MGPIO7A_F2H_GPIN => 
        VCC_net_1, MGPIO8A_F2H_GPIN => VCC_net_1, 
        MGPIO9A_F2H_GPIN => VCC_net_1, MMUART0_CTS_F2H_SCP => 
        VCC_net_1, MMUART0_DCD_F2H_SCP => VCC_net_1, 
        MMUART0_DSR_F2H_SCP => VCC_net_1, MMUART0_DTR_F2H_SCP => 
        VCC_net_1, MMUART0_RI_F2H_SCP => VCC_net_1, 
        MMUART0_RTS_F2H_SCP => VCC_net_1, MMUART0_RXD_F2H_SCP => 
        VCC_net_1, MMUART0_SCK_F2H_SCP => VCC_net_1, 
        MMUART0_TXD_F2H_SCP => VCC_net_1, MMUART1_CTS_F2H_SCP => 
        VCC_net_1, MMUART1_DCD_F2H_SCP => VCC_net_1, 
        MMUART1_DSR_F2H_SCP => VCC_net_1, MMUART1_RI_F2H_SCP => 
        VCC_net_1, MMUART1_RTS_F2H_SCP => VCC_net_1, 
        MMUART1_RXD_F2H_SCP => VCC_net_1, MMUART1_SCK_F2H_SCP => 
        VCC_net_1, MMUART1_TXD_F2H_SCP => VCC_net_1, 
        PER2_FABRIC_PRDATA(31) => GND_net_1, 
        PER2_FABRIC_PRDATA(30) => GND_net_1, 
        PER2_FABRIC_PRDATA(29) => GND_net_1, 
        PER2_FABRIC_PRDATA(28) => GND_net_1, 
        PER2_FABRIC_PRDATA(27) => GND_net_1, 
        PER2_FABRIC_PRDATA(26) => GND_net_1, 
        PER2_FABRIC_PRDATA(25) => GND_net_1, 
        PER2_FABRIC_PRDATA(24) => GND_net_1, 
        PER2_FABRIC_PRDATA(23) => GND_net_1, 
        PER2_FABRIC_PRDATA(22) => GND_net_1, 
        PER2_FABRIC_PRDATA(21) => GND_net_1, 
        PER2_FABRIC_PRDATA(20) => GND_net_1, 
        PER2_FABRIC_PRDATA(19) => GND_net_1, 
        PER2_FABRIC_PRDATA(18) => GND_net_1, 
        PER2_FABRIC_PRDATA(17) => GND_net_1, 
        PER2_FABRIC_PRDATA(16) => GND_net_1, 
        PER2_FABRIC_PRDATA(15) => GND_net_1, 
        PER2_FABRIC_PRDATA(14) => GND_net_1, 
        PER2_FABRIC_PRDATA(13) => GND_net_1, 
        PER2_FABRIC_PRDATA(12) => GND_net_1, 
        PER2_FABRIC_PRDATA(11) => GND_net_1, 
        PER2_FABRIC_PRDATA(10) => GND_net_1, 
        PER2_FABRIC_PRDATA(9) => GND_net_1, PER2_FABRIC_PRDATA(8)
         => GND_net_1, PER2_FABRIC_PRDATA(7) => GND_net_1, 
        PER2_FABRIC_PRDATA(6) => GND_net_1, PER2_FABRIC_PRDATA(5)
         => GND_net_1, PER2_FABRIC_PRDATA(4) => GND_net_1, 
        PER2_FABRIC_PRDATA(3) => GND_net_1, PER2_FABRIC_PRDATA(2)
         => GND_net_1, PER2_FABRIC_PRDATA(1) => GND_net_1, 
        PER2_FABRIC_PRDATA(0) => GND_net_1, PER2_FABRIC_PREADY
         => VCC_net_1, PER2_FABRIC_PSLVERR => GND_net_1, RCGF(9)
         => VCC_net_1, RCGF(8) => VCC_net_1, RCGF(7) => VCC_net_1, 
        RCGF(6) => VCC_net_1, RCGF(5) => VCC_net_1, RCGF(4) => 
        VCC_net_1, RCGF(3) => VCC_net_1, RCGF(2) => VCC_net_1, 
        RCGF(1) => VCC_net_1, RCGF(0) => VCC_net_1, RX_CLKPF => 
        VCC_net_1, RX_DVF => VCC_net_1, RX_ERRF => VCC_net_1, 
        RX_EV => VCC_net_1, RXDF(7) => VCC_net_1, RXDF(6) => 
        VCC_net_1, RXDF(5) => VCC_net_1, RXDF(4) => VCC_net_1, 
        RXDF(3) => VCC_net_1, RXDF(2) => VCC_net_1, RXDF(1) => 
        VCC_net_1, RXDF(0) => VCC_net_1, SLEEPHOLDREQ => 
        GND_net_1, SMBALERT_NI0 => VCC_net_1, SMBALERT_NI1 => 
        VCC_net_1, SMBSUS_NI0 => VCC_net_1, SMBSUS_NI1 => 
        VCC_net_1, SPI0_CLK_IN => VCC_net_1, SPI0_SDI_F2H_SCP => 
        VCC_net_1, SPI0_SDO_F2H_SCP => VCC_net_1, 
        SPI0_SS0_F2H_SCP => VCC_net_1, SPI0_SS1_F2H_SCP => 
        VCC_net_1, SPI0_SS2_F2H_SCP => VCC_net_1, 
        SPI0_SS3_F2H_SCP => VCC_net_1, SPI1_CLK_IN => VCC_net_1, 
        SPI1_SDI_F2H_SCP => VCC_net_1, SPI1_SDO_F2H_SCP => 
        VCC_net_1, SPI1_SS0_F2H_SCP => VCC_net_1, 
        SPI1_SS1_F2H_SCP => VCC_net_1, SPI1_SS2_F2H_SCP => 
        VCC_net_1, SPI1_SS3_F2H_SCP => VCC_net_1, TX_CLKPF => 
        VCC_net_1, USER_MSS_GPIO_RESET_N => VCC_net_1, 
        USER_MSS_RESET_N => VCC_net_1, XCLK_FAB => VCC_net_1, 
        CLK_MDDR_APB => VCC_net_1, F_ARADDR_HADDR1(31) => 
        VCC_net_1, F_ARADDR_HADDR1(30) => VCC_net_1, 
        F_ARADDR_HADDR1(29) => VCC_net_1, F_ARADDR_HADDR1(28) => 
        VCC_net_1, F_ARADDR_HADDR1(27) => VCC_net_1, 
        F_ARADDR_HADDR1(26) => VCC_net_1, F_ARADDR_HADDR1(25) => 
        VCC_net_1, F_ARADDR_HADDR1(24) => VCC_net_1, 
        F_ARADDR_HADDR1(23) => VCC_net_1, F_ARADDR_HADDR1(22) => 
        VCC_net_1, F_ARADDR_HADDR1(21) => VCC_net_1, 
        F_ARADDR_HADDR1(20) => VCC_net_1, F_ARADDR_HADDR1(19) => 
        VCC_net_1, F_ARADDR_HADDR1(18) => VCC_net_1, 
        F_ARADDR_HADDR1(17) => VCC_net_1, F_ARADDR_HADDR1(16) => 
        VCC_net_1, F_ARADDR_HADDR1(15) => VCC_net_1, 
        F_ARADDR_HADDR1(14) => VCC_net_1, F_ARADDR_HADDR1(13) => 
        VCC_net_1, F_ARADDR_HADDR1(12) => VCC_net_1, 
        F_ARADDR_HADDR1(11) => VCC_net_1, F_ARADDR_HADDR1(10) => 
        VCC_net_1, F_ARADDR_HADDR1(9) => VCC_net_1, 
        F_ARADDR_HADDR1(8) => VCC_net_1, F_ARADDR_HADDR1(7) => 
        VCC_net_1, F_ARADDR_HADDR1(6) => VCC_net_1, 
        F_ARADDR_HADDR1(5) => VCC_net_1, F_ARADDR_HADDR1(4) => 
        VCC_net_1, F_ARADDR_HADDR1(3) => VCC_net_1, 
        F_ARADDR_HADDR1(2) => VCC_net_1, F_ARADDR_HADDR1(1) => 
        VCC_net_1, F_ARADDR_HADDR1(0) => VCC_net_1, 
        F_ARBURST_HTRANS1(1) => GND_net_1, F_ARBURST_HTRANS1(0)
         => GND_net_1, F_ARID_HSEL1(3) => GND_net_1, 
        F_ARID_HSEL1(2) => GND_net_1, F_ARID_HSEL1(1) => 
        GND_net_1, F_ARID_HSEL1(0) => GND_net_1, 
        F_ARLEN_HBURST1(3) => GND_net_1, F_ARLEN_HBURST1(2) => 
        GND_net_1, F_ARLEN_HBURST1(1) => GND_net_1, 
        F_ARLEN_HBURST1(0) => GND_net_1, F_ARLOCK_HMASTLOCK1(1)
         => GND_net_1, F_ARLOCK_HMASTLOCK1(0) => GND_net_1, 
        F_ARSIZE_HSIZE1(1) => GND_net_1, F_ARSIZE_HSIZE1(0) => 
        GND_net_1, F_ARVALID_HWRITE1 => GND_net_1, 
        F_AWADDR_HADDR0(31) => VCC_net_1, F_AWADDR_HADDR0(30) => 
        VCC_net_1, F_AWADDR_HADDR0(29) => VCC_net_1, 
        F_AWADDR_HADDR0(28) => VCC_net_1, F_AWADDR_HADDR0(27) => 
        VCC_net_1, F_AWADDR_HADDR0(26) => VCC_net_1, 
        F_AWADDR_HADDR0(25) => VCC_net_1, F_AWADDR_HADDR0(24) => 
        VCC_net_1, F_AWADDR_HADDR0(23) => VCC_net_1, 
        F_AWADDR_HADDR0(22) => VCC_net_1, F_AWADDR_HADDR0(21) => 
        VCC_net_1, F_AWADDR_HADDR0(20) => VCC_net_1, 
        F_AWADDR_HADDR0(19) => VCC_net_1, F_AWADDR_HADDR0(18) => 
        VCC_net_1, F_AWADDR_HADDR0(17) => VCC_net_1, 
        F_AWADDR_HADDR0(16) => VCC_net_1, F_AWADDR_HADDR0(15) => 
        VCC_net_1, F_AWADDR_HADDR0(14) => VCC_net_1, 
        F_AWADDR_HADDR0(13) => VCC_net_1, F_AWADDR_HADDR0(12) => 
        VCC_net_1, F_AWADDR_HADDR0(11) => VCC_net_1, 
        F_AWADDR_HADDR0(10) => VCC_net_1, F_AWADDR_HADDR0(9) => 
        VCC_net_1, F_AWADDR_HADDR0(8) => VCC_net_1, 
        F_AWADDR_HADDR0(7) => VCC_net_1, F_AWADDR_HADDR0(6) => 
        VCC_net_1, F_AWADDR_HADDR0(5) => VCC_net_1, 
        F_AWADDR_HADDR0(4) => VCC_net_1, F_AWADDR_HADDR0(3) => 
        VCC_net_1, F_AWADDR_HADDR0(2) => VCC_net_1, 
        F_AWADDR_HADDR0(1) => VCC_net_1, F_AWADDR_HADDR0(0) => 
        VCC_net_1, F_AWBURST_HTRANS0(1) => GND_net_1, 
        F_AWBURST_HTRANS0(0) => GND_net_1, F_AWID_HSEL0(3) => 
        GND_net_1, F_AWID_HSEL0(2) => GND_net_1, F_AWID_HSEL0(1)
         => GND_net_1, F_AWID_HSEL0(0) => GND_net_1, 
        F_AWLEN_HBURST0(3) => GND_net_1, F_AWLEN_HBURST0(2) => 
        GND_net_1, F_AWLEN_HBURST0(1) => GND_net_1, 
        F_AWLEN_HBURST0(0) => GND_net_1, F_AWLOCK_HMASTLOCK0(1)
         => GND_net_1, F_AWLOCK_HMASTLOCK0(0) => GND_net_1, 
        F_AWSIZE_HSIZE0(1) => GND_net_1, F_AWSIZE_HSIZE0(0) => 
        GND_net_1, F_AWVALID_HWRITE0 => GND_net_1, F_BREADY => 
        GND_net_1, F_RMW_AXI => GND_net_1, F_RREADY => GND_net_1, 
        F_WDATA_HWDATA01(63) => VCC_net_1, F_WDATA_HWDATA01(62)
         => VCC_net_1, F_WDATA_HWDATA01(61) => VCC_net_1, 
        F_WDATA_HWDATA01(60) => VCC_net_1, F_WDATA_HWDATA01(59)
         => VCC_net_1, F_WDATA_HWDATA01(58) => VCC_net_1, 
        F_WDATA_HWDATA01(57) => VCC_net_1, F_WDATA_HWDATA01(56)
         => VCC_net_1, F_WDATA_HWDATA01(55) => VCC_net_1, 
        F_WDATA_HWDATA01(54) => VCC_net_1, F_WDATA_HWDATA01(53)
         => VCC_net_1, F_WDATA_HWDATA01(52) => VCC_net_1, 
        F_WDATA_HWDATA01(51) => VCC_net_1, F_WDATA_HWDATA01(50)
         => VCC_net_1, F_WDATA_HWDATA01(49) => VCC_net_1, 
        F_WDATA_HWDATA01(48) => VCC_net_1, F_WDATA_HWDATA01(47)
         => VCC_net_1, F_WDATA_HWDATA01(46) => VCC_net_1, 
        F_WDATA_HWDATA01(45) => VCC_net_1, F_WDATA_HWDATA01(44)
         => VCC_net_1, F_WDATA_HWDATA01(43) => VCC_net_1, 
        F_WDATA_HWDATA01(42) => VCC_net_1, F_WDATA_HWDATA01(41)
         => VCC_net_1, F_WDATA_HWDATA01(40) => VCC_net_1, 
        F_WDATA_HWDATA01(39) => VCC_net_1, F_WDATA_HWDATA01(38)
         => VCC_net_1, F_WDATA_HWDATA01(37) => VCC_net_1, 
        F_WDATA_HWDATA01(36) => VCC_net_1, F_WDATA_HWDATA01(35)
         => VCC_net_1, F_WDATA_HWDATA01(34) => VCC_net_1, 
        F_WDATA_HWDATA01(33) => VCC_net_1, F_WDATA_HWDATA01(32)
         => VCC_net_1, F_WDATA_HWDATA01(31) => VCC_net_1, 
        F_WDATA_HWDATA01(30) => VCC_net_1, F_WDATA_HWDATA01(29)
         => VCC_net_1, F_WDATA_HWDATA01(28) => VCC_net_1, 
        F_WDATA_HWDATA01(27) => VCC_net_1, F_WDATA_HWDATA01(26)
         => VCC_net_1, F_WDATA_HWDATA01(25) => VCC_net_1, 
        F_WDATA_HWDATA01(24) => VCC_net_1, F_WDATA_HWDATA01(23)
         => VCC_net_1, F_WDATA_HWDATA01(22) => VCC_net_1, 
        F_WDATA_HWDATA01(21) => VCC_net_1, F_WDATA_HWDATA01(20)
         => VCC_net_1, F_WDATA_HWDATA01(19) => VCC_net_1, 
        F_WDATA_HWDATA01(18) => VCC_net_1, F_WDATA_HWDATA01(17)
         => VCC_net_1, F_WDATA_HWDATA01(16) => VCC_net_1, 
        F_WDATA_HWDATA01(15) => VCC_net_1, F_WDATA_HWDATA01(14)
         => VCC_net_1, F_WDATA_HWDATA01(13) => VCC_net_1, 
        F_WDATA_HWDATA01(12) => VCC_net_1, F_WDATA_HWDATA01(11)
         => VCC_net_1, F_WDATA_HWDATA01(10) => VCC_net_1, 
        F_WDATA_HWDATA01(9) => VCC_net_1, F_WDATA_HWDATA01(8) => 
        VCC_net_1, F_WDATA_HWDATA01(7) => VCC_net_1, 
        F_WDATA_HWDATA01(6) => VCC_net_1, F_WDATA_HWDATA01(5) => 
        VCC_net_1, F_WDATA_HWDATA01(4) => VCC_net_1, 
        F_WDATA_HWDATA01(3) => VCC_net_1, F_WDATA_HWDATA01(2) => 
        VCC_net_1, F_WDATA_HWDATA01(1) => VCC_net_1, 
        F_WDATA_HWDATA01(0) => VCC_net_1, F_WID_HREADY01(3) => 
        GND_net_1, F_WID_HREADY01(2) => GND_net_1, 
        F_WID_HREADY01(1) => GND_net_1, F_WID_HREADY01(0) => 
        GND_net_1, F_WLAST => GND_net_1, F_WSTRB(7) => GND_net_1, 
        F_WSTRB(6) => GND_net_1, F_WSTRB(5) => GND_net_1, 
        F_WSTRB(4) => GND_net_1, F_WSTRB(3) => GND_net_1, 
        F_WSTRB(2) => GND_net_1, F_WSTRB(1) => GND_net_1, 
        F_WSTRB(0) => GND_net_1, F_WVALID => GND_net_1, 
        FPGA_MDDR_ARESET_N => VCC_net_1, MDDR_FABRIC_PADDR(10)
         => VCC_net_1, MDDR_FABRIC_PADDR(9) => VCC_net_1, 
        MDDR_FABRIC_PADDR(8) => VCC_net_1, MDDR_FABRIC_PADDR(7)
         => VCC_net_1, MDDR_FABRIC_PADDR(6) => VCC_net_1, 
        MDDR_FABRIC_PADDR(5) => VCC_net_1, MDDR_FABRIC_PADDR(4)
         => VCC_net_1, MDDR_FABRIC_PADDR(3) => VCC_net_1, 
        MDDR_FABRIC_PADDR(2) => VCC_net_1, MDDR_FABRIC_PENABLE
         => VCC_net_1, MDDR_FABRIC_PSEL => VCC_net_1, 
        MDDR_FABRIC_PWDATA(15) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(14) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(13) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(12) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(11) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(10) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(9) => VCC_net_1, MDDR_FABRIC_PWDATA(8)
         => VCC_net_1, MDDR_FABRIC_PWDATA(7) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(6) => VCC_net_1, MDDR_FABRIC_PWDATA(5)
         => VCC_net_1, MDDR_FABRIC_PWDATA(4) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(3) => VCC_net_1, MDDR_FABRIC_PWDATA(2)
         => VCC_net_1, MDDR_FABRIC_PWDATA(1) => VCC_net_1, 
        MDDR_FABRIC_PWDATA(0) => VCC_net_1, MDDR_FABRIC_PWRITE
         => VCC_net_1, PRESET_N => GND_net_1, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_IN => GND_net_1, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN => GND_net_1, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_IN => GND_net_1, DM_IN(4)
         => GND_net_1, DM_IN(3) => GND_net_1, DM_IN(2) => 
        GND_net_1, DM_IN(1) => GND_net_1, DM_IN(0) => GND_net_1, 
        DRAM_DQ_IN(35) => GND_net_1, DRAM_DQ_IN(34) => GND_net_1, 
        DRAM_DQ_IN(33) => GND_net_1, DRAM_DQ_IN(32) => GND_net_1, 
        DRAM_DQ_IN(31) => GND_net_1, DRAM_DQ_IN(30) => GND_net_1, 
        DRAM_DQ_IN(29) => GND_net_1, DRAM_DQ_IN(28) => GND_net_1, 
        DRAM_DQ_IN(27) => GND_net_1, DRAM_DQ_IN(26) => GND_net_1, 
        DRAM_DQ_IN(25) => GND_net_1, DRAM_DQ_IN(24) => GND_net_1, 
        DRAM_DQ_IN(23) => GND_net_1, DRAM_DQ_IN(22) => GND_net_1, 
        DRAM_DQ_IN(21) => GND_net_1, DRAM_DQ_IN(20) => GND_net_1, 
        DRAM_DQ_IN(19) => GND_net_1, DRAM_DQ_IN(18) => GND_net_1, 
        DRAM_DQ_IN(17) => GND_net_1, DRAM_DQ_IN(16) => GND_net_1, 
        DRAM_DQ_IN(15) => GND_net_1, DRAM_DQ_IN(14) => GND_net_1, 
        DRAM_DQ_IN(13) => GND_net_1, DRAM_DQ_IN(12) => GND_net_1, 
        DRAM_DQ_IN(11) => GND_net_1, DRAM_DQ_IN(10) => GND_net_1, 
        DRAM_DQ_IN(9) => GND_net_1, DRAM_DQ_IN(8) => GND_net_1, 
        DRAM_DQ_IN(7) => GND_net_1, DRAM_DQ_IN(6) => GND_net_1, 
        DRAM_DQ_IN(5) => GND_net_1, DRAM_DQ_IN(4) => GND_net_1, 
        DRAM_DQ_IN(3) => GND_net_1, DRAM_DQ_IN(2) => GND_net_1, 
        DRAM_DQ_IN(1) => GND_net_1, DRAM_DQ_IN(0) => GND_net_1, 
        DRAM_DQS_IN(4) => GND_net_1, DRAM_DQS_IN(3) => GND_net_1, 
        DRAM_DQS_IN(2) => GND_net_1, DRAM_DQS_IN(1) => GND_net_1, 
        DRAM_DQS_IN(0) => GND_net_1, DRAM_FIFO_WE_IN(2) => 
        GND_net_1, DRAM_FIFO_WE_IN(1) => GND_net_1, 
        DRAM_FIFO_WE_IN(0) => GND_net_1, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_IN => GND_net_1, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_IN => GND_net_1, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_IN => GND_net_1, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_IN => GND_net_1, MGPIO0B_IN
         => GND_net_1, MGPIO10B_IN => GND_net_1, MGPIO1B_IN => 
        GND_net_1, MGPIO25A_IN => GND_net_1, MGPIO26A_IN => 
        GND_net_1, MGPIO27A_IN => GND_net_1, MGPIO28A_IN => 
        GND_net_1, MGPIO29A_IN => GND_net_1, MGPIO2B_IN => 
        GND_net_1, MGPIO30A_IN => GND_net_1, MGPIO31A_IN => 
        GND_net_1, MGPIO3B_IN => GND_net_1, MGPIO4B_IN => 
        GND_net_1, MGPIO5B_IN => GND_net_1, MGPIO6B_IN => 
        GND_net_1, MGPIO7B_IN => GND_net_1, MGPIO8B_IN => 
        GND_net_1, MGPIO9B_IN => GND_net_1, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_IN => GND_net_1, 
        MMUART0_DCD_MGPIO22B_IN => GND_net_1, 
        MMUART0_DSR_MGPIO20B_IN => GND_net_1, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_IN => GND_net_1, 
        MMUART0_RI_MGPIO21B_IN => GND_net_1, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_IN => GND_net_1, 
        MMUART0_RXD_USBC_STP_MGPIO28B_IN => MMUART_0_RXD_PAD_Y, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_IN => GND_net_1, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_IN => GND_net_1, 
        MMUART1_CTS_MGPIO13B_IN => GND_net_1, 
        MMUART1_DCD_MGPIO16B_IN => GND_net_1, 
        MMUART1_DSR_MGPIO14B_IN => GND_net_1, 
        MMUART1_DTR_MGPIO12B_IN => GND_net_1, 
        MMUART1_RI_MGPIO15B_IN => GND_net_1, 
        MMUART1_RTS_MGPIO11B_IN => GND_net_1, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_IN => GND_net_1, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_IN => GND_net_1, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_IN => GND_net_1, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN => GND_net_1, 
        RGMII_MDC_RMII_MDC_IN => GND_net_1, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN => GND_net_1, 
        RGMII_RX_CLK_IN => GND_net_1, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN => GND_net_1, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN => GND_net_1, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN => GND_net_1, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN => GND_net_1, 
        RGMII_RXD3_USBB_DATA4_IN => GND_net_1, RGMII_TX_CLK_IN
         => GND_net_1, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN => 
        GND_net_1, RGMII_TXD0_RMII_TXD0_USBB_DIR_IN => GND_net_1, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_IN => GND_net_1, 
        RGMII_TXD2_USBB_DATA5_IN => GND_net_1, 
        RGMII_TXD3_USBB_DATA6_IN => GND_net_1, 
        SPI0_SCK_USBA_XCLK_IN => GND_net_1, 
        SPI0_SDI_USBA_DIR_MGPIO5A_IN => GND_net_1, 
        SPI0_SDO_USBA_STP_MGPIO6A_IN => GND_net_1, 
        SPI0_SS0_USBA_NXT_MGPIO7A_IN => GND_net_1, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_IN => GND_net_1, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_IN => GND_net_1, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_IN => GND_net_1, 
        SPI0_SS4_MGPIO19A_IN => GND_net_1, SPI0_SS5_MGPIO20A_IN
         => GND_net_1, SPI0_SS6_MGPIO21A_IN => GND_net_1, 
        SPI0_SS7_MGPIO22A_IN => GND_net_1, SPI1_SCK_IN => 
        GND_net_1, SPI1_SDI_MGPIO11A_IN => GND_net_1, 
        SPI1_SDO_MGPIO12A_IN => GND_net_1, SPI1_SS0_MGPIO13A_IN
         => GND_net_1, SPI1_SS1_MGPIO14A_IN => GND_net_1, 
        SPI1_SS2_MGPIO15A_IN => GND_net_1, SPI1_SS3_MGPIO16A_IN
         => GND_net_1, SPI1_SS4_MGPIO17A_IN => GND_net_1, 
        SPI1_SS5_MGPIO18A_IN => GND_net_1, SPI1_SS6_MGPIO23A_IN
         => GND_net_1, SPI1_SS7_MGPIO24A_IN => GND_net_1, 
        USBC_XCLK_IN => GND_net_1, USBD_DATA0_IN => GND_net_1, 
        USBD_DATA1_IN => GND_net_1, USBD_DATA2_IN => GND_net_1, 
        USBD_DATA3_IN => GND_net_1, USBD_DATA4_IN => GND_net_1, 
        USBD_DATA5_IN => GND_net_1, USBD_DATA6_IN => GND_net_1, 
        USBD_DATA7_MGPIO23B_IN => GND_net_1, USBD_DIR_IN => 
        GND_net_1, USBD_NXT_IN => GND_net_1, USBD_STP_IN => 
        GND_net_1, USBD_XCLK_IN => GND_net_1, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT => OPEN, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT => OPEN, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT => OPEN, DRAM_ADDR(15)
         => nc434, DRAM_ADDR(14) => nc387, DRAM_ADDR(13) => nc571, 
        DRAM_ADDR(12) => nc2, DRAM_ADDR(11) => nc82, 
        DRAM_ADDR(10) => nc284, DRAM_ADDR(9) => nc420, 
        DRAM_ADDR(8) => nc35, DRAM_ADDR(7) => nc295, DRAM_ADDR(6)
         => nc355, DRAM_ADDR(5) => nc258, DRAM_ADDR(4) => nc263, 
        DRAM_ADDR(3) => nc180, DRAM_ADDR(2) => nc364, 
        DRAM_ADDR(1) => nc357, DRAM_ADDR(0) => nc174, DRAM_BA(2)
         => nc585, DRAM_BA(1) => nc431, DRAM_BA(0) => nc473, 
        DRAM_CASN => OPEN, DRAM_CKE => OPEN, DRAM_CLK => OPEN, 
        DRAM_CSN => OPEN, DRAM_DM_RDQS_OUT(4) => nc388, 
        DRAM_DM_RDQS_OUT(3) => nc254, DRAM_DM_RDQS_OUT(2) => 
        nc574, DRAM_DM_RDQS_OUT(1) => nc141, DRAM_DM_RDQS_OUT(0)
         => nc276, DRAM_DQ_OUT(35) => nc147, DRAM_DQ_OUT(34) => 
        nc48, DRAM_DQ_OUT(33) => nc7, DRAM_DQ_OUT(32) => nc5, 
        DRAM_DQ_OUT(31) => nc150, DRAM_DQ_OUT(30) => nc277, 
        DRAM_DQ_OUT(29) => nc292, DRAM_DQ_OUT(28) => nc249, 
        DRAM_DQ_OUT(27) => nc555, DRAM_DQ_OUT(26) => nc527, 
        DRAM_DQ_OUT(25) => nc358, DRAM_DQ_OUT(24) => nc569, 
        DRAM_DQ_OUT(23) => nc487, DRAM_DQ_OUT(22) => nc479, 
        DRAM_DQ_OUT(21) => nc45, DRAM_DQ_OUT(20) => nc382, 
        DRAM_DQ_OUT(19) => nc486, DRAM_DQ_OUT(18) => nc201, 
        DRAM_DQ_OUT(17) => nc105, DRAM_DQ_OUT(16) => nc457, 
        DRAM_DQ_OUT(15) => nc166, DRAM_DQ_OUT(14) => nc26, 
        DRAM_DQ_OUT(13) => nc129, DRAM_DQ_OUT(12) => nc300, 
        DRAM_DQ_OUT(11) => nc389, DRAM_DQ_OUT(10) => nc211, 
        DRAM_DQ_OUT(9) => nc115, DRAM_DQ_OUT(8) => nc275, 
        DRAM_DQ_OUT(7) => nc352, DRAM_DQ_OUT(6) => nc456, 
        DRAM_DQ_OUT(5) => nc310, DRAM_DQ_OUT(4) => nc482, 
        DRAM_DQ_OUT(3) => nc532, DRAM_DQ_OUT(2) => nc359, 
        DRAM_DQ_OUT(1) => nc191, DRAM_DQ_OUT(0) => nc83, 
        DRAM_DQS_OUT(4) => nc197, DRAM_DQS_OUT(3) => nc430, 
        DRAM_DQS_OUT(2) => nc76, DRAM_DQS_OUT(1) => nc56, 
        DRAM_DQS_OUT(0) => nc243, DRAM_FIFO_WE_OUT(2) => nc68, 
        DRAM_FIFO_WE_OUT(1) => nc344, DRAM_FIFO_WE_OUT(0) => 
        nc452, DRAM_ODT => OPEN, DRAM_RASN => OPEN, DRAM_RSTN => 
        OPEN, DRAM_WEN => OPEN, I2C0_SCL_USBC_DATA1_MGPIO31B_OUT
         => OPEN, I2C0_SDA_USBC_DATA0_MGPIO30B_OUT => OPEN, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT => OPEN, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT => OPEN, MGPIO0B_OUT => 
        OPEN, MGPIO10B_OUT => OPEN, MGPIO1B_OUT => OPEN, 
        MGPIO25A_OUT => OPEN, MGPIO26A_OUT => OPEN, MGPIO27A_OUT
         => OPEN, MGPIO28A_OUT => OPEN, MGPIO29A_OUT => OPEN, 
        MGPIO2B_OUT => OPEN, MGPIO30A_OUT => OPEN, MGPIO31A_OUT
         => OPEN, MGPIO3B_OUT => OPEN, MGPIO4B_OUT => OPEN, 
        MGPIO5B_OUT => OPEN, MGPIO6B_OUT => OPEN, MGPIO7B_OUT => 
        OPEN, MGPIO8B_OUT => OPEN, MGPIO9B_OUT => OPEN, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT => OPEN, 
        MMUART0_DCD_MGPIO22B_OUT => OPEN, 
        MMUART0_DSR_MGPIO20B_OUT => OPEN, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT => OPEN, 
        MMUART0_RI_MGPIO21B_OUT => OPEN, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT => OPEN, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT => OPEN, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT => OPEN, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT => 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_CTS_MGPIO13B_OUT => OPEN, 
        MMUART1_DCD_MGPIO16B_OUT => OPEN, 
        MMUART1_DSR_MGPIO14B_OUT => OPEN, 
        MMUART1_DTR_MGPIO12B_OUT => OPEN, MMUART1_RI_MGPIO15B_OUT
         => OPEN, MMUART1_RTS_MGPIO11B_OUT => OPEN, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT => OPEN, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT => OPEN, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT => OPEN, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT => OPEN, 
        RGMII_MDC_RMII_MDC_OUT => OPEN, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT => OPEN, 
        RGMII_RX_CLK_OUT => OPEN, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT => OPEN, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT => OPEN, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT => OPEN, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT => OPEN, 
        RGMII_RXD3_USBB_DATA4_OUT => OPEN, RGMII_TX_CLK_OUT => 
        OPEN, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT => OPEN, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT => OPEN, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OUT => OPEN, 
        RGMII_TXD2_USBB_DATA5_OUT => OPEN, 
        RGMII_TXD3_USBB_DATA6_OUT => OPEN, SPI0_SCK_USBA_XCLK_OUT
         => OPEN, SPI0_SDI_USBA_DIR_MGPIO5A_OUT => OPEN, 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT => OPEN, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT => OPEN, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT => OPEN, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT => OPEN, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT => OPEN, 
        SPI0_SS4_MGPIO19A_OUT => OPEN, SPI0_SS5_MGPIO20A_OUT => 
        OPEN, SPI0_SS6_MGPIO21A_OUT => OPEN, 
        SPI0_SS7_MGPIO22A_OUT => OPEN, SPI1_SCK_OUT => OPEN, 
        SPI1_SDI_MGPIO11A_OUT => OPEN, SPI1_SDO_MGPIO12A_OUT => 
        OPEN, SPI1_SS0_MGPIO13A_OUT => OPEN, 
        SPI1_SS1_MGPIO14A_OUT => OPEN, SPI1_SS2_MGPIO15A_OUT => 
        OPEN, SPI1_SS3_MGPIO16A_OUT => OPEN, 
        SPI1_SS4_MGPIO17A_OUT => OPEN, SPI1_SS5_MGPIO18A_OUT => 
        OPEN, SPI1_SS6_MGPIO23A_OUT => OPEN, 
        SPI1_SS7_MGPIO24A_OUT => OPEN, USBC_XCLK_OUT => OPEN, 
        USBD_DATA0_OUT => OPEN, USBD_DATA1_OUT => OPEN, 
        USBD_DATA2_OUT => OPEN, USBD_DATA3_OUT => OPEN, 
        USBD_DATA4_OUT => OPEN, USBD_DATA5_OUT => OPEN, 
        USBD_DATA6_OUT => OPEN, USBD_DATA7_MGPIO23B_OUT => OPEN, 
        USBD_DIR_OUT => OPEN, USBD_NXT_OUT => OPEN, USBD_STP_OUT
         => OPEN, USBD_XCLK_OUT => OPEN, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE => OPEN, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE => OPEN, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE => OPEN, DM_OE(4) => 
        nc299, DM_OE(3) => nc272, DM_OE(2) => nc182, DM_OE(1) => 
        nc30, DM_OE(0) => nc305, DRAM_DQ_OE(35) => nc208, 
        DRAM_DQ_OE(34) => nc307, DRAM_DQ_OE(33) => nc31, 
        DRAM_DQ_OE(32) => nc65, DRAM_DQ_OE(31) => nc315, 
        DRAM_DQ_OE(30) => nc218, DRAM_DQ_OE(29) => nc168, 
        DRAM_DQ_OE(28) => nc18, DRAM_DQ_OE(27) => nc317, 
        DRAM_DQ_OE(26) => nc549, DRAM_DQ_OE(25) => nc366, 
        DRAM_DQ_OE(24) => nc152, DRAM_DQ_OE(23) => nc204, 
        DRAM_DQ_OE(22) => nc537, DRAM_DQ_OE(21) => nc100, 
        DRAM_DQ_OE(20) => nc214, DRAM_DQ_OE(19) => nc505, 
        DRAM_DQ_OE(18) => nc308, DRAM_DQ_OE(17) => nc15, 
        DRAM_DQ_OE(16) => nc110, DRAM_DQ_OE(15) => nc515, 
        DRAM_DQ_OE(14) => nc318, DRAM_DQ_OE(13) => nc40, 
        DRAM_DQ_OE(12) => nc146, DRAM_DQ_OE(11) => nc24, 
        DRAM_DQ_OE(10) => nc221, DRAM_DQ_OE(9) => nc125, 
        DRAM_DQ_OE(8) => nc183, DRAM_DQ_OE(7) => nc139, 
        DRAM_DQ_OE(6) => nc361, DRAM_DQ_OE(5) => nc41, 
        DRAM_DQ_OE(4) => nc293, DRAM_DQ_OE(3) => nc171, 
        DRAM_DQ_OE(2) => nc320, DRAM_DQ_OE(1) => nc394, 
        DRAM_DQ_OE(0) => nc177, DRAM_DQS_OE(4) => nc407, 
        DRAM_DQS_OE(3) => nc464, DRAM_DQS_OE(2) => nc279, 
        DRAM_DQS_OE(1) => nc417, DRAM_DQS_OE(0) => nc153, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE => OPEN, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE => OPEN, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE => OPEN, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE => OPEN, MGPIO0B_OE => 
        OPEN, MGPIO10B_OE => OPEN, MGPIO1B_OE => OPEN, 
        MGPIO25A_OE => OPEN, MGPIO26A_OE => OPEN, MGPIO27A_OE => 
        OPEN, MGPIO28A_OE => OPEN, MGPIO29A_OE => OPEN, 
        MGPIO2B_OE => OPEN, MGPIO30A_OE => OPEN, MGPIO31A_OE => 
        OPEN, MGPIO3B_OE => OPEN, MGPIO4B_OE => OPEN, MGPIO5B_OE
         => OPEN, MGPIO6B_OE => OPEN, MGPIO7B_OE => OPEN, 
        MGPIO8B_OE => OPEN, MGPIO9B_OE => OPEN, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE => OPEN, 
        MMUART0_DCD_MGPIO22B_OE => OPEN, MMUART0_DSR_MGPIO20B_OE
         => OPEN, MMUART0_DTR_USBC_DATA6_MGPIO18B_OE => OPEN, 
        MMUART0_RI_MGPIO21B_OE => OPEN, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE => OPEN, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE => OPEN, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE => OPEN, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE => 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_CTS_MGPIO13B_OE => OPEN, MMUART1_DCD_MGPIO16B_OE
         => OPEN, MMUART1_DSR_MGPIO14B_OE => OPEN, 
        MMUART1_DTR_MGPIO12B_OE => OPEN, MMUART1_RI_MGPIO15B_OE
         => OPEN, MMUART1_RTS_MGPIO11B_OE => OPEN, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE => OPEN, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE => OPEN, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE => OPEN, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE => OPEN, 
        RGMII_MDC_RMII_MDC_OE => OPEN, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE => OPEN, 
        RGMII_RX_CLK_OE => OPEN, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE => OPEN, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE => OPEN, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE => OPEN, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE => OPEN, 
        RGMII_RXD3_USBB_DATA4_OE => OPEN, RGMII_TX_CLK_OE => OPEN, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE => OPEN, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE => OPEN, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OE => OPEN, 
        RGMII_TXD2_USBB_DATA5_OE => OPEN, 
        RGMII_TXD3_USBB_DATA6_OE => OPEN, SPI0_SCK_USBA_XCLK_OE
         => OPEN, SPI0_SDI_USBA_DIR_MGPIO5A_OE => OPEN, 
        SPI0_SDO_USBA_STP_MGPIO6A_OE => OPEN, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE => OPEN, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE => OPEN, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE => OPEN, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE => OPEN, 
        SPI0_SS4_MGPIO19A_OE => OPEN, SPI0_SS5_MGPIO20A_OE => 
        OPEN, SPI0_SS6_MGPIO21A_OE => OPEN, SPI0_SS7_MGPIO22A_OE
         => OPEN, SPI1_SCK_OE => OPEN, SPI1_SDI_MGPIO11A_OE => 
        OPEN, SPI1_SDO_MGPIO12A_OE => OPEN, SPI1_SS0_MGPIO13A_OE
         => OPEN, SPI1_SS1_MGPIO14A_OE => OPEN, 
        SPI1_SS2_MGPIO15A_OE => OPEN, SPI1_SS3_MGPIO16A_OE => 
        OPEN, SPI1_SS4_MGPIO17A_OE => OPEN, SPI1_SS5_MGPIO18A_OE
         => OPEN, SPI1_SS6_MGPIO23A_OE => OPEN, 
        SPI1_SS7_MGPIO24A_OE => OPEN, USBC_XCLK_OE => OPEN, 
        USBD_DATA0_OE => OPEN, USBD_DATA1_OE => OPEN, 
        USBD_DATA2_OE => OPEN, USBD_DATA3_OE => OPEN, 
        USBD_DATA4_OE => OPEN, USBD_DATA5_OE => OPEN, 
        USBD_DATA6_OE => OPEN, USBD_DATA7_MGPIO23B_OE => OPEN, 
        USBD_DIR_OE => OPEN, USBD_NXT_OE => OPEN, USBD_STP_OE => 
        OPEN, USBD_XCLK_OE => OPEN);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    MMUART_0_TXD_PAD : TRIBUFF
      port map(D => 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, E => 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE, PAD => 
        MMUART_0_TXD);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity AHB_Bus_Matrix_sb_CCC_0_FCCC is

    port( AHB_Bus_Matrix_sb_0_FIC_0_CLK                      : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_1_CLK                      : out   std_logic;
          FIC_1_LOCK                                         : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic
        );

end AHB_Bus_Matrix_sb_CCC_0_FCCC;

architecture DEF_ARCH of AHB_Bus_Matrix_sb_CCC_0_FCCC is 

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CCC

            generic (INIT:std_logic_vector(209 downto 0) := "00" & x"0000000000000000000000000000000000000000000000000000"; 
        VCOFREQUENCY:real := 0.0);

    port( Y0              : out   std_logic;
          Y1              : out   std_logic;
          Y2              : out   std_logic;
          Y3              : out   std_logic;
          PRDATA          : out   std_logic_vector(7 downto 0);
          LOCK            : out   std_logic;
          BUSY            : out   std_logic;
          CLK0            : in    std_logic := 'U';
          CLK1            : in    std_logic := 'U';
          CLK2            : in    std_logic := 'U';
          CLK3            : in    std_logic := 'U';
          NGMUX0_SEL      : in    std_logic := 'U';
          NGMUX1_SEL      : in    std_logic := 'U';
          NGMUX2_SEL      : in    std_logic := 'U';
          NGMUX3_SEL      : in    std_logic := 'U';
          NGMUX0_HOLD_N   : in    std_logic := 'U';
          NGMUX1_HOLD_N   : in    std_logic := 'U';
          NGMUX2_HOLD_N   : in    std_logic := 'U';
          NGMUX3_HOLD_N   : in    std_logic := 'U';
          NGMUX0_ARST_N   : in    std_logic := 'U';
          NGMUX1_ARST_N   : in    std_logic := 'U';
          NGMUX2_ARST_N   : in    std_logic := 'U';
          NGMUX3_ARST_N   : in    std_logic := 'U';
          PLL_BYPASS_N    : in    std_logic := 'U';
          PLL_ARST_N      : in    std_logic := 'U';
          PLL_POWERDOWN_N : in    std_logic := 'U';
          GPD0_ARST_N     : in    std_logic := 'U';
          GPD1_ARST_N     : in    std_logic := 'U';
          GPD2_ARST_N     : in    std_logic := 'U';
          GPD3_ARST_N     : in    std_logic := 'U';
          PRESET_N        : in    std_logic := 'U';
          PCLK            : in    std_logic := 'U';
          PSEL            : in    std_logic := 'U';
          PENABLE         : in    std_logic := 'U';
          PWRITE          : in    std_logic := 'U';
          PADDR           : in    std_logic_vector(7 downto 2) := (others => 'U');
          PWDATA          : in    std_logic_vector(7 downto 0) := (others => 'U');
          CLK0_PAD        : in    std_logic := 'U';
          CLK1_PAD        : in    std_logic := 'U';
          CLK2_PAD        : in    std_logic := 'U';
          CLK3_PAD        : in    std_logic := 'U';
          GL0             : out   std_logic;
          GL1             : out   std_logic;
          GL2             : out   std_logic;
          GL3             : out   std_logic;
          RCOSC_25_50MHZ  : in    std_logic := 'U';
          RCOSC_1MHZ      : in    std_logic := 'U';
          XTLOSC          : in    std_logic := 'U'
        );
  end component;

    signal GL0_net, GL1_net, VCC_net_1, GND_net_1 : std_logic;
    signal nc8, nc7, nc6, nc2, nc5, nc4, nc3, nc1 : std_logic;

begin 


    GL1_INST : CLKINT
      port map(A => GL1_net, Y => AHB_Bus_Matrix_sb_0_FIC_1_CLK);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    GL0_INST : CLKINT
      port map(A => GL0_net, Y => AHB_Bus_Matrix_sb_0_FIC_0_CLK);
    
    CCC_INST : CCC

              generic map(INIT => "00" & x"000007FB8000044D64000318C6307C1F18C61EC0404040400301",
         VCOFREQUENCY => 800.0)

      port map(Y0 => OPEN, Y1 => OPEN, Y2 => OPEN, Y3 => OPEN, 
        PRDATA(7) => nc8, PRDATA(6) => nc7, PRDATA(5) => nc6, 
        PRDATA(4) => nc2, PRDATA(3) => nc5, PRDATA(2) => nc4, 
        PRDATA(1) => nc3, PRDATA(0) => nc1, LOCK => FIC_1_LOCK, 
        BUSY => OPEN, CLK0 => VCC_net_1, CLK1 => VCC_net_1, CLK2
         => VCC_net_1, CLK3 => VCC_net_1, NGMUX0_SEL => GND_net_1, 
        NGMUX1_SEL => GND_net_1, NGMUX2_SEL => GND_net_1, 
        NGMUX3_SEL => GND_net_1, NGMUX0_HOLD_N => VCC_net_1, 
        NGMUX1_HOLD_N => VCC_net_1, NGMUX2_HOLD_N => VCC_net_1, 
        NGMUX3_HOLD_N => VCC_net_1, NGMUX0_ARST_N => VCC_net_1, 
        NGMUX1_ARST_N => VCC_net_1, NGMUX2_ARST_N => VCC_net_1, 
        NGMUX3_ARST_N => VCC_net_1, PLL_BYPASS_N => VCC_net_1, 
        PLL_ARST_N => VCC_net_1, PLL_POWERDOWN_N => VCC_net_1, 
        GPD0_ARST_N => VCC_net_1, GPD1_ARST_N => VCC_net_1, 
        GPD2_ARST_N => VCC_net_1, GPD3_ARST_N => VCC_net_1, 
        PRESET_N => GND_net_1, PCLK => VCC_net_1, PSEL => 
        VCC_net_1, PENABLE => VCC_net_1, PWRITE => VCC_net_1, 
        PADDR(7) => VCC_net_1, PADDR(6) => VCC_net_1, PADDR(5)
         => VCC_net_1, PADDR(4) => VCC_net_1, PADDR(3) => 
        VCC_net_1, PADDR(2) => VCC_net_1, PWDATA(7) => VCC_net_1, 
        PWDATA(6) => VCC_net_1, PWDATA(5) => VCC_net_1, PWDATA(4)
         => VCC_net_1, PWDATA(3) => VCC_net_1, PWDATA(2) => 
        VCC_net_1, PWDATA(1) => VCC_net_1, PWDATA(0) => VCC_net_1, 
        CLK0_PAD => GND_net_1, CLK1_PAD => GND_net_1, CLK2_PAD
         => GND_net_1, CLK3_PAD => GND_net_1, GL0 => GL0_net, GL1
         => GL1_net, GL2 => OPEN, GL3 => OPEN, RCOSC_25_50MHZ => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        RCOSC_1MHZ => GND_net_1, XTLOSC => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity AHB_Bus_Matrix_sb is

    port( Fabric_Master1_0_BIF_1_HADDR     : in    std_logic_vector(31 downto 0);
          Fabric_Master1_0_BIF_1_HSIZE     : in    std_logic_vector(1 downto 0);
          Fabric_Master1_0_BIF_1_HTRANS    : in    std_logic_vector(1 to 1);
          Fabric_Master1_0_BIF_1_HWDATA    : in    std_logic_vector(31 downto 0);
          Fabric_Master2_0_BIF_1_HADDR     : in    std_logic_vector(31 downto 0);
          Fabric_Master2_0_BIF_1_HSIZE     : in    std_logic_vector(1 downto 0);
          Fabric_Master2_0_BIF_1_HTRANS    : in    std_logic_vector(1 to 1);
          Fabric_Master2_0_BIF_1_HWDATA    : in    std_logic_vector(31 downto 0);
          DEVRST_N                         : in    std_logic;
          MMUART_0_TXD                     : out   std_logic;
          MMUART_0_RXD                     : in    std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_2_M2F   : out   std_logic;
          Fabric_Master1_0_BIF_1_HREADYOUT : out   std_logic;
          Fabric_Master2_0_BIF_1_HREADYOUT : out   std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_0_M2F   : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK    : out   std_logic;
          AND2_0_Y                         : in    std_logic;
          Fabric_Master1_0_BIF_1_HSELx     : in    std_logic;
          Fabric_Master1_0_BIF_1_HWRITE    : in    std_logic;
          Fabric_Master2_0_BIF_1_HSELx     : in    std_logic;
          Fabric_Master2_0_BIF_1_HWRITE    : in    std_logic;
          AHB_Bus_Matrix_sb_0_FIC_1_CLK    : out   std_logic;
          AHB_Bus_Matrix_sb_0_MSS_READY    : out   std_logic
        );

end AHB_Bus_Matrix_sb;

architecture DEF_ARCH of AHB_Bus_Matrix_sb is 

  component AHB_Bus_Matrix_sb_FABOSC_0_OSC
    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );
  end component;

  component CoreResetP
    port( AHB_Bus_Matrix_sb_0_MSS_READY                    : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK                    : in    std_logic := 'U';
          AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N : in    std_logic := 'U';
          POWER_ON_RESET_N                                 : in    std_logic := 'U';
          AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F      : in    std_logic := 'U'
        );
  end component;

  component AHB_Bus_Matrix_sb_MSS
    port( Fabric_Master1_0_BIF_1_HADDR                     : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master1_0_BIF_1_HSIZE                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          Fabric_Master1_0_BIF_1_HTRANS                    : in    std_logic_vector(1 to 1) := (others => 'U');
          Fabric_Master1_0_BIF_1_HWDATA                    : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HADDR                     : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HSIZE                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HTRANS                    : in    std_logic_vector(1 to 1) := (others => 'U');
          Fabric_Master2_0_BIF_1_HWDATA                    : in    std_logic_vector(31 downto 0) := (others => 'U');
          MMUART_0_TXD                                     : out   std_logic;
          MMUART_0_RXD                                     : in    std_logic := 'U';
          AHB_Bus_Matrix_sb_0_GPIO_2_M2F                   : out   std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N : out   std_logic;
          Fabric_Master1_0_BIF_1_HREADYOUT                 : out   std_logic;
          Fabric_Master2_0_BIF_1_HREADYOUT                 : out   std_logic;
          AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F      : out   std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_0_M2F                   : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK                    : in    std_logic := 'U';
          AND2_0_Y                                         : in    std_logic := 'U';
          Fabric_Master1_0_BIF_1_HSELx                     : in    std_logic := 'U';
          Fabric_Master1_0_BIF_1_HWRITE                    : in    std_logic := 'U';
          Fabric_Master2_0_BIF_1_HSELx                     : in    std_logic := 'U';
          Fabric_Master2_0_BIF_1_HWRITE                    : in    std_logic := 'U';
          FIC_1_LOCK                                       : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component AHB_Bus_Matrix_sb_CCC_0_FCCC
    port( AHB_Bus_Matrix_sb_0_FIC_0_CLK                      : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_1_CLK                      : out   std_logic;
          FIC_1_LOCK                                         : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component SYSRESET
    port( POWER_ON_RESET_N : out   std_logic;
          DEVRST_N         : in    std_logic := 'U'
        );
  end component;

    signal POWER_ON_RESET_N, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F, 
        \AHB_Bus_Matrix_sb_0_FIC_0_CLK\, FIC_1_LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        GND_net_1, VCC_net_1 : std_logic;

    for all : AHB_Bus_Matrix_sb_FABOSC_0_OSC
	Use entity work.AHB_Bus_Matrix_sb_FABOSC_0_OSC(DEF_ARCH);
    for all : CoreResetP
	Use entity work.CoreResetP(DEF_ARCH);
    for all : AHB_Bus_Matrix_sb_MSS
	Use entity work.AHB_Bus_Matrix_sb_MSS(DEF_ARCH);
    for all : AHB_Bus_Matrix_sb_CCC_0_FCCC
	Use entity work.AHB_Bus_Matrix_sb_CCC_0_FCCC(DEF_ARCH);
begin 

    AHB_Bus_Matrix_sb_0_FIC_0_CLK <= 
        \AHB_Bus_Matrix_sb_0_FIC_0_CLK\;

    FABOSC_0 : AHB_Bus_Matrix_sb_FABOSC_0_OSC
      port map(FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
         => FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    CORERESETP_0 : CoreResetP
      port map(AHB_Bus_Matrix_sb_0_MSS_READY => 
        AHB_Bus_Matrix_sb_0_MSS_READY, 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK => 
        \AHB_Bus_Matrix_sb_0_FIC_0_CLK\, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, 
        POWER_ON_RESET_N => POWER_ON_RESET_N, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F);
    
    AHB_Bus_Matrix_sb_MSS_0 : AHB_Bus_Matrix_sb_MSS
      port map(Fabric_Master1_0_BIF_1_HADDR(31) => 
        Fabric_Master1_0_BIF_1_HADDR(31), 
        Fabric_Master1_0_BIF_1_HADDR(30) => 
        Fabric_Master1_0_BIF_1_HADDR(30), 
        Fabric_Master1_0_BIF_1_HADDR(29) => 
        Fabric_Master1_0_BIF_1_HADDR(29), 
        Fabric_Master1_0_BIF_1_HADDR(28) => 
        Fabric_Master1_0_BIF_1_HADDR(28), 
        Fabric_Master1_0_BIF_1_HADDR(27) => 
        Fabric_Master1_0_BIF_1_HADDR(27), 
        Fabric_Master1_0_BIF_1_HADDR(26) => 
        Fabric_Master1_0_BIF_1_HADDR(26), 
        Fabric_Master1_0_BIF_1_HADDR(25) => 
        Fabric_Master1_0_BIF_1_HADDR(25), 
        Fabric_Master1_0_BIF_1_HADDR(24) => 
        Fabric_Master1_0_BIF_1_HADDR(24), 
        Fabric_Master1_0_BIF_1_HADDR(23) => 
        Fabric_Master1_0_BIF_1_HADDR(23), 
        Fabric_Master1_0_BIF_1_HADDR(22) => 
        Fabric_Master1_0_BIF_1_HADDR(22), 
        Fabric_Master1_0_BIF_1_HADDR(21) => 
        Fabric_Master1_0_BIF_1_HADDR(21), 
        Fabric_Master1_0_BIF_1_HADDR(20) => 
        Fabric_Master1_0_BIF_1_HADDR(20), 
        Fabric_Master1_0_BIF_1_HADDR(19) => 
        Fabric_Master1_0_BIF_1_HADDR(19), 
        Fabric_Master1_0_BIF_1_HADDR(18) => 
        Fabric_Master1_0_BIF_1_HADDR(18), 
        Fabric_Master1_0_BIF_1_HADDR(17) => 
        Fabric_Master1_0_BIF_1_HADDR(17), 
        Fabric_Master1_0_BIF_1_HADDR(16) => 
        Fabric_Master1_0_BIF_1_HADDR(16), 
        Fabric_Master1_0_BIF_1_HADDR(15) => 
        Fabric_Master1_0_BIF_1_HADDR(15), 
        Fabric_Master1_0_BIF_1_HADDR(14) => 
        Fabric_Master1_0_BIF_1_HADDR(14), 
        Fabric_Master1_0_BIF_1_HADDR(13) => 
        Fabric_Master1_0_BIF_1_HADDR(13), 
        Fabric_Master1_0_BIF_1_HADDR(12) => 
        Fabric_Master1_0_BIF_1_HADDR(12), 
        Fabric_Master1_0_BIF_1_HADDR(11) => 
        Fabric_Master1_0_BIF_1_HADDR(11), 
        Fabric_Master1_0_BIF_1_HADDR(10) => 
        Fabric_Master1_0_BIF_1_HADDR(10), 
        Fabric_Master1_0_BIF_1_HADDR(9) => 
        Fabric_Master1_0_BIF_1_HADDR(9), 
        Fabric_Master1_0_BIF_1_HADDR(8) => 
        Fabric_Master1_0_BIF_1_HADDR(8), 
        Fabric_Master1_0_BIF_1_HADDR(7) => 
        Fabric_Master1_0_BIF_1_HADDR(7), 
        Fabric_Master1_0_BIF_1_HADDR(6) => 
        Fabric_Master1_0_BIF_1_HADDR(6), 
        Fabric_Master1_0_BIF_1_HADDR(5) => 
        Fabric_Master1_0_BIF_1_HADDR(5), 
        Fabric_Master1_0_BIF_1_HADDR(4) => 
        Fabric_Master1_0_BIF_1_HADDR(4), 
        Fabric_Master1_0_BIF_1_HADDR(3) => 
        Fabric_Master1_0_BIF_1_HADDR(3), 
        Fabric_Master1_0_BIF_1_HADDR(2) => 
        Fabric_Master1_0_BIF_1_HADDR(2), 
        Fabric_Master1_0_BIF_1_HADDR(1) => 
        Fabric_Master1_0_BIF_1_HADDR(1), 
        Fabric_Master1_0_BIF_1_HADDR(0) => 
        Fabric_Master1_0_BIF_1_HADDR(0), 
        Fabric_Master1_0_BIF_1_HSIZE(1) => 
        Fabric_Master1_0_BIF_1_HSIZE(1), 
        Fabric_Master1_0_BIF_1_HSIZE(0) => 
        Fabric_Master1_0_BIF_1_HSIZE(0), 
        Fabric_Master1_0_BIF_1_HTRANS(1) => 
        Fabric_Master1_0_BIF_1_HTRANS(1), 
        Fabric_Master1_0_BIF_1_HWDATA(31) => 
        Fabric_Master1_0_BIF_1_HWDATA(31), 
        Fabric_Master1_0_BIF_1_HWDATA(30) => 
        Fabric_Master1_0_BIF_1_HWDATA(30), 
        Fabric_Master1_0_BIF_1_HWDATA(29) => 
        Fabric_Master1_0_BIF_1_HWDATA(29), 
        Fabric_Master1_0_BIF_1_HWDATA(28) => 
        Fabric_Master1_0_BIF_1_HWDATA(28), 
        Fabric_Master1_0_BIF_1_HWDATA(27) => 
        Fabric_Master1_0_BIF_1_HWDATA(27), 
        Fabric_Master1_0_BIF_1_HWDATA(26) => 
        Fabric_Master1_0_BIF_1_HWDATA(26), 
        Fabric_Master1_0_BIF_1_HWDATA(25) => 
        Fabric_Master1_0_BIF_1_HWDATA(25), 
        Fabric_Master1_0_BIF_1_HWDATA(24) => 
        Fabric_Master1_0_BIF_1_HWDATA(24), 
        Fabric_Master1_0_BIF_1_HWDATA(23) => 
        Fabric_Master1_0_BIF_1_HWDATA(23), 
        Fabric_Master1_0_BIF_1_HWDATA(22) => 
        Fabric_Master1_0_BIF_1_HWDATA(22), 
        Fabric_Master1_0_BIF_1_HWDATA(21) => 
        Fabric_Master1_0_BIF_1_HWDATA(21), 
        Fabric_Master1_0_BIF_1_HWDATA(20) => 
        Fabric_Master1_0_BIF_1_HWDATA(20), 
        Fabric_Master1_0_BIF_1_HWDATA(19) => 
        Fabric_Master1_0_BIF_1_HWDATA(19), 
        Fabric_Master1_0_BIF_1_HWDATA(18) => 
        Fabric_Master1_0_BIF_1_HWDATA(18), 
        Fabric_Master1_0_BIF_1_HWDATA(17) => 
        Fabric_Master1_0_BIF_1_HWDATA(17), 
        Fabric_Master1_0_BIF_1_HWDATA(16) => 
        Fabric_Master1_0_BIF_1_HWDATA(16), 
        Fabric_Master1_0_BIF_1_HWDATA(15) => 
        Fabric_Master1_0_BIF_1_HWDATA(15), 
        Fabric_Master1_0_BIF_1_HWDATA(14) => 
        Fabric_Master1_0_BIF_1_HWDATA(14), 
        Fabric_Master1_0_BIF_1_HWDATA(13) => 
        Fabric_Master1_0_BIF_1_HWDATA(13), 
        Fabric_Master1_0_BIF_1_HWDATA(12) => 
        Fabric_Master1_0_BIF_1_HWDATA(12), 
        Fabric_Master1_0_BIF_1_HWDATA(11) => 
        Fabric_Master1_0_BIF_1_HWDATA(11), 
        Fabric_Master1_0_BIF_1_HWDATA(10) => 
        Fabric_Master1_0_BIF_1_HWDATA(10), 
        Fabric_Master1_0_BIF_1_HWDATA(9) => 
        Fabric_Master1_0_BIF_1_HWDATA(9), 
        Fabric_Master1_0_BIF_1_HWDATA(8) => 
        Fabric_Master1_0_BIF_1_HWDATA(8), 
        Fabric_Master1_0_BIF_1_HWDATA(7) => 
        Fabric_Master1_0_BIF_1_HWDATA(7), 
        Fabric_Master1_0_BIF_1_HWDATA(6) => 
        Fabric_Master1_0_BIF_1_HWDATA(6), 
        Fabric_Master1_0_BIF_1_HWDATA(5) => 
        Fabric_Master1_0_BIF_1_HWDATA(5), 
        Fabric_Master1_0_BIF_1_HWDATA(4) => 
        Fabric_Master1_0_BIF_1_HWDATA(4), 
        Fabric_Master1_0_BIF_1_HWDATA(3) => 
        Fabric_Master1_0_BIF_1_HWDATA(3), 
        Fabric_Master1_0_BIF_1_HWDATA(2) => 
        Fabric_Master1_0_BIF_1_HWDATA(2), 
        Fabric_Master1_0_BIF_1_HWDATA(1) => 
        Fabric_Master1_0_BIF_1_HWDATA(1), 
        Fabric_Master1_0_BIF_1_HWDATA(0) => 
        Fabric_Master1_0_BIF_1_HWDATA(0), 
        Fabric_Master2_0_BIF_1_HADDR(31) => 
        Fabric_Master2_0_BIF_1_HADDR(31), 
        Fabric_Master2_0_BIF_1_HADDR(30) => 
        Fabric_Master2_0_BIF_1_HADDR(30), 
        Fabric_Master2_0_BIF_1_HADDR(29) => 
        Fabric_Master2_0_BIF_1_HADDR(29), 
        Fabric_Master2_0_BIF_1_HADDR(28) => 
        Fabric_Master2_0_BIF_1_HADDR(28), 
        Fabric_Master2_0_BIF_1_HADDR(27) => 
        Fabric_Master2_0_BIF_1_HADDR(27), 
        Fabric_Master2_0_BIF_1_HADDR(26) => 
        Fabric_Master2_0_BIF_1_HADDR(26), 
        Fabric_Master2_0_BIF_1_HADDR(25) => 
        Fabric_Master2_0_BIF_1_HADDR(25), 
        Fabric_Master2_0_BIF_1_HADDR(24) => 
        Fabric_Master2_0_BIF_1_HADDR(24), 
        Fabric_Master2_0_BIF_1_HADDR(23) => 
        Fabric_Master2_0_BIF_1_HADDR(23), 
        Fabric_Master2_0_BIF_1_HADDR(22) => 
        Fabric_Master2_0_BIF_1_HADDR(22), 
        Fabric_Master2_0_BIF_1_HADDR(21) => 
        Fabric_Master2_0_BIF_1_HADDR(21), 
        Fabric_Master2_0_BIF_1_HADDR(20) => 
        Fabric_Master2_0_BIF_1_HADDR(20), 
        Fabric_Master2_0_BIF_1_HADDR(19) => 
        Fabric_Master2_0_BIF_1_HADDR(19), 
        Fabric_Master2_0_BIF_1_HADDR(18) => 
        Fabric_Master2_0_BIF_1_HADDR(18), 
        Fabric_Master2_0_BIF_1_HADDR(17) => 
        Fabric_Master2_0_BIF_1_HADDR(17), 
        Fabric_Master2_0_BIF_1_HADDR(16) => 
        Fabric_Master2_0_BIF_1_HADDR(16), 
        Fabric_Master2_0_BIF_1_HADDR(15) => 
        Fabric_Master2_0_BIF_1_HADDR(15), 
        Fabric_Master2_0_BIF_1_HADDR(14) => 
        Fabric_Master2_0_BIF_1_HADDR(14), 
        Fabric_Master2_0_BIF_1_HADDR(13) => 
        Fabric_Master2_0_BIF_1_HADDR(13), 
        Fabric_Master2_0_BIF_1_HADDR(12) => 
        Fabric_Master2_0_BIF_1_HADDR(12), 
        Fabric_Master2_0_BIF_1_HADDR(11) => 
        Fabric_Master2_0_BIF_1_HADDR(11), 
        Fabric_Master2_0_BIF_1_HADDR(10) => 
        Fabric_Master2_0_BIF_1_HADDR(10), 
        Fabric_Master2_0_BIF_1_HADDR(9) => 
        Fabric_Master2_0_BIF_1_HADDR(9), 
        Fabric_Master2_0_BIF_1_HADDR(8) => 
        Fabric_Master2_0_BIF_1_HADDR(8), 
        Fabric_Master2_0_BIF_1_HADDR(7) => 
        Fabric_Master2_0_BIF_1_HADDR(7), 
        Fabric_Master2_0_BIF_1_HADDR(6) => 
        Fabric_Master2_0_BIF_1_HADDR(6), 
        Fabric_Master2_0_BIF_1_HADDR(5) => 
        Fabric_Master2_0_BIF_1_HADDR(5), 
        Fabric_Master2_0_BIF_1_HADDR(4) => 
        Fabric_Master2_0_BIF_1_HADDR(4), 
        Fabric_Master2_0_BIF_1_HADDR(3) => 
        Fabric_Master2_0_BIF_1_HADDR(3), 
        Fabric_Master2_0_BIF_1_HADDR(2) => 
        Fabric_Master2_0_BIF_1_HADDR(2), 
        Fabric_Master2_0_BIF_1_HADDR(1) => 
        Fabric_Master2_0_BIF_1_HADDR(1), 
        Fabric_Master2_0_BIF_1_HADDR(0) => 
        Fabric_Master2_0_BIF_1_HADDR(0), 
        Fabric_Master2_0_BIF_1_HSIZE(1) => 
        Fabric_Master2_0_BIF_1_HSIZE(1), 
        Fabric_Master2_0_BIF_1_HSIZE(0) => 
        Fabric_Master2_0_BIF_1_HSIZE(0), 
        Fabric_Master2_0_BIF_1_HTRANS(1) => 
        Fabric_Master2_0_BIF_1_HTRANS(1), 
        Fabric_Master2_0_BIF_1_HWDATA(31) => 
        Fabric_Master2_0_BIF_1_HWDATA(31), 
        Fabric_Master2_0_BIF_1_HWDATA(30) => 
        Fabric_Master2_0_BIF_1_HWDATA(30), 
        Fabric_Master2_0_BIF_1_HWDATA(29) => 
        Fabric_Master2_0_BIF_1_HWDATA(29), 
        Fabric_Master2_0_BIF_1_HWDATA(28) => 
        Fabric_Master2_0_BIF_1_HWDATA(28), 
        Fabric_Master2_0_BIF_1_HWDATA(27) => 
        Fabric_Master2_0_BIF_1_HWDATA(27), 
        Fabric_Master2_0_BIF_1_HWDATA(26) => 
        Fabric_Master2_0_BIF_1_HWDATA(26), 
        Fabric_Master2_0_BIF_1_HWDATA(25) => 
        Fabric_Master2_0_BIF_1_HWDATA(25), 
        Fabric_Master2_0_BIF_1_HWDATA(24) => 
        Fabric_Master2_0_BIF_1_HWDATA(24), 
        Fabric_Master2_0_BIF_1_HWDATA(23) => 
        Fabric_Master2_0_BIF_1_HWDATA(23), 
        Fabric_Master2_0_BIF_1_HWDATA(22) => 
        Fabric_Master2_0_BIF_1_HWDATA(22), 
        Fabric_Master2_0_BIF_1_HWDATA(21) => 
        Fabric_Master2_0_BIF_1_HWDATA(21), 
        Fabric_Master2_0_BIF_1_HWDATA(20) => 
        Fabric_Master2_0_BIF_1_HWDATA(20), 
        Fabric_Master2_0_BIF_1_HWDATA(19) => 
        Fabric_Master2_0_BIF_1_HWDATA(19), 
        Fabric_Master2_0_BIF_1_HWDATA(18) => 
        Fabric_Master2_0_BIF_1_HWDATA(18), 
        Fabric_Master2_0_BIF_1_HWDATA(17) => 
        Fabric_Master2_0_BIF_1_HWDATA(17), 
        Fabric_Master2_0_BIF_1_HWDATA(16) => 
        Fabric_Master2_0_BIF_1_HWDATA(16), 
        Fabric_Master2_0_BIF_1_HWDATA(15) => 
        Fabric_Master2_0_BIF_1_HWDATA(15), 
        Fabric_Master2_0_BIF_1_HWDATA(14) => 
        Fabric_Master2_0_BIF_1_HWDATA(14), 
        Fabric_Master2_0_BIF_1_HWDATA(13) => 
        Fabric_Master2_0_BIF_1_HWDATA(13), 
        Fabric_Master2_0_BIF_1_HWDATA(12) => 
        Fabric_Master2_0_BIF_1_HWDATA(12), 
        Fabric_Master2_0_BIF_1_HWDATA(11) => 
        Fabric_Master2_0_BIF_1_HWDATA(11), 
        Fabric_Master2_0_BIF_1_HWDATA(10) => 
        Fabric_Master2_0_BIF_1_HWDATA(10), 
        Fabric_Master2_0_BIF_1_HWDATA(9) => 
        Fabric_Master2_0_BIF_1_HWDATA(9), 
        Fabric_Master2_0_BIF_1_HWDATA(8) => 
        Fabric_Master2_0_BIF_1_HWDATA(8), 
        Fabric_Master2_0_BIF_1_HWDATA(7) => 
        Fabric_Master2_0_BIF_1_HWDATA(7), 
        Fabric_Master2_0_BIF_1_HWDATA(6) => 
        Fabric_Master2_0_BIF_1_HWDATA(6), 
        Fabric_Master2_0_BIF_1_HWDATA(5) => 
        Fabric_Master2_0_BIF_1_HWDATA(5), 
        Fabric_Master2_0_BIF_1_HWDATA(4) => 
        Fabric_Master2_0_BIF_1_HWDATA(4), 
        Fabric_Master2_0_BIF_1_HWDATA(3) => 
        Fabric_Master2_0_BIF_1_HWDATA(3), 
        Fabric_Master2_0_BIF_1_HWDATA(2) => 
        Fabric_Master2_0_BIF_1_HWDATA(2), 
        Fabric_Master2_0_BIF_1_HWDATA(1) => 
        Fabric_Master2_0_BIF_1_HWDATA(1), 
        Fabric_Master2_0_BIF_1_HWDATA(0) => 
        Fabric_Master2_0_BIF_1_HWDATA(0), MMUART_0_TXD => 
        MMUART_0_TXD, MMUART_0_RXD => MMUART_0_RXD, 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F => 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, 
        Fabric_Master1_0_BIF_1_HREADYOUT => 
        Fabric_Master1_0_BIF_1_HREADYOUT, 
        Fabric_Master2_0_BIF_1_HREADYOUT => 
        Fabric_Master2_0_BIF_1_HREADYOUT, 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F => 
        AHB_Bus_Matrix_sb_MSS_TMP_0_MSS_RESET_N_M2F, 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F => 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F, 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK => 
        \AHB_Bus_Matrix_sb_0_FIC_0_CLK\, AND2_0_Y => AND2_0_Y, 
        Fabric_Master1_0_BIF_1_HSELx => 
        Fabric_Master1_0_BIF_1_HSELx, 
        Fabric_Master1_0_BIF_1_HWRITE => 
        Fabric_Master1_0_BIF_1_HWRITE, 
        Fabric_Master2_0_BIF_1_HSELx => 
        Fabric_Master2_0_BIF_1_HSELx, 
        Fabric_Master2_0_BIF_1_HWRITE => 
        Fabric_Master2_0_BIF_1_HWRITE, FIC_1_LOCK => FIC_1_LOCK);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    CCC_0 : AHB_Bus_Matrix_sb_CCC_0_FCCC
      port map(AHB_Bus_Matrix_sb_0_FIC_0_CLK => 
        \AHB_Bus_Matrix_sb_0_FIC_0_CLK\, 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK => 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK, FIC_1_LOCK => FIC_1_LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    SYSRESET_POR : SYSRESET
      port map(POWER_ON_RESET_N => POWER_ON_RESET_N, DEVRST_N => 
        DEVRST_N);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity Fabric_Master1 is

    port( HTRANS        : out   std_logic_vector(1 downto 0);
          HSIZE         : out   std_logic_vector(1 downto 0);
          HWDATA        : out   std_logic_vector(31 downto 0);
          HADDR         : out   std_logic_vector(31 downto 0);
          HRDATA        : in    std_logic_vector(31 downto 0);
          RESET_N       : in    std_logic;
          HCLK          : in    std_logic;
          HWRITE        : out   std_logic;
          HMASTLOCK     : out   std_logic;
          HREADY        : out   std_logic;
          HSEL          : out   std_logic;
          HREADYOUT     : in    std_logic;
          HRESP         : in    std_logic;
          INT1          : out   std_logic;
          MASTER1_START : in    std_logic;
          MASTER1_STOP  : in    std_logic
        );

end Fabric_Master1;

architecture DEF_ARCH of Fabric_Master1 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \HWDATA[0]\, \HADDR[0]\, \HADDR[1]\, \HADDR[2]\, 
        \HADDR[3]\, \HADDR[4]\, \HADDR[5]\, \HADDR[6]\, 
        \HADDR[7]\, \HADDR[8]\, \HADDR[9]\, \HADDR[10]\, 
        \HADDR[11]\, \HADDR[12]\, \HADDR[13]\, \HADDR[14]\, 
        \HADDR[15]\, \HADDR[16]\, \HADDR[17]\, \HADDR[18]\, 
        \HADDR[19]\, \HADDR[20]\, \HADDR[21]\, \HADDR[22]\, 
        \HADDR[23]\, \HADDR[24]\, \HADDR[25]\, \HADDR[26]\, 
        \HADDR[27]\, \HADDR[28]\, \HADDR[29]\, \HADDR[30]\, 
        \HADDR[31]\, \HMASTLOCK\, \HREADY\, HSEL_net_1, 
        \un8_hready_flngedge\, \un12_clock_count\, 
        \HADDR_TEMP_7_cry_2_0_RNO\, \ahb_states[5]_net_1\, 
        clock_count, \ahb_states[3]_net_1\, \ahb_states[2]_net_1\, 
        \ahb_states[1]_net_1\, \ahb_states[0]_net_1\, 
        \clock_count[0]_net_1\, \clock_count[1]_net_1\, 
        \clock_count[2]_net_1\, \clock_count[3]_net_1\, 
        \clock_count[4]_net_1\, \clock_count[5]_net_1\, 
        \clock_count[6]_net_1\, \clock_count[7]_net_1\, 
        \clock_count[8]_net_1\, \clock_count[9]_net_1\, 
        \clock_count[10]_net_1\, \clock_count[11]_net_1\, 
        \clock_count[12]_net_1\, \clock_count[13]_net_1\, 
        \clock_count[14]_net_1\, \clock_count[15]_net_1\, 
        \clock_count[16]_net_1\, \clock_count[17]_net_1\, 
        \clock_count[18]_net_1\, \clock_count[19]_net_1\, 
        \clock_count[20]_net_1\, \clock_count[21]_net_1\, 
        \clock_count[22]_net_1\, \clock_count[23]_net_1\, 
        \clock_count[24]_net_1\, \clock_count[25]_net_1\, 
        \clock_count[26]_net_1\, \clock_count[27]_net_1\, 
        \clock_count[28]_net_1\, \clock_count[29]_net_1\, 
        \clock_count[30]_net_1\, \clock_count[31]_net_1\, 
        \HrdyCount[0]_net_1\, \Res_Enable\, \HREADY_Int0\, 
        \Tr_Enable\, \HrdyCount[1]_net_1\, \ahb_states[6]_net_1\, 
        \HrdyCount_3[0]_net_1\, \HrdyCount_3[1]_net_1\, 
        \count_Temp1[0]_net_1\, \Recount[0]_net_1\, 
        \HADDR_TEMP_7[3]\, \HADDR_TEMP_7[4]\, \HADDR_TEMP_7[5]\, 
        \HADDR_TEMP_7[6]\, \HADDR_TEMP_7[7]\, \HADDR_TEMP_7[8]\, 
        \HADDR_TEMP_7[9]\, \HADDR_TEMP_7[10]\, \HADDR_TEMP_7[11]\, 
        \HADDR_TEMP_7[12]\, \HADDR_TEMP_7[13]\, 
        \HADDR_TEMP_7[14]\, \HADDR_TEMP_7[15]\, 
        \HADDR_TEMP_7[16]\, \HADDR_TEMP_7[17]\, 
        \HADDR_TEMP_7[18]\, \HADDR_TEMP_7[19]\, 
        \HADDR_TEMP_7[20]\, \HADDR_TEMP_7[21]\, 
        \HADDR_TEMP_7[22]\, \HADDR_TEMP_7[23]\, 
        \HADDR_TEMP_7[24]\, \HADDR_TEMP_7[25]\, 
        \HADDR_TEMP_7[26]\, \HADDR_TEMP_7[27]\, 
        \HADDR_TEMP_7[28]\, \HADDR_TEMP_7[29]\, 
        \HADDR_TEMP_7[30]\, \HADDR_TEMP_7[31]\, Recounte, 
        clock_counte, count_Temp1e, \un1_HSEL_1_u_ns\, 
        \htrans7_4_RNI0E4A\, \HREADY_flngedge\, \htrans11\, 
        \htrans9_2\, htrans9_3, \htrans7_4\, \htrans9\, 
        \htrans10\, htrans6_3, \htrans6\, \HADDR_TEMP_1_sqmuxa\, 
        \un2_hrdycount\, \un1_hready_flngedge\, \un1_hreadyout\, 
        \un5_clock_count\, \un7_clock_count\, N_151, N_230, N_200, 
        N_201, N_202, N_203, N_204, N_205, N_206, N_207, N_208, 
        N_209, N_210, N_211, N_212, N_213, N_214, N_215, N_216, 
        N_217, N_218, N_219, N_220, N_221, N_222, N_223, N_224, 
        N_225, N_226, N_227, N_228, N_229, 
        \un1_ahb_states_1_sqmuxa_2\, HADDR_TEMP_0_sqmuxa_out, 
        \HWRITE_DATA_TEMP_lm[0]\, \HWDATA[1]\, 
        \HWRITE_DATA_TEMP_cry[1]_net_1\, \HWRITE_DATA_TEMP_s[1]\, 
        \HWRITE_DATA_TEMP_lm[1]\, \HWDATA[2]\, 
        \HWRITE_DATA_TEMP_cry[2]_net_1\, \HWRITE_DATA_TEMP_s[2]\, 
        \HWRITE_DATA_TEMP_lm[2]\, \HWDATA[3]\, 
        \HWRITE_DATA_TEMP_cry[3]_net_1\, \HWRITE_DATA_TEMP_s[3]\, 
        \HWRITE_DATA_TEMP_lm[3]\, \HWDATA[4]\, 
        \HWRITE_DATA_TEMP_cry[4]_net_1\, \HWRITE_DATA_TEMP_s[4]\, 
        \HWRITE_DATA_TEMP_lm[4]\, \HWDATA[5]\, 
        \HWRITE_DATA_TEMP_cry[5]_net_1\, \HWRITE_DATA_TEMP_s[5]\, 
        \HWRITE_DATA_TEMP_lm[5]\, \HWDATA[6]\, 
        \HWRITE_DATA_TEMP_cry[6]_net_1\, \HWRITE_DATA_TEMP_s[6]\, 
        \HWRITE_DATA_TEMP_lm[6]\, \HWDATA[7]\, 
        \HWRITE_DATA_TEMP_cry[7]_net_1\, \HWRITE_DATA_TEMP_s[7]\, 
        \HWRITE_DATA_TEMP_lm[7]\, \HWDATA[8]\, 
        \HWRITE_DATA_TEMP_cry[8]_net_1\, \HWRITE_DATA_TEMP_s[8]\, 
        \HWRITE_DATA_TEMP_lm[8]\, \HWDATA[9]\, 
        \HWRITE_DATA_TEMP_cry[9]_net_1\, \HWRITE_DATA_TEMP_s[9]\, 
        \HWRITE_DATA_TEMP_lm[9]\, \HWDATA[10]\, 
        \HWRITE_DATA_TEMP_cry[10]_net_1\, 
        \HWRITE_DATA_TEMP_s[10]\, \HWRITE_DATA_TEMP_lm[10]\, 
        \HWDATA[11]\, \HWRITE_DATA_TEMP_cry[11]_net_1\, 
        \HWRITE_DATA_TEMP_s[11]\, \HWRITE_DATA_TEMP_lm[11]\, 
        \HWDATA[12]\, \HWRITE_DATA_TEMP_cry[12]_net_1\, 
        \HWRITE_DATA_TEMP_s[12]\, \HWRITE_DATA_TEMP_lm[12]\, 
        \HWDATA[13]\, \HWRITE_DATA_TEMP_cry[13]_net_1\, 
        \HWRITE_DATA_TEMP_s[13]\, \HWRITE_DATA_TEMP_lm[13]\, 
        \HWDATA[14]\, \HWRITE_DATA_TEMP_cry[14]_net_1\, 
        \HWRITE_DATA_TEMP_s[14]\, \HWRITE_DATA_TEMP_lm[14]\, 
        \HWDATA[15]\, \HWRITE_DATA_TEMP_cry[15]_net_1\, 
        \HWRITE_DATA_TEMP_s[15]\, \HWRITE_DATA_TEMP_lm[15]\, 
        \HWDATA[16]\, \HWRITE_DATA_TEMP_cry[16]_net_1\, 
        \HWRITE_DATA_TEMP_s[16]\, \HWRITE_DATA_TEMP_lm[16]\, 
        \HWDATA[17]\, \HWRITE_DATA_TEMP_cry[17]_net_1\, 
        \HWRITE_DATA_TEMP_s[17]\, \HWRITE_DATA_TEMP_lm[17]\, 
        \HWDATA[18]\, \HWRITE_DATA_TEMP_cry[18]_net_1\, 
        \HWRITE_DATA_TEMP_s[18]\, \HWRITE_DATA_TEMP_lm[18]\, 
        \HWDATA[19]\, \HWRITE_DATA_TEMP_cry[19]_net_1\, 
        \HWRITE_DATA_TEMP_s[19]\, \HWRITE_DATA_TEMP_lm[19]\, 
        \HWDATA[20]\, \HWRITE_DATA_TEMP_cry[20]_net_1\, 
        \HWRITE_DATA_TEMP_s[20]\, \HWRITE_DATA_TEMP_lm[20]\, 
        \HWDATA[21]\, \HWRITE_DATA_TEMP_cry[21]_net_1\, 
        \HWRITE_DATA_TEMP_s[21]\, \HWRITE_DATA_TEMP_lm[21]\, 
        \HWDATA[22]\, \HWRITE_DATA_TEMP_cry[22]_net_1\, 
        \HWRITE_DATA_TEMP_s[22]\, \HWRITE_DATA_TEMP_lm[22]\, 
        \HWDATA[23]\, \HWRITE_DATA_TEMP_cry[23]_net_1\, 
        \HWRITE_DATA_TEMP_s[23]\, \HWRITE_DATA_TEMP_lm[23]\, 
        \HWDATA[24]\, \HWRITE_DATA_TEMP_cry[24]_net_1\, 
        \HWRITE_DATA_TEMP_s[24]\, \HWRITE_DATA_TEMP_lm[24]\, 
        \HWDATA[25]\, \HWRITE_DATA_TEMP_cry[25]_net_1\, 
        \HWRITE_DATA_TEMP_s[25]\, \HWRITE_DATA_TEMP_lm[25]\, 
        \HWDATA[26]\, \HWRITE_DATA_TEMP_cry[26]_net_1\, 
        \HWRITE_DATA_TEMP_s[26]\, \HWRITE_DATA_TEMP_lm[26]\, 
        \HWDATA[27]\, \HWRITE_DATA_TEMP_cry[27]_net_1\, 
        \HWRITE_DATA_TEMP_s[27]\, \HWRITE_DATA_TEMP_lm[27]\, 
        \HWDATA[28]\, \HWRITE_DATA_TEMP_cry[28]_net_1\, 
        \HWRITE_DATA_TEMP_s[28]\, \HWRITE_DATA_TEMP_lm[28]\, 
        \HWDATA[29]\, \HWRITE_DATA_TEMP_cry[29]_net_1\, 
        \HWRITE_DATA_TEMP_s[29]\, \HWRITE_DATA_TEMP_lm[29]\, 
        \HWDATA[30]\, \HWRITE_DATA_TEMP_cry[30]_net_1\, 
        \HWRITE_DATA_TEMP_s[30]\, \HWRITE_DATA_TEMP_lm[30]\, 
        \HWDATA[31]\, \HWRITE_DATA_TEMP_s[31]_net_1\, 
        \HWRITE_DATA_TEMP_lm[31]\, \Recount_lm[0]\, 
        \Recount[1]_net_1\, \Recount_cry[1]_net_1\, 
        \Recount_s[1]\, \Recount_lm[1]\, \Recount[2]_net_1\, 
        \Recount_cry[2]_net_1\, \Recount_s[2]\, \Recount_lm[2]\, 
        \Recount[3]_net_1\, \Recount_cry[3]_net_1\, 
        \Recount_s[3]\, \Recount_lm[3]\, \Recount[4]_net_1\, 
        \Recount_cry[4]_net_1\, \Recount_s[4]\, \Recount_lm[4]\, 
        \Recount[5]_net_1\, \Recount_cry[5]_net_1\, 
        \Recount_s[5]\, \Recount_lm[5]\, \Recount[6]_net_1\, 
        \Recount_cry[6]_net_1\, \Recount_s[6]\, \Recount_lm[6]\, 
        \Recount[7]_net_1\, \Recount_cry[7]_net_1\, 
        \Recount_s[7]\, \Recount_lm[7]\, \Recount[8]_net_1\, 
        \Recount_cry[8]_net_1\, \Recount_s[8]\, \Recount_lm[8]\, 
        \Recount[9]_net_1\, \Recount_cry[9]_net_1\, 
        \Recount_s[9]\, \Recount_lm[9]\, \Recount[10]_net_1\, 
        \Recount_cry[10]_net_1\, \Recount_s[10]\, 
        \Recount_lm[10]\, \Recount[11]_net_1\, 
        \Recount_cry[11]_net_1\, \Recount_s[11]\, 
        \Recount_lm[11]\, \Recount[12]_net_1\, 
        \Recount_cry[12]_net_1\, \Recount_s[12]\, 
        \Recount_lm[12]\, \Recount[13]_net_1\, 
        \Recount_cry[13]_net_1\, \Recount_s[13]\, 
        \Recount_lm[13]\, \Recount[14]_net_1\, 
        \Recount_cry[14]_net_1\, \Recount_s[14]\, 
        \Recount_lm[14]\, \Recount[15]_net_1\, 
        \Recount_cry[15]_net_1\, \Recount_s[15]\, 
        \Recount_lm[15]\, \Recount[16]_net_1\, 
        \Recount_cry[16]_net_1\, \Recount_s[16]\, 
        \Recount_lm[16]\, \Recount[17]_net_1\, 
        \Recount_cry[17]_net_1\, \Recount_s[17]\, 
        \Recount_lm[17]\, \Recount[18]_net_1\, 
        \Recount_cry[18]_net_1\, \Recount_s[18]\, 
        \Recount_lm[18]\, \Recount[19]_net_1\, 
        \Recount_cry[19]_net_1\, \Recount_s[19]\, 
        \Recount_lm[19]\, \Recount[20]_net_1\, 
        \Recount_cry[20]_net_1\, \Recount_s[20]\, 
        \Recount_lm[20]\, \Recount[21]_net_1\, 
        \Recount_cry[21]_net_1\, \Recount_s[21]\, 
        \Recount_lm[21]\, \Recount[22]_net_1\, 
        \Recount_cry[22]_net_1\, \Recount_s[22]\, 
        \Recount_lm[22]\, \Recount[23]_net_1\, 
        \Recount_cry[23]_net_1\, \Recount_s[23]\, 
        \Recount_lm[23]\, \Recount[24]_net_1\, 
        \Recount_cry[24]_net_1\, \Recount_s[24]\, 
        \Recount_lm[24]\, \Recount[25]_net_1\, 
        \Recount_cry[25]_net_1\, \Recount_s[25]\, 
        \Recount_lm[25]\, \Recount[26]_net_1\, 
        \Recount_cry[26]_net_1\, \Recount_s[26]\, 
        \Recount_lm[26]\, \Recount[27]_net_1\, 
        \Recount_cry[27]_net_1\, \Recount_s[27]\, 
        \Recount_lm[27]\, \Recount[28]_net_1\, 
        \Recount_cry[28]_net_1\, \Recount_s[28]\, 
        \Recount_lm[28]\, \Recount[29]_net_1\, 
        \Recount_cry[29]_net_1\, \Recount_s[29]\, 
        \Recount_lm[29]\, \Recount[30]_net_1\, 
        \Recount_cry[30]_net_1\, \Recount_s[30]\, 
        \Recount_lm[30]\, \Recount[31]_net_1\, 
        \Recount_s[31]_net_1\, \Recount_lm[31]\, 
        \count_Temp1_lm[0]\, \count_Temp1[1]_net_1\, 
        \count_Temp1_cry[1]_net_1\, \count_Temp1_s[1]\, 
        \count_Temp1_lm[1]\, \count_Temp1[2]_net_1\, 
        \count_Temp1_cry[2]_net_1\, \count_Temp1_s[2]\, 
        \count_Temp1_lm[2]\, \count_Temp1[3]_net_1\, 
        \count_Temp1_cry[3]_net_1\, \count_Temp1_s[3]\, 
        \count_Temp1_lm[3]\, \count_Temp1[4]_net_1\, 
        \count_Temp1_cry[4]_net_1\, \count_Temp1_s[4]\, 
        \count_Temp1_lm[4]\, \count_Temp1[5]_net_1\, 
        \count_Temp1_cry[5]_net_1\, \count_Temp1_s[5]\, 
        \count_Temp1_lm[5]\, \count_Temp1[6]_net_1\, 
        \count_Temp1_cry[6]_net_1\, \count_Temp1_s[6]\, 
        \count_Temp1_lm[6]\, \count_Temp1[7]_net_1\, 
        \count_Temp1_cry[7]_net_1\, \count_Temp1_s[7]\, 
        \count_Temp1_lm[7]\, \count_Temp1[8]_net_1\, 
        \count_Temp1_cry[8]_net_1\, \count_Temp1_s[8]\, 
        \count_Temp1_lm[8]\, \count_Temp1[9]_net_1\, 
        \count_Temp1_cry[9]_net_1\, \count_Temp1_s[9]\, 
        \count_Temp1_lm[9]\, \count_Temp1[10]_net_1\, 
        \count_Temp1_cry[10]_net_1\, \count_Temp1_s[10]\, 
        \count_Temp1_lm[10]\, \count_Temp1[11]_net_1\, 
        \count_Temp1_cry[11]_net_1\, \count_Temp1_s[11]\, 
        \count_Temp1_lm[11]\, \count_Temp1[12]_net_1\, 
        \count_Temp1_cry[12]_net_1\, \count_Temp1_s[12]\, 
        \count_Temp1_lm[12]\, \count_Temp1[13]_net_1\, 
        \count_Temp1_cry[13]_net_1\, \count_Temp1_s[13]\, 
        \count_Temp1_lm[13]\, \count_Temp1[14]_net_1\, 
        \count_Temp1_cry[14]_net_1\, \count_Temp1_s[14]\, 
        \count_Temp1_lm[14]\, \count_Temp1[15]_net_1\, 
        \count_Temp1_cry[15]_net_1\, \count_Temp1_s[15]\, 
        \count_Temp1_lm[15]\, \count_Temp1[16]_net_1\, 
        \count_Temp1_cry[16]_net_1\, \count_Temp1_s[16]\, 
        \count_Temp1_lm[16]\, \count_Temp1[17]_net_1\, 
        \count_Temp1_cry[17]_net_1\, \count_Temp1_s[17]\, 
        \count_Temp1_lm[17]\, \count_Temp1[18]_net_1\, 
        \count_Temp1_cry[18]_net_1\, \count_Temp1_s[18]\, 
        \count_Temp1_lm[18]\, \count_Temp1[19]_net_1\, 
        \count_Temp1_cry[19]_net_1\, \count_Temp1_s[19]\, 
        \count_Temp1_lm[19]\, \count_Temp1[20]_net_1\, 
        \count_Temp1_cry[20]_net_1\, \count_Temp1_s[20]\, 
        \count_Temp1_lm[20]\, \count_Temp1[21]_net_1\, 
        \count_Temp1_cry[21]_net_1\, \count_Temp1_s[21]\, 
        \count_Temp1_lm[21]\, \count_Temp1[22]_net_1\, 
        \count_Temp1_cry[22]_net_1\, \count_Temp1_s[22]\, 
        \count_Temp1_lm[22]\, \count_Temp1[23]_net_1\, 
        \count_Temp1_cry[23]_net_1\, \count_Temp1_s[23]\, 
        \count_Temp1_lm[23]\, \count_Temp1[24]_net_1\, 
        \count_Temp1_cry[24]_net_1\, \count_Temp1_s[24]\, 
        \count_Temp1_lm[24]\, \count_Temp1[25]_net_1\, 
        \count_Temp1_cry[25]_net_1\, \count_Temp1_s[25]\, 
        \count_Temp1_lm[25]\, \count_Temp1[26]_net_1\, 
        \count_Temp1_cry[26]_net_1\, \count_Temp1_s[26]\, 
        \count_Temp1_lm[26]\, \count_Temp1[27]_net_1\, 
        \count_Temp1_cry[27]_net_1\, \count_Temp1_s[27]\, 
        \count_Temp1_lm[27]\, \count_Temp1[28]_net_1\, 
        \count_Temp1_cry[28]_net_1\, \count_Temp1_s[28]\, 
        \count_Temp1_lm[28]\, \count_Temp1[29]_net_1\, 
        \count_Temp1_cry[29]_net_1\, \count_Temp1_s[29]\, 
        \count_Temp1_lm[29]\, \count_Temp1[30]_net_1\, 
        \count_Temp1_cry[30]_net_1\, \count_Temp1_s[30]\, 
        \count_Temp1_lm[30]\, \count_Temp1[31]_net_1\, 
        \count_Temp1_s[31]_net_1\, \count_Temp1_lm[31]\, 
        \clock_count_cry[0]_net_1\, \clock_count_s[0]\, 
        \clock_count_cry[1]_net_1\, \clock_count_s[1]\, 
        \clock_count_cry[2]_net_1\, \clock_count_s[2]\, 
        \clock_count_cry[3]_net_1\, \clock_count_s[3]\, 
        \clock_count_cry[4]_net_1\, \clock_count_s[4]\, 
        \clock_count_cry[5]_net_1\, \clock_count_s[5]\, 
        \clock_count_cry[6]_net_1\, \clock_count_s[6]\, 
        \clock_count_cry[7]_net_1\, \clock_count_s[7]\, 
        \clock_count_cry[8]_net_1\, \clock_count_s[8]\, 
        \clock_count_cry[9]_net_1\, \clock_count_s[9]\, 
        \clock_count_cry[10]_net_1\, \clock_count_s[10]\, 
        \clock_count_cry[11]_net_1\, \clock_count_s[11]\, 
        \clock_count_cry[12]_net_1\, \clock_count_s[12]\, 
        \clock_count_cry[13]_net_1\, \clock_count_s[13]\, 
        \clock_count_cry[14]_net_1\, \clock_count_s[14]\, 
        \clock_count_cry[15]_net_1\, \clock_count_s[15]\, 
        \clock_count_cry[16]_net_1\, \clock_count_s[16]\, 
        \clock_count_cry[17]_net_1\, \clock_count_s[17]\, 
        \clock_count_cry[18]_net_1\, \clock_count_s[18]\, 
        \clock_count_cry[19]_net_1\, \clock_count_s[19]\, 
        \clock_count_cry[20]_net_1\, \clock_count_s[20]\, 
        \clock_count_cry[21]_net_1\, \clock_count_s[21]\, 
        \clock_count_cry[22]_net_1\, \clock_count_s[22]\, 
        \clock_count_cry[23]_net_1\, \clock_count_s[23]\, 
        \clock_count_cry[24]_net_1\, \clock_count_s[24]\, 
        \clock_count_cry[25]_net_1\, \clock_count_s[25]\, 
        \clock_count_cry[26]_net_1\, \clock_count_s[26]\, 
        \clock_count_cry[27]_net_1\, \clock_count_s[27]\, 
        \clock_count_cry[28]_net_1\, \clock_count_s[28]\, 
        \clock_count_cry[29]_net_1\, \clock_count_s[29]\, 
        \clock_count_cry[30]_net_1\, \clock_count_s[30]\, 
        \clock_count_s[31]_net_1\, \HADDR_TEMP_7[0]_net_1\, 
        \HADDR_TEMP_7[1]_net_1\, HADDR_TEMP_7_cry_2, 
        \HADDR_TEMP_7_cry_3\, \HADDR_TEMP_7_cry_4\, 
        \HADDR_TEMP_7_cry_5\, \HADDR_TEMP_7_cry_6\, 
        \HADDR_TEMP_7_cry_7\, \HADDR_TEMP_7_cry_8\, 
        \HADDR_TEMP_7_cry_9\, \HADDR_TEMP_7_cry_10\, 
        \HADDR_TEMP_7_cry_11\, \HADDR_TEMP_7_cry_12\, 
        \HADDR_TEMP_7_cry_13\, \HADDR_TEMP_7_cry_14\, 
        \HADDR_TEMP_7_cry_15\, \HADDR_TEMP_7_cry_16\, 
        \HADDR_TEMP_7_cry_17\, \HADDR_TEMP_7_cry_18\, 
        \HADDR_TEMP_7_cry_19\, \HADDR_TEMP_7_cry_20\, 
        \HADDR_TEMP_7_cry_21\, \HADDR_TEMP_7_cry_22\, 
        \HADDR_TEMP_7_cry_23\, \HADDR_TEMP_7_cry_24\, 
        \HADDR_TEMP_7_cry_25\, \HADDR_TEMP_7_cry_26\, 
        \HADDR_TEMP_7_cry_27\, \HADDR_TEMP_7_cry_28\, 
        \HADDR_TEMP_7_cry_29\, \HADDR_TEMP_7_cry_30\, 
        \htrans11_1\, \htrans6_1\, \un7_clock_count_13\, 
        \un7_clock_count_16\, \un7_clock_count_17\, 
        \un7_clock_count_18\, \un7_clock_count_19\, 
        \un7_clock_count_20\, \un7_clock_count_21\, 
        \un7_clock_count_23\, \un7_clock_count_27\, 
        \un7_clock_count_28\, \HADDR_TEMP_1_sqmuxa_0\, 
        \un1_hreadyout_6\, \un1_hreadyout_7\, \un1_hreadyout_8\, 
        \un1_htrans6_4_1\, clock_countlde_0, 
        \un1_ahb_states_1_sqmuxa_0\, \un1_ahb_states_1_sqmuxa_1\, 
        \ahb_states_i_0[0]\, un1_htrans6_4_i_0, 
        un1_ahb_states_1_sqmuxa_i_0, un1_htrans6_2_i_0, 
        un1_htrans10_2_i_0, \un1_HSEL_1_u_ns_1\, 
        \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\, N_6, g2_1, 
        clock_count_s_134_FCO, count_Temp1_s_135_FCO, 
        Recount_s_136_FCO, HWRITE_DATA_TEMP_s_137_FCO, 
        HADDR_TEMP_7_cry_2_0_Y, un1_reset_n_2_i, \un1_reset_n_2\
         : std_logic;

begin 

    HTRANS(0) <= \HMASTLOCK\;
    HWDATA(31) <= \HWDATA[31]\;
    HWDATA(30) <= \HWDATA[30]\;
    HWDATA(29) <= \HWDATA[29]\;
    HWDATA(28) <= \HWDATA[28]\;
    HWDATA(27) <= \HWDATA[27]\;
    HWDATA(26) <= \HWDATA[26]\;
    HWDATA(25) <= \HWDATA[25]\;
    HWDATA(24) <= \HWDATA[24]\;
    HWDATA(23) <= \HWDATA[23]\;
    HWDATA(22) <= \HWDATA[22]\;
    HWDATA(21) <= \HWDATA[21]\;
    HWDATA(20) <= \HWDATA[20]\;
    HWDATA(19) <= \HWDATA[19]\;
    HWDATA(18) <= \HWDATA[18]\;
    HWDATA(17) <= \HWDATA[17]\;
    HWDATA(16) <= \HWDATA[16]\;
    HWDATA(15) <= \HWDATA[15]\;
    HWDATA(14) <= \HWDATA[14]\;
    HWDATA(13) <= \HWDATA[13]\;
    HWDATA(12) <= \HWDATA[12]\;
    HWDATA(11) <= \HWDATA[11]\;
    HWDATA(10) <= \HWDATA[10]\;
    HWDATA(9) <= \HWDATA[9]\;
    HWDATA(8) <= \HWDATA[8]\;
    HWDATA(7) <= \HWDATA[7]\;
    HWDATA(6) <= \HWDATA[6]\;
    HWDATA(5) <= \HWDATA[5]\;
    HWDATA(4) <= \HWDATA[4]\;
    HWDATA(3) <= \HWDATA[3]\;
    HWDATA(2) <= \HWDATA[2]\;
    HWDATA(1) <= \HWDATA[1]\;
    HWDATA(0) <= \HWDATA[0]\;
    HADDR(31) <= \HADDR[31]\;
    HADDR(30) <= \HADDR[30]\;
    HADDR(29) <= \HADDR[29]\;
    HADDR(28) <= \HADDR[28]\;
    HADDR(27) <= \HADDR[27]\;
    HADDR(26) <= \HADDR[26]\;
    HADDR(25) <= \HADDR[25]\;
    HADDR(24) <= \HADDR[24]\;
    HADDR(23) <= \HADDR[23]\;
    HADDR(22) <= \HADDR[22]\;
    HADDR(21) <= \HADDR[21]\;
    HADDR(20) <= \HADDR[20]\;
    HADDR(19) <= \HADDR[19]\;
    HADDR(18) <= \HADDR[18]\;
    HADDR(17) <= \HADDR[17]\;
    HADDR(16) <= \HADDR[16]\;
    HADDR(15) <= \HADDR[15]\;
    HADDR(14) <= \HADDR[14]\;
    HADDR(13) <= \HADDR[13]\;
    HADDR(12) <= \HADDR[12]\;
    HADDR(11) <= \HADDR[11]\;
    HADDR(10) <= \HADDR[10]\;
    HADDR(9) <= \HADDR[9]\;
    HADDR(8) <= \HADDR[8]\;
    HADDR(7) <= \HADDR[7]\;
    HADDR(6) <= \HADDR[6]\;
    HADDR(5) <= \HADDR[5]\;
    HADDR(4) <= \HADDR[4]\;
    HADDR(3) <= \HADDR[3]\;
    HADDR(2) <= \HADDR[2]\;
    HADDR(1) <= \HADDR[1]\;
    HADDR(0) <= \HADDR[0]\;
    HMASTLOCK <= \HMASTLOCK\;
    HREADY <= \HREADY\;
    HSEL <= HSEL_net_1;

    HADDR_TEMP_7_cry_16 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[16]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_15\, S => 
        \HADDR_TEMP_7[16]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_16\);
    
    \count_Temp1_lm_0[13]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[13]\, 
        Y => \count_Temp1_lm[13]\);
    
    \HWRITE_DATA_TEMP[18]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[18]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[18]\);
    
    HADDR_TEMP_7_cry_23 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[23]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_22\, S => 
        \HADDR_TEMP_7[23]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_23\);
    
    \Recount[22]\ : SLE
      port map(D => \Recount_lm[22]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[22]_net_1\);
    
    \HrdyCount[1]\ : SLE
      port map(D => \HrdyCount_3[1]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HrdyCount[1]_net_1\);
    
    \HADDR_TEMP[20]\ : SLE
      port map(D => \HADDR_TEMP_7[20]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[20]\);
    
    \ahb_states[0]\ : SLE
      port map(D => \ahb_states[2]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[0]_net_1\);
    
    HADDR_TEMP_7_cry_25 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[25]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_24\, S => 
        \HADDR_TEMP_7[25]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_25\);
    
    \Recount[4]\ : SLE
      port map(D => \Recount_lm[4]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[4]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[15]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[15]\, C => N_214, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[15]\);
    
    \HWRITE_DATA_TEMP_lm_0[31]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[31]_net_1\, C => N_230, D => 
        \htrans11\, Y => \HWRITE_DATA_TEMP_lm[31]\);
    
    \Recount_lm_0[11]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[11]\, Y => 
        \Recount_lm[11]\);
    
    un1_hreadyout : CFG4
      generic map(INIT => x"8000")

      port map(A => \un1_hreadyout_8\, B => \un1_hreadyout_7\, C
         => \un1_hreadyout_6\, D => HREADYOUT, Y => 
        \un1_hreadyout\);
    
    \Recount[17]\ : SLE
      port map(D => \Recount_lm[17]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[17]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[6]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[5]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[6]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[6]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[11]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[11]_net_1\, D => \Recount[11]_net_1\, Y => 
        N_210);
    
    \HADDR_TEMP[2]\ : SLE
      port map(D => HADDR_TEMP_7_cry_2_0_Y, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[2]\);
    
    \count_Temp1[17]\ : SLE
      port map(D => \count_Temp1_lm[17]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[17]_net_1\);
    
    \clock_count[4]\ : SLE
      port map(D => \clock_count_s[4]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[4]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[10]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[10]_net_1\, D => \Recount[10]_net_1\, Y => 
        N_209);
    
    \clock_count[22]\ : SLE
      port map(D => \clock_count_s[22]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[22]_net_1\);
    
    \Recount_lm_0[1]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[1]\, Y => \Recount_lm[1]\);
    
    \HWRITE_DATA_TEMP[21]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[21]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[21]\);
    
    \ahb_states[4]\ : SLE
      port map(D => \ahb_states[5]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => clock_count);
    
    HADDR_TEMP_7_cry_27 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[27]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_26\, S => 
        \HADDR_TEMP_7[27]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_27\);
    
    \Recount[27]\ : SLE
      port map(D => \Recount_lm[27]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[27]_net_1\);
    
    \Recount[15]\ : SLE
      port map(D => \Recount_lm[15]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[15]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[21]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[21]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[20]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[21]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[21]_net_1\);
    
    \Recount_cry[15]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[15]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[14]_net_1\, S => \Recount_s[15]\, Y => OPEN, 
        FCO => \Recount_cry[15]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[14]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[14]\, C => N_213, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[14]\);
    
    \HWRITE_DATA_TEMP[27]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[27]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[27]\);
    
    \count_Temp1[14]\ : SLE
      port map(D => \count_Temp1_lm[14]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[14]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[18]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[18]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[17]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[18]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[18]_net_1\);
    
    \count_Temp1_lm_0[10]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[10]\, 
        Y => \count_Temp1_lm[10]\);
    
    \HWRITE_DATA_TEMP_lm_0[7]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[7]\, C => N_206, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[7]\);
    
    \HWRITE_DATA_TEMP[31]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[31]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[31]\);
    
    \HWRITE_DATA_TEMP[3]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[3]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[3]\);
    
    \count_Temp1[16]\ : SLE
      port map(D => \count_Temp1_lm[16]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[16]_net_1\);
    
    \clock_count_cry[17]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[17]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[16]_net_1\, S => \clock_count_s[17]\, Y
         => OPEN, FCO => \clock_count_cry[17]_net_1\);
    
    \ahb_states_RNI6OC1[0]\ : CFG1
      generic map(INIT => "01")

      port map(A => \ahb_states[0]_net_1\, Y => 
        \ahb_states_i_0[0]\);
    
    \count_Temp1[8]\ : SLE
      port map(D => \count_Temp1_lm[8]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[8]_net_1\);
    
    \Recount[25]\ : SLE
      port map(D => \Recount_lm[25]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[25]_net_1\);
    
    \Recount_cry[17]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[17]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[16]_net_1\, S => \Recount_s[17]\, Y => OPEN, 
        FCO => \Recount_cry[17]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[4]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[4]\, C => N_203, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[4]\);
    
    \clock_count[5]\ : SLE
      port map(D => \clock_count_s[5]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[5]_net_1\);
    
    htrans9_2 : CFG2
      generic map(INIT => x"1")

      port map(A => \ahb_states[3]_net_1\, B => 
        \ahb_states[5]_net_1\, Y => \htrans9_2\);
    
    \count_Temp1_lm_0[22]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[22]\, 
        Y => \count_Temp1_lm[22]\);
    
    \HWRITE_DATA_TEMP_cry[23]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[23]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[22]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[23]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[23]_net_1\);
    
    un1_reset_n_2_RNIK4E5 : CLKINT
      port map(A => \un1_reset_n_2\, Y => un1_reset_n_2_i);
    
    \HWRITE_DATA_TEMP_cry[8]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[8]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[7]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[8]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[8]_net_1\);
    
    \count_Temp1_cry[15]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[15]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[14]_net_1\, S => \count_Temp1_s[15]\, Y
         => OPEN, FCO => \count_Temp1_cry[15]_net_1\);
    
    \clock_count[28]\ : SLE
      port map(D => \clock_count_s[28]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[28]_net_1\);
    
    HADDR_TEMP_7_cry_5 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[5]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_4\, S => 
        \HADDR_TEMP_7[5]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_5\);
    
    HADDR_TEMP_7_cry_14 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[14]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_13\, S => 
        \HADDR_TEMP_7[14]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_14\);
    
    \count_Temp1_lm_0[3]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[3]\, Y
         => \count_Temp1_lm[3]\);
    
    un5_clock_count : CFG3
      generic map(INIT => x"C8")

      port map(A => \ahb_states[1]_net_1\, B => \un7_clock_count\, 
        C => \ahb_states[2]_net_1\, Y => \un5_clock_count\);
    
    \HWRITE_DATA_TEMP_lm_0[13]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[13]\, C => N_212, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[13]\);
    
    \count_Temp1_cry[17]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[17]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[16]_net_1\, S => \count_Temp1_s[17]\, Y
         => OPEN, FCO => \count_Temp1_cry[17]_net_1\);
    
    \count_Temp1[0]\ : SLE
      port map(D => \count_Temp1_lm[0]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[0]_net_1\);
    
    \Recount_lm_0[25]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[25]\, Y => 
        \Recount_lm[25]\);
    
    \HWRITE_DATA_TEMP[20]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[20]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[20]\);
    
    un17_clock_count_x_RNI3IKC : CFG4
      generic map(INIT => x"AA80")

      port map(A => \un7_clock_count\, B => \ahb_states[3]_net_1\, 
        C => \HREADY_flngedge\, D => N_151, Y => Recounte);
    
    \Recount_lm_0[26]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[26]\, Y => 
        \Recount_lm[26]\);
    
    HADDR_TEMP_7_cry_26 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[26]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_25\, S => 
        \HADDR_TEMP_7[26]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_26\);
    
    \count_Temp1_lm_0[4]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[4]\, Y
         => \count_Temp1_lm[4]\);
    
    \HWRITE_DATA_TEMP_cry[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[7]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[6]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[7]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[7]_net_1\);
    
    \HADDR_TEMP[13]\ : SLE
      port map(D => \HADDR_TEMP_7[13]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[13]\);
    
    \clock_count[16]\ : SLE
      port map(D => \clock_count_s[16]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[16]_net_1\);
    
    \Recount_lm_0[17]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[17]\, Y => 
        \Recount_lm[17]\);
    
    \count_Temp1_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[3]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[2]_net_1\, S => \count_Temp1_s[3]\, Y
         => OPEN, FCO => \count_Temp1_cry[3]_net_1\);
    
    htrans9_RNIGB0O1 : CFG4
      generic map(INIT => x"FFE0")

      port map(A => \htrans10\, B => \htrans9\, C => 
        \HREADY_flngedge\, D => clock_countlde_0, Y => 
        clock_counte);
    
    \HADDR_TEMP[15]\ : SLE
      port map(D => \HADDR_TEMP_7[15]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HMASTLOCK\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[15]\);
    
    \Recount_cry[19]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[19]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[18]_net_1\, S => \Recount_s[19]\, Y => OPEN, 
        FCO => \Recount_cry[19]_net_1\);
    
    \Recount[13]\ : SLE
      port map(D => \Recount_lm[13]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[13]_net_1\);
    
    \HWRITE_DATA_TEMP[11]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[11]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[11]\);
    
    \count_Temp1_cry[25]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[25]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[24]_net_1\, S => \count_Temp1_s[25]\, Y
         => OPEN, FCO => \count_Temp1_cry[25]_net_1\);
    
    \Recount_lm_0[3]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[3]\, Y => \Recount_lm[3]\);
    
    \Recount[0]\ : SLE
      port map(D => \Recount_lm[0]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[0]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[25]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[25]_net_1\, D => \Recount[25]_net_1\, Y => 
        N_224);
    
    \HWRITE_DATA_TEMP[30]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[30]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[30]\);
    
    \HWRITE_DATA_TEMP_6_0[5]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[5]_net_1\, D => \Recount[5]_net_1\, Y => 
        N_204);
    
    \HADDR_TEMP[30]\ : SLE
      port map(D => \HADDR_TEMP_7[30]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[30]\);
    
    \HWRITE_DATA_TEMP_lm_0[18]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[18]\, C => N_217, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[18]\);
    
    \HSEL\ : SLE
      port map(D => \un1_HSEL_1_u_ns\, CLK => HCLK, EN => RESET_N, 
        ALn => \HREADY\, ADn => \HREADY\, SLn => \HREADY\, SD => 
        \HMASTLOCK\, LAT => \HMASTLOCK\, Q => HSEL_net_1);
    
    \count_Temp1_cry[27]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[27]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[26]_net_1\, S => \count_Temp1_s[27]\, Y
         => OPEN, FCO => \count_Temp1_cry[27]_net_1\);
    
    \HWRITE_DATA_TEMP[17]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[17]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[17]\);
    
    \count_Temp1[4]\ : SLE
      port map(D => \count_Temp1_lm[4]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[4]_net_1\);
    
    \Recount[23]\ : SLE
      port map(D => \Recount_lm[23]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[23]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[2]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[1]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[2]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[2]_net_1\);
    
    \Recount_cry[11]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[11]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[10]_net_1\, S => \Recount_s[11]\, Y => OPEN, 
        FCO => \Recount_cry[11]_net_1\);
    
    \HWRITE_DATA_TEMP[1]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[1]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[1]\);
    
    \count_Temp1[13]\ : SLE
      port map(D => \count_Temp1_lm[13]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[13]_net_1\);
    
    INT1_TEMP : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans10_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => INT1);
    
    htrans11_1 : CFG4
      generic map(INIT => x"0002")

      port map(A => \ahb_states[0]_net_1\, B => 
        \ahb_states[3]_net_1\, C => \ahb_states[2]_net_1\, D => 
        \ahb_states[1]_net_1\, Y => \htrans11_1\);
    
    \count_Temp1_lm_0[29]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[29]\, 
        Y => \count_Temp1_lm[29]\);
    
    \HWRITE_DATA_TEMP_lm_0[17]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[17]\, C => N_216, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[17]\);
    
    \HWRITE_DATA_TEMP_lm_0[26]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[26]\, C => N_225, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[26]\);
    
    htrans7_4 : CFG4
      generic map(INIT => x"0010")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => clock_count, D => 
        \ahb_states[3]_net_1\, Y => \htrans7_4\);
    
    \count_Temp1[19]\ : SLE
      port map(D => \count_Temp1_lm[19]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[19]_net_1\);
    
    \HADDR_TEMP[14]\ : SLE
      port map(D => \HADDR_TEMP_7[14]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[14]\);
    
    \GND\ : GND
      port map(Y => \HMASTLOCK\);
    
    \count_Temp1[10]\ : SLE
      port map(D => \count_Temp1_lm[10]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[10]_net_1\);
    
    HADDR_TEMP_7_cry_3 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[3]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => HADDR_TEMP_7_cry_2, S => 
        \HADDR_TEMP_7[3]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_3\);
    
    \Recount_cry[9]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[9]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[8]_net_1\, S => \Recount_s[9]\, Y => OPEN, 
        FCO => \Recount_cry[9]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0_1_0[0]\ : CFG4
      generic map(INIT => x"078F")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[0]_net_1\, D => \Recount[0]_net_1\, Y => 
        \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\);
    
    \count_Temp1[11]\ : SLE
      port map(D => \count_Temp1_lm[11]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[11]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[20]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[20]\, C => N_219, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[20]\);
    
    \HWRITE_DATA_TEMP_lm_0[6]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[6]\, C => N_205, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[6]\);
    
    \HWRITE_DATA_TEMP[10]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[10]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[10]\);
    
    \Recount_lm_0[8]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[8]\, Y => \Recount_lm[8]\);
    
    \Recount_lm_0[22]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[22]\, Y => 
        \Recount_lm[22]\);
    
    HADDR_TEMP_7_cry_10 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[10]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_9\, S => 
        \HADDR_TEMP_7[10]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_10\);
    
    \count_Temp1_cry[8]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[8]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[7]_net_1\, S => \count_Temp1_s[8]\, Y
         => OPEN, FCO => \count_Temp1_cry[8]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[30]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[30]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[29]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[30]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[30]_net_1\);
    
    HADDR_TEMP_7_cry_24 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[24]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_23\, S => 
        \HADDR_TEMP_7[24]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_24\);
    
    \HADDR_TEMP[5]\ : SLE
      port map(D => \HADDR_TEMP_7[5]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[5]\);
    
    \count_Temp1_lm_0[17]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[17]\, 
        Y => \count_Temp1_lm[17]\);
    
    \Recount_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[4]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[3]_net_1\, S => \Recount_s[4]\, Y => OPEN, 
        FCO => \Recount_cry[4]_net_1\);
    
    \count_Temp1_cry[11]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[11]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[10]_net_1\, S => \count_Temp1_s[11]\, Y
         => OPEN, FCO => \count_Temp1_cry[11]_net_1\);
    
    \clock_count[30]\ : SLE
      port map(D => \clock_count_s[30]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[30]_net_1\);
    
    \Recount_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[6]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[5]_net_1\, S => \Recount_s[6]\, Y => OPEN, 
        FCO => \Recount_cry[6]_net_1\);
    
    HADDR_TEMP_7_cry_9 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[9]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_8\, S => 
        \HADDR_TEMP_7[9]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_9\);
    
    \Recount_cry[26]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[26]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[25]_net_1\, S => \Recount_s[26]\, Y => OPEN, 
        FCO => \Recount_cry[26]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[3]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[3]_net_1\, D => \Recount[3]_net_1\, Y => 
        N_202);
    
    \HADDR_TEMP_7[0]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \htrans11\, B => \HADDR[0]\, Y => 
        \HADDR_TEMP_7[0]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[1]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[1]\, C => N_200, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[1]\);
    
    \HWRITE_DATA_TEMP[26]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[26]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[26]\);
    
    \HWRITE_DATA_TEMP_6_0[15]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[15]_net_1\, D => \Recount[15]_net_1\, Y => 
        N_214);
    
    \count_Temp1_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[5]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[4]_net_1\, S => \count_Temp1_s[5]\, Y
         => OPEN, FCO => \count_Temp1_cry[5]_net_1\);
    
    \clock_count_cry[24]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[24]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[23]_net_1\, S => \clock_count_s[24]\, Y
         => OPEN, FCO => \clock_count_cry[24]_net_1\);
    
    \count_Temp1[28]\ : SLE
      port map(D => \count_Temp1_lm[28]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[28]_net_1\);
    
    htrans6_1 : CFG3
      generic map(INIT => x"02")

      port map(A => \ahb_states[6]_net_1\, B => 
        \ahb_states[1]_net_1\, C => \ahb_states[0]_net_1\, Y => 
        \htrans6_1\);
    
    un12_clock_count : CFG4
      generic map(INIT => x"2000")

      port map(A => \un7_clock_count\, B => HREADYOUT, C => 
        \HREADY_Int0\, D => \ahb_states[3]_net_1\, Y => 
        \un12_clock_count\);
    
    \clock_count_cry[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[1]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[0]_net_1\, S => \clock_count_s[1]\, Y
         => OPEN, FCO => \clock_count_cry[1]_net_1\);
    
    \clock_count[25]\ : SLE
      port map(D => \clock_count_s[25]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[25]_net_1\);
    
    \count_Temp1_lm_0[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[2]\, Y
         => \count_Temp1_lm[2]\);
    
    \clock_count[13]\ : SLE
      port map(D => \clock_count_s[13]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[13]_net_1\);
    
    un1_ahb_states_1_sqmuxa_0 : CFG4
      generic map(INIT => x"7530")

      port map(A => \un2_hrdycount\, B => MASTER1_STOP, C => 
        \ahb_states[2]_net_1\, D => \ahb_states[5]_net_1\, Y => 
        \un1_ahb_states_1_sqmuxa_0\);
    
    \Recount_lm_0[29]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[29]\, Y => 
        \Recount_lm[29]\);
    
    \HWRITE_DATA_TEMP_lm_0[2]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[2]\, C => N_201, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[2]\);
    
    \HADDR_TEMP[9]\ : SLE
      port map(D => \HADDR_TEMP_7[9]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[9]\);
    
    \HWRITE_DATA_TEMP_6_0[4]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[4]_net_1\, D => \Recount[4]_net_1\, Y => 
        N_203);
    
    \HWRITE_DATA_TEMP[0]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[0]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[0]\);
    
    \HrdyCount_3[1]\ : CFG4
      generic map(INIT => x"286C")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, C => \un1_hready_flngedge\, D => 
        clock_count, Y => \HrdyCount_3[1]_net_1\);
    
    \count_Temp1_cry[21]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[21]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[20]_net_1\, S => \count_Temp1_s[21]\, Y
         => OPEN, FCO => \count_Temp1_cry[21]_net_1\);
    
    \count_Temp1_cry[16]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[16]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[15]_net_1\, S => \count_Temp1_s[16]\, Y
         => OPEN, FCO => \count_Temp1_cry[16]_net_1\);
    
    \clock_count_cry[21]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[21]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[20]_net_1\, S => \clock_count_s[21]\, Y
         => OPEN, FCO => \clock_count_cry[21]_net_1\);
    
    \clock_count_cry[20]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[20]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[19]_net_1\, S => \clock_count_s[20]\, Y
         => OPEN, FCO => \clock_count_cry[20]_net_1\);
    
    un1_hready_flngedge : CFG3
      generic map(INIT => x"08")

      port map(A => \ahb_states[5]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, Y => \un1_hready_flngedge\);
    
    \Recount_lm_0[0]\ : CFG4
      generic map(INIT => x"0D0F")

      port map(A => \ahb_states[3]_net_1\, B => HREADYOUT, C => 
        \Recount[0]_net_1\, D => \HREADY_Int0\, Y => 
        \Recount_lm[0]\);
    
    \HWRITE_DATA_TEMP_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[4]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[3]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[4]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[4]_net_1\);
    
    clock_count_s_134 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => clock_count, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, Y => OPEN, 
        FCO => clock_count_s_134_FCO);
    
    \Recount_lm_0[5]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[5]\, Y => \Recount_lm[5]\);
    
    \Recount_lm_0[14]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[14]\, Y => 
        \Recount_lm[14]\);
    
    \HADDR_TEMP[7]\ : SLE
      port map(D => \HADDR_TEMP_7[7]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[7]\);
    
    HADDR_TEMP_7_cry_11 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[11]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_10\, S => 
        \HADDR_TEMP_7[11]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_11\);
    
    \HWRITE_DATA_TEMP_6_0[9]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[9]_net_1\, D => \Recount[9]_net_1\, Y => 
        N_208);
    
    \HADDR_TEMP[3]\ : SLE
      port map(D => \HADDR_TEMP_7[3]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[3]\);
    
    \clock_count[24]\ : SLE
      port map(D => \clock_count_s[24]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[24]_net_1\);
    
    \clock_count[17]\ : SLE
      port map(D => \clock_count_s[17]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[17]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[5]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[4]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[5]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[5]_net_1\);
    
    \HWRITE_DATA_TEMP[9]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[9]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[9]\);
    
    \clock_count[10]\ : SLE
      port map(D => \clock_count_s[10]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[10]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[9]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[9]\, C => N_208, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[9]\);
    
    \count_Temp1_lm_0[6]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[6]\, Y
         => \count_Temp1_lm[6]\);
    
    \clock_count_cry[28]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[28]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[27]_net_1\, S => \clock_count_s[28]\, Y
         => OPEN, FCO => \clock_count_cry[28]_net_1\);
    
    un1_htrans6_4_1 : CFG3
      generic map(INIT => x"FE")

      port map(A => \htrans6\, B => \ahb_states[5]_net_1\, C => 
        \htrans9\, Y => \un1_htrans6_4_1\);
    
    \count_Temp1[6]\ : SLE
      port map(D => \count_Temp1_lm[6]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[6]_net_1\);
    
    \clock_count_cry[8]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[8]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[7]_net_1\, S => \clock_count_s[8]\, Y
         => OPEN, FCO => \clock_count_cry[8]_net_1\);
    
    \clock_count_cry[26]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[26]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[25]_net_1\, S => \clock_count_s[26]\, Y
         => OPEN, FCO => \clock_count_cry[26]_net_1\);
    
    \Recount_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[3]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[2]_net_1\, S => \Recount_s[3]\, Y => OPEN, 
        FCO => \Recount_cry[3]_net_1\);
    
    \count_Temp1_cry[26]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[26]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[25]_net_1\, S => \count_Temp1_s[26]\, Y
         => OPEN, FCO => \count_Temp1_cry[26]_net_1\);
    
    \Recount[31]\ : SLE
      port map(D => \Recount_lm[31]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[31]_net_1\);
    
    \clock_count_cry[22]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[22]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[21]_net_1\, S => \clock_count_s[22]\, Y
         => OPEN, FCO => \clock_count_cry[22]_net_1\);
    
    \HADDR_TEMP[28]\ : SLE
      port map(D => \HADDR_TEMP_7[28]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[28]\);
    
    \clock_count_cry[0]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[0]_net_1\, D => \HMASTLOCK\, FCI => 
        clock_count_s_134_FCO, S => \clock_count_s[0]\, Y => OPEN, 
        FCO => \clock_count_cry[0]_net_1\);
    
    \count_Temp1_cry[13]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[13]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[12]_net_1\, S => \count_Temp1_s[13]\, Y
         => OPEN, FCO => \count_Temp1_cry[13]_net_1\);
    
    un1_ahb_states_1_sqmuxa_1_RNIHHOJ : CFG4
      generic map(INIT => x"0301")

      port map(A => clock_count, B => \un1_ahb_states_1_sqmuxa_1\, 
        C => \un1_ahb_states_1_sqmuxa_2\, D => \un1_hreadyout\, Y
         => un1_ahb_states_1_sqmuxa_i_0);
    
    \HWRITE_DATA_TEMP_6_0[2]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[2]_net_1\, D => \Recount[2]_net_1\, Y => 
        N_201);
    
    \HWRITE_DATA_TEMP_6_0[29]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[29]_net_1\, D => \Recount[29]_net_1\, Y => 
        N_228);
    
    \count_Temp1_lm_0[12]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[12]\, 
        Y => \count_Temp1_lm[12]\);
    
    \VCC\ : VCC
      port map(Y => \HREADY\);
    
    \HWRITE_DATA_TEMP_cry[25]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[25]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[24]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[25]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[25]_net_1\);
    
    \count_Temp1_lm_0[28]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[28]\, 
        Y => \count_Temp1_lm[28]\);
    
    \HWRITE_DATA_TEMP_6_0[22]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[22]_net_1\, D => \Recount[22]_net_1\, Y => 
        N_221);
    
    \Recount_cry[20]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[20]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[19]_net_1\, S => \Recount_s[20]\, Y => OPEN, 
        FCO => \Recount_cry[20]_net_1\);
    
    HADDR_TEMP_7_cry_20 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[20]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_19\, S => 
        \HADDR_TEMP_7[20]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_20\);
    
    \HWRITE_DATA_TEMP[16]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[16]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[16]\);
    
    \count_Temp1_lm_0[24]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[24]\, 
        Y => \count_Temp1_lm[24]\);
    
    \HWRITE_DATA_TEMP_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[3]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[2]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[3]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[3]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[11]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[11]\, C => N_210, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[11]\);
    
    \HWRITE_DATA_TEMP_cry[11]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[11]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[10]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[11]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[11]_net_1\);
    
    \Recount[5]\ : SLE
      port map(D => \Recount_lm[5]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[5]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[12]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[12]\, C => N_211, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[12]\);
    
    \HADDR_TEMP[19]\ : SLE
      port map(D => \HADDR_TEMP_7[19]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[19]\);
    
    \count_Temp1_cry[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[7]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[6]_net_1\, S => \count_Temp1_s[7]\, Y
         => OPEN, FCO => \count_Temp1_cry[7]_net_1\);
    
    \count_Temp1_lm_0[25]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[25]\, 
        Y => \count_Temp1_lm[25]\);
    
    un1_htrans6_4_1_RNIB5F61 : CFG4
      generic map(INIT => x"0301")

      port map(A => \htrans10\, B => \un1_htrans6_4_1\, C => 
        \HADDR_TEMP_1_sqmuxa\, D => \HREADY_flngedge\, Y => 
        un1_htrans6_4_i_0);
    
    \count_Temp1[9]\ : SLE
      port map(D => \count_Temp1_lm[9]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[9]_net_1\);
    
    htrans11_3 : CFG2
      generic map(INIT => x"1")

      port map(A => clock_count, B => \ahb_states[5]_net_1\, Y
         => htrans6_3);
    
    \count_Temp1_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[1]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        count_Temp1_s_135_FCO, S => \count_Temp1_s[1]\, Y => OPEN, 
        FCO => \count_Temp1_cry[1]_net_1\);
    
    \HADDR_TEMP[21]\ : SLE
      port map(D => \HADDR_TEMP_7[21]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[21]\);
    
    \count_Temp1_cry[23]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[23]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[22]_net_1\, S => \count_Temp1_s[23]\, Y
         => OPEN, FCO => \count_Temp1_cry[23]_net_1\);
    
    \count_Temp1_cry[14]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[14]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[13]_net_1\, S => \count_Temp1_s[14]\, Y
         => OPEN, FCO => \count_Temp1_cry[14]_net_1\);
    
    \HADDR_TEMP[27]\ : SLE
      port map(D => \HADDR_TEMP_7[27]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[27]\);
    
    \Recount[19]\ : SLE
      port map(D => \Recount_lm[19]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[19]_net_1\);
    
    HADDR_TEMP_7_cry_2_0 : ARI1
      generic map(INIT => x"54488")

      port map(A => \HADDR[2]\, B => \HADDR_TEMP_7_cry_2_0_RNO\, 
        C => \htrans11\, D => \HMASTLOCK\, FCI => \HMASTLOCK\, S
         => OPEN, Y => HADDR_TEMP_7_cry_2_0_Y, FCO => 
        HADDR_TEMP_7_cry_2);
    
    \Recount_lm_0[2]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[2]\, Y => \Recount_lm[2]\);
    
    HADDR_TEMP_1_sqmuxa_0 : CFG3
      generic map(INIT => x"10")

      port map(A => \ahb_states[0]_net_1\, B => 
        \ahb_states[5]_net_1\, C => \htrans7_4\, Y => 
        \HADDR_TEMP_1_sqmuxa_0\);
    
    \HADDR_TEMP[6]\ : SLE
      port map(D => \HADDR_TEMP_7[6]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[6]\);
    
    \count_Temp1_lm_0[31]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => 
        \count_Temp1_s[31]_net_1\, Y => \count_Temp1_lm[31]\);
    
    \Recount_lm_0[20]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[20]\, Y => 
        \Recount_lm[20]\);
    
    \HWRITE_DATA_TEMP_lm_0[25]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[25]\, C => N_224, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[25]\);
    
    \count_Temp1_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[4]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[3]_net_1\, S => \count_Temp1_s[4]\, Y
         => OPEN, FCO => \count_Temp1_cry[4]_net_1\);
    
    \Recount_lm_0[30]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[30]\, Y => 
        \Recount_lm[30]\);
    
    \Recount_cry[24]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[24]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[23]_net_1\, S => \Recount_s[24]\, Y => OPEN, 
        FCO => \Recount_cry[24]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[13]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[13]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[12]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[13]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[13]_net_1\);
    
    \Recount[29]\ : SLE
      port map(D => \Recount_lm[29]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[29]_net_1\);
    
    \count_Temp1_lm_0[0]\ : CFG2
      generic map(INIT => x"1")

      port map(A => \un5_clock_count\, B => 
        \count_Temp1[0]_net_1\, Y => \count_Temp1_lm[0]\);
    
    \HWRITE_DATA_TEMP_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[1]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => HWRITE_DATA_TEMP_s_137_FCO, S
         => \HWRITE_DATA_TEMP_s[1]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[1]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[1]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[1]_net_1\, D => \Recount[1]_net_1\, Y => 
        N_200);
    
    \clock_count[6]\ : SLE
      port map(D => \clock_count_s[6]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[6]_net_1\);
    
    HADDR_TEMP_7_cry_21 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[21]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_20\, S => 
        \HADDR_TEMP_7[21]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_21\);
    
    \HADDR_TEMP[12]\ : SLE
      port map(D => \HADDR_TEMP_7[12]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[12]\);
    
    \count_Temp1_lm_0[19]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[19]\, 
        Y => \count_Temp1_lm[19]\);
    
    \count_Temp1_cry[24]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[24]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[23]_net_1\, S => \count_Temp1_s[24]\, Y
         => OPEN, FCO => \count_Temp1_cry[24]_net_1\);
    
    \clock_count[3]\ : SLE
      port map(D => \clock_count_s[3]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[3]_net_1\);
    
    \count_Temp1_cry[30]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[30]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[29]_net_1\, S => \count_Temp1_s[30]\, Y
         => OPEN, FCO => \count_Temp1_cry[30]_net_1\);
    
    \clock_count_cry[9]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[9]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[8]_net_1\, S => \clock_count_s[9]\, Y
         => OPEN, FCO => \clock_count_cry[9]_net_1\);
    
    \Recount_cry[28]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[28]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[27]_net_1\, S => \Recount_s[28]\, Y => OPEN, 
        FCO => \Recount_cry[28]_net_1\);
    
    HREADY_Int0 : SLE
      port map(D => HREADYOUT, CLK => HCLK, EN => \HREADY\, ALn
         => RESET_N, ADn => \HREADY\, SLn => \HREADY\, SD => 
        \HMASTLOCK\, LAT => \HMASTLOCK\, Q => \HREADY_Int0\);
    
    \HWRITE_DATA_TEMP_lm_0[24]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[24]\, C => N_223, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[24]\);
    
    HADDR_TEMP_7_cry_4 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[4]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_3\, S => 
        \HADDR_TEMP_7[4]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_4\);
    
    \count_Temp1_lm_0[21]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[21]\, 
        Y => \count_Temp1_lm[21]\);
    
    \Recount_cry[23]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[23]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[22]_net_1\, S => \Recount_s[23]\, Y => OPEN, 
        FCO => \Recount_cry[23]_net_1\);
    
    \Recount[8]\ : SLE
      port map(D => \Recount_lm[8]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[8]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[22]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[22]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[21]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[22]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[22]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[6]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[6]_net_1\, D => \Recount[6]_net_1\, Y => 
        N_205);
    
    un17_clock_count_x : CFG2
      generic map(INIT => x"2")

      port map(A => HREADYOUT, B => \Res_Enable\, Y => N_151);
    
    \HWRITE_DATA_TEMP_6_0[19]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[19]_net_1\, D => \Recount[19]_net_1\, Y => 
        N_218);
    
    \count_Temp1[22]\ : SLE
      port map(D => \count_Temp1_lm[22]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[22]_net_1\);
    
    \Recount_lm_0[23]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[23]\, Y => 
        \Recount_lm[23]\);
    
    \Recount_lm_0[15]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[15]\, Y => 
        \Recount_lm[15]\);
    
    \Recount[6]\ : SLE
      port map(D => \Recount_lm[6]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[6]_net_1\);
    
    \HADDR_TEMP[26]\ : SLE
      port map(D => \HADDR_TEMP_7[26]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[26]\);
    
    \Recount_lm_0[7]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[7]\, Y => \Recount_lm[7]\);
    
    \Recount_lm_0[16]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[16]\, Y => 
        \Recount_lm[16]\);
    
    \HWRITE_DATA_TEMP_6_0[12]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[12]_net_1\, D => \Recount[12]_net_1\, Y => 
        N_211);
    
    \HWRITE_DATA_TEMP[24]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[24]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[24]\);
    
    HADDR_TEMP_7_cry_12 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[12]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_11\, S => 
        \HADDR_TEMP_7[12]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_12\);
    
    \clock_count_cry[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[3]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[2]_net_1\, S => \clock_count_s[3]\, Y
         => OPEN, FCO => \clock_count_cry[3]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[30]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[30]\, C => N_229, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[30]\);
    
    \Recount_lm_0[28]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[28]\, Y => 
        \Recount_lm[28]\);
    
    \HSIZE[1]\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HSIZE(1));
    
    \clock_count[26]\ : SLE
      port map(D => \clock_count_s[26]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[26]_net_1\);
    
    \Recount_cry[16]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[16]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[15]_net_1\, S => \Recount_s[16]\, Y => OPEN, 
        FCO => \Recount_cry[16]_net_1\);
    
    \clock_count_cry[30]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[30]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[29]_net_1\, S => \clock_count_s[30]\, Y
         => OPEN, FCO => \clock_count_cry[30]_net_1\);
    
    \Recount[7]\ : SLE
      port map(D => \Recount_lm[7]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[7]_net_1\);
    
    \Recount_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[2]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[1]_net_1\, S => \Recount_s[2]\, Y => OPEN, 
        FCO => \Recount_cry[2]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[23]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[23]\, C => N_222, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[23]\);
    
    un7_clock_count : CFG4
      generic map(INIT => x"8000")

      port map(A => \un7_clock_count_20\, B => 
        \un7_clock_count_21\, C => \un7_clock_count_27\, D => 
        \un7_clock_count_28\, Y => \un7_clock_count\);
    
    \ahb_states[3]\ : SLE
      port map(D => clock_count, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[3]_net_1\);
    
    \count_Temp1_lm_0[9]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[9]\, Y
         => \count_Temp1_lm[9]\);
    
    \clock_count[1]\ : SLE
      port map(D => \clock_count_s[1]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[1]_net_1\);
    
    \HADDR_TEMP_7[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \htrans11\, B => \HADDR[1]\, Y => 
        \HADDR_TEMP_7[1]_net_1\);
    
    \count_Temp1_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[2]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[1]_net_1\, S => \count_Temp1_s[2]\, Y
         => OPEN, FCO => \count_Temp1_cry[2]_net_1\);
    
    \count_Temp1[18]\ : SLE
      port map(D => \count_Temp1_lm[18]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[18]_net_1\);
    
    un1_reset_n_2 : CFG2
      generic map(INIT => x"2")

      port map(A => RESET_N, B => \ahb_states[6]_net_1\, Y => 
        \un1_reset_n_2\);
    
    \Recount[30]\ : SLE
      port map(D => \Recount_lm[30]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[30]_net_1\);
    
    \clock_count_cry[14]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[14]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[13]_net_1\, S => \clock_count_s[14]\, Y
         => OPEN, FCO => \clock_count_cry[14]_net_1\);
    
    \HADDR_TEMP[31]\ : SLE
      port map(D => \HADDR_TEMP_7[31]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[31]\);
    
    un1_hreadyout_6 : CFG4
      generic map(INIT => x"4000")

      port map(A => \clock_count[10]_net_1\, B => 
        \clock_count[9]_net_1\, C => \clock_count[8]_net_1\, D
         => \clock_count[7]_net_1\, Y => \un1_hreadyout_6\);
    
    \HADDR_TEMP[10]\ : SLE
      port map(D => \HADDR_TEMP_7[10]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[10]\);
    
    \ahb_states[2]\ : SLE
      port map(D => \ahb_states[1]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[2]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[28]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[28]\, C => N_227, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[28]\);
    
    \clock_count[8]\ : SLE
      port map(D => \clock_count_s[8]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[8]_net_1\);
    
    \clock_count[19]\ : SLE
      port map(D => \clock_count_s[19]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[19]_net_1\);
    
    \HWRITE_DATA_TEMP[4]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[4]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[4]\);
    
    \clock_count_cry[11]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[11]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[10]_net_1\, S => \clock_count_s[11]\, Y
         => OPEN, FCO => \clock_count_cry[11]_net_1\);
    
    \clock_count_cry[10]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[10]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[9]_net_1\, S => \clock_count_s[10]\, Y
         => OPEN, FCO => \clock_count_cry[10]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[26]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[26]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[25]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[26]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[26]_net_1\);
    
    \count_Temp1_lm_0[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[7]\, Y
         => \count_Temp1_lm[7]\);
    
    \Recount_cry[22]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[22]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[21]_net_1\, S => \Recount_s[22]\, Y => OPEN, 
        FCO => \Recount_cry[22]_net_1\);
    
    \Recount[11]\ : SLE
      port map(D => \Recount_lm[11]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[11]_net_1\);
    
    \HWRITE_DATA_TEMP[29]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[29]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[29]\);
    
    \count_Temp1_cry[18]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[18]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[17]_net_1\, S => \count_Temp1_s[18]\, Y
         => OPEN, FCO => \count_Temp1_cry[18]_net_1\);
    
    \clock_count[31]\ : SLE
      port map(D => \clock_count_s[31]_net_1\, CLK => HCLK, EN
         => clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \clock_count[31]_net_1\);
    
    un2_hrdycount : CFG2
      generic map(INIT => x"4")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, Y => \un2_hrdycount\);
    
    \HWRITE_DATA_TEMP_lm_0[27]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[27]\, C => N_226, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[27]\);
    
    \HSIZE[0]\ : SLE
      port map(D => \HMASTLOCK\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HSIZE(0));
    
    HREADY_flngedge : CFG2
      generic map(INIT => x"4")

      port map(A => HREADYOUT, B => \HREADY_Int0\, Y => 
        \HREADY_flngedge\);
    
    \HWRITE_DATA_TEMP_6_0[24]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[24]_net_1\, D => \Recount[24]_net_1\, Y => 
        N_223);
    
    \HWRITE_DATA_TEMP[14]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[14]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[14]\);
    
    \Recount_lm_0[12]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[12]\, Y => 
        \Recount_lm[12]\);
    
    \HADDR_TEMP[8]\ : SLE
      port map(D => \HADDR_TEMP_7[8]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[8]\);
    
    \clock_count_cry[18]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[18]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[17]_net_1\, S => \clock_count_s[18]\, Y
         => OPEN, FCO => \clock_count_cry[18]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[27]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[27]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[26]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[27]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[27]_net_1\);
    
    \Recount_lm_0[6]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[6]\, Y => \Recount_lm[6]\);
    
    \Recount_s[31]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[31]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[30]_net_1\, S => \Recount_s[31]_net_1\, Y
         => OPEN, FCO => OPEN);
    
    \Recount[21]\ : SLE
      port map(D => \Recount_lm[21]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[21]_net_1\);
    
    \clock_count_cry[16]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[16]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[15]_net_1\, S => \clock_count_s[16]\, Y
         => OPEN, FCO => \clock_count_cry[16]_net_1\);
    
    count_Temp1_s_135 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[0]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, 
        Y => OPEN, FCO => count_Temp1_s_135_FCO);
    
    \Recount_cry[10]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[10]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[9]_net_1\, S => \Recount_s[10]\, Y => OPEN, 
        FCO => \Recount_cry[10]_net_1\);
    
    \clock_count_cry[12]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[12]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[11]_net_1\, S => \clock_count_s[12]\, Y
         => OPEN, FCO => \clock_count_cry[12]_net_1\);
    
    MASTER1_START_RNI4N3I1 : CFG4
      generic map(INIT => x"11D1")

      port map(A => \htrans11\, B => \htrans6\, C => 
        MASTER1_START, D => MASTER1_STOP, Y => un1_htrans6_2_i_0);
    
    \count_Temp1_lm_0[26]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[26]\, 
        Y => \count_Temp1_lm[26]\);
    
    un7_clock_count_13 : CFG2
      generic map(INIT => x"1")

      port map(A => \clock_count[3]_net_1\, B => 
        \clock_count[4]_net_1\, Y => \un7_clock_count_13\);
    
    HADDR_TEMP_7_cry_22 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[22]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_21\, S => 
        \HADDR_TEMP_7[22]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_22\);
    
    \HWRITE_DATA_TEMP_lm_0[19]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[19]\, C => N_218, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[19]\);
    
    \HADDR_TEMP[23]\ : SLE
      port map(D => \HADDR_TEMP_7[23]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[23]\);
    
    \count_Temp1_lm_0[18]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[18]\, 
        Y => \count_Temp1_lm[18]\);
    
    \count_Temp1_cry[28]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[28]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[27]_net_1\, S => \count_Temp1_s[28]\, Y
         => OPEN, FCO => \count_Temp1_cry[28]_net_1\);
    
    HADDR_TEMP_1_sqmuxa : CFG3
      generic map(INIT => x"70")

      port map(A => HREADYOUT, B => \Tr_Enable\, C => 
        \HADDR_TEMP_1_sqmuxa_0\, Y => \HADDR_TEMP_1_sqmuxa\);
    
    \HADDR_TEMP[25]\ : SLE
      port map(D => \HADDR_TEMP_7[25]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[25]\);
    
    \count_Temp1_lm_0[14]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[14]\, 
        Y => \count_Temp1_lm[14]\);
    
    \HWRITE_DATA_TEMP[23]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[23]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[23]\);
    
    HADDR_TEMP_7_cry_7 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[7]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_6\, S => 
        \HADDR_TEMP_7[7]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_7\);
    
    \count_Temp1[25]\ : SLE
      port map(D => \count_Temp1_lm[25]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[25]_net_1\);
    
    \HWRITE_DATA_TEMP[7]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[7]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[7]\);
    
    \Recount_lm_0[19]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[19]\, Y => 
        \Recount_lm[19]\);
    
    \HWRITE_DATA_TEMP_lm_0[8]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[8]\, C => N_207, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[8]\);
    
    \HWRITE_DATA_TEMP_6_0[8]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[8]_net_1\, D => \Recount[8]_net_1\, Y => 
        N_207);
    
    \clock_count[11]\ : SLE
      port map(D => \clock_count_s[11]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[11]_net_1\);
    
    HADDR_TEMP_7_cry_8 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[8]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_7\, S => 
        \HADDR_TEMP_7[8]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_8\);
    
    \count_Temp1_lm_0[15]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[15]\, 
        Y => \count_Temp1_lm[15]\);
    
    \clock_count[23]\ : SLE
      port map(D => \clock_count_s[23]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[23]_net_1\);
    
    \clock_count_cry[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[2]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[1]_net_1\, S => \clock_count_s[2]\, Y
         => OPEN, FCO => \clock_count_cry[2]_net_1\);
    
    \clock_count_cry[23]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[23]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[22]_net_1\, S => \clock_count_s[23]\, Y
         => OPEN, FCO => \clock_count_cry[23]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[20]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[20]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[19]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[20]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[20]_net_1\);
    
    \Recount_cry[14]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[14]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[13]_net_1\, S => \Recount_s[14]\, Y => OPEN, 
        FCO => \Recount_cry[14]_net_1\);
    
    \clock_count_cry[25]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[25]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[24]_net_1\, S => \clock_count_s[25]\, Y
         => OPEN, FCO => \clock_count_cry[25]_net_1\);
    
    un8_hready_flngedge : CFG3
      generic map(INIT => x"75")

      port map(A => clock_count, B => HREADYOUT, C => 
        \HREADY_Int0\, Y => \un8_hready_flngedge\);
    
    HADDR_TEMP_7_cry_30 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[30]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_29\, S => 
        \HADDR_TEMP_7[30]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_30\);
    
    \HWRITE_DATA_TEMP_6_0[26]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[26]_net_1\, D => \Recount[26]_net_1\, Y => 
        N_225);
    
    \HWRITE_DATA_TEMP[22]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[22]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[22]\);
    
    un7_clock_count_23 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[11]_net_1\, B => 
        \clock_count[9]_net_1\, C => \clock_count[8]_net_1\, D
         => \clock_count[7]_net_1\, Y => \un7_clock_count_23\);
    
    \HWRITE_DATA_TEMP[25]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[25]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[25]\);
    
    htrans11 : CFG3
      generic map(INIT => x"EF")

      port map(A => \ahb_states[5]_net_1\, B => clock_count, C
         => \htrans11_1\, Y => \htrans11\);
    
    \count_Temp1_lm_0[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[1]\, Y
         => \count_Temp1_lm[1]\);
    
    \clock_count[27]\ : SLE
      port map(D => \clock_count_s[27]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[27]_net_1\);
    
    Tr_Enable_RNI3NMM : CFG4
      generic map(INIT => x"AAEA")

      port map(A => \un5_clock_count\, B => HREADYOUT, C => 
        \Tr_Enable\, D => \HREADY_Int0\, Y => count_Temp1e);
    
    \HWRITE_DATA_TEMP[19]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[19]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[19]\);
    
    \HADDR_TEMP[24]\ : SLE
      port map(D => \HADDR_TEMP_7[24]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[24]\);
    
    \HWRITE_DATA_TEMP_cry[15]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[15]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[14]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[15]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[15]_net_1\);
    
    \clock_count_cry[29]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[29]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[28]_net_1\, S => \clock_count_s[29]\, Y
         => OPEN, FCO => \clock_count_cry[29]_net_1\);
    
    \clock_count[20]\ : SLE
      port map(D => \clock_count_s[20]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[20]_net_1\);
    
    \clock_count[9]\ : SLE
      port map(D => \clock_count_s[9]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[9]_net_1\);
    
    \Recount_cry[18]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[18]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[17]_net_1\, S => \Recount_s[18]\, Y => OPEN, 
        FCO => \Recount_cry[18]_net_1\);
    
    \HWRITE\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HWRITE);
    
    \HWRITE_DATA_TEMP_lm_0[0]\ : CFG4
      generic map(INIT => x"2722")

      port map(A => \htrans7_4_RNI0E4A\, B => \HWDATA[0]\, C => 
        \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[0]\);
    
    \HWRITE_DATA_TEMP_cry[24]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[24]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[23]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[24]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[24]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[29]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[29]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[28]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[29]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[29]_net_1\);
    
    \ahb_states[5]\ : SLE
      port map(D => \ahb_states[6]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[5]_net_1\);
    
    \Recount_lm_0[21]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[21]\, Y => 
        \Recount_lm[21]\);
    
    \Recount_cry[13]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[13]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[12]_net_1\, S => \Recount_s[13]\, Y => OPEN, 
        FCO => \Recount_cry[13]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[14]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[14]_net_1\, D => \Recount[14]_net_1\, Y => 
        N_213);
    
    HADDR_TEMP_0_sqmuxa_s : CFG4
      generic map(INIT => x"0200")

      port map(A => \Tr_Enable\, B => \ahb_states[0]_net_1\, C
         => \ahb_states[5]_net_1\, D => \htrans7_4\, Y => 
        HADDR_TEMP_0_sqmuxa_out);
    
    \count_Temp1_lm_0[5]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[5]\, Y
         => \count_Temp1_lm[5]\);
    
    \clock_count_cry[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[7]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[6]_net_1\, S => \clock_count_s[7]\, Y
         => OPEN, FCO => \clock_count_cry[7]_net_1\);
    
    \clock_count[12]\ : SLE
      port map(D => \clock_count_s[12]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[12]_net_1\);
    
    \Recount_lm_0[31]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[31]_net_1\, Y => 
        \Recount_lm[31]\);
    
    \Recount[3]\ : SLE
      port map(D => \Recount_lm[3]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[3]_net_1\);
    
    \count_Temp1_lm_0[11]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[11]\, 
        Y => \count_Temp1_lm[11]\);
    
    \clock_count[0]\ : SLE
      port map(D => \clock_count_s[0]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[0]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[7]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[7]_net_1\, D => \Recount[7]_net_1\, Y => 
        N_206);
    
    \HWRITE_DATA_TEMP[5]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[5]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[5]\);
    
    \HADDR_TEMP[0]\ : SLE
      port map(D => \HADDR_TEMP_7[0]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[0]\);
    
    \count_Temp1[12]\ : SLE
      port map(D => \count_Temp1_lm[12]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[12]_net_1\);
    
    \clock_count_cry[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[6]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[5]_net_1\, S => \clock_count_s[6]\, Y
         => OPEN, FCO => \clock_count_cry[6]_net_1\);
    
    \clock_count_cry[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[4]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[3]_net_1\, S => \clock_count_s[4]\, Y
         => OPEN, FCO => \clock_count_cry[4]_net_1\);
    
    \ahb_states[1]\ : SLE
      port map(D => \ahb_states[3]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[1]_net_1\);
    
    \count_Temp1_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[6]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[5]_net_1\, S => \count_Temp1_s[6]\, Y
         => OPEN, FCO => \count_Temp1_cry[6]_net_1\);
    
    \Recount[16]\ : SLE
      port map(D => \Recount_lm[16]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[16]_net_1\);
    
    \Recount_lm_0[9]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[9]\, Y => \Recount_lm[9]\);
    
    \HWRITE_DATA_TEMP[6]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[6]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[6]\);
    
    \HWRITE_DATA_TEMP[13]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[13]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[13]\);
    
    \HADDR_TEMP[4]\ : SLE
      port map(D => \HADDR_TEMP_7[4]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[4]\);
    
    \Recount[9]\ : SLE
      port map(D => \Recount_lm[9]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[9]_net_1\);
    
    \Recount[18]\ : SLE
      port map(D => \Recount_lm[18]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[18]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[23]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[23]_net_1\, D => \Recount[23]_net_1\, Y => 
        N_222);
    
    \HrdyCount[0]\ : SLE
      port map(D => \HrdyCount_3[0]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HrdyCount[0]_net_1\);
    
    \Recount[10]\ : SLE
      port map(D => \Recount_lm[10]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[10]_net_1\);
    
    htrans8_3 : CFG2
      generic map(INIT => x"1")

      port map(A => clock_count, B => \ahb_states[0]_net_1\, Y
         => htrans9_3);
    
    \Recount[26]\ : SLE
      port map(D => \Recount_lm[26]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[26]_net_1\);
    
    \count_Temp1_lm_0[23]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[23]\, 
        Y => \count_Temp1_lm[23]\);
    
    un1_hreadyout_8 : CFG4
      generic map(INIT => x"4000")

      port map(A => \clock_count[11]_net_1\, B => 
        \clock_count[2]_net_1\, C => \clock_count[1]_net_1\, D
         => \clock_count[0]_net_1\, Y => \un1_hreadyout_8\);
    
    \Recount_lm_0[10]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[10]\, Y => 
        \Recount_lm[10]\);
    
    HADDR_TEMP_7_cry_19 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[19]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_18\, S => 
        \HADDR_TEMP_7[19]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_19\);
    
    \clock_count[18]\ : SLE
      port map(D => \clock_count_s[18]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[18]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[21]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[21]\, C => N_220, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[21]\);
    
    Recount_s_136 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[0]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, 
        Y => OPEN, FCO => Recount_s_136_FCO);
    
    \Recount[28]\ : SLE
      port map(D => \Recount_lm[28]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[28]_net_1\);
    
    \HWRITE_DATA_TEMP[12]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[12]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[12]\);
    
    \clock_count[7]\ : SLE
      port map(D => \clock_count_s[7]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[7]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[22]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[22]\, C => N_221, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[22]\);
    
    \HWRITE_DATA_TEMP[15]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[15]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[15]\);
    
    un7_clock_count_21 : CFG4
      generic map(INIT => x"0002")

      port map(A => \clock_count[10]_net_1\, B => 
        \clock_count[2]_net_1\, C => \clock_count[1]_net_1\, D
         => \clock_count[0]_net_1\, Y => \un7_clock_count_21\);
    
    un1_HSEL_1_u_ns : CFG4
      generic map(INIT => x"66E6")

      port map(A => \un1_HSEL_1_u_ns_1\, B => \htrans6\, C => 
        MASTER1_START, D => MASTER1_STOP, Y => \un1_HSEL_1_u_ns\);
    
    \HWRITE_DATA_TEMP_cry[28]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[28]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[27]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[28]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[28]_net_1\);
    
    \Recount[20]\ : SLE
      port map(D => \Recount_lm[20]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[20]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[12]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[12]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[11]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[12]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[12]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[16]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[16]_net_1\, D => \Recount[16]_net_1\, Y => 
        N_215);
    
    HADDR_TEMP_7_s_31 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[31]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_30\, S => 
        \HADDR_TEMP_7[31]\, Y => OPEN, FCO => OPEN);
    
    un7_clock_count_20 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[23]_net_1\, B => 
        \clock_count[22]_net_1\, C => \clock_count[21]_net_1\, D
         => \clock_count[20]_net_1\, Y => \un7_clock_count_20\);
    
    \Recount_cry[30]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[30]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[29]_net_1\, S => \Recount_s[30]\, Y => OPEN, 
        FCO => \Recount_cry[30]_net_1\);
    
    \Recount_cry[8]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[8]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[7]_net_1\, S => \Recount_s[8]\, Y => OPEN, 
        FCO => \Recount_cry[8]_net_1\);
    
    \count_Temp1_lm_0[30]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[30]\, 
        Y => \count_Temp1_lm[30]\);
    
    htrans7_4_RNI0E4A : CFG2
      generic map(INIT => x"2")

      port map(A => \htrans7_4\, B => \ahb_states[0]_net_1\, Y
         => \htrans7_4_RNI0E4A\);
    
    HADDR_TEMP_7_cry_2_0_RNO_1 : CFG4
      generic map(INIT => x"023C")

      port map(A => \Tr_Enable\, B => \ahb_states[1]_net_1\, C
         => \ahb_states[3]_net_1\, D => clock_count, Y => N_6);
    
    HADDR_TEMP_7_cry_18 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[18]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_17\, S => 
        \HADDR_TEMP_7[18]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_18\);
    
    \count_Temp1[27]\ : SLE
      port map(D => \count_Temp1_lm[27]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[27]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[3]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[3]\, C => N_202, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[3]\);
    
    \HWRITE_DATA_TEMP_6_0[28]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[28]_net_1\, D => \Recount[28]_net_1\, Y => 
        N_227);
    
    \Recount_lm_0[27]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[27]\, Y => 
        \Recount_lm[27]\);
    
    \Recount_cry[12]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[12]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[11]_net_1\, S => \Recount_s[12]\, Y => OPEN, 
        FCO => \Recount_cry[12]_net_1\);
    
    \count_Temp1[5]\ : SLE
      port map(D => \count_Temp1_lm[5]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[5]_net_1\);
    
    \clock_count_s[31]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[31]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[30]_net_1\, S => 
        \clock_count_s[31]_net_1\, Y => OPEN, FCO => OPEN);
    
    \Recount[2]\ : SLE
      port map(D => \Recount_lm[2]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[2]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[16]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[16]\, C => N_215, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[16]\);
    
    \HWRITE_DATA_TEMP_cry[9]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[9]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[8]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[9]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[9]_net_1\);
    
    HADDR_TEMP_7_cry_2_0_RNO : CFG4
      generic map(INIT => x"D555")

      port map(A => \htrans11\, B => HREADYOUT, C => g2_1, D => 
        N_6, Y => \HADDR_TEMP_7_cry_2_0_RNO\);
    
    HWRITE_DATA_TEMP_s_137 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[0]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, Y => OPEN, 
        FCO => HWRITE_DATA_TEMP_s_137_FCO);
    
    \count_Temp1_cry[9]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[9]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[8]_net_1\, S => \count_Temp1_s[9]\, Y
         => OPEN, FCO => \count_Temp1_cry[9]_net_1\);
    
    \Recount_lm_0[13]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[13]\, Y => 
        \Recount_lm[13]\);
    
    \Recount_lm_0[4]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[4]\, Y => \Recount_lm[4]\);
    
    \Recount[14]\ : SLE
      port map(D => \Recount_lm[14]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[14]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[27]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[27]_net_1\, D => \Recount[27]_net_1\, Y => 
        N_226);
    
    \HTRANS[1]\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HTRANS(1));
    
    un7_clock_count_17 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[27]_net_1\, B => 
        \clock_count[26]_net_1\, C => \clock_count[25]_net_1\, D
         => \clock_count[24]_net_1\, Y => \un7_clock_count_17\);
    
    \count_Temp1_lm_0[20]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[20]\, 
        Y => \count_Temp1_lm[20]\);
    
    \count_Temp1[24]\ : SLE
      port map(D => \count_Temp1_lm[24]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[24]_net_1\);
    
    \clock_count_cry[27]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[27]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[26]_net_1\, S => \clock_count_s[27]\, Y
         => OPEN, FCO => \clock_count_cry[27]_net_1\);
    
    HADDR_TEMP_0_sqmuxa_s_RNIU1IS : CFG3
      generic map(INIT => x"8F")

      port map(A => HREADYOUT, B => HADDR_TEMP_0_sqmuxa_out, C
         => \htrans11\, Y => clock_countlde_0);
    
    \count_Temp1[3]\ : SLE
      port map(D => \count_Temp1_lm[3]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[3]_net_1\);
    
    \Recount_lm_0[18]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[18]\, Y => 
        \Recount_lm[18]\);
    
    \HWRITE_DATA_TEMP_lm_0[10]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[10]\, C => N_209, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[10]\);
    
    \count_Temp1_cry[10]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[10]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[9]_net_1\, S => \count_Temp1_s[10]\, Y
         => OPEN, FCO => \count_Temp1_cry[10]_net_1\);
    
    \count_Temp1[26]\ : SLE
      port map(D => \count_Temp1_lm[26]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[26]_net_1\);
    
    \Recount_cry[25]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[25]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[24]_net_1\, S => \Recount_s[25]\, Y => OPEN, 
        FCO => \Recount_cry[25]_net_1\);
    
    htrans6 : CFG4
      generic map(INIT => x"1000")

      port map(A => \ahb_states[2]_net_1\, B => 
        \ahb_states[3]_net_1\, C => \htrans6_1\, D => htrans6_3, 
        Y => \htrans6\);
    
    HADDR_TEMP_7_cry_2_0_RNO_0 : CFG3
      generic map(INIT => x"01")

      port map(A => \ahb_states[0]_net_1\, B => 
        \ahb_states[5]_net_1\, C => \ahb_states[2]_net_1\, Y => 
        g2_1);
    
    Res_Enable : SLE
      port map(D => \HREADY\, CLK => HCLK, EN => 
        \un12_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Res_Enable\);
    
    \count_Temp1[7]\ : SLE
      port map(D => \count_Temp1_lm[7]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[7]_net_1\);
    
    un1_ahb_states_1_sqmuxa_1 : CFG4
      generic map(INIT => x"FCDC")

      port map(A => MASTER1_START, B => 
        \un1_ahb_states_1_sqmuxa_0\, C => \ahb_states[6]_net_1\, 
        D => MASTER1_STOP, Y => \un1_ahb_states_1_sqmuxa_1\);
    
    \Recount[24]\ : SLE
      port map(D => \Recount_lm[24]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[24]_net_1\);
    
    \count_Temp1_lm_0[16]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[16]\, 
        Y => \count_Temp1_lm[16]\);
    
    \HWRITE_DATA_TEMP_6_0[13]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[13]_net_1\, D => \Recount[13]_net_1\, Y => 
        N_212);
    
    \HADDR_TEMP[29]\ : SLE
      port map(D => \HADDR_TEMP_7[29]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HMASTLOCK\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[29]\);
    
    \Recount_cry[27]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[27]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[26]_net_1\, S => \Recount_s[27]\, Y => OPEN, 
        FCO => \Recount_cry[27]_net_1\);
    
    un7_clock_count_18 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[31]_net_1\, B => 
        \clock_count[30]_net_1\, C => \clock_count[29]_net_1\, D
         => \clock_count[28]_net_1\, Y => \un7_clock_count_18\);
    
    \HWRITE_DATA_TEMP_cry[16]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[16]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[15]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[16]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[16]_net_1\);
    
    \HADDR_TEMP[18]\ : SLE
      port map(D => \HADDR_TEMP_7[18]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[18]\);
    
    HADDR_TEMP_7_cry_13 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[13]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_12\, S => 
        \HADDR_TEMP_7[13]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_13\);
    
    \count_Temp1[15]\ : SLE
      port map(D => \count_Temp1_lm[15]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[15]_net_1\);
    
    \count_Temp1_cry[20]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[20]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[19]_net_1\, S => \count_Temp1_s[20]\, Y
         => OPEN, FCO => \count_Temp1_cry[20]_net_1\);
    
    \HWRITE_DATA_TEMP_s[31]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[31]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[30]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[31]_net_1\, Y => OPEN, FCO => 
        OPEN);
    
    htrans9 : CFG4
      generic map(INIT => x"2000")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => htrans9_3, D => \htrans9_2\, 
        Y => \htrans9\);
    
    htrans10 : CFG4
      generic map(INIT => x"4000")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => htrans9_3, D => \htrans9_2\, 
        Y => \htrans10\);
    
    HADDR_TEMP_7_cry_29 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => \HADDR[29]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_28\, S => 
        \HADDR_TEMP_7[29]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_29\);
    
    un7_clock_count_27 : CFG4
      generic map(INIT => x"1000")

      port map(A => \clock_count[5]_net_1\, B => 
        \clock_count[6]_net_1\, C => \un7_clock_count_23\, D => 
        \un7_clock_count_13\, Y => \un7_clock_count_27\);
    
    \Recount[1]\ : SLE
      port map(D => \Recount_lm[1]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[1]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[17]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[17]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[16]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[17]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[17]_net_1\);
    
    HADDR_TEMP_7_cry_15 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => \HADDR[15]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_14\, S => 
        \HADDR_TEMP_7[15]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_15\);
    
    un1_ahb_states_1_sqmuxa_2 : CFG3
      generic map(INIT => x"32")

      port map(A => \ahb_states[3]_net_1\, B => HREADYOUT, C => 
        \ahb_states[1]_net_1\, Y => \un1_ahb_states_1_sqmuxa_2\);
    
    \clock_count[29]\ : SLE
      port map(D => \clock_count_s[29]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[29]_net_1\);
    
    \Recount_cry[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[7]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[6]_net_1\, S => \Recount_s[7]\, Y => OPEN, 
        FCO => \Recount_cry[7]_net_1\);
    
    \HWRITE_DATA_TEMP[28]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[28]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[28]\);
    
    \clock_count_cry[13]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[13]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[12]_net_1\, S => \clock_count_s[13]\, Y
         => OPEN, FCO => \clock_count_cry[13]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[31]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[31]_net_1\, D => \Recount[31]_net_1\, Y => 
        N_230);
    
    \HWRITE_DATA_TEMP_6_0[18]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[18]_net_1\, D => \Recount[18]_net_1\, Y => 
        N_217);
    
    \HWRITE_DATA_TEMP_6_0[30]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[30]_net_1\, D => \Recount[30]_net_1\, Y => 
        N_229);
    
    \HADDR_TEMP[22]\ : SLE
      port map(D => \HADDR_TEMP_7[22]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[22]\);
    
    \clock_count_cry[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[5]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[4]_net_1\, S => \clock_count_s[5]\, Y
         => OPEN, FCO => \clock_count_cry[5]_net_1\);
    
    \clock_count_cry[15]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[15]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[14]_net_1\, S => \clock_count_s[15]\, Y
         => OPEN, FCO => \clock_count_cry[15]_net_1\);
    
    \Recount_cry[29]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[29]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[28]_net_1\, S => \Recount_s[29]\, Y => OPEN, 
        FCO => \Recount_cry[29]_net_1\);
    
    HADDR_TEMP_7_cry_28 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[28]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_27\, S => 
        \HADDR_TEMP_7[28]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_28\);
    
    un1_HSEL_1_u_ns_1 : CFG4
      generic map(INIT => x"343C")

      port map(A => htrans6_3, B => HSEL_net_1, C => \htrans6\, D
         => \htrans11_1\, Y => \un1_HSEL_1_u_ns_1\);
    
    \count_Temp1_cry[19]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[19]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[18]_net_1\, S => \count_Temp1_s[19]\, Y
         => OPEN, FCO => \count_Temp1_cry[19]_net_1\);
    
    \count_Temp1[30]\ : SLE
      port map(D => \count_Temp1_lm[30]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[30]_net_1\);
    
    \ahb_states[6]\ : SLE
      port map(D => \ahb_states[0]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HMASTLOCK\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[6]_net_1\);
    
    \HADDR_TEMP[11]\ : SLE
      port map(D => \HADDR_TEMP_7[11]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[11]\);
    
    \count_Temp1[2]\ : SLE
      port map(D => \count_Temp1_lm[2]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[2]_net_1\);
    
    un7_clock_count_28 : CFG4
      generic map(INIT => x"8000")

      port map(A => \un7_clock_count_19\, B => 
        \un7_clock_count_18\, C => \un7_clock_count_17\, D => 
        \un7_clock_count_16\, Y => \un7_clock_count_28\);
    
    \HADDR_TEMP[17]\ : SLE
      port map(D => \HADDR_TEMP_7[17]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[17]\);
    
    \count_Temp1_cry[12]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[12]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[11]_net_1\, S => \count_Temp1_s[12]\, Y
         => OPEN, FCO => \count_Temp1_cry[12]_net_1\);
    
    un7_clock_count_16 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[15]_net_1\, B => 
        \clock_count[14]_net_1\, C => \clock_count[13]_net_1\, D
         => \clock_count[12]_net_1\, Y => \un7_clock_count_16\);
    
    \HWRITE_DATA_TEMP_6_0[21]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[21]_net_1\, D => \Recount[21]_net_1\, Y => 
        N_220);
    
    \HADDR_TEMP[1]\ : SLE
      port map(D => \HADDR_TEMP_7[1]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[1]\);
    
    \clock_count_cry[19]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[19]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[18]_net_1\, S => \clock_count_s[19]\, Y
         => OPEN, FCO => \clock_count_cry[19]_net_1\);
    
    un1_hreadyout_7 : CFG4
      generic map(INIT => x"8000")

      port map(A => \clock_count[6]_net_1\, B => 
        \clock_count[5]_net_1\, C => \clock_count[4]_net_1\, D
         => \clock_count[3]_net_1\, Y => \un1_hreadyout_7\);
    
    \Recount_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[5]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[4]_net_1\, S => \Recount_s[5]\, Y => OPEN, 
        FCO => \Recount_cry[5]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[5]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[5]\, C => N_204, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[5]\);
    
    HADDR_TEMP_7_cry_17 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[17]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_16\, S => 
        \HADDR_TEMP_7[17]\, Y => OPEN, FCO => 
        \HADDR_TEMP_7_cry_17\);
    
    \count_Temp1[23]\ : SLE
      port map(D => \count_Temp1_lm[23]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[23]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[20]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[20]_net_1\, D => \Recount[20]_net_1\, Y => 
        N_219);
    
    \count_Temp1[31]\ : SLE
      port map(D => \count_Temp1_lm[31]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[31]_net_1\);
    
    \clock_count[15]\ : SLE
      port map(D => \clock_count_s[15]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[15]_net_1\);
    
    \HWRITE_DATA_TEMP_6_0[17]\ : CFG4
      generic map(INIT => x"F870")

      port map(A => \htrans10\, B => \HREADY_flngedge\, C => 
        \count_Temp1[17]_net_1\, D => \Recount[17]_net_1\, Y => 
        N_216);
    
    \count_Temp1[29]\ : SLE
      port map(D => \count_Temp1_lm[29]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[29]_net_1\);
    
    \count_Temp1_lm_0[8]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[8]\, Y
         => \count_Temp1_lm[8]\);
    
    \count_Temp1[1]\ : SLE
      port map(D => \count_Temp1_lm[1]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[1]_net_1\);
    
    \Recount_cry[21]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[21]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[20]_net_1\, S => \Recount_s[21]\, Y => OPEN, 
        FCO => \Recount_cry[21]_net_1\);
    
    \count_Temp1_s[31]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[31]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[30]_net_1\, S => 
        \count_Temp1_s[31]_net_1\, Y => OPEN, FCO => OPEN);
    
    \count_Temp1[20]\ : SLE
      port map(D => \count_Temp1_lm[20]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[20]_net_1\);
    
    \Recount_lm_0[24]\ : CFG4
      generic map(INIT => x"F700")

      port map(A => \ahb_states[3]_net_1\, B => \HREADY_Int0\, C
         => HREADYOUT, D => \Recount_s[24]\, Y => 
        \Recount_lm[24]\);
    
    \HWRITE_DATA_TEMP_cry[10]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[10]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[9]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[10]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[10]_net_1\);
    
    \clock_count[14]\ : SLE
      port map(D => \clock_count_s[14]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[14]_net_1\);
    
    \count_Temp1_cry[29]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[29]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[28]_net_1\, S => \count_Temp1_s[29]\, Y
         => OPEN, FCO => \count_Temp1_cry[29]_net_1\);
    
    \count_Temp1[21]\ : SLE
      port map(D => \count_Temp1_lm[21]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[21]_net_1\);
    
    Tr_Enable : SLE
      port map(D => clock_count, CLK => HCLK, EN => 
        \un8_hready_flngedge\, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \Tr_Enable\);
    
    \count_Temp1_cry[22]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[22]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[21]_net_1\, S => \count_Temp1_s[22]\, Y
         => OPEN, FCO => \count_Temp1_cry[22]_net_1\);
    
    \HrdyCount_3[0]\ : CFG4
      generic map(INIT => x"1A5A")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, C => \un1_hready_flngedge\, D => 
        clock_count, Y => \HrdyCount_3[0]_net_1\);
    
    \Recount_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \Recount[1]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => Recount_s_136_FCO, 
        S => \Recount_s[1]\, Y => OPEN, FCO => 
        \Recount_cry[1]_net_1\);
    
    \clock_count[2]\ : SLE
      port map(D => \clock_count_s[2]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[2]_net_1\);
    
    HADDR_TEMP_7_cry_6 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[6]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_7_cry_5\, S => 
        \HADDR_TEMP_7[6]\, Y => OPEN, FCO => \HADDR_TEMP_7_cry_6\);
    
    \Recount[12]\ : SLE
      port map(D => \Recount_lm[12]\, CLK => HCLK, EN => Recounte, 
        ALn => un1_reset_n_2_i, ADn => \HREADY\, SLn => \HREADY\, 
        SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \Recount[12]_net_1\);
    
    \clock_count[21]\ : SLE
      port map(D => \clock_count_s[21]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[21]_net_1\);
    
    INT1_TEMP_RNO : CFG4
      generic map(INIT => x"3055")

      port map(A => \htrans11\, B => HREADYOUT, C => 
        \HREADY_Int0\, D => \htrans10\, Y => un1_htrans10_2_i_0);
    
    \HWRITE_DATA_TEMP_lm_0[29]\ : CFG4
      generic map(INIT => x"D888")

      port map(A => \htrans7_4_RNI0E4A\, B => 
        \HWRITE_DATA_TEMP_s[29]\, C => N_228, D => \htrans11\, Y
         => \HWRITE_DATA_TEMP_lm[29]\);
    
    \HWRITE_DATA_TEMP[8]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[8]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[8]\);
    
    \count_Temp1_lm_0[27]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \un5_clock_count\, B => \count_Temp1_s[27]\, 
        Y => \count_Temp1_lm[27]\);
    
    un7_clock_count_19 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[19]_net_1\, B => 
        \clock_count[18]_net_1\, C => \clock_count[17]_net_1\, D
         => \clock_count[16]_net_1\, Y => \un7_clock_count_19\);
    
    \HWRITE_DATA_TEMP_cry[14]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[14]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[13]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[14]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[14]_net_1\);
    
    \HADDR_TEMP[16]\ : SLE
      port map(D => \HADDR_TEMP_7[16]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[16]\);
    
    \HWRITE_DATA_TEMP_cry[19]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[19]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[18]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[19]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[19]_net_1\);
    
    \HWRITE_DATA_TEMP[2]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[2]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[2]\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity Fabric_Master2 is

    port( HTRANS        : out   std_logic_vector(1 downto 0);
          HSIZE         : out   std_logic_vector(1 downto 0);
          HWDATA        : out   std_logic_vector(31 downto 0);
          HADDR         : out   std_logic_vector(31 downto 0);
          HRDATA        : in    std_logic_vector(31 downto 0);
          RESET_N       : in    std_logic;
          HCLK          : in    std_logic;
          HWRITE        : out   std_logic;
          HMASTLOCK     : out   std_logic;
          HREADY        : out   std_logic;
          HSEL          : out   std_logic;
          HREADYOUT     : in    std_logic;
          HRESP         : in    std_logic;
          INT2          : out   std_logic;
          MASTER2_START : in    std_logic;
          MASTER2_STOP  : in    std_logic
        );

end Fabric_Master2;

architecture DEF_ARCH of Fabric_Master2 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \HWDATA[0]\, \HADDR[0]\, \HADDR[1]\, \HADDR[2]\, 
        \HADDR[3]\, \HADDR[4]\, \HADDR[5]\, \HADDR[6]\, 
        \HADDR[7]\, \HADDR[8]\, \HADDR[9]\, \HADDR[10]\, 
        \HADDR[11]\, \HADDR[12]\, \HADDR[13]\, \HADDR[14]\, 
        \HADDR[15]\, \HADDR[16]\, \HADDR[17]\, \HADDR[18]\, 
        \HADDR[19]\, \HADDR[20]\, \HADDR[21]\, \HADDR[22]\, 
        \HADDR[23]\, \HADDR[24]\, \HADDR[25]\, \HADDR[26]\, 
        \HADDR[27]\, \HADDR[28]\, \HADDR[29]\, \HADDR[30]\, 
        \HADDR[31]\, \HMASTLOCK\, \HREADY\, HSEL_net_1, 
        \un8_hready_flngedge\, \un12_clock_count\, 
        \ahb_states[5]_net_1\, clock_count, \ahb_states[3]_net_1\, 
        \ahb_states[2]_net_1\, \ahb_states[1]_net_1\, 
        \ahb_states[0]_net_1\, \clock_count[0]_net_1\, 
        \clock_count[1]_net_1\, \clock_count[2]_net_1\, 
        \clock_count[3]_net_1\, \clock_count[4]_net_1\, 
        \clock_count[5]_net_1\, \clock_count[6]_net_1\, 
        \clock_count[7]_net_1\, \clock_count[8]_net_1\, 
        \clock_count[9]_net_1\, \clock_count[10]_net_1\, 
        \clock_count[11]_net_1\, \clock_count[12]_net_1\, 
        \clock_count[13]_net_1\, \clock_count[14]_net_1\, 
        \clock_count[15]_net_1\, \clock_count[16]_net_1\, 
        \clock_count[17]_net_1\, \clock_count[18]_net_1\, 
        \clock_count[19]_net_1\, \clock_count[20]_net_1\, 
        \clock_count[21]_net_1\, \clock_count[22]_net_1\, 
        \clock_count[23]_net_1\, \clock_count[24]_net_1\, 
        \clock_count[25]_net_1\, \clock_count[26]_net_1\, 
        \clock_count[27]_net_1\, \clock_count[28]_net_1\, 
        \clock_count[29]_net_1\, \clock_count[30]_net_1\, 
        \clock_count[31]_net_1\, \HrdyCount[0]_net_1\, 
        \Res_Enable\, \HREADY_Int0\, \Tr_Enable\, 
        \HrdyCount[1]_net_1\, \ahb_states[6]_net_1\, 
        \HrdyCount_3[0]_net_1\, \HrdyCount_3[1]_net_1\, 
        \count_Temp1[0]_net_1\, \Recount[0]_net_1\, 
        \Recount[1]_net_1\, \Recount[2]_net_1\, 
        \Recount[3]_net_1\, \Recount[4]_net_1\, 
        \Recount[5]_net_1\, \Recount[6]_net_1\, 
        \Recount[7]_net_1\, \Recount[8]_net_1\, 
        \Recount[9]_net_1\, \Recount[10]_net_1\, 
        \Recount[11]_net_1\, \Recount[12]_net_1\, 
        \Recount[13]_net_1\, \Recount[14]_net_1\, 
        \Recount[15]_net_1\, \Recount[16]_net_1\, 
        \Recount[17]_net_1\, \Recount[18]_net_1\, 
        \Recount[19]_net_1\, \Recount[20]_net_1\, 
        \Recount[21]_net_1\, \Recount[22]_net_1\, 
        \Recount[23]_net_1\, \Recount[24]_net_1\, 
        \Recount[25]_net_1\, \Recount[26]_net_1\, 
        \Recount[27]_net_1\, \Recount[28]_net_1\, 
        \Recount[29]_net_1\, \Recount[30]_net_1\, 
        \Recount[31]_net_1\, \HADDR_TEMP_6[3]\, \HADDR_TEMP_6[4]\, 
        \HADDR_TEMP_6[5]\, \HADDR_TEMP_6[6]\, \HADDR_TEMP_6[7]\, 
        \HADDR_TEMP_6[8]\, \HADDR_TEMP_6[9]\, \HADDR_TEMP_6[10]\, 
        \HADDR_TEMP_6[11]\, \HADDR_TEMP_6[12]\, 
        \HADDR_TEMP_6[13]\, \HADDR_TEMP_6[14]\, 
        \HADDR_TEMP_6[15]\, \HADDR_TEMP_6[16]\, 
        \HADDR_TEMP_6[17]\, \HADDR_TEMP_6[18]\, 
        \HADDR_TEMP_6[19]\, \HADDR_TEMP_6[20]\, 
        \HADDR_TEMP_6[21]\, \HADDR_TEMP_6[22]\, 
        \HADDR_TEMP_6[23]\, \HADDR_TEMP_6[24]\, 
        \HADDR_TEMP_6[25]\, \HADDR_TEMP_6[26]\, 
        \HADDR_TEMP_6[27]\, \HADDR_TEMP_6[28]\, 
        \HADDR_TEMP_6[29]\, \HADDR_TEMP_6[30]\, 
        \HADDR_TEMP_6[31]\, clock_counte, count_Temp1e, 
        \un1_HSEL_1_u\, \HWRITE_DATA_TEMP_6[1]_net_1\, 
        \HWRITE_DATA_TEMP_6[2]_net_1\, 
        \HWRITE_DATA_TEMP_6[3]_net_1\, 
        \HWRITE_DATA_TEMP_6[4]_net_1\, 
        \HWRITE_DATA_TEMP_6[5]_net_1\, 
        \HWRITE_DATA_TEMP_6[6]_net_1\, 
        \HWRITE_DATA_TEMP_6[7]_net_1\, 
        \HWRITE_DATA_TEMP_6[8]_net_1\, 
        \HWRITE_DATA_TEMP_6[9]_net_1\, 
        \HWRITE_DATA_TEMP_6[10]_net_1\, 
        \HWRITE_DATA_TEMP_6[11]_net_1\, 
        \HWRITE_DATA_TEMP_6[12]_net_1\, 
        \HWRITE_DATA_TEMP_6[13]_net_1\, 
        \HWRITE_DATA_TEMP_6[14]_net_1\, 
        \HWRITE_DATA_TEMP_6[15]_net_1\, 
        \HWRITE_DATA_TEMP_6[16]_net_1\, 
        \HWRITE_DATA_TEMP_6[17]_net_1\, 
        \HWRITE_DATA_TEMP_6[18]_net_1\, 
        \HWRITE_DATA_TEMP_6[19]_net_1\, 
        \HWRITE_DATA_TEMP_6[20]_net_1\, 
        \HWRITE_DATA_TEMP_6[21]_net_1\, 
        \HWRITE_DATA_TEMP_6[22]_net_1\, 
        \HWRITE_DATA_TEMP_6[23]_net_1\, 
        \HWRITE_DATA_TEMP_6[24]_net_1\, 
        \HWRITE_DATA_TEMP_6[25]_net_1\, 
        \HWRITE_DATA_TEMP_6[26]_net_1\, 
        \HWRITE_DATA_TEMP_6[27]_net_1\, 
        \HWRITE_DATA_TEMP_6[28]_net_1\, 
        \HWRITE_DATA_TEMP_6[29]_net_1\, 
        \HWRITE_DATA_TEMP_6[30]_net_1\, 
        \HWRITE_DATA_TEMP_6[31]_net_1\, \un1_master2_start\, 
        \un1_hreadyout\, \htrans11\, \htrans7_4\, \htrans10\, 
        \htrans9\, \htrans6\, \INT2_TEMP_1_sqmuxa\, 
        \clock_count_0_sqmuxa\, \INT2_TEMP_0_sqmuxa\, 
        \un1_hready_flngedge\, htrans6_3, \un7_clock_count\, 
        \un3_hready_rsngedge\, \htrans9_1\, 
        \HADDR_TEMP_1_sqmuxa_1_c\, \HADDR_TEMP_1_sqmuxa_1_d\, 
        ahb_states_1_sqmuxa_1, \HWRITE_DATA_TEMP_lm[0]\, 
        \HWDATA[1]\, \HWRITE_DATA_TEMP_cry[1]_net_1\, 
        \HWRITE_DATA_TEMP_s[1]\, \HWRITE_DATA_TEMP_lm[1]\, 
        \HWDATA[2]\, \HWRITE_DATA_TEMP_cry[2]_net_1\, 
        \HWRITE_DATA_TEMP_s[2]\, \HWRITE_DATA_TEMP_lm[2]\, 
        \HWDATA[3]\, \HWRITE_DATA_TEMP_cry[3]_net_1\, 
        \HWRITE_DATA_TEMP_s[3]\, \HWRITE_DATA_TEMP_lm[3]\, 
        \HWDATA[4]\, \HWRITE_DATA_TEMP_cry[4]_net_1\, 
        \HWRITE_DATA_TEMP_s[4]\, \HWRITE_DATA_TEMP_lm[4]\, 
        \HWDATA[5]\, \HWRITE_DATA_TEMP_cry[5]_net_1\, 
        \HWRITE_DATA_TEMP_s[5]\, \HWRITE_DATA_TEMP_lm[5]\, 
        \HWDATA[6]\, \HWRITE_DATA_TEMP_cry[6]_net_1\, 
        \HWRITE_DATA_TEMP_s[6]\, \HWRITE_DATA_TEMP_lm[6]\, 
        \HWDATA[7]\, \HWRITE_DATA_TEMP_cry[7]_net_1\, 
        \HWRITE_DATA_TEMP_s[7]\, \HWRITE_DATA_TEMP_lm[7]\, 
        \HWDATA[8]\, \HWRITE_DATA_TEMP_cry[8]_net_1\, 
        \HWRITE_DATA_TEMP_s[8]\, \HWRITE_DATA_TEMP_lm[8]\, 
        \HWDATA[9]\, \HWRITE_DATA_TEMP_cry[9]_net_1\, 
        \HWRITE_DATA_TEMP_s[9]\, \HWRITE_DATA_TEMP_lm[9]\, 
        \HWDATA[10]\, \HWRITE_DATA_TEMP_cry[10]_net_1\, 
        \HWRITE_DATA_TEMP_s[10]\, \HWRITE_DATA_TEMP_lm[10]\, 
        \HWDATA[11]\, \HWRITE_DATA_TEMP_cry[11]_net_1\, 
        \HWRITE_DATA_TEMP_s[11]\, \HWRITE_DATA_TEMP_lm[11]\, 
        \HWDATA[12]\, \HWRITE_DATA_TEMP_cry[12]_net_1\, 
        \HWRITE_DATA_TEMP_s[12]\, \HWRITE_DATA_TEMP_lm[12]\, 
        \HWDATA[13]\, \HWRITE_DATA_TEMP_cry[13]_net_1\, 
        \HWRITE_DATA_TEMP_s[13]\, \HWRITE_DATA_TEMP_lm[13]\, 
        \HWDATA[14]\, \HWRITE_DATA_TEMP_cry[14]_net_1\, 
        \HWRITE_DATA_TEMP_s[14]\, \HWRITE_DATA_TEMP_lm[14]\, 
        \HWDATA[15]\, \HWRITE_DATA_TEMP_cry[15]_net_1\, 
        \HWRITE_DATA_TEMP_s[15]\, \HWRITE_DATA_TEMP_lm[15]\, 
        \HWDATA[16]\, \HWRITE_DATA_TEMP_cry[16]_net_1\, 
        \HWRITE_DATA_TEMP_s[16]\, \HWRITE_DATA_TEMP_lm[16]\, 
        \HWDATA[17]\, \HWRITE_DATA_TEMP_cry[17]_net_1\, 
        \HWRITE_DATA_TEMP_s[17]\, \HWRITE_DATA_TEMP_lm[17]\, 
        \HWDATA[18]\, \HWRITE_DATA_TEMP_cry[18]_net_1\, 
        \HWRITE_DATA_TEMP_s[18]\, \HWRITE_DATA_TEMP_lm[18]\, 
        \HWDATA[19]\, \HWRITE_DATA_TEMP_cry[19]_net_1\, 
        \HWRITE_DATA_TEMP_s[19]\, \HWRITE_DATA_TEMP_lm[19]\, 
        \HWDATA[20]\, \HWRITE_DATA_TEMP_cry[20]_net_1\, 
        \HWRITE_DATA_TEMP_s[20]\, \HWRITE_DATA_TEMP_lm[20]\, 
        \HWDATA[21]\, \HWRITE_DATA_TEMP_cry[21]_net_1\, 
        \HWRITE_DATA_TEMP_s[21]\, \HWRITE_DATA_TEMP_lm[21]\, 
        \HWDATA[22]\, \HWRITE_DATA_TEMP_cry[22]_net_1\, 
        \HWRITE_DATA_TEMP_s[22]\, \HWRITE_DATA_TEMP_lm[22]\, 
        \HWDATA[23]\, \HWRITE_DATA_TEMP_cry[23]_net_1\, 
        \HWRITE_DATA_TEMP_s[23]\, \HWRITE_DATA_TEMP_lm[23]\, 
        \HWDATA[24]\, \HWRITE_DATA_TEMP_cry[24]_net_1\, 
        \HWRITE_DATA_TEMP_s[24]\, \HWRITE_DATA_TEMP_lm[24]\, 
        \HWDATA[25]\, \HWRITE_DATA_TEMP_cry[25]_net_1\, 
        \HWRITE_DATA_TEMP_s[25]\, \HWRITE_DATA_TEMP_lm[25]\, 
        \HWDATA[26]\, \HWRITE_DATA_TEMP_cry[26]_net_1\, 
        \HWRITE_DATA_TEMP_s[26]\, \HWRITE_DATA_TEMP_lm[26]\, 
        \HWDATA[27]\, \HWRITE_DATA_TEMP_cry[27]_net_1\, 
        \HWRITE_DATA_TEMP_s[27]\, \HWRITE_DATA_TEMP_lm[27]\, 
        \HWDATA[28]\, \HWRITE_DATA_TEMP_cry[28]_net_1\, 
        \HWRITE_DATA_TEMP_s[28]\, \HWRITE_DATA_TEMP_lm[28]\, 
        \HWDATA[29]\, \HWRITE_DATA_TEMP_cry[29]_net_1\, 
        \HWRITE_DATA_TEMP_s[29]\, \HWRITE_DATA_TEMP_lm[29]\, 
        \HWDATA[30]\, \HWRITE_DATA_TEMP_cry[30]_net_1\, 
        \HWRITE_DATA_TEMP_s[30]\, \HWRITE_DATA_TEMP_lm[30]\, 
        \HWDATA[31]\, \HWRITE_DATA_TEMP_s[31]_net_1\, 
        \HWRITE_DATA_TEMP_lm[31]\, \count_Temp1_lm[0]\, 
        \count_Temp1[1]_net_1\, \count_Temp1_cry[1]_net_1\, 
        \count_Temp1_s[1]\, \count_Temp1_lm[1]\, 
        \count_Temp1[2]_net_1\, \count_Temp1_cry[2]_net_1\, 
        \count_Temp1_s[2]\, \count_Temp1_lm[2]\, 
        \count_Temp1[3]_net_1\, \count_Temp1_cry[3]_net_1\, 
        \count_Temp1_s[3]\, \count_Temp1_lm[3]\, 
        \count_Temp1[4]_net_1\, \count_Temp1_cry[4]_net_1\, 
        \count_Temp1_s[4]\, \count_Temp1_lm[4]\, 
        \count_Temp1[5]_net_1\, \count_Temp1_cry[5]_net_1\, 
        \count_Temp1_s[5]\, \count_Temp1_lm[5]\, 
        \count_Temp1[6]_net_1\, \count_Temp1_cry[6]_net_1\, 
        \count_Temp1_s[6]\, \count_Temp1_lm[6]\, 
        \count_Temp1[7]_net_1\, \count_Temp1_cry[7]_net_1\, 
        \count_Temp1_s[7]\, \count_Temp1_lm[7]\, 
        \count_Temp1[8]_net_1\, \count_Temp1_cry[8]_net_1\, 
        \count_Temp1_s[8]\, \count_Temp1_lm[8]\, 
        \count_Temp1[9]_net_1\, \count_Temp1_cry[9]_net_1\, 
        \count_Temp1_s[9]\, \count_Temp1_lm[9]\, 
        \count_Temp1[10]_net_1\, \count_Temp1_cry[10]_net_1\, 
        \count_Temp1_s[10]\, \count_Temp1_lm[10]\, 
        \count_Temp1[11]_net_1\, \count_Temp1_cry[11]_net_1\, 
        \count_Temp1_s[11]\, \count_Temp1_lm[11]\, 
        \count_Temp1[12]_net_1\, \count_Temp1_cry[12]_net_1\, 
        \count_Temp1_s[12]\, \count_Temp1_lm[12]\, 
        \count_Temp1[13]_net_1\, \count_Temp1_cry[13]_net_1\, 
        \count_Temp1_s[13]\, \count_Temp1_lm[13]\, 
        \count_Temp1[14]_net_1\, \count_Temp1_cry[14]_net_1\, 
        \count_Temp1_s[14]\, \count_Temp1_lm[14]\, 
        \count_Temp1[15]_net_1\, \count_Temp1_cry[15]_net_1\, 
        \count_Temp1_s[15]\, \count_Temp1_lm[15]\, 
        \count_Temp1[16]_net_1\, \count_Temp1_cry[16]_net_1\, 
        \count_Temp1_s[16]\, \count_Temp1_lm[16]\, 
        \count_Temp1[17]_net_1\, \count_Temp1_cry[17]_net_1\, 
        \count_Temp1_s[17]\, \count_Temp1_lm[17]\, 
        \count_Temp1[18]_net_1\, \count_Temp1_cry[18]_net_1\, 
        \count_Temp1_s[18]\, \count_Temp1_lm[18]\, 
        \count_Temp1[19]_net_1\, \count_Temp1_cry[19]_net_1\, 
        \count_Temp1_s[19]\, \count_Temp1_lm[19]\, 
        \count_Temp1[20]_net_1\, \count_Temp1_cry[20]_net_1\, 
        \count_Temp1_s[20]\, \count_Temp1_lm[20]\, 
        \count_Temp1[21]_net_1\, \count_Temp1_cry[21]_net_1\, 
        \count_Temp1_s[21]\, \count_Temp1_lm[21]\, 
        \count_Temp1[22]_net_1\, \count_Temp1_cry[22]_net_1\, 
        \count_Temp1_s[22]\, \count_Temp1_lm[22]\, 
        \count_Temp1[23]_net_1\, \count_Temp1_cry[23]_net_1\, 
        \count_Temp1_s[23]\, \count_Temp1_lm[23]\, 
        \count_Temp1[24]_net_1\, \count_Temp1_cry[24]_net_1\, 
        \count_Temp1_s[24]\, \count_Temp1_lm[24]\, 
        \count_Temp1[25]_net_1\, \count_Temp1_cry[25]_net_1\, 
        \count_Temp1_s[25]\, \count_Temp1_lm[25]\, 
        \count_Temp1[26]_net_1\, \count_Temp1_cry[26]_net_1\, 
        \count_Temp1_s[26]\, \count_Temp1_lm[26]\, 
        \count_Temp1[27]_net_1\, \count_Temp1_cry[27]_net_1\, 
        \count_Temp1_s[27]\, \count_Temp1_lm[27]\, 
        \count_Temp1[28]_net_1\, \count_Temp1_cry[28]_net_1\, 
        \count_Temp1_s[28]\, \count_Temp1_lm[28]\, 
        \count_Temp1[29]_net_1\, \count_Temp1_cry[29]_net_1\, 
        \count_Temp1_s[29]\, \count_Temp1_lm[29]\, 
        \count_Temp1[30]_net_1\, \count_Temp1_cry[30]_net_1\, 
        \count_Temp1_s[30]\, \count_Temp1_lm[30]\, 
        \count_Temp1[31]_net_1\, \count_Temp1_s[31]_net_1\, 
        \count_Temp1_lm[31]\, Recount, \Recount_cry[0]\, 
        \Recount_s[0]\, \Recount_cry[1]\, \Recount_s[1]\, 
        \Recount_cry[2]\, \Recount_s[2]\, \Recount_cry[3]\, 
        \Recount_s[3]\, \Recount_cry[4]\, \Recount_s[4]\, 
        \Recount_cry[5]\, \Recount_s[5]\, \Recount_cry[6]\, 
        \Recount_s[6]\, \Recount_cry[7]\, \Recount_s[7]\, 
        \Recount_cry[8]\, \Recount_s[8]\, \Recount_cry[9]\, 
        \Recount_s[9]\, \Recount_cry[10]\, \Recount_s[10]\, 
        \Recount_cry[11]\, \Recount_s[11]\, \Recount_cry[12]\, 
        \Recount_s[12]\, \Recount_cry[13]\, \Recount_s[13]\, 
        \Recount_cry[14]\, \Recount_s[14]\, \Recount_cry[15]\, 
        \Recount_s[15]\, \Recount_cry[16]\, \Recount_s[16]\, 
        \Recount_cry[17]\, \Recount_s[17]\, \Recount_cry[18]\, 
        \Recount_s[18]\, \Recount_cry[19]\, \Recount_s[19]\, 
        \Recount_cry[20]\, \Recount_s[20]\, \Recount_cry[21]\, 
        \Recount_s[21]\, \Recount_cry[22]\, \Recount_s[22]\, 
        \Recount_cry[23]\, \Recount_s[23]\, \Recount_cry[24]\, 
        \Recount_s[24]\, \Recount_cry[25]\, \Recount_s[25]\, 
        \Recount_cry[26]\, \Recount_s[26]\, \Recount_cry[27]\, 
        \Recount_s[27]\, \Recount_cry[28]\, \Recount_s[28]\, 
        \Recount_cry[29]\, \Recount_s[29]\, \Recount_cry[30]\, 
        \Recount_s[30]\, \Recount_s[31]\, 
        \clock_count_cry[0]_net_1\, \clock_count_s[0]\, 
        \clock_count_cry[1]_net_1\, \clock_count_s[1]\, 
        \clock_count_cry[2]_net_1\, \clock_count_s[2]\, 
        \clock_count_cry[3]_net_1\, \clock_count_s[3]\, 
        \clock_count_cry[4]_net_1\, \clock_count_s[4]\, 
        \clock_count_cry[5]_net_1\, \clock_count_s[5]\, 
        \clock_count_cry[6]_net_1\, \clock_count_s[6]\, 
        \clock_count_cry[7]_net_1\, \clock_count_s[7]\, 
        \clock_count_cry[8]_net_1\, \clock_count_s[8]\, 
        \clock_count_cry[9]_net_1\, \clock_count_s[9]\, 
        \clock_count_cry[10]_net_1\, \clock_count_s[10]\, 
        \clock_count_cry[11]_net_1\, \clock_count_s[11]\, 
        \clock_count_cry[12]_net_1\, \clock_count_s[12]\, 
        \clock_count_cry[13]_net_1\, \clock_count_s[13]\, 
        \clock_count_cry[14]_net_1\, \clock_count_s[14]\, 
        \clock_count_cry[15]_net_1\, \clock_count_s[15]\, 
        \clock_count_cry[16]_net_1\, \clock_count_s[16]\, 
        \clock_count_cry[17]_net_1\, \clock_count_s[17]\, 
        \clock_count_cry[18]_net_1\, \clock_count_s[18]\, 
        \clock_count_cry[19]_net_1\, \clock_count_s[19]\, 
        \clock_count_cry[20]_net_1\, \clock_count_s[20]\, 
        \clock_count_cry[21]_net_1\, \clock_count_s[21]\, 
        \clock_count_cry[22]_net_1\, \clock_count_s[22]\, 
        \clock_count_cry[23]_net_1\, \clock_count_s[23]\, 
        \clock_count_cry[24]_net_1\, \clock_count_s[24]\, 
        \clock_count_cry[25]_net_1\, \clock_count_s[25]\, 
        \clock_count_cry[26]_net_1\, \clock_count_s[26]\, 
        \clock_count_cry[27]_net_1\, \clock_count_s[27]\, 
        \clock_count_cry[28]_net_1\, \clock_count_s[28]\, 
        \clock_count_cry[29]_net_1\, \clock_count_s[29]\, 
        \clock_count_cry[30]_net_1\, \clock_count_s[30]\, 
        \clock_count_s[31]_net_1\, \HADDR_TEMP_6[0]_net_1\, 
        \HADDR_TEMP_6[1]_net_1\, HADDR_TEMP_6_cry_2, 
        \HADDR_TEMP_6_cry_3\, \HADDR_TEMP_6_cry_4\, 
        \HADDR_TEMP_6_cry_5\, \HADDR_TEMP_6_cry_6\, 
        \HADDR_TEMP_6_cry_7\, \HADDR_TEMP_6_cry_8\, 
        \HADDR_TEMP_6_cry_9\, \HADDR_TEMP_6_cry_10\, 
        \HADDR_TEMP_6_cry_11\, \HADDR_TEMP_6_cry_12\, 
        \HADDR_TEMP_6_cry_13\, \HADDR_TEMP_6_cry_14\, 
        \HADDR_TEMP_6_cry_15\, \HADDR_TEMP_6_cry_16\, 
        \HADDR_TEMP_6_cry_17\, \HADDR_TEMP_6_cry_18\, 
        \HADDR_TEMP_6_cry_19\, \HADDR_TEMP_6_cry_20\, 
        \HADDR_TEMP_6_cry_21\, \HADDR_TEMP_6_cry_22\, 
        \HADDR_TEMP_6_cry_23\, \HADDR_TEMP_6_cry_24\, 
        \HADDR_TEMP_6_cry_25\, \HADDR_TEMP_6_cry_26\, 
        \HADDR_TEMP_6_cry_27\, \HADDR_TEMP_6_cry_28\, 
        \HADDR_TEMP_6_cry_29\, \HADDR_TEMP_6_cry_30\, 
        \htrans11_0\, \htrans10_1\, \un1_hreadyout_0\, 
        \un1_hreadyout_7\, \un1_hreadyout_8\, \un1_hreadyout_9\, 
        \htrans6_1\, \HADDR_TEMP_1_sqmuxa_1_c_1\, 
        \HADDR_TEMP_0_sqmuxa_0\, \HADDR_TEMP_1_sqmuxa_0\, 
        \un7_clock_count_13\, \un7_clock_count_16\, 
        \un7_clock_count_17\, \un7_clock_count_18\, 
        \un7_clock_count_19\, \un7_clock_count_20\, 
        \un7_clock_count_21\, \un7_clock_count_23\, 
        \un7_clock_count_27\, \un7_clock_count_28\, 
        \un1_ahb_states_1_sqmuxa_0\, \un1_ahb_states_1_sqmuxa_1\, 
        \un1_ahb_states_1_sqmuxa_2\, un1_htrans6_6_2, 
        \un1_htrans6_6_3\, \ahb_states_i_0[0]\, un1_htrans6_4_i_0, 
        un1_htrans6_2_i_0, un1_htrans10_2_i_0, 
        un1_ahb_states_1_sqmuxa_i_0, Recount_lcry_cy, 
        \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\, 
        clock_count_s_131_FCO, count_Temp1_s_132_FCO, 
        HWRITE_DATA_TEMP_s_133_FCO, HADDR_TEMP_6_cry_2_0_Y, 
        HREADYOUT_RNIVC501_Y, Res_Enable_RNI54OF_Y, 
        un1_reset_n_2_i, \un1_reset_n_2\ : std_logic;

begin 

    HTRANS(0) <= \HMASTLOCK\;
    HWDATA(31) <= \HWDATA[31]\;
    HWDATA(30) <= \HWDATA[30]\;
    HWDATA(29) <= \HWDATA[29]\;
    HWDATA(28) <= \HWDATA[28]\;
    HWDATA(27) <= \HWDATA[27]\;
    HWDATA(26) <= \HWDATA[26]\;
    HWDATA(25) <= \HWDATA[25]\;
    HWDATA(24) <= \HWDATA[24]\;
    HWDATA(23) <= \HWDATA[23]\;
    HWDATA(22) <= \HWDATA[22]\;
    HWDATA(21) <= \HWDATA[21]\;
    HWDATA(20) <= \HWDATA[20]\;
    HWDATA(19) <= \HWDATA[19]\;
    HWDATA(18) <= \HWDATA[18]\;
    HWDATA(17) <= \HWDATA[17]\;
    HWDATA(16) <= \HWDATA[16]\;
    HWDATA(15) <= \HWDATA[15]\;
    HWDATA(14) <= \HWDATA[14]\;
    HWDATA(13) <= \HWDATA[13]\;
    HWDATA(12) <= \HWDATA[12]\;
    HWDATA(11) <= \HWDATA[11]\;
    HWDATA(10) <= \HWDATA[10]\;
    HWDATA(9) <= \HWDATA[9]\;
    HWDATA(8) <= \HWDATA[8]\;
    HWDATA(7) <= \HWDATA[7]\;
    HWDATA(6) <= \HWDATA[6]\;
    HWDATA(5) <= \HWDATA[5]\;
    HWDATA(4) <= \HWDATA[4]\;
    HWDATA(3) <= \HWDATA[3]\;
    HWDATA(2) <= \HWDATA[2]\;
    HWDATA(1) <= \HWDATA[1]\;
    HWDATA(0) <= \HWDATA[0]\;
    HADDR(31) <= \HADDR[31]\;
    HADDR(30) <= \HADDR[30]\;
    HADDR(29) <= \HADDR[29]\;
    HADDR(28) <= \HADDR[28]\;
    HADDR(27) <= \HADDR[27]\;
    HADDR(26) <= \HADDR[26]\;
    HADDR(25) <= \HADDR[25]\;
    HADDR(24) <= \HADDR[24]\;
    HADDR(23) <= \HADDR[23]\;
    HADDR(22) <= \HADDR[22]\;
    HADDR(21) <= \HADDR[21]\;
    HADDR(20) <= \HADDR[20]\;
    HADDR(19) <= \HADDR[19]\;
    HADDR(18) <= \HADDR[18]\;
    HADDR(17) <= \HADDR[17]\;
    HADDR(16) <= \HADDR[16]\;
    HADDR(15) <= \HADDR[15]\;
    HADDR(14) <= \HADDR[14]\;
    HADDR(13) <= \HADDR[13]\;
    HADDR(12) <= \HADDR[12]\;
    HADDR(11) <= \HADDR[11]\;
    HADDR(10) <= \HADDR[10]\;
    HADDR(9) <= \HADDR[9]\;
    HADDR(8) <= \HADDR[8]\;
    HADDR(7) <= \HADDR[7]\;
    HADDR(6) <= \HADDR[6]\;
    HADDR(5) <= \HADDR[5]\;
    HADDR(4) <= \HADDR[4]\;
    HADDR(3) <= \HADDR[3]\;
    HADDR(2) <= \HADDR[2]\;
    HADDR(1) <= \HADDR[1]\;
    HADDR(0) <= \HADDR[0]\;
    HMASTLOCK <= \HMASTLOCK\;
    HREADY <= \HREADY\;
    HSEL <= HSEL_net_1;

    \count_Temp1_lm_0[13]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[13]\, Y => \count_Temp1_lm[13]\);
    
    \HWRITE_DATA_TEMP[18]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[18]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[18]\);
    
    \Recount[22]\ : SLE
      port map(D => \Recount_s[22]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[22]_net_1\);
    
    \HrdyCount[1]\ : SLE
      port map(D => \HrdyCount_3[1]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HrdyCount[1]_net_1\);
    
    \HADDR_TEMP[20]\ : SLE
      port map(D => \HADDR_TEMP_6[20]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[20]\);
    
    \HWRITE_DATA_TEMP_6[19]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[19]_net_1\, D => \Recount[19]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[19]_net_1\);
    
    \ahb_states[0]\ : SLE
      port map(D => \ahb_states[2]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[0]_net_1\);
    
    \Recount[4]\ : SLE
      port map(D => \Recount_s[4]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[4]_net_1\);
    
    un3_hready_rsngedge : CFG3
      generic map(INIT => x"40")

      port map(A => \HREADY_Int0\, B => HREADYOUT, C => 
        \Tr_Enable\, Y => \un3_hready_rsngedge\);
    
    \HWRITE_DATA_TEMP_lm_0[15]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[15]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[15]\, Y
         => \HWRITE_DATA_TEMP_lm[15]\);
    
    \HWRITE_DATA_TEMP_lm_0[31]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[31]_net_1\, C => 
        \ahb_states[0]_net_1\, D => 
        \HWRITE_DATA_TEMP_s[31]_net_1\, Y => 
        \HWRITE_DATA_TEMP_lm[31]\);
    
    \HADDR_TEMP_6[0]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \htrans11\, B => \HADDR[0]\, Y => 
        \HADDR_TEMP_6[0]_net_1\);
    
    un1_hreadyout : CFG3
      generic map(INIT => x"80")

      port map(A => \un1_hreadyout_7\, B => \un1_hreadyout_9\, C
         => \un1_hreadyout_8\, Y => \un1_hreadyout\);
    
    \Recount[17]\ : SLE
      port map(D => \Recount_s[17]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[17]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[6]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[5]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[6]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[6]_net_1\);
    
    \HADDR_TEMP[2]\ : SLE
      port map(D => HADDR_TEMP_6_cry_2_0_Y, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[2]\);
    
    \count_Temp1[17]\ : SLE
      port map(D => \count_Temp1_lm[17]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[17]_net_1\);
    
    \clock_count[4]\ : SLE
      port map(D => \clock_count_s[4]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[4]_net_1\);
    
    \HWRITE_DATA_TEMP_6[15]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[15]_net_1\, D => \Recount[15]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[15]_net_1\);
    
    \clock_count[22]\ : SLE
      port map(D => \clock_count_s[22]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[22]_net_1\);
    
    \HWRITE_DATA_TEMP[21]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[21]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[21]\);
    
    HADDR_TEMP_6_cry_4 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[4]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_3\, S => 
        \HADDR_TEMP_6[4]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_4\);
    
    \ahb_states[4]\ : SLE
      port map(D => \ahb_states[5]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => clock_count);
    
    \Recount[27]\ : SLE
      port map(D => \Recount_s[27]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[27]_net_1\);
    
    \Recount[15]\ : SLE
      port map(D => \Recount_s[15]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[15]_net_1\);
    
    INT2_TEMP_0_sqmuxa : CFG3
      generic map(INIT => x"40")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => 
        \htrans10\, Y => \INT2_TEMP_0_sqmuxa\);
    
    \HWRITE_DATA_TEMP_cry[21]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[21]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[20]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[21]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[21]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[14]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[14]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[14]\, Y
         => \HWRITE_DATA_TEMP_lm[14]\);
    
    \HWRITE_DATA_TEMP[27]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[27]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[27]\);
    
    HWRITE_DATA_TEMP_s_133 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[0]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, Y => OPEN, 
        FCO => HWRITE_DATA_TEMP_s_133_FCO);
    
    \count_Temp1[14]\ : SLE
      port map(D => \count_Temp1_lm[14]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[14]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[18]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[18]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[17]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[18]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[18]_net_1\);
    
    \HWRITE_DATA_TEMP_6[18]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[18]_net_1\, D => \Recount[18]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[18]_net_1\);
    
    \count_Temp1_lm_0[10]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[10]\, Y => \count_Temp1_lm[10]\);
    
    \Recount_RNIO16SS[22]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[22]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[21]\, S => \Recount_s[22]\, Y => OPEN, FCO
         => \Recount_cry[22]\);
    
    \HWRITE_DATA_TEMP_lm_0[7]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[7]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[7]\, Y => 
        \HWRITE_DATA_TEMP_lm[7]\);
    
    \HWRITE_DATA_TEMP[31]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[31]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[31]\);
    
    \HWRITE_DATA_TEMP[3]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[3]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[3]\);
    
    \count_Temp1[16]\ : SLE
      port map(D => \count_Temp1_lm[16]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[16]_net_1\);
    
    \Recount_RNIA787P[19]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[19]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[18]\, S => \Recount_s[19]\, Y => OPEN, FCO
         => \Recount_cry[19]\);
    
    \clock_count_cry[17]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[17]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[16]_net_1\, S => \clock_count_s[17]\, Y
         => OPEN, FCO => \clock_count_cry[17]_net_1\);
    
    \ahb_states_RNI6OC1[0]\ : CFG1
      generic map(INIT => "01")

      port map(A => \ahb_states[0]_net_1\, Y => 
        \ahb_states_i_0[0]\);
    
    \count_Temp1[8]\ : SLE
      port map(D => \count_Temp1_lm[8]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[8]_net_1\);
    
    \Recount_RNIKC53U[23]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[23]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[22]\, S => \Recount_s[23]\, Y => OPEN, FCO
         => \Recount_cry[23]\);
    
    \Recount[25]\ : SLE
      port map(D => \Recount_s[25]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[25]_net_1\);
    
    \HWRITE_DATA_TEMP_6[7]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[7]_net_1\, D => \Recount[7]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[7]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[4]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[4]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[4]\, Y => 
        \HWRITE_DATA_TEMP_lm[4]\);
    
    \clock_count[5]\ : SLE
      port map(D => \clock_count_s[5]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[5]_net_1\);
    
    HADDR_TEMP_6_cry_20 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[20]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_19\, S => 
        \HADDR_TEMP_6[20]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_20\);
    
    \count_Temp1_lm_0[22]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[22]\, Y => \count_Temp1_lm[22]\);
    
    \HWRITE_DATA_TEMP_cry[23]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[23]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[22]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[23]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[23]_net_1\);
    
    un1_reset_n_2_RNIK4E5 : CLKINT
      port map(A => \un1_reset_n_2\, Y => un1_reset_n_2_i);
    
    \HWRITE_DATA_TEMP_cry[8]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[8]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[7]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[8]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[8]_net_1\);
    
    HREADYOUT_RNIVC501 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => HREADYOUT, C => 
        Res_Enable_RNI54OF_Y, D => \HMASTLOCK\, FCI => 
        Recount_lcry_cy, S => OPEN, Y => HREADYOUT_RNIVC501_Y, 
        FCO => Recount);
    
    \count_Temp1_cry[15]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[15]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[14]_net_1\, S => \count_Temp1_s[15]\, Y
         => OPEN, FCO => \count_Temp1_cry[15]_net_1\);
    
    \clock_count[28]\ : SLE
      port map(D => \clock_count_s[28]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[28]_net_1\);
    
    \count_Temp1_lm_0[3]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[3]\, Y => \count_Temp1_lm[3]\);
    
    \HWRITE_DATA_TEMP_lm_0[13]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[13]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[13]\, Y
         => \HWRITE_DATA_TEMP_lm[13]\);
    
    \count_Temp1_cry[17]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[17]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[16]_net_1\, S => \count_Temp1_s[17]\, Y
         => OPEN, FCO => \count_Temp1_cry[17]_net_1\);
    
    \count_Temp1[0]\ : SLE
      port map(D => \count_Temp1_lm[0]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[0]_net_1\);
    
    \HWRITE_DATA_TEMP_6[6]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[6]_net_1\, D => \Recount[6]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[6]_net_1\);
    
    \HWRITE_DATA_TEMP[20]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[20]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[20]\);
    
    \HWRITE_DATA_TEMP_6[4]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[4]_net_1\, D => \Recount[4]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[4]_net_1\);
    
    \count_Temp1_lm_0[4]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[4]\, Y => \count_Temp1_lm[4]\);
    
    \HWRITE_DATA_TEMP_cry[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[7]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[6]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[7]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[7]_net_1\);
    
    \HADDR_TEMP[13]\ : SLE
      port map(D => \HADDR_TEMP_6[13]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[13]\);
    
    \clock_count[16]\ : SLE
      port map(D => \clock_count_s[16]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[16]_net_1\);
    
    \count_Temp1_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[3]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[2]_net_1\, S => \count_Temp1_s[3]\, Y
         => OPEN, FCO => \count_Temp1_cry[3]_net_1\);
    
    \HADDR_TEMP[15]\ : SLE
      port map(D => \HADDR_TEMP_6[15]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HMASTLOCK\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[15]\);
    
    \Recount[13]\ : SLE
      port map(D => \Recount_s[13]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[13]_net_1\);
    
    \HWRITE_DATA_TEMP[11]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[11]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[11]\);
    
    \count_Temp1_cry[25]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[25]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[24]_net_1\, S => \count_Temp1_s[25]\, Y
         => OPEN, FCO => \count_Temp1_cry[25]_net_1\);
    
    \Recount[0]\ : SLE
      port map(D => \Recount_s[0]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[0]_net_1\);
    
    \HWRITE_DATA_TEMP[30]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[30]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[30]\);
    
    \HADDR_TEMP[30]\ : SLE
      port map(D => \HADDR_TEMP_6[30]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[30]\);
    
    \HWRITE_DATA_TEMP_lm_0[18]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[18]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[18]\, Y
         => \HWRITE_DATA_TEMP_lm[18]\);
    
    \HSEL\ : SLE
      port map(D => \un1_HSEL_1_u\, CLK => HCLK, EN => RESET_N, 
        ALn => \HREADY\, ADn => \HREADY\, SLn => \HREADY\, SD => 
        \HMASTLOCK\, LAT => \HMASTLOCK\, Q => HSEL_net_1);
    
    \Recount_RNICHEBK[15]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[15]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[14]\, S => \Recount_s[15]\, Y => OPEN, FCO
         => \Recount_cry[15]\);
    
    HADDR_TEMP_6_cry_19 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[19]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_18\, S => 
        \HADDR_TEMP_6[19]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_19\);
    
    \count_Temp1_cry[27]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[27]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[26]_net_1\, S => \count_Temp1_s[27]\, Y
         => OPEN, FCO => \count_Temp1_cry[27]_net_1\);
    
    HADDR_TEMP_6_cry_21 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[21]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_20\, S => 
        \HADDR_TEMP_6[21]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_21\);
    
    \HWRITE_DATA_TEMP_6[31]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[31]_net_1\, D => \Recount[31]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[31]_net_1\);
    
    \HWRITE_DATA_TEMP_6[11]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[11]_net_1\, D => \Recount[11]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[11]_net_1\);
    
    \HWRITE_DATA_TEMP[17]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[17]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[17]\);
    
    \count_Temp1[4]\ : SLE
      port map(D => \count_Temp1_lm[4]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[4]_net_1\);
    
    \Recount[23]\ : SLE
      port map(D => \Recount_s[23]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[23]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[2]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[1]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[2]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[2]_net_1\);
    
    \HWRITE_DATA_TEMP[1]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[1]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[1]\);
    
    \count_Temp1[13]\ : SLE
      port map(D => \count_Temp1_lm[13]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[13]_net_1\);
    
    \count_Temp1_lm_0[29]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[29]\, Y => \count_Temp1_lm[29]\);
    
    \HWRITE_DATA_TEMP_lm_0[17]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[17]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[17]\, Y
         => \HWRITE_DATA_TEMP_lm[17]\);
    
    \HWRITE_DATA_TEMP_lm_0[26]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[26]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[26]\, Y
         => \HWRITE_DATA_TEMP_lm[26]\);
    
    htrans7_4 : CFG4
      generic map(INIT => x"0004")

      port map(A => \ahb_states[1]_net_1\, B => clock_count, C
         => \ahb_states[3]_net_1\, D => \ahb_states[2]_net_1\, Y
         => \htrans7_4\);
    
    \count_Temp1[19]\ : SLE
      port map(D => \count_Temp1_lm[19]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[19]_net_1\);
    
    HADDR_TEMP_6_cry_18 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[18]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_17\, S => 
        \HADDR_TEMP_6[18]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_18\);
    
    \HWRITE_DATA_TEMP_6[17]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[17]_net_1\, D => \Recount[17]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[17]_net_1\);
    
    \HADDR_TEMP[14]\ : SLE
      port map(D => \HADDR_TEMP_6[14]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HMASTLOCK\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[14]\);
    
    \Recount_RNIF54H01[25]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[25]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[24]\, S => \Recount_s[25]\, Y => OPEN, FCO
         => \Recount_cry[25]\);
    
    \GND\ : GND
      port map(Y => \HMASTLOCK\);
    
    \count_Temp1[10]\ : SLE
      port map(D => \count_Temp1_lm[10]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[10]_net_1\);
    
    \HWRITE_DATA_TEMP_6[5]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[5]_net_1\, D => \Recount[5]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[5]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0_1_0[0]\ : CFG4
      generic map(INIT => x"5D7F")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \Recount[0]_net_1\, D => \count_Temp1[0]_net_1\, Y => 
        \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\);
    
    \count_Temp1[11]\ : SLE
      port map(D => \count_Temp1_lm[11]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[11]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[20]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[20]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[20]\, Y
         => \HWRITE_DATA_TEMP_lm[20]\);
    
    HADDR_TEMP_6_cry_3 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[3]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => HADDR_TEMP_6_cry_2, S => 
        \HADDR_TEMP_6[3]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_3\);
    
    \HWRITE_DATA_TEMP_lm_0[6]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[6]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[6]\, Y => 
        \HWRITE_DATA_TEMP_lm[6]\);
    
    \HWRITE_DATA_TEMP[10]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[10]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[10]\);
    
    \Recount_RNI9O90O[18]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[18]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[17]\, S => \Recount_s[18]\, Y => OPEN, FCO
         => \Recount_cry[18]\);
    
    \Recount_RNIBD2K61[30]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[30]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[29]\, S => \Recount_s[30]\, Y => OPEN, FCO
         => \Recount_cry[30]\);
    
    \count_Temp1_cry[8]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[8]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[7]_net_1\, S => \count_Temp1_s[8]\, Y
         => OPEN, FCO => \count_Temp1_cry[8]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[30]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[30]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[29]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[30]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[30]_net_1\);
    
    HADDR_TEMP_6_cry_8 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[8]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_7\, S => 
        \HADDR_TEMP_6[8]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_8\);
    
    \HADDR_TEMP[5]\ : SLE
      port map(D => \HADDR_TEMP_6[5]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[5]\);
    
    \count_Temp1_lm_0[17]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[17]\, Y => \count_Temp1_lm[17]\);
    
    htrans9_1 : CFG4
      generic map(INIT => x"0010")

      port map(A => \ahb_states[5]_net_1\, B => 
        \ahb_states[3]_net_1\, C => \ahb_states[1]_net_1\, D => 
        \ahb_states[2]_net_1\, Y => \htrans9_1\);
    
    \count_Temp1_cry[11]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[11]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[10]_net_1\, S => \count_Temp1_s[11]\, Y
         => OPEN, FCO => \count_Temp1_cry[11]_net_1\);
    
    \clock_count[30]\ : SLE
      port map(D => \clock_count_s[30]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[30]_net_1\);
    
    \Recount_RNIHO4AV[24]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[24]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[23]\, S => \Recount_s[24]\, Y => OPEN, FCO
         => \Recount_cry[24]\);
    
    HADDR_TEMP_1_sqmuxa_1_c_0 : CFG2
      generic map(INIT => x"2")

      port map(A => \ahb_states[3]_net_1\, B => HREADYOUT, Y => 
        ahb_states_1_sqmuxa_1);
    
    \HWRITE_DATA_TEMP_lm_0[1]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[1]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[1]\, Y => 
        \HWRITE_DATA_TEMP_lm[1]\);
    
    \HWRITE_DATA_TEMP[26]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[26]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[26]\);
    
    \count_Temp1_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[5]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[4]_net_1\, S => \count_Temp1_s[5]\, Y
         => OPEN, FCO => \count_Temp1_cry[5]_net_1\);
    
    \clock_count_cry[24]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[24]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[23]_net_1\, S => \clock_count_s[24]\, Y
         => OPEN, FCO => \clock_count_cry[24]_net_1\);
    
    \Recount_RNITN6LR[21]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[21]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[20]\, S => \Recount_s[21]\, Y => OPEN, FCO
         => \Recount_cry[21]\);
    
    \count_Temp1[28]\ : SLE
      port map(D => \count_Temp1_lm[28]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[28]_net_1\);
    
    \HWRITE_DATA_TEMP_6[29]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[29]_net_1\, D => \Recount[29]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[29]_net_1\);
    
    htrans6_1 : CFG3
      generic map(INIT => x"02")

      port map(A => \ahb_states[6]_net_1\, B => 
        \ahb_states[1]_net_1\, C => \ahb_states[0]_net_1\, Y => 
        \htrans6_1\);
    
    un1_hreadyout_9 : CFG4
      generic map(INIT => x"0008")

      port map(A => \clock_count[9]_net_1\, B => 
        \un1_hreadyout_0\, C => \clock_count[11]_net_1\, D => 
        \clock_count[10]_net_1\, Y => \un1_hreadyout_9\);
    
    clock_count_s_131 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => clock_count, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, Y => OPEN, 
        FCO => clock_count_s_131_FCO);
    
    un1_htrans6_6_3 : CFG4
      generic map(INIT => x"FFFE")

      port map(A => \HADDR_TEMP_1_sqmuxa_1_c\, B => 
        \ahb_states[5]_net_1\, C => \htrans10\, D => 
        \HADDR_TEMP_1_sqmuxa_1_d\, Y => \un1_htrans6_6_3\);
    
    HADDR_TEMP_6_s_31 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[31]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_30\, S => 
        \HADDR_TEMP_6[31]\, Y => OPEN, FCO => OPEN);
    
    un12_clock_count : CFG4
      generic map(INIT => x"4000")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => 
        \ahb_states[3]_net_1\, D => \un7_clock_count\, Y => 
        \un12_clock_count\);
    
    HADDR_TEMP_6_cry_13 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[13]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_12\, S => 
        \HADDR_TEMP_6[13]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_13\);
    
    \clock_count_cry[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[1]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[0]_net_1\, S => \clock_count_s[1]\, Y
         => OPEN, FCO => \clock_count_cry[1]_net_1\);
    
    \clock_count[25]\ : SLE
      port map(D => \clock_count_s[25]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[25]_net_1\);
    
    \count_Temp1_lm_0[2]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[2]\, Y => \count_Temp1_lm[2]\);
    
    \clock_count[13]\ : SLE
      port map(D => \clock_count_s[13]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[13]_net_1\);
    
    un1_ahb_states_1_sqmuxa_0 : CFG4
      generic map(INIT => x"0ACE")

      port map(A => \ahb_states[6]_net_1\, B => 
        \ahb_states[1]_net_1\, C => \un1_master2_start\, D => 
        HREADYOUT, Y => \un1_ahb_states_1_sqmuxa_0\);
    
    \HWRITE_DATA_TEMP_lm_0[2]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[2]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[2]\, Y => 
        \HWRITE_DATA_TEMP_lm[2]\);
    
    \HADDR_TEMP[9]\ : SLE
      port map(D => \HADDR_TEMP_6[9]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[9]\);
    
    \HWRITE_DATA_TEMP[0]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[0]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[0]\);
    
    \HrdyCount_3[1]\ : CFG4
      generic map(INIT => x"286C")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, C => \un1_hready_flngedge\, D => 
        clock_count, Y => \HrdyCount_3[1]_net_1\);
    
    \count_Temp1_cry[21]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[21]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[20]_net_1\, S => \count_Temp1_s[21]\, Y
         => OPEN, FCO => \count_Temp1_cry[21]_net_1\);
    
    \count_Temp1_cry[16]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[16]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[15]_net_1\, S => \count_Temp1_s[16]\, Y
         => OPEN, FCO => \count_Temp1_cry[16]_net_1\);
    
    \clock_count_cry[21]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[21]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[20]_net_1\, S => \clock_count_s[21]\, Y
         => OPEN, FCO => \clock_count_cry[21]_net_1\);
    
    \clock_count_cry[20]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[20]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[19]_net_1\, S => \clock_count_s[20]\, Y
         => OPEN, FCO => \clock_count_cry[20]_net_1\);
    
    un1_hready_flngedge : CFG3
      generic map(INIT => x"40")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => 
        \ahb_states[5]_net_1\, Y => \un1_hready_flngedge\);
    
    \HWRITE_DATA_TEMP_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[4]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[3]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[4]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[4]_net_1\);
    
    HADDR_TEMP_6_cry_15 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => \HADDR[15]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_14\, S => 
        \HADDR_TEMP_6[15]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_15\);
    
    \HWRITE_DATA_TEMP_6[25]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[25]_net_1\, D => \Recount[25]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[25]_net_1\);
    
    \HADDR_TEMP[7]\ : SLE
      port map(D => \HADDR_TEMP_6[7]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[7]\);
    
    INT2_TEMP_1_sqmuxa_RNIG7AO : CFG4
      generic map(INIT => x"0001")

      port map(A => un1_htrans6_6_2, B => \INT2_TEMP_1_sqmuxa\, C
         => \ahb_states[5]_net_1\, D => \htrans9\, Y => 
        un1_htrans6_4_i_0);
    
    \HADDR_TEMP[3]\ : SLE
      port map(D => \HADDR_TEMP_6[3]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[3]\);
    
    \clock_count[24]\ : SLE
      port map(D => \clock_count_s[24]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[24]_net_1\);
    
    \clock_count[17]\ : SLE
      port map(D => \clock_count_s[17]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[17]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[5]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[4]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[5]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[5]_net_1\);
    
    \HWRITE_DATA_TEMP[9]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[9]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[9]\);
    
    \clock_count[10]\ : SLE
      port map(D => \clock_count_s[10]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[10]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[9]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[9]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[9]\, Y => 
        \HWRITE_DATA_TEMP_lm[9]\);
    
    INT2_TEMP_RNO : CFG3
      generic map(INIT => x"31")

      port map(A => \htrans11\, B => \INT2_TEMP_1_sqmuxa\, C => 
        \htrans10\, Y => un1_htrans10_2_i_0);
    
    \count_Temp1_lm_0[6]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[6]\, Y => \count_Temp1_lm[6]\);
    
    \clock_count_cry[28]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[28]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[27]_net_1\, S => \clock_count_s[28]\, Y
         => OPEN, FCO => \clock_count_cry[28]_net_1\);
    
    un1_htrans6_4_1 : CFG3
      generic map(INIT => x"EA")

      port map(A => \htrans6\, B => \HADDR_TEMP_1_sqmuxa_0\, C
         => \htrans7_4\, Y => un1_htrans6_6_2);
    
    \count_Temp1[6]\ : SLE
      port map(D => \count_Temp1_lm[6]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[6]_net_1\);
    
    Res_Enable_RNI54OF : ARI1
      generic map(INIT => x"44E0A")

      port map(A => \ahb_states[3]_net_1\, B => HREADYOUT, C => 
        \HREADY_Int0\, D => \Res_Enable\, FCI => \HREADY\, S => 
        OPEN, Y => Res_Enable_RNI54OF_Y, FCO => Recount_lcry_cy);
    
    \clock_count_cry[8]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[8]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[7]_net_1\, S => \clock_count_s[8]\, Y
         => OPEN, FCO => \clock_count_cry[8]_net_1\);
    
    \clock_count_cry[26]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[26]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[25]_net_1\, S => \clock_count_s[26]\, Y
         => OPEN, FCO => \clock_count_cry[26]_net_1\);
    
    \HWRITE_DATA_TEMP_6[28]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[28]_net_1\, D => \Recount[28]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[28]_net_1\);
    
    HADDR_TEMP_6_cry_22 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[22]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_21\, S => 
        \HADDR_TEMP_6[22]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_22\);
    
    HADDR_TEMP_6_cry_17 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[17]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_16\, S => 
        \HADDR_TEMP_6[17]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_17\);
    
    \count_Temp1_cry[26]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[26]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[25]_net_1\, S => \count_Temp1_s[26]\, Y
         => OPEN, FCO => \count_Temp1_cry[26]_net_1\);
    
    \Recount[31]\ : SLE
      port map(D => \Recount_s[31]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[31]_net_1\);
    
    \clock_count_cry[22]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[22]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[21]_net_1\, S => \clock_count_s[22]\, Y
         => OPEN, FCO => \clock_count_cry[22]_net_1\);
    
    \HADDR_TEMP[28]\ : SLE
      port map(D => \HADDR_TEMP_6[28]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[28]\);
    
    \clock_count_cry[0]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[0]_net_1\, D => \HMASTLOCK\, FCI => 
        clock_count_s_131_FCO, S => \clock_count_s[0]\, Y => OPEN, 
        FCO => \clock_count_cry[0]_net_1\);
    
    \count_Temp1_cry[13]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[13]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[12]_net_1\, S => \count_Temp1_s[13]\, Y
         => OPEN, FCO => \count_Temp1_cry[13]_net_1\);
    
    un1_ahb_states_1_sqmuxa_1_RNIHHOJ : CFG4
      generic map(INIT => x"0501")

      port map(A => \un1_ahb_states_1_sqmuxa_1\, B => clock_count, 
        C => \un1_ahb_states_1_sqmuxa_2\, D => \un1_hreadyout\, Y
         => un1_ahb_states_1_sqmuxa_i_0);
    
    \count_Temp1_lm_0[12]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[12]\, Y => \count_Temp1_lm[12]\);
    
    \VCC\ : VCC
      port map(Y => \HREADY\);
    
    \HWRITE_DATA_TEMP_cry[25]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[25]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[24]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[25]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[25]_net_1\);
    
    \count_Temp1_lm_0[28]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[28]\, Y => \count_Temp1_lm[28]\);
    
    \HWRITE_DATA_TEMP_6[16]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[16]_net_1\, D => \Recount[16]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[16]_net_1\);
    
    \HWRITE_DATA_TEMP[16]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[16]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[16]\);
    
    \count_Temp1_lm_0[24]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[24]\, Y => \count_Temp1_lm[24]\);
    
    \HWRITE_DATA_TEMP_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[3]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[2]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[3]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[3]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[11]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[11]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[11]\, Y
         => \HWRITE_DATA_TEMP_lm[11]\);
    
    \HWRITE_DATA_TEMP_cry[11]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[11]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[10]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[11]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[11]_net_1\);
    
    \Recount[5]\ : SLE
      port map(D => \Recount_s[5]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[5]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[12]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[12]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[12]\, Y
         => \HWRITE_DATA_TEMP_lm[12]\);
    
    \HADDR_TEMP[19]\ : SLE
      port map(D => \HADDR_TEMP_6[19]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[19]\);
    
    \count_Temp1_cry[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[7]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[6]_net_1\, S => \count_Temp1_s[7]\, Y
         => OPEN, FCO => \count_Temp1_cry[7]_net_1\);
    
    \count_Temp1_lm_0[25]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[25]\, Y => \count_Temp1_lm[25]\);
    
    \count_Temp1[9]\ : SLE
      port map(D => \count_Temp1_lm[9]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[9]_net_1\);
    
    htrans11_3 : CFG2
      generic map(INIT => x"1")

      port map(A => clock_count, B => \ahb_states[5]_net_1\, Y
         => htrans6_3);
    
    \count_Temp1_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[1]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        count_Temp1_s_132_FCO, S => \count_Temp1_s[1]\, Y => OPEN, 
        FCO => \count_Temp1_cry[1]_net_1\);
    
    \HADDR_TEMP[21]\ : SLE
      port map(D => \HADDR_TEMP_6[21]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[21]\);
    
    \count_Temp1_cry[23]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[23]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[22]_net_1\, S => \count_Temp1_s[23]\, Y
         => OPEN, FCO => \count_Temp1_cry[23]_net_1\);
    
    \count_Temp1_cry[14]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[14]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[13]_net_1\, S => \count_Temp1_s[14]\, Y
         => OPEN, FCO => \count_Temp1_cry[14]_net_1\);
    
    \HADDR_TEMP[27]\ : SLE
      port map(D => \HADDR_TEMP_6[27]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[27]\);
    
    clock_count_0_sqmuxa : CFG4
      generic map(INIT => x"4440")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => \htrans9\, 
        D => \htrans10\, Y => \clock_count_0_sqmuxa\);
    
    \Recount[19]\ : SLE
      port map(D => \Recount_s[19]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[19]_net_1\);
    
    un1_master2_start : CFG2
      generic map(INIT => x"2")

      port map(A => MASTER2_START, B => MASTER2_STOP, Y => 
        \un1_master2_start\);
    
    \Recount_RNIJ3718[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[5]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[4]\, S => \Recount_s[5]\, Y => OPEN, FCO => 
        \Recount_cry[5]\);
    
    HADDR_TEMP_1_sqmuxa_0 : CFG4
      generic map(INIT => x"0007")

      port map(A => \Tr_Enable\, B => HREADYOUT, C => 
        \ahb_states[0]_net_1\, D => \ahb_states[5]_net_1\, Y => 
        \HADDR_TEMP_1_sqmuxa_0\);
    
    \HADDR_TEMP[6]\ : SLE
      port map(D => \HADDR_TEMP_6[6]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[6]\);
    
    \count_Temp1_lm_0[31]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[31]_net_1\, Y => \count_Temp1_lm[31]\);
    
    \HWRITE_DATA_TEMP_lm_0[25]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[25]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[25]\, Y
         => \HWRITE_DATA_TEMP_lm[25]\);
    
    HADDR_TEMP_6_cry_16 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[16]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_15\, S => 
        \HADDR_TEMP_6[16]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_16\);
    
    \HWRITE_DATA_TEMP_6[13]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[13]_net_1\, D => \Recount[13]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[13]_net_1\);
    
    \count_Temp1_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[4]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[3]_net_1\, S => \count_Temp1_s[4]\, Y
         => OPEN, FCO => \count_Temp1_cry[4]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[13]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[13]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[12]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[13]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[13]_net_1\);
    
    \Recount[29]\ : SLE
      port map(D => \Recount_s[29]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[29]_net_1\);
    
    \count_Temp1_lm_0[0]\ : CFG4
      generic map(INIT => x"0307")

      port map(A => \ahb_states[1]_net_1\, B => \un7_clock_count\, 
        C => \count_Temp1[0]_net_1\, D => \ahb_states[2]_net_1\, 
        Y => \count_Temp1_lm[0]\);
    
    \HWRITE_DATA_TEMP_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[1]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => HWRITE_DATA_TEMP_s_133_FCO, S
         => \HWRITE_DATA_TEMP_s[1]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[1]_net_1\);
    
    \HWRITE_DATA_TEMP_6[21]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[21]_net_1\, D => \Recount[21]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[21]_net_1\);
    
    \clock_count[6]\ : SLE
      port map(D => \clock_count_s[6]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[6]_net_1\);
    
    \HADDR_TEMP[12]\ : SLE
      port map(D => \HADDR_TEMP_6[12]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[12]\);
    
    \count_Temp1_lm_0[19]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[19]\, Y => \count_Temp1_lm[19]\);
    
    \count_Temp1_cry[24]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[24]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[23]_net_1\, S => \count_Temp1_s[24]\, Y
         => OPEN, FCO => \count_Temp1_cry[24]_net_1\);
    
    \clock_count[3]\ : SLE
      port map(D => \clock_count_s[3]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[3]_net_1\);
    
    \Recount_RNIF6G4J[14]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[14]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[13]\, S => \Recount_s[14]\, Y => OPEN, FCO
         => \Recount_cry[14]\);
    
    \count_Temp1_cry[30]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[30]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[29]_net_1\, S => \count_Temp1_s[30]\, Y
         => OPEN, FCO => \count_Temp1_cry[30]_net_1\);
    
    \Recount_RNI7N2P6[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[4]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[3]\, S => \Recount_s[4]\, Y => OPEN, FCO => 
        \Recount_cry[4]\);
    
    \clock_count_cry[9]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[9]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[8]_net_1\, S => \clock_count_s[9]\, Y
         => OPEN, FCO => \clock_count_cry[9]_net_1\);
    
    HREADY_Int0 : SLE
      port map(D => HREADYOUT, CLK => HCLK, EN => \HREADY\, ALn
         => RESET_N, ADn => \HREADY\, SLn => \HREADY\, SD => 
        \HMASTLOCK\, LAT => \HMASTLOCK\, Q => \HREADY_Int0\);
    
    \HWRITE_DATA_TEMP_6[27]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[27]_net_1\, D => \Recount[27]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[27]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[24]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[24]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[24]\, Y
         => \HWRITE_DATA_TEMP_lm[24]\);
    
    HADDR_TEMP_6_cry_5 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[5]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_4\, S => 
        \HADDR_TEMP_6[5]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_5\);
    
    \count_Temp1_lm_0[21]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[21]\, Y => \count_Temp1_lm[21]\);
    
    \Recount[8]\ : SLE
      port map(D => \Recount_s[8]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[8]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[22]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[22]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[21]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[22]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[22]_net_1\);
    
    \count_Temp1[22]\ : SLE
      port map(D => \count_Temp1_lm[22]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[22]_net_1\);
    
    \Recount_RNI55N8E[10]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[10]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[9]\, S => \Recount_s[10]\, Y => OPEN, FCO
         => \Recount_cry[10]\);
    
    \Recount[6]\ : SLE
      port map(D => \Recount_s[6]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[6]_net_1\);
    
    \HADDR_TEMP[26]\ : SLE
      port map(D => \HADDR_TEMP_6[26]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[26]\);
    
    \HWRITE_DATA_TEMP_6[12]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[12]_net_1\, D => \Recount[12]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[12]_net_1\);
    
    \HWRITE_DATA_TEMP[24]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[24]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[24]\);
    
    HADDR_TEMP_1_sqmuxa_1_c : CFG4
      generic map(INIT => x"1000")

      port map(A => clock_count, B => \ahb_states[0]_net_1\, C
         => \HADDR_TEMP_1_sqmuxa_1_c_1\, D => 
        ahb_states_1_sqmuxa_1, Y => \HADDR_TEMP_1_sqmuxa_1_c\);
    
    \clock_count_cry[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[3]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[2]_net_1\, S => \clock_count_s[3]\, Y
         => OPEN, FCO => \clock_count_cry[3]_net_1\);
    
    htrans11_0 : CFG2
      generic map(INIT => x"2")

      port map(A => \ahb_states[0]_net_1\, B => 
        \ahb_states[1]_net_1\, Y => \htrans11_0\);
    
    \Recount_RNI9ABPM[17]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[17]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[16]\, S => \Recount_s[17]\, Y => OPEN, FCO
         => \Recount_cry[17]\);
    
    \HWRITE_DATA_TEMP_lm_0[30]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[30]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[30]\, Y
         => \HWRITE_DATA_TEMP_lm[30]\);
    
    \HSIZE[1]\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HSIZE(1));
    
    HADDR_TEMP_6_cry_9 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[9]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_8\, S => 
        \HADDR_TEMP_6[9]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_9\);
    
    \clock_count[26]\ : SLE
      port map(D => \clock_count_s[26]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[26]_net_1\);
    
    \clock_count_cry[30]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[30]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[29]_net_1\, S => \clock_count_s[30]\, Y
         => OPEN, FCO => \clock_count_cry[30]_net_1\);
    
    \Recount[7]\ : SLE
      port map(D => \Recount_s[7]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[7]_net_1\);
    
    clock_count_0_sqmuxa_RNI1P761 : CFG4
      generic map(INIT => x"F8FF")

      port map(A => \htrans7_4\, B => \HADDR_TEMP_0_sqmuxa_0\, C
         => \clock_count_0_sqmuxa\, D => \htrans11\, Y => 
        clock_counte);
    
    \HWRITE_DATA_TEMP_lm_0[23]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[23]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[23]\, Y
         => \HWRITE_DATA_TEMP_lm[23]\);
    
    un7_clock_count : CFG4
      generic map(INIT => x"8000")

      port map(A => \un7_clock_count_20\, B => 
        \un7_clock_count_21\, C => \un7_clock_count_27\, D => 
        \un7_clock_count_28\, Y => \un7_clock_count\);
    
    \Recount_RNIEJ3O11[26]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[26]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[25]\, S => \Recount_s[26]\, Y => OPEN, FCO
         => \Recount_cry[26]\);
    
    \ahb_states[3]\ : SLE
      port map(D => clock_count, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[3]_net_1\);
    
    un1_hreadyout_0 : CFG2
      generic map(INIT => x"8")

      port map(A => \clock_count[0]_net_1\, B => HREADYOUT, Y => 
        \un1_hreadyout_0\);
    
    \count_Temp1_lm_0[9]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[9]\, Y => \count_Temp1_lm[9]\);
    
    \clock_count[1]\ : SLE
      port map(D => \clock_count_s[1]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[1]_net_1\);
    
    HADDR_TEMP_6_cry_14 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => \HADDR[14]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_13\, S => 
        \HADDR_TEMP_6[14]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_14\);
    
    \count_Temp1_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[2]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[1]_net_1\, S => \count_Temp1_s[2]\, Y
         => OPEN, FCO => \count_Temp1_cry[2]_net_1\);
    
    \count_Temp1[18]\ : SLE
      port map(D => \count_Temp1_lm[18]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[18]_net_1\);
    
    un1_reset_n_2 : CFG2
      generic map(INIT => x"2")

      port map(A => RESET_N, B => \ahb_states[6]_net_1\, Y => 
        \un1_reset_n_2\);
    
    \Recount[30]\ : SLE
      port map(D => \Recount_s[30]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[30]_net_1\);
    
    \clock_count_cry[14]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[14]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[13]_net_1\, S => \clock_count_s[14]\, Y
         => OPEN, FCO => \clock_count_cry[14]_net_1\);
    
    \HADDR_TEMP[31]\ : SLE
      port map(D => \HADDR_TEMP_6[31]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[31]\);
    
    \Recount_RNI3F7EQ[20]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[20]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[19]\, S => \Recount_s[20]\, Y => OPEN, FCO
         => \Recount_cry[20]\);
    
    \HADDR_TEMP[10]\ : SLE
      port map(D => \HADDR_TEMP_6[10]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[10]\);
    
    \ahb_states[2]\ : SLE
      port map(D => \ahb_states[1]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[2]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[28]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[28]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[28]\, Y
         => \HWRITE_DATA_TEMP_lm[28]\);
    
    \clock_count[8]\ : SLE
      port map(D => \clock_count_s[8]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[8]_net_1\);
    
    \clock_count[19]\ : SLE
      port map(D => \clock_count_s[19]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[19]_net_1\);
    
    \HWRITE_DATA_TEMP[4]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[4]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[4]\);
    
    \clock_count_cry[11]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[11]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[10]_net_1\, S => \clock_count_s[11]\, Y
         => OPEN, FCO => \clock_count_cry[11]_net_1\);
    
    \clock_count_cry[10]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[10]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[9]_net_1\, S => \clock_count_s[10]\, Y
         => OPEN, FCO => \clock_count_cry[10]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[26]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[26]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[25]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[26]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[26]_net_1\);
    
    \count_Temp1_lm_0[7]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[7]\, Y => \count_Temp1_lm[7]\);
    
    HADDR_TEMP_0_sqmuxa_0 : CFG4
      generic map(INIT => x"0008")

      port map(A => \Tr_Enable\, B => HREADYOUT, C => 
        \ahb_states[0]_net_1\, D => \ahb_states[5]_net_1\, Y => 
        \HADDR_TEMP_0_sqmuxa_0\);
    
    \Recount[11]\ : SLE
      port map(D => \Recount_s[11]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[11]_net_1\);
    
    \HWRITE_DATA_TEMP[29]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[29]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[29]\);
    
    \count_Temp1_cry[18]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[18]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[17]_net_1\, S => \count_Temp1_s[18]\, Y
         => OPEN, FCO => \count_Temp1_cry[18]_net_1\);
    
    \clock_count[31]\ : SLE
      port map(D => \clock_count_s[31]_net_1\, CLK => HCLK, EN
         => clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \clock_count[31]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[27]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[27]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[27]\, Y
         => \HWRITE_DATA_TEMP_lm[27]\);
    
    \HSIZE[0]\ : SLE
      port map(D => \HMASTLOCK\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HSIZE(0));
    
    un1_HSEL_1_u : CFG4
      generic map(INIT => x"EEA0")

      port map(A => \htrans6\, B => \htrans11\, C => 
        \un1_master2_start\, D => HSEL_net_1, Y => \un1_HSEL_1_u\);
    
    \HWRITE_DATA_TEMP[14]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[14]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[14]\);
    
    \HADDR_TEMP[8]\ : SLE
      port map(D => \HADDR_TEMP_6[8]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[8]\);
    
    \clock_count_cry[18]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[18]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[17]_net_1\, S => \clock_count_s[18]\, Y
         => OPEN, FCO => \clock_count_cry[18]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[27]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[27]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[26]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[27]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[27]_net_1\);
    
    \Recount[21]\ : SLE
      port map(D => \Recount_s[21]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[21]_net_1\);
    
    \clock_count_cry[16]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[16]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[15]_net_1\, S => \clock_count_s[16]\, Y
         => OPEN, FCO => \clock_count_cry[16]_net_1\);
    
    \HWRITE_DATA_TEMP_6[2]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[2]_net_1\, D => \Recount[2]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[2]_net_1\);
    
    HADDR_TEMP_1_sqmuxa_1_d : CFG4
      generic map(INIT => x"0100")

      port map(A => HREADYOUT, B => \ahb_states[0]_net_1\, C => 
        clock_count, D => \htrans9_1\, Y => 
        \HADDR_TEMP_1_sqmuxa_1_d\);
    
    \clock_count_cry[12]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[12]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[11]_net_1\, S => \clock_count_s[12]\, Y
         => OPEN, FCO => \clock_count_cry[12]_net_1\);
    
    \count_Temp1_lm_0[26]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[26]\, Y => \count_Temp1_lm[26]\);
    
    un7_clock_count_13 : CFG2
      generic map(INIT => x"1")

      port map(A => \clock_count[2]_net_1\, B => 
        \clock_count[3]_net_1\, Y => \un7_clock_count_13\);
    
    \HWRITE_DATA_TEMP_lm_0[19]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[19]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[19]\, Y
         => \HWRITE_DATA_TEMP_lm[19]\);
    
    \Recount_RNIJSHTH[13]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[13]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[12]\, S => \Recount_s[13]\, Y => OPEN, FCO
         => \Recount_cry[13]\);
    
    \HADDR_TEMP[23]\ : SLE
      port map(D => \HADDR_TEMP_6[23]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[23]\);
    
    \count_Temp1_lm_0[18]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[18]\, Y => \count_Temp1_lm[18]\);
    
    \count_Temp1_cry[28]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[28]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[27]_net_1\, S => \count_Temp1_s[28]\, Y
         => OPEN, FCO => \count_Temp1_cry[28]_net_1\);
    
    HADDR_TEMP_6_cry_29 : ARI1
      generic map(INIT => x"4BB00")

      port map(A => \HREADY\, B => \HADDR[29]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_28\, S => 
        \HADDR_TEMP_6[29]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_29\);
    
    \HADDR_TEMP[25]\ : SLE
      port map(D => \HADDR_TEMP_6[25]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[25]\);
    
    \HWRITE_DATA_TEMP_6[26]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[26]_net_1\, D => \Recount[26]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[26]_net_1\);
    
    \count_Temp1_lm_0[14]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[14]\, Y => \count_Temp1_lm[14]\);
    
    \HWRITE_DATA_TEMP[23]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[23]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[23]\);
    
    \count_Temp1[25]\ : SLE
      port map(D => \count_Temp1_lm[25]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[25]_net_1\);
    
    \HWRITE_DATA_TEMP[7]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[7]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[7]\);
    
    \HWRITE_DATA_TEMP_lm_0[8]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[8]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[8]\, Y => 
        \HWRITE_DATA_TEMP_lm[8]\);
    
    \clock_count[11]\ : SLE
      port map(D => \clock_count_s[11]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[11]_net_1\);
    
    \count_Temp1_lm_0[15]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[15]\, Y => \count_Temp1_lm[15]\);
    
    INT2_TEMP : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans10_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => INT2);
    
    \clock_count[23]\ : SLE
      port map(D => \clock_count_s[23]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[23]_net_1\);
    
    \clock_count_cry[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[2]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[1]_net_1\, S => \clock_count_s[2]\, Y
         => OPEN, FCO => \clock_count_cry[2]_net_1\);
    
    \Recount_RNIATCIL[16]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[16]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[15]\, S => \Recount_s[16]\, Y => OPEN, FCO
         => \Recount_cry[16]\);
    
    HADDR_TEMP_6_cry_28 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[28]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_27\, S => 
        \HADDR_TEMP_6[28]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_28\);
    
    HADDR_TEMP_6_cry_10 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[10]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_9\, S => 
        \HADDR_TEMP_6[10]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_10\);
    
    \clock_count_cry[23]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[23]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[22]_net_1\, S => \clock_count_s[23]\, Y
         => OPEN, FCO => \clock_count_cry[23]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[20]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[20]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[19]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[20]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[20]_net_1\);
    
    \clock_count_cry[25]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[25]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[24]_net_1\, S => \clock_count_s[25]\, Y
         => OPEN, FCO => \clock_count_cry[25]_net_1\);
    
    un8_hready_flngedge : CFG3
      generic map(INIT => x"4F")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => 
        clock_count, Y => \un8_hready_flngedge\);
    
    \HWRITE_DATA_TEMP[22]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[22]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[22]\);
    
    un7_clock_count_23 : CFG4
      generic map(INIT => x"0004")

      port map(A => \clock_count[11]_net_1\, B => 
        \clock_count[10]_net_1\, C => \clock_count[1]_net_1\, D
         => \clock_count[0]_net_1\, Y => \un7_clock_count_23\);
    
    \HWRITE_DATA_TEMP[25]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[25]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[25]\);
    
    un3_hready_rsngedge_RNIS5BI : CFG4
      generic map(INIT => x"FCF8")

      port map(A => \ahb_states[1]_net_1\, B => \un7_clock_count\, 
        C => \un3_hready_rsngedge\, D => \ahb_states[2]_net_1\, Y
         => count_Temp1e);
    
    \HWRITE_DATA_TEMP_6[8]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[8]_net_1\, D => \Recount[8]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[8]_net_1\);
    
    htrans11 : CFG4
      generic map(INIT => x"EFFF")

      port map(A => \ahb_states[3]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \htrans11_0\, D => htrans6_3, 
        Y => \htrans11\);
    
    \count_Temp1_lm_0[1]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[1]\, Y => \count_Temp1_lm[1]\);
    
    \clock_count[27]\ : SLE
      port map(D => \clock_count_s[27]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[27]_net_1\);
    
    \HWRITE_DATA_TEMP[19]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[19]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[19]\);
    
    \HADDR_TEMP[24]\ : SLE
      port map(D => \HADDR_TEMP_6[24]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[24]\);
    
    \HWRITE_DATA_TEMP_cry[15]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[15]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[14]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[15]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[15]_net_1\);
    
    \HWRITE_DATA_TEMP_6[23]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[23]_net_1\, D => \Recount[23]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[23]_net_1\);
    
    \clock_count_cry[29]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[29]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[28]_net_1\, S => \clock_count_s[29]\, Y
         => OPEN, FCO => \clock_count_cry[29]_net_1\);
    
    \clock_count[20]\ : SLE
      port map(D => \clock_count_s[20]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[20]_net_1\);
    
    \Recount_RNISBUG5[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[3]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[2]\, S => \Recount_s[3]\, Y => OPEN, FCO => 
        \Recount_cry[3]\);
    
    \clock_count[9]\ : SLE
      port map(D => \clock_count_s[9]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[9]_net_1\);
    
    HADDR_TEMP_6_cry_30 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[30]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_29\, S => 
        \HADDR_TEMP_6[30]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_30\);
    
    \HWRITE_DATA_TEMP_6[9]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[9]_net_1\, D => \Recount[9]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[9]_net_1\);
    
    \HWRITE\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HWRITE);
    
    \HWRITE_DATA_TEMP_lm_0[0]\ : CFG4
      generic map(INIT => x"1B0F")

      port map(A => \ahb_states[0]_net_1\, B => \HWDATA[0]\, C
         => \HWRITE_DATA_TEMP_lm_0_1_0[0]_net_1\, D => 
        \htrans7_4\, Y => \HWRITE_DATA_TEMP_lm[0]\);
    
    \HWRITE_DATA_TEMP_cry[24]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[24]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[23]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[24]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[24]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[29]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[29]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[28]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[29]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[29]_net_1\);
    
    \ahb_states[5]\ : SLE
      port map(D => \ahb_states[6]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[5]_net_1\);
    
    \count_Temp1_lm_0[5]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[5]\, Y => \count_Temp1_lm[5]\);
    
    \clock_count_cry[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[7]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[6]_net_1\, S => \clock_count_s[7]\, Y
         => OPEN, FCO => \clock_count_cry[7]_net_1\);
    
    \clock_count[12]\ : SLE
      port map(D => \clock_count_s[12]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[12]_net_1\);
    
    \Recount_RNI9OL03[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[1]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[0]\, S => \Recount_s[1]\, Y => OPEN, FCO => 
        \Recount_cry[1]\);
    
    \Recount[3]\ : SLE
      port map(D => \Recount_s[3]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[3]_net_1\);
    
    \count_Temp1_lm_0[11]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[11]\, Y => \count_Temp1_lm[11]\);
    
    \Recount_RNIOJJMG[12]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[12]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[11]\, S => \Recount_s[12]\, Y => OPEN, FCO
         => \Recount_cry[12]\);
    
    HADDR_TEMP_6_cry_6 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[6]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_5\, S => 
        \HADDR_TEMP_6[6]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_6\);
    
    \clock_count[0]\ : SLE
      port map(D => \clock_count_s[0]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[0]_net_1\);
    
    \HWRITE_DATA_TEMP[5]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[5]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[5]\);
    
    HADDR_TEMP_6_cry_11 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[11]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_10\, S => 
        \HADDR_TEMP_6[11]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_11\);
    
    \HADDR_TEMP[0]\ : SLE
      port map(D => \HADDR_TEMP_6[0]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[0]\);
    
    \count_Temp1[12]\ : SLE
      port map(D => \count_Temp1_lm[12]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[12]_net_1\);
    
    \clock_count_cry[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[6]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[5]_net_1\, S => \clock_count_s[6]\, Y
         => OPEN, FCO => \clock_count_cry[6]_net_1\);
    
    \clock_count_cry[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[4]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[3]_net_1\, S => \clock_count_s[4]\, Y
         => OPEN, FCO => \clock_count_cry[4]_net_1\);
    
    \ahb_states[1]\ : SLE
      port map(D => \ahb_states[3]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[1]_net_1\);
    
    \count_Temp1_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[6]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[5]_net_1\, S => \count_Temp1_s[6]\, Y
         => OPEN, FCO => \count_Temp1_cry[6]_net_1\);
    
    \Recount[16]\ : SLE
      port map(D => \Recount_s[16]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[16]_net_1\);
    
    \HWRITE_DATA_TEMP_6[22]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[22]_net_1\, D => \Recount[22]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[22]_net_1\);
    
    \HWRITE_DATA_TEMP_6[14]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[14]_net_1\, D => \Recount[14]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[14]_net_1\);
    
    \HWRITE_DATA_TEMP[6]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[6]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[6]\);
    
    \HWRITE_DATA_TEMP[13]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[13]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[13]\);
    
    \HADDR_TEMP[4]\ : SLE
      port map(D => \HADDR_TEMP_6[4]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[4]\);
    
    \HWRITE_DATA_TEMP_6[30]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[30]_net_1\, D => \Recount[30]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[30]_net_1\);
    
    \HWRITE_DATA_TEMP_6[10]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[10]_net_1\, D => \Recount[10]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[10]_net_1\);
    
    \Recount_RNIH32D51[29]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[29]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[28]\, S => \Recount_s[29]\, Y => OPEN, FCO
         => \Recount_cry[29]\);
    
    \Recount[9]\ : SLE
      port map(D => \Recount_s[9]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[9]_net_1\);
    
    HADDR_TEMP_6_cry_23 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[23]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_22\, S => 
        \HADDR_TEMP_6[23]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_23\);
    
    \Recount[18]\ : SLE
      port map(D => \Recount_s[18]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[18]_net_1\);
    
    \Recount_RNITEKPB[8]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[8]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[7]\, S => \Recount_s[8]\, Y => OPEN, FCO => 
        \Recount_cry[8]\);
    
    HADDR_TEMP_6_cry_2_0 : ARI1
      generic map(INIT => x"5A802")

      port map(A => \HADDR[2]\, B => \htrans11\, C => 
        un1_htrans6_6_2, D => \un1_htrans6_6_3\, FCI => 
        \HMASTLOCK\, S => OPEN, Y => HADDR_TEMP_6_cry_2_0_Y, FCO
         => HADDR_TEMP_6_cry_2);
    
    \HrdyCount[0]\ : SLE
      port map(D => \HrdyCount_3[0]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HrdyCount[0]_net_1\);
    
    \Recount[10]\ : SLE
      port map(D => \Recount_s[10]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[10]_net_1\);
    
    \Recount[26]\ : SLE
      port map(D => \Recount_s[26]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[26]_net_1\);
    
    \count_Temp1_lm_0[23]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[23]\, Y => \count_Temp1_lm[23]\);
    
    un1_hreadyout_8 : CFG4
      generic map(INIT => x"8000")

      port map(A => \clock_count[8]_net_1\, B => 
        \clock_count[7]_net_1\, C => \clock_count[6]_net_1\, D
         => \clock_count[5]_net_1\, Y => \un1_hreadyout_8\);
    
    \Recount_RNI0HB99[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[6]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[5]\, S => \Recount_s[6]\, Y => OPEN, FCO => 
        \Recount_cry[6]\);
    
    HADDR_TEMP_6_cry_25 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[25]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_24\, S => 
        \HADDR_TEMP_6[25]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_25\);
    
    \clock_count[18]\ : SLE
      port map(D => \clock_count_s[18]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[18]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[21]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[21]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[21]\, Y
         => \HWRITE_DATA_TEMP_lm[21]\);
    
    \Recount[28]\ : SLE
      port map(D => \Recount_s[28]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[28]_net_1\);
    
    \HWRITE_DATA_TEMP[12]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[12]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[12]\);
    
    \HADDR_TEMP_6[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \htrans11\, B => \HADDR[1]\, Y => 
        \HADDR_TEMP_6[1]_net_1\);
    
    \clock_count[7]\ : SLE
      port map(D => \clock_count_s[7]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[7]_net_1\);
    
    MASTER2_START_RNI62TG1 : CFG4
      generic map(INIT => x"220F")

      port map(A => MASTER2_START, B => MASTER2_STOP, C => 
        \htrans11\, D => \htrans6\, Y => un1_htrans6_2_i_0);
    
    \HWRITE_DATA_TEMP_lm_0[22]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[22]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[22]\, Y
         => \HWRITE_DATA_TEMP_lm[22]\);
    
    \HWRITE_DATA_TEMP[15]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[15]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[15]\);
    
    un7_clock_count_21 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[9]_net_1\, B => 
        \clock_count[8]_net_1\, C => \clock_count[7]_net_1\, D
         => \clock_count[6]_net_1\, Y => \un7_clock_count_21\);
    
    \HWRITE_DATA_TEMP_cry[28]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[28]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[27]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[28]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[28]_net_1\);
    
    \Recount[20]\ : SLE
      port map(D => \Recount_s[20]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[20]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[12]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[12]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[11]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[12]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[12]_net_1\);
    
    un7_clock_count_20 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[15]_net_1\, B => 
        \clock_count[14]_net_1\, C => \clock_count[13]_net_1\, D
         => \clock_count[12]_net_1\, Y => \un7_clock_count_20\);
    
    \Recount_RNI1GHO1[0]\ : ARI1
      generic map(INIT => x"4A200")

      port map(A => \HREADY\, B => \Recount[0]_net_1\, C => 
        Res_Enable_RNI54OF_Y, D => HREADYOUT, FCI => Recount, S
         => \Recount_s[0]\, Y => OPEN, FCO => \Recount_cry[0]\);
    
    \count_Temp1_lm_0[30]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[30]\, Y => \count_Temp1_lm[30]\);
    
    HADDR_TEMP_6_cry_27 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[27]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_26\, S => 
        \HADDR_TEMP_6[27]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_27\);
    
    \count_Temp1[27]\ : SLE
      port map(D => \count_Temp1_lm[27]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[27]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[3]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[3]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[3]\, Y => 
        \HWRITE_DATA_TEMP_lm[3]\);
    
    count_Temp1_s_132 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[0]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => \HREADY\, S => OPEN, 
        Y => OPEN, FCO => count_Temp1_s_132_FCO);
    
    \count_Temp1[5]\ : SLE
      port map(D => \count_Temp1_lm[5]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[5]_net_1\);
    
    \clock_count_s[31]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[31]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[30]_net_1\, S => 
        \clock_count_s[31]_net_1\, Y => OPEN, FCO => OPEN);
    
    \Recount[2]\ : SLE
      port map(D => \Recount_s[2]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[2]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[16]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[16]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[16]\, Y
         => \HWRITE_DATA_TEMP_lm[16]\);
    
    \HWRITE_DATA_TEMP_cry[9]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[9]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[8]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[9]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[9]_net_1\);
    
    \count_Temp1_cry[9]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[9]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[8]_net_1\, S => \count_Temp1_s[9]\, Y
         => OPEN, FCO => \count_Temp1_cry[9]_net_1\);
    
    \Recount[14]\ : SLE
      port map(D => \Recount_s[14]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[14]_net_1\);
    
    \HTRANS[1]\ : SLE
      port map(D => \ahb_states_i_0[0]\, CLK => HCLK, EN => 
        un1_htrans6_2_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => HTRANS(1));
    
    un7_clock_count_17 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[27]_net_1\, B => 
        \clock_count[26]_net_1\, C => \clock_count[25]_net_1\, D
         => \clock_count[24]_net_1\, Y => \un7_clock_count_17\);
    
    \count_Temp1_lm_0[20]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[20]\, Y => \count_Temp1_lm[20]\);
    
    \count_Temp1[24]\ : SLE
      port map(D => \count_Temp1_lm[24]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[24]_net_1\);
    
    \clock_count_cry[27]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[27]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[26]_net_1\, S => \clock_count_s[27]\, Y
         => OPEN, FCO => \clock_count_cry[27]_net_1\);
    
    \count_Temp1[3]\ : SLE
      port map(D => \count_Temp1_lm[3]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[3]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[10]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[10]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[10]\, Y
         => \HWRITE_DATA_TEMP_lm[10]\);
    
    \HWRITE_DATA_TEMP_6[3]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[3]_net_1\, D => \Recount[3]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[3]_net_1\);
    
    \count_Temp1_cry[10]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[10]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[9]_net_1\, S => \count_Temp1_s[10]\, Y
         => OPEN, FCO => \count_Temp1_cry[10]_net_1\);
    
    \count_Temp1[26]\ : SLE
      port map(D => \count_Temp1_lm[26]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[26]_net_1\);
    
    htrans6 : CFG4
      generic map(INIT => x"1000")

      port map(A => \ahb_states[3]_net_1\, B => 
        \ahb_states[2]_net_1\, C => htrans6_3, D => \htrans6_1\, 
        Y => \htrans6\);
    
    Res_Enable : SLE
      port map(D => \HREADY\, CLK => HCLK, EN => 
        \un12_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Res_Enable\);
    
    \count_Temp1[7]\ : SLE
      port map(D => \count_Temp1_lm[7]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[7]_net_1\);
    
    un1_ahb_states_1_sqmuxa_1 : CFG3
      generic map(INIT => x"F4")

      port map(A => MASTER2_STOP, B => \ahb_states[2]_net_1\, C
         => ahb_states_1_sqmuxa_1, Y => 
        \un1_ahb_states_1_sqmuxa_1\);
    
    \Recount[24]\ : SLE
      port map(D => \Recount_s[24]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[24]_net_1\);
    
    \count_Temp1_lm_0[16]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[16]\, Y => \count_Temp1_lm[16]\);
    
    \HADDR_TEMP[29]\ : SLE
      port map(D => \HADDR_TEMP_6[29]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HMASTLOCK\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[29]\);
    
    un7_clock_count_18 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[23]_net_1\, B => 
        \clock_count[22]_net_1\, C => \clock_count[21]_net_1\, D
         => \clock_count[20]_net_1\, Y => \un7_clock_count_18\);
    
    \Recount_RNIFI2641[28]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[28]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[27]\, S => \Recount_s[28]\, Y => OPEN, FCO
         => \Recount_cry[28]\);
    
    HADDR_TEMP_6_cry_26 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[26]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_25\, S => 
        \HADDR_TEMP_6[26]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_26\);
    
    \HWRITE_DATA_TEMP_cry[16]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[16]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[15]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[16]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[16]_net_1\);
    
    \HADDR_TEMP[18]\ : SLE
      port map(D => \HADDR_TEMP_6[18]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[18]\);
    
    \Recount_RNIE23V21[27]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[27]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[26]\, S => \Recount_s[27]\, Y => OPEN, FCO
         => \Recount_cry[27]\);
    
    \count_Temp1[15]\ : SLE
      port map(D => \count_Temp1_lm[15]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[15]_net_1\);
    
    \Recount_RNIUBLFF[11]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[11]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[10]\, S => \Recount_s[11]\, Y => OPEN, FCO
         => \Recount_cry[11]\);
    
    \count_Temp1_cry[20]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[20]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[19]_net_1\, S => \count_Temp1_s[20]\, Y
         => OPEN, FCO => \count_Temp1_cry[20]_net_1\);
    
    \HWRITE_DATA_TEMP_s[31]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[31]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[30]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[31]_net_1\, Y => OPEN, FCO => 
        OPEN);
    
    htrans9 : CFG3
      generic map(INIT => x"10")

      port map(A => \ahb_states[0]_net_1\, B => clock_count, C
         => \htrans9_1\, Y => \htrans9\);
    
    htrans10 : CFG3
      generic map(INIT => x"10")

      port map(A => \ahb_states[0]_net_1\, B => clock_count, C
         => \htrans10_1\, Y => \htrans10\);
    
    HADDR_TEMP_6_cry_12 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[12]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_11\, S => 
        \HADDR_TEMP_6[12]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_12\);
    
    un7_clock_count_27 : CFG4
      generic map(INIT => x"1000")

      port map(A => \clock_count[4]_net_1\, B => 
        \clock_count[5]_net_1\, C => \un7_clock_count_23\, D => 
        \un7_clock_count_13\, Y => \un7_clock_count_27\);
    
    \Recount[1]\ : SLE
      port map(D => \Recount_s[1]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[1]_net_1\);
    
    \HWRITE_DATA_TEMP_cry[17]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[17]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[16]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[17]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[17]_net_1\);
    
    un1_ahb_states_1_sqmuxa_2 : CFG4
      generic map(INIT => x"FBF0")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, C => \un1_ahb_states_1_sqmuxa_0\, D
         => \ahb_states[5]_net_1\, Y => 
        \un1_ahb_states_1_sqmuxa_2\);
    
    \clock_count[29]\ : SLE
      port map(D => \clock_count_s[29]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[29]_net_1\);
    
    \Recount_RNII1Q84[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[2]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[1]\, S => \Recount_s[2]\, Y => OPEN, FCO => 
        \Recount_cry[2]\);
    
    \HWRITE_DATA_TEMP[28]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[28]\, CLK => HCLK, EN
         => un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[28]\);
    
    \clock_count_cry[13]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[13]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[12]_net_1\, S => \clock_count_s[13]\, Y
         => OPEN, FCO => \clock_count_cry[13]_net_1\);
    
    \HWRITE_DATA_TEMP_6[1]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[1]_net_1\, D => \Recount[1]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[1]_net_1\);
    
    \HADDR_TEMP[22]\ : SLE
      port map(D => \HADDR_TEMP_6[22]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[22]\);
    
    \clock_count_cry[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[5]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[4]_net_1\, S => \clock_count_s[5]\, Y
         => OPEN, FCO => \clock_count_cry[5]_net_1\);
    
    \clock_count_cry[15]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[15]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[14]_net_1\, S => \clock_count_s[15]\, Y
         => OPEN, FCO => \clock_count_cry[15]_net_1\);
    
    \Recount_RNO[31]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[31]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[30]\, S => \Recount_s[31]\, Y => OPEN, FCO
         => OPEN);
    
    htrans10_1 : CFG4
      generic map(INIT => x"0100")

      port map(A => \ahb_states[5]_net_1\, B => 
        \ahb_states[3]_net_1\, C => \ahb_states[1]_net_1\, D => 
        \ahb_states[2]_net_1\, Y => \htrans10_1\);
    
    HADDR_TEMP_6_cry_7 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[7]\, C => \htrans11\, D
         => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_6\, S => 
        \HADDR_TEMP_6[7]\, Y => OPEN, FCO => \HADDR_TEMP_6_cry_7\);
    
    \count_Temp1_cry[19]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[19]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[18]_net_1\, S => \count_Temp1_s[19]\, Y
         => OPEN, FCO => \count_Temp1_cry[19]_net_1\);
    
    \count_Temp1[30]\ : SLE
      port map(D => \count_Temp1_lm[30]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[30]_net_1\);
    
    \ahb_states[6]\ : SLE
      port map(D => \ahb_states[0]_net_1\, CLK => HCLK, EN => 
        un1_ahb_states_1_sqmuxa_i_0, ALn => RESET_N, ADn => 
        \HMASTLOCK\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \ahb_states[6]_net_1\);
    
    \HADDR_TEMP[11]\ : SLE
      port map(D => \HADDR_TEMP_6[11]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[11]\);
    
    \count_Temp1[2]\ : SLE
      port map(D => \count_Temp1_lm[2]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[2]_net_1\);
    
    un7_clock_count_28 : CFG4
      generic map(INIT => x"8000")

      port map(A => \un7_clock_count_19\, B => 
        \un7_clock_count_18\, C => \un7_clock_count_17\, D => 
        \un7_clock_count_16\, Y => \un7_clock_count_28\);
    
    \HADDR_TEMP[17]\ : SLE
      port map(D => \HADDR_TEMP_6[17]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[17]\);
    
    \count_Temp1_cry[12]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[12]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[11]_net_1\, S => \count_Temp1_s[12]\, Y
         => OPEN, FCO => \count_Temp1_cry[12]_net_1\);
    
    un7_clock_count_16 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[31]_net_1\, B => 
        \clock_count[30]_net_1\, C => \clock_count[29]_net_1\, D
         => \clock_count[28]_net_1\, Y => \un7_clock_count_16\);
    
    \HADDR_TEMP[1]\ : SLE
      port map(D => \HADDR_TEMP_6[1]_net_1\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[1]\);
    
    \clock_count_cry[19]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => clock_count, C => 
        \clock_count[19]_net_1\, D => \HMASTLOCK\, FCI => 
        \clock_count_cry[18]_net_1\, S => \clock_count_s[19]\, Y
         => OPEN, FCO => \clock_count_cry[19]_net_1\);
    
    un1_hreadyout_7 : CFG4
      generic map(INIT => x"8000")

      port map(A => \clock_count[4]_net_1\, B => 
        \clock_count[3]_net_1\, C => \clock_count[2]_net_1\, D
         => \clock_count[1]_net_1\, Y => \un1_hreadyout_7\);
    
    \HWRITE_DATA_TEMP_lm_0[5]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[5]_net_1\, C => \ahb_states[0]_net_1\, 
        D => \HWRITE_DATA_TEMP_s[5]\, Y => 
        \HWRITE_DATA_TEMP_lm[5]\);
    
    HADDR_TEMP_1_sqmuxa_1_c_1 : CFG3
      generic map(INIT => x"01")

      port map(A => \ahb_states[5]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \ahb_states[1]_net_1\, Y => 
        \HADDR_TEMP_1_sqmuxa_1_c_1\);
    
    \count_Temp1[23]\ : SLE
      port map(D => \count_Temp1_lm[23]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[23]_net_1\);
    
    INT2_TEMP_1_sqmuxa : CFG3
      generic map(INIT => x"B0")

      port map(A => HREADYOUT, B => \HREADY_Int0\, C => 
        \htrans10\, Y => \INT2_TEMP_1_sqmuxa\);
    
    \count_Temp1[31]\ : SLE
      port map(D => \count_Temp1_lm[31]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[31]_net_1\);
    
    \clock_count[15]\ : SLE
      port map(D => \clock_count_s[15]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[15]_net_1\);
    
    \count_Temp1[29]\ : SLE
      port map(D => \count_Temp1_lm[29]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[29]_net_1\);
    
    \count_Temp1_lm_0[8]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[8]\, Y => \count_Temp1_lm[8]\);
    
    \count_Temp1[1]\ : SLE
      port map(D => \count_Temp1_lm[1]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[1]_net_1\);
    
    \count_Temp1_s[31]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[31]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[30]_net_1\, S => 
        \count_Temp1_s[31]_net_1\, Y => OPEN, FCO => OPEN);
    
    \count_Temp1[20]\ : SLE
      port map(D => \count_Temp1_lm[20]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[20]_net_1\);
    
    \Recount_RNIDVO1D[9]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[9]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[8]\, S => \Recount_s[9]\, Y => OPEN, FCO => 
        \Recount_cry[9]\);
    
    \HWRITE_DATA_TEMP_cry[10]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[10]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[9]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[10]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[10]_net_1\);
    
    \clock_count[14]\ : SLE
      port map(D => \clock_count_s[14]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[14]_net_1\);
    
    \count_Temp1_cry[29]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[29]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[28]_net_1\, S => \count_Temp1_s[29]\, Y
         => OPEN, FCO => \count_Temp1_cry[29]_net_1\);
    
    \count_Temp1[21]\ : SLE
      port map(D => \count_Temp1_lm[21]\, CLK => HCLK, EN => 
        count_Temp1e, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \count_Temp1[21]_net_1\);
    
    Tr_Enable : SLE
      port map(D => clock_count, CLK => HCLK, EN => 
        \un8_hready_flngedge\, ALn => RESET_N, ADn => \HREADY\, 
        SLn => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \Tr_Enable\);
    
    \count_Temp1_cry[22]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \count_Temp1[22]_net_1\, C => 
        \HMASTLOCK\, D => \HMASTLOCK\, FCI => 
        \count_Temp1_cry[21]_net_1\, S => \count_Temp1_s[22]\, Y
         => OPEN, FCO => \count_Temp1_cry[22]_net_1\);
    
    HADDR_TEMP_6_cry_24 : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => \HADDR[24]\, C => \htrans11\, 
        D => \HMASTLOCK\, FCI => \HADDR_TEMP_6_cry_23\, S => 
        \HADDR_TEMP_6[24]\, Y => OPEN, FCO => 
        \HADDR_TEMP_6_cry_24\);
    
    \HrdyCount_3[0]\ : CFG4
      generic map(INIT => x"1A5A")

      port map(A => \HrdyCount[0]_net_1\, B => 
        \HrdyCount[1]_net_1\, C => \un1_hready_flngedge\, D => 
        clock_count, Y => \HrdyCount_3[0]_net_1\);
    
    \Recount_RNIEVFHA[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \HREADY\, B => HREADYOUT_RNIVC501_Y, C => 
        \Recount[7]_net_1\, D => \HMASTLOCK\, FCI => 
        \Recount_cry[6]\, S => \Recount_s[7]\, Y => OPEN, FCO => 
        \Recount_cry[7]\);
    
    \clock_count[2]\ : SLE
      port map(D => \clock_count_s[2]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[2]_net_1\);
    
    \Recount[12]\ : SLE
      port map(D => \Recount_s[12]\, CLK => HCLK, EN => 
        \un7_clock_count\, ALn => un1_reset_n_2_i, ADn => 
        \HREADY\, SLn => \HREADY\, SD => \HMASTLOCK\, LAT => 
        \HMASTLOCK\, Q => \Recount[12]_net_1\);
    
    \HWRITE_DATA_TEMP_6[24]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[24]_net_1\, D => \Recount[24]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[24]_net_1\);
    
    \clock_count[21]\ : SLE
      port map(D => \clock_count_s[21]\, CLK => HCLK, EN => 
        clock_counte, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \clock_count[21]_net_1\);
    
    \HWRITE_DATA_TEMP_lm_0[29]\ : CFG4
      generic map(INIT => x"CEC4")

      port map(A => \htrans7_4\, B => 
        \HWRITE_DATA_TEMP_6[29]_net_1\, C => 
        \ahb_states[0]_net_1\, D => \HWRITE_DATA_TEMP_s[29]\, Y
         => \HWRITE_DATA_TEMP_lm[29]\);
    
    \HWRITE_DATA_TEMP_6[20]\ : CFG4
      generic map(INIT => x"A820")

      port map(A => \htrans11\, B => \INT2_TEMP_0_sqmuxa\, C => 
        \count_Temp1[20]_net_1\, D => \Recount[20]_net_1\, Y => 
        \HWRITE_DATA_TEMP_6[20]_net_1\);
    
    \HWRITE_DATA_TEMP[8]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[8]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[8]\);
    
    \count_Temp1_lm_0[27]\ : CFG4
      generic map(INIT => x"1F00")

      port map(A => \ahb_states[1]_net_1\, B => 
        \ahb_states[2]_net_1\, C => \un7_clock_count\, D => 
        \count_Temp1_s[27]\, Y => \count_Temp1_lm[27]\);
    
    un7_clock_count_19 : CFG4
      generic map(INIT => x"0001")

      port map(A => \clock_count[19]_net_1\, B => 
        \clock_count[18]_net_1\, C => \clock_count[17]_net_1\, D
         => \clock_count[16]_net_1\, Y => \un7_clock_count_19\);
    
    \HWRITE_DATA_TEMP_cry[14]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[14]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[13]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[14]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[14]_net_1\);
    
    \HADDR_TEMP[16]\ : SLE
      port map(D => \HADDR_TEMP_6[16]\, CLK => HCLK, EN => 
        \HREADY\, ALn => RESET_N, ADn => \HREADY\, SLn => 
        \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q => 
        \HADDR[16]\);
    
    \HWRITE_DATA_TEMP_cry[19]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \HREADY\, B => \HWDATA[19]\, C => \HMASTLOCK\, 
        D => \HMASTLOCK\, FCI => \HWRITE_DATA_TEMP_cry[18]_net_1\, 
        S => \HWRITE_DATA_TEMP_s[19]\, Y => OPEN, FCO => 
        \HWRITE_DATA_TEMP_cry[19]_net_1\);
    
    \HWRITE_DATA_TEMP[2]\ : SLE
      port map(D => \HWRITE_DATA_TEMP_lm[2]\, CLK => HCLK, EN => 
        un1_htrans6_4_i_0, ALn => RESET_N, ADn => \HREADY\, SLn
         => \HREADY\, SD => \HMASTLOCK\, LAT => \HMASTLOCK\, Q
         => \HWDATA[2]\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity AHB_Bus_Matrix is

    port( DEVRST_N     : in    std_logic;
          MMUART_0_RXD : in    std_logic;
          MMUART_0_TXD : out   std_logic
        );

end AHB_Bus_Matrix;

architecture DEF_ARCH of AHB_Bus_Matrix is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component AHB_Bus_Matrix_sb
    port( Fabric_Master1_0_BIF_1_HADDR     : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master1_0_BIF_1_HSIZE     : in    std_logic_vector(1 downto 0) := (others => 'U');
          Fabric_Master1_0_BIF_1_HTRANS    : in    std_logic_vector(1 to 1) := (others => 'U');
          Fabric_Master1_0_BIF_1_HWDATA    : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HADDR     : in    std_logic_vector(31 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HSIZE     : in    std_logic_vector(1 downto 0) := (others => 'U');
          Fabric_Master2_0_BIF_1_HTRANS    : in    std_logic_vector(1 to 1) := (others => 'U');
          Fabric_Master2_0_BIF_1_HWDATA    : in    std_logic_vector(31 downto 0) := (others => 'U');
          DEVRST_N                         : in    std_logic := 'U';
          MMUART_0_TXD                     : out   std_logic;
          MMUART_0_RXD                     : in    std_logic := 'U';
          AHB_Bus_Matrix_sb_0_GPIO_2_M2F   : out   std_logic;
          Fabric_Master1_0_BIF_1_HREADYOUT : out   std_logic;
          Fabric_Master2_0_BIF_1_HREADYOUT : out   std_logic;
          AHB_Bus_Matrix_sb_0_GPIO_0_M2F   : out   std_logic;
          AHB_Bus_Matrix_sb_0_FIC_0_CLK    : out   std_logic;
          AND2_0_Y                         : in    std_logic := 'U';
          Fabric_Master1_0_BIF_1_HSELx     : in    std_logic := 'U';
          Fabric_Master1_0_BIF_1_HWRITE    : in    std_logic := 'U';
          Fabric_Master2_0_BIF_1_HSELx     : in    std_logic := 'U';
          Fabric_Master2_0_BIF_1_HWRITE    : in    std_logic := 'U';
          AHB_Bus_Matrix_sb_0_FIC_1_CLK    : out   std_logic;
          AHB_Bus_Matrix_sb_0_MSS_READY    : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Fabric_Master1
    port( HTRANS        : out   std_logic_vector(1 downto 0);
          HSIZE         : out   std_logic_vector(1 downto 0);
          HWDATA        : out   std_logic_vector(31 downto 0);
          HADDR         : out   std_logic_vector(31 downto 0);
          HRDATA        : in    std_logic_vector(31 downto 0) := (others => 'U');
          RESET_N       : in    std_logic := 'U';
          HCLK          : in    std_logic := 'U';
          HWRITE        : out   std_logic;
          HMASTLOCK     : out   std_logic;
          HREADY        : out   std_logic;
          HSEL          : out   std_logic;
          HREADYOUT     : in    std_logic := 'U';
          HRESP         : in    std_logic := 'U';
          INT1          : out   std_logic;
          MASTER1_START : in    std_logic := 'U';
          MASTER1_STOP  : in    std_logic := 'U'
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component Fabric_Master2
    port( HTRANS        : out   std_logic_vector(1 downto 0);
          HSIZE         : out   std_logic_vector(1 downto 0);
          HWDATA        : out   std_logic_vector(31 downto 0);
          HADDR         : out   std_logic_vector(31 downto 0);
          HRDATA        : in    std_logic_vector(31 downto 0) := (others => 'U');
          RESET_N       : in    std_logic := 'U';
          HCLK          : in    std_logic := 'U';
          HWRITE        : out   std_logic;
          HMASTLOCK     : out   std_logic;
          HREADY        : out   std_logic;
          HSEL          : out   std_logic;
          HREADYOUT     : in    std_logic := 'U';
          HRESP         : in    std_logic := 'U';
          INT2          : out   std_logic;
          MASTER2_START : in    std_logic := 'U';
          MASTER2_STOP  : in    std_logic := 'U'
        );
  end component;

    signal VCC_net_1, \Fabric_Master1_0_BIF_1_HADDR[0]\, 
        \Fabric_Master1_0_BIF_1_HADDR[1]\, 
        \Fabric_Master1_0_BIF_1_HADDR[2]\, 
        \Fabric_Master1_0_BIF_1_HADDR[3]\, 
        \Fabric_Master1_0_BIF_1_HADDR[4]\, 
        \Fabric_Master1_0_BIF_1_HADDR[5]\, 
        \Fabric_Master1_0_BIF_1_HADDR[6]\, 
        \Fabric_Master1_0_BIF_1_HADDR[7]\, 
        \Fabric_Master1_0_BIF_1_HADDR[8]\, 
        \Fabric_Master1_0_BIF_1_HADDR[9]\, 
        \Fabric_Master1_0_BIF_1_HADDR[10]\, 
        \Fabric_Master1_0_BIF_1_HADDR[11]\, 
        \Fabric_Master1_0_BIF_1_HADDR[12]\, 
        \Fabric_Master1_0_BIF_1_HADDR[13]\, 
        \Fabric_Master1_0_BIF_1_HADDR[14]\, 
        \Fabric_Master1_0_BIF_1_HADDR[15]\, 
        \Fabric_Master1_0_BIF_1_HADDR[16]\, 
        \Fabric_Master1_0_BIF_1_HADDR[17]\, 
        \Fabric_Master1_0_BIF_1_HADDR[18]\, 
        \Fabric_Master1_0_BIF_1_HADDR[19]\, 
        \Fabric_Master1_0_BIF_1_HADDR[20]\, 
        \Fabric_Master1_0_BIF_1_HADDR[21]\, 
        \Fabric_Master1_0_BIF_1_HADDR[22]\, 
        \Fabric_Master1_0_BIF_1_HADDR[23]\, 
        \Fabric_Master1_0_BIF_1_HADDR[24]\, 
        \Fabric_Master1_0_BIF_1_HADDR[25]\, 
        \Fabric_Master1_0_BIF_1_HADDR[26]\, 
        \Fabric_Master1_0_BIF_1_HADDR[27]\, 
        \Fabric_Master1_0_BIF_1_HADDR[28]\, 
        \Fabric_Master1_0_BIF_1_HADDR[29]\, 
        \Fabric_Master1_0_BIF_1_HADDR[30]\, 
        \Fabric_Master1_0_BIF_1_HADDR[31]\, 
        Fabric_Master1_0_BIF_1_HSELx, 
        \Fabric_Master1_0_BIF_1_HSIZE[0]\, 
        \Fabric_Master1_0_BIF_1_HSIZE[1]\, 
        \Fabric_Master1_0_BIF_1_HTRANS[1]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[0]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[1]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[2]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[3]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[4]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[5]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[6]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[7]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[8]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[9]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[10]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[11]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[12]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[13]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[14]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[15]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[16]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[17]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[18]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[19]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[20]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[21]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[22]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[23]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[24]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[25]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[26]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[27]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[28]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[29]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[30]\, 
        \Fabric_Master1_0_BIF_1_HWDATA[31]\, 
        Fabric_Master1_0_BIF_1_HWRITE, 
        \Fabric_Master2_0_BIF_1_HADDR[0]\, 
        \Fabric_Master2_0_BIF_1_HADDR[1]\, 
        \Fabric_Master2_0_BIF_1_HADDR[2]\, 
        \Fabric_Master2_0_BIF_1_HADDR[3]\, 
        \Fabric_Master2_0_BIF_1_HADDR[4]\, 
        \Fabric_Master2_0_BIF_1_HADDR[5]\, 
        \Fabric_Master2_0_BIF_1_HADDR[6]\, 
        \Fabric_Master2_0_BIF_1_HADDR[7]\, 
        \Fabric_Master2_0_BIF_1_HADDR[8]\, 
        \Fabric_Master2_0_BIF_1_HADDR[9]\, 
        \Fabric_Master2_0_BIF_1_HADDR[10]\, 
        \Fabric_Master2_0_BIF_1_HADDR[11]\, 
        \Fabric_Master2_0_BIF_1_HADDR[12]\, 
        \Fabric_Master2_0_BIF_1_HADDR[13]\, 
        \Fabric_Master2_0_BIF_1_HADDR[14]\, 
        \Fabric_Master2_0_BIF_1_HADDR[15]\, 
        \Fabric_Master2_0_BIF_1_HADDR[16]\, 
        \Fabric_Master2_0_BIF_1_HADDR[17]\, 
        \Fabric_Master2_0_BIF_1_HADDR[18]\, 
        \Fabric_Master2_0_BIF_1_HADDR[19]\, 
        \Fabric_Master2_0_BIF_1_HADDR[20]\, 
        \Fabric_Master2_0_BIF_1_HADDR[21]\, 
        \Fabric_Master2_0_BIF_1_HADDR[22]\, 
        \Fabric_Master2_0_BIF_1_HADDR[23]\, 
        \Fabric_Master2_0_BIF_1_HADDR[24]\, 
        \Fabric_Master2_0_BIF_1_HADDR[25]\, 
        \Fabric_Master2_0_BIF_1_HADDR[26]\, 
        \Fabric_Master2_0_BIF_1_HADDR[27]\, 
        \Fabric_Master2_0_BIF_1_HADDR[28]\, 
        \Fabric_Master2_0_BIF_1_HADDR[29]\, 
        \Fabric_Master2_0_BIF_1_HADDR[30]\, 
        \Fabric_Master2_0_BIF_1_HADDR[31]\, 
        Fabric_Master2_0_BIF_1_HSELx, 
        \Fabric_Master2_0_BIF_1_HSIZE[0]\, 
        \Fabric_Master2_0_BIF_1_HSIZE[1]\, 
        \Fabric_Master2_0_BIF_1_HTRANS[1]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[0]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[1]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[2]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[3]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[4]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[5]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[6]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[7]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[8]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[9]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[10]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[11]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[12]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[13]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[14]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[15]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[16]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[17]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[18]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[19]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[20]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[21]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[22]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[23]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[24]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[25]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[26]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[27]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[28]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[29]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[30]\, 
        \Fabric_Master2_0_BIF_1_HWDATA[31]\, 
        Fabric_Master2_0_BIF_1_HWRITE, AND2_0_Y, 
        Fabric_Master1_0_BIF_1_HREADYOUT, 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, 
        Fabric_Master2_0_BIF_1_HREADYOUT, 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK, 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F, 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F, 
        AHB_Bus_Matrix_sb_0_MSS_READY, Fabric_Master1_0_INT1, 
        Fabric_Master2_0_INT2, GND_net_1 : std_logic;
    signal nc2, nc1 : std_logic;

    for all : AHB_Bus_Matrix_sb
	Use entity work.AHB_Bus_Matrix_sb(DEF_ARCH);
    for all : Fabric_Master1
	Use entity work.Fabric_Master1(DEF_ARCH);
    for all : Fabric_Master2
	Use entity work.Fabric_Master2(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    AHB_Bus_Matrix_sb_0 : AHB_Bus_Matrix_sb
      port map(Fabric_Master1_0_BIF_1_HADDR(31) => 
        \Fabric_Master1_0_BIF_1_HADDR[31]\, 
        Fabric_Master1_0_BIF_1_HADDR(30) => 
        \Fabric_Master1_0_BIF_1_HADDR[30]\, 
        Fabric_Master1_0_BIF_1_HADDR(29) => 
        \Fabric_Master1_0_BIF_1_HADDR[29]\, 
        Fabric_Master1_0_BIF_1_HADDR(28) => 
        \Fabric_Master1_0_BIF_1_HADDR[28]\, 
        Fabric_Master1_0_BIF_1_HADDR(27) => 
        \Fabric_Master1_0_BIF_1_HADDR[27]\, 
        Fabric_Master1_0_BIF_1_HADDR(26) => 
        \Fabric_Master1_0_BIF_1_HADDR[26]\, 
        Fabric_Master1_0_BIF_1_HADDR(25) => 
        \Fabric_Master1_0_BIF_1_HADDR[25]\, 
        Fabric_Master1_0_BIF_1_HADDR(24) => 
        \Fabric_Master1_0_BIF_1_HADDR[24]\, 
        Fabric_Master1_0_BIF_1_HADDR(23) => 
        \Fabric_Master1_0_BIF_1_HADDR[23]\, 
        Fabric_Master1_0_BIF_1_HADDR(22) => 
        \Fabric_Master1_0_BIF_1_HADDR[22]\, 
        Fabric_Master1_0_BIF_1_HADDR(21) => 
        \Fabric_Master1_0_BIF_1_HADDR[21]\, 
        Fabric_Master1_0_BIF_1_HADDR(20) => 
        \Fabric_Master1_0_BIF_1_HADDR[20]\, 
        Fabric_Master1_0_BIF_1_HADDR(19) => 
        \Fabric_Master1_0_BIF_1_HADDR[19]\, 
        Fabric_Master1_0_BIF_1_HADDR(18) => 
        \Fabric_Master1_0_BIF_1_HADDR[18]\, 
        Fabric_Master1_0_BIF_1_HADDR(17) => 
        \Fabric_Master1_0_BIF_1_HADDR[17]\, 
        Fabric_Master1_0_BIF_1_HADDR(16) => 
        \Fabric_Master1_0_BIF_1_HADDR[16]\, 
        Fabric_Master1_0_BIF_1_HADDR(15) => 
        \Fabric_Master1_0_BIF_1_HADDR[15]\, 
        Fabric_Master1_0_BIF_1_HADDR(14) => 
        \Fabric_Master1_0_BIF_1_HADDR[14]\, 
        Fabric_Master1_0_BIF_1_HADDR(13) => 
        \Fabric_Master1_0_BIF_1_HADDR[13]\, 
        Fabric_Master1_0_BIF_1_HADDR(12) => 
        \Fabric_Master1_0_BIF_1_HADDR[12]\, 
        Fabric_Master1_0_BIF_1_HADDR(11) => 
        \Fabric_Master1_0_BIF_1_HADDR[11]\, 
        Fabric_Master1_0_BIF_1_HADDR(10) => 
        \Fabric_Master1_0_BIF_1_HADDR[10]\, 
        Fabric_Master1_0_BIF_1_HADDR(9) => 
        \Fabric_Master1_0_BIF_1_HADDR[9]\, 
        Fabric_Master1_0_BIF_1_HADDR(8) => 
        \Fabric_Master1_0_BIF_1_HADDR[8]\, 
        Fabric_Master1_0_BIF_1_HADDR(7) => 
        \Fabric_Master1_0_BIF_1_HADDR[7]\, 
        Fabric_Master1_0_BIF_1_HADDR(6) => 
        \Fabric_Master1_0_BIF_1_HADDR[6]\, 
        Fabric_Master1_0_BIF_1_HADDR(5) => 
        \Fabric_Master1_0_BIF_1_HADDR[5]\, 
        Fabric_Master1_0_BIF_1_HADDR(4) => 
        \Fabric_Master1_0_BIF_1_HADDR[4]\, 
        Fabric_Master1_0_BIF_1_HADDR(3) => 
        \Fabric_Master1_0_BIF_1_HADDR[3]\, 
        Fabric_Master1_0_BIF_1_HADDR(2) => 
        \Fabric_Master1_0_BIF_1_HADDR[2]\, 
        Fabric_Master1_0_BIF_1_HADDR(1) => 
        \Fabric_Master1_0_BIF_1_HADDR[1]\, 
        Fabric_Master1_0_BIF_1_HADDR(0) => 
        \Fabric_Master1_0_BIF_1_HADDR[0]\, 
        Fabric_Master1_0_BIF_1_HSIZE(1) => 
        \Fabric_Master1_0_BIF_1_HSIZE[1]\, 
        Fabric_Master1_0_BIF_1_HSIZE(0) => 
        \Fabric_Master1_0_BIF_1_HSIZE[0]\, 
        Fabric_Master1_0_BIF_1_HTRANS(1) => 
        \Fabric_Master1_0_BIF_1_HTRANS[1]\, 
        Fabric_Master1_0_BIF_1_HWDATA(31) => 
        \Fabric_Master1_0_BIF_1_HWDATA[31]\, 
        Fabric_Master1_0_BIF_1_HWDATA(30) => 
        \Fabric_Master1_0_BIF_1_HWDATA[30]\, 
        Fabric_Master1_0_BIF_1_HWDATA(29) => 
        \Fabric_Master1_0_BIF_1_HWDATA[29]\, 
        Fabric_Master1_0_BIF_1_HWDATA(28) => 
        \Fabric_Master1_0_BIF_1_HWDATA[28]\, 
        Fabric_Master1_0_BIF_1_HWDATA(27) => 
        \Fabric_Master1_0_BIF_1_HWDATA[27]\, 
        Fabric_Master1_0_BIF_1_HWDATA(26) => 
        \Fabric_Master1_0_BIF_1_HWDATA[26]\, 
        Fabric_Master1_0_BIF_1_HWDATA(25) => 
        \Fabric_Master1_0_BIF_1_HWDATA[25]\, 
        Fabric_Master1_0_BIF_1_HWDATA(24) => 
        \Fabric_Master1_0_BIF_1_HWDATA[24]\, 
        Fabric_Master1_0_BIF_1_HWDATA(23) => 
        \Fabric_Master1_0_BIF_1_HWDATA[23]\, 
        Fabric_Master1_0_BIF_1_HWDATA(22) => 
        \Fabric_Master1_0_BIF_1_HWDATA[22]\, 
        Fabric_Master1_0_BIF_1_HWDATA(21) => 
        \Fabric_Master1_0_BIF_1_HWDATA[21]\, 
        Fabric_Master1_0_BIF_1_HWDATA(20) => 
        \Fabric_Master1_0_BIF_1_HWDATA[20]\, 
        Fabric_Master1_0_BIF_1_HWDATA(19) => 
        \Fabric_Master1_0_BIF_1_HWDATA[19]\, 
        Fabric_Master1_0_BIF_1_HWDATA(18) => 
        \Fabric_Master1_0_BIF_1_HWDATA[18]\, 
        Fabric_Master1_0_BIF_1_HWDATA(17) => 
        \Fabric_Master1_0_BIF_1_HWDATA[17]\, 
        Fabric_Master1_0_BIF_1_HWDATA(16) => 
        \Fabric_Master1_0_BIF_1_HWDATA[16]\, 
        Fabric_Master1_0_BIF_1_HWDATA(15) => 
        \Fabric_Master1_0_BIF_1_HWDATA[15]\, 
        Fabric_Master1_0_BIF_1_HWDATA(14) => 
        \Fabric_Master1_0_BIF_1_HWDATA[14]\, 
        Fabric_Master1_0_BIF_1_HWDATA(13) => 
        \Fabric_Master1_0_BIF_1_HWDATA[13]\, 
        Fabric_Master1_0_BIF_1_HWDATA(12) => 
        \Fabric_Master1_0_BIF_1_HWDATA[12]\, 
        Fabric_Master1_0_BIF_1_HWDATA(11) => 
        \Fabric_Master1_0_BIF_1_HWDATA[11]\, 
        Fabric_Master1_0_BIF_1_HWDATA(10) => 
        \Fabric_Master1_0_BIF_1_HWDATA[10]\, 
        Fabric_Master1_0_BIF_1_HWDATA(9) => 
        \Fabric_Master1_0_BIF_1_HWDATA[9]\, 
        Fabric_Master1_0_BIF_1_HWDATA(8) => 
        \Fabric_Master1_0_BIF_1_HWDATA[8]\, 
        Fabric_Master1_0_BIF_1_HWDATA(7) => 
        \Fabric_Master1_0_BIF_1_HWDATA[7]\, 
        Fabric_Master1_0_BIF_1_HWDATA(6) => 
        \Fabric_Master1_0_BIF_1_HWDATA[6]\, 
        Fabric_Master1_0_BIF_1_HWDATA(5) => 
        \Fabric_Master1_0_BIF_1_HWDATA[5]\, 
        Fabric_Master1_0_BIF_1_HWDATA(4) => 
        \Fabric_Master1_0_BIF_1_HWDATA[4]\, 
        Fabric_Master1_0_BIF_1_HWDATA(3) => 
        \Fabric_Master1_0_BIF_1_HWDATA[3]\, 
        Fabric_Master1_0_BIF_1_HWDATA(2) => 
        \Fabric_Master1_0_BIF_1_HWDATA[2]\, 
        Fabric_Master1_0_BIF_1_HWDATA(1) => 
        \Fabric_Master1_0_BIF_1_HWDATA[1]\, 
        Fabric_Master1_0_BIF_1_HWDATA(0) => 
        \Fabric_Master1_0_BIF_1_HWDATA[0]\, 
        Fabric_Master2_0_BIF_1_HADDR(31) => 
        \Fabric_Master2_0_BIF_1_HADDR[31]\, 
        Fabric_Master2_0_BIF_1_HADDR(30) => 
        \Fabric_Master2_0_BIF_1_HADDR[30]\, 
        Fabric_Master2_0_BIF_1_HADDR(29) => 
        \Fabric_Master2_0_BIF_1_HADDR[29]\, 
        Fabric_Master2_0_BIF_1_HADDR(28) => 
        \Fabric_Master2_0_BIF_1_HADDR[28]\, 
        Fabric_Master2_0_BIF_1_HADDR(27) => 
        \Fabric_Master2_0_BIF_1_HADDR[27]\, 
        Fabric_Master2_0_BIF_1_HADDR(26) => 
        \Fabric_Master2_0_BIF_1_HADDR[26]\, 
        Fabric_Master2_0_BIF_1_HADDR(25) => 
        \Fabric_Master2_0_BIF_1_HADDR[25]\, 
        Fabric_Master2_0_BIF_1_HADDR(24) => 
        \Fabric_Master2_0_BIF_1_HADDR[24]\, 
        Fabric_Master2_0_BIF_1_HADDR(23) => 
        \Fabric_Master2_0_BIF_1_HADDR[23]\, 
        Fabric_Master2_0_BIF_1_HADDR(22) => 
        \Fabric_Master2_0_BIF_1_HADDR[22]\, 
        Fabric_Master2_0_BIF_1_HADDR(21) => 
        \Fabric_Master2_0_BIF_1_HADDR[21]\, 
        Fabric_Master2_0_BIF_1_HADDR(20) => 
        \Fabric_Master2_0_BIF_1_HADDR[20]\, 
        Fabric_Master2_0_BIF_1_HADDR(19) => 
        \Fabric_Master2_0_BIF_1_HADDR[19]\, 
        Fabric_Master2_0_BIF_1_HADDR(18) => 
        \Fabric_Master2_0_BIF_1_HADDR[18]\, 
        Fabric_Master2_0_BIF_1_HADDR(17) => 
        \Fabric_Master2_0_BIF_1_HADDR[17]\, 
        Fabric_Master2_0_BIF_1_HADDR(16) => 
        \Fabric_Master2_0_BIF_1_HADDR[16]\, 
        Fabric_Master2_0_BIF_1_HADDR(15) => 
        \Fabric_Master2_0_BIF_1_HADDR[15]\, 
        Fabric_Master2_0_BIF_1_HADDR(14) => 
        \Fabric_Master2_0_BIF_1_HADDR[14]\, 
        Fabric_Master2_0_BIF_1_HADDR(13) => 
        \Fabric_Master2_0_BIF_1_HADDR[13]\, 
        Fabric_Master2_0_BIF_1_HADDR(12) => 
        \Fabric_Master2_0_BIF_1_HADDR[12]\, 
        Fabric_Master2_0_BIF_1_HADDR(11) => 
        \Fabric_Master2_0_BIF_1_HADDR[11]\, 
        Fabric_Master2_0_BIF_1_HADDR(10) => 
        \Fabric_Master2_0_BIF_1_HADDR[10]\, 
        Fabric_Master2_0_BIF_1_HADDR(9) => 
        \Fabric_Master2_0_BIF_1_HADDR[9]\, 
        Fabric_Master2_0_BIF_1_HADDR(8) => 
        \Fabric_Master2_0_BIF_1_HADDR[8]\, 
        Fabric_Master2_0_BIF_1_HADDR(7) => 
        \Fabric_Master2_0_BIF_1_HADDR[7]\, 
        Fabric_Master2_0_BIF_1_HADDR(6) => 
        \Fabric_Master2_0_BIF_1_HADDR[6]\, 
        Fabric_Master2_0_BIF_1_HADDR(5) => 
        \Fabric_Master2_0_BIF_1_HADDR[5]\, 
        Fabric_Master2_0_BIF_1_HADDR(4) => 
        \Fabric_Master2_0_BIF_1_HADDR[4]\, 
        Fabric_Master2_0_BIF_1_HADDR(3) => 
        \Fabric_Master2_0_BIF_1_HADDR[3]\, 
        Fabric_Master2_0_BIF_1_HADDR(2) => 
        \Fabric_Master2_0_BIF_1_HADDR[2]\, 
        Fabric_Master2_0_BIF_1_HADDR(1) => 
        \Fabric_Master2_0_BIF_1_HADDR[1]\, 
        Fabric_Master2_0_BIF_1_HADDR(0) => 
        \Fabric_Master2_0_BIF_1_HADDR[0]\, 
        Fabric_Master2_0_BIF_1_HSIZE(1) => 
        \Fabric_Master2_0_BIF_1_HSIZE[1]\, 
        Fabric_Master2_0_BIF_1_HSIZE(0) => 
        \Fabric_Master2_0_BIF_1_HSIZE[0]\, 
        Fabric_Master2_0_BIF_1_HTRANS(1) => 
        \Fabric_Master2_0_BIF_1_HTRANS[1]\, 
        Fabric_Master2_0_BIF_1_HWDATA(31) => 
        \Fabric_Master2_0_BIF_1_HWDATA[31]\, 
        Fabric_Master2_0_BIF_1_HWDATA(30) => 
        \Fabric_Master2_0_BIF_1_HWDATA[30]\, 
        Fabric_Master2_0_BIF_1_HWDATA(29) => 
        \Fabric_Master2_0_BIF_1_HWDATA[29]\, 
        Fabric_Master2_0_BIF_1_HWDATA(28) => 
        \Fabric_Master2_0_BIF_1_HWDATA[28]\, 
        Fabric_Master2_0_BIF_1_HWDATA(27) => 
        \Fabric_Master2_0_BIF_1_HWDATA[27]\, 
        Fabric_Master2_0_BIF_1_HWDATA(26) => 
        \Fabric_Master2_0_BIF_1_HWDATA[26]\, 
        Fabric_Master2_0_BIF_1_HWDATA(25) => 
        \Fabric_Master2_0_BIF_1_HWDATA[25]\, 
        Fabric_Master2_0_BIF_1_HWDATA(24) => 
        \Fabric_Master2_0_BIF_1_HWDATA[24]\, 
        Fabric_Master2_0_BIF_1_HWDATA(23) => 
        \Fabric_Master2_0_BIF_1_HWDATA[23]\, 
        Fabric_Master2_0_BIF_1_HWDATA(22) => 
        \Fabric_Master2_0_BIF_1_HWDATA[22]\, 
        Fabric_Master2_0_BIF_1_HWDATA(21) => 
        \Fabric_Master2_0_BIF_1_HWDATA[21]\, 
        Fabric_Master2_0_BIF_1_HWDATA(20) => 
        \Fabric_Master2_0_BIF_1_HWDATA[20]\, 
        Fabric_Master2_0_BIF_1_HWDATA(19) => 
        \Fabric_Master2_0_BIF_1_HWDATA[19]\, 
        Fabric_Master2_0_BIF_1_HWDATA(18) => 
        \Fabric_Master2_0_BIF_1_HWDATA[18]\, 
        Fabric_Master2_0_BIF_1_HWDATA(17) => 
        \Fabric_Master2_0_BIF_1_HWDATA[17]\, 
        Fabric_Master2_0_BIF_1_HWDATA(16) => 
        \Fabric_Master2_0_BIF_1_HWDATA[16]\, 
        Fabric_Master2_0_BIF_1_HWDATA(15) => 
        \Fabric_Master2_0_BIF_1_HWDATA[15]\, 
        Fabric_Master2_0_BIF_1_HWDATA(14) => 
        \Fabric_Master2_0_BIF_1_HWDATA[14]\, 
        Fabric_Master2_0_BIF_1_HWDATA(13) => 
        \Fabric_Master2_0_BIF_1_HWDATA[13]\, 
        Fabric_Master2_0_BIF_1_HWDATA(12) => 
        \Fabric_Master2_0_BIF_1_HWDATA[12]\, 
        Fabric_Master2_0_BIF_1_HWDATA(11) => 
        \Fabric_Master2_0_BIF_1_HWDATA[11]\, 
        Fabric_Master2_0_BIF_1_HWDATA(10) => 
        \Fabric_Master2_0_BIF_1_HWDATA[10]\, 
        Fabric_Master2_0_BIF_1_HWDATA(9) => 
        \Fabric_Master2_0_BIF_1_HWDATA[9]\, 
        Fabric_Master2_0_BIF_1_HWDATA(8) => 
        \Fabric_Master2_0_BIF_1_HWDATA[8]\, 
        Fabric_Master2_0_BIF_1_HWDATA(7) => 
        \Fabric_Master2_0_BIF_1_HWDATA[7]\, 
        Fabric_Master2_0_BIF_1_HWDATA(6) => 
        \Fabric_Master2_0_BIF_1_HWDATA[6]\, 
        Fabric_Master2_0_BIF_1_HWDATA(5) => 
        \Fabric_Master2_0_BIF_1_HWDATA[5]\, 
        Fabric_Master2_0_BIF_1_HWDATA(4) => 
        \Fabric_Master2_0_BIF_1_HWDATA[4]\, 
        Fabric_Master2_0_BIF_1_HWDATA(3) => 
        \Fabric_Master2_0_BIF_1_HWDATA[3]\, 
        Fabric_Master2_0_BIF_1_HWDATA(2) => 
        \Fabric_Master2_0_BIF_1_HWDATA[2]\, 
        Fabric_Master2_0_BIF_1_HWDATA(1) => 
        \Fabric_Master2_0_BIF_1_HWDATA[1]\, 
        Fabric_Master2_0_BIF_1_HWDATA(0) => 
        \Fabric_Master2_0_BIF_1_HWDATA[0]\, DEVRST_N => DEVRST_N, 
        MMUART_0_TXD => MMUART_0_TXD, MMUART_0_RXD => 
        MMUART_0_RXD, AHB_Bus_Matrix_sb_0_GPIO_2_M2F => 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F, 
        Fabric_Master1_0_BIF_1_HREADYOUT => 
        Fabric_Master1_0_BIF_1_HREADYOUT, 
        Fabric_Master2_0_BIF_1_HREADYOUT => 
        Fabric_Master2_0_BIF_1_HREADYOUT, 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F => 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F, 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, AND2_0_Y => AND2_0_Y, 
        Fabric_Master1_0_BIF_1_HSELx => 
        Fabric_Master1_0_BIF_1_HSELx, 
        Fabric_Master1_0_BIF_1_HWRITE => 
        Fabric_Master1_0_BIF_1_HWRITE, 
        Fabric_Master2_0_BIF_1_HSELx => 
        Fabric_Master2_0_BIF_1_HSELx, 
        Fabric_Master2_0_BIF_1_HWRITE => 
        Fabric_Master2_0_BIF_1_HWRITE, 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK => 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK, 
        AHB_Bus_Matrix_sb_0_MSS_READY => 
        AHB_Bus_Matrix_sb_0_MSS_READY);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Fabric_Master1_0 : Fabric_Master1
      port map(HTRANS(1) => \Fabric_Master1_0_BIF_1_HTRANS[1]\, 
        HTRANS(0) => nc2, HSIZE(1) => 
        \Fabric_Master1_0_BIF_1_HSIZE[1]\, HSIZE(0) => 
        \Fabric_Master1_0_BIF_1_HSIZE[0]\, HWDATA(31) => 
        \Fabric_Master1_0_BIF_1_HWDATA[31]\, HWDATA(30) => 
        \Fabric_Master1_0_BIF_1_HWDATA[30]\, HWDATA(29) => 
        \Fabric_Master1_0_BIF_1_HWDATA[29]\, HWDATA(28) => 
        \Fabric_Master1_0_BIF_1_HWDATA[28]\, HWDATA(27) => 
        \Fabric_Master1_0_BIF_1_HWDATA[27]\, HWDATA(26) => 
        \Fabric_Master1_0_BIF_1_HWDATA[26]\, HWDATA(25) => 
        \Fabric_Master1_0_BIF_1_HWDATA[25]\, HWDATA(24) => 
        \Fabric_Master1_0_BIF_1_HWDATA[24]\, HWDATA(23) => 
        \Fabric_Master1_0_BIF_1_HWDATA[23]\, HWDATA(22) => 
        \Fabric_Master1_0_BIF_1_HWDATA[22]\, HWDATA(21) => 
        \Fabric_Master1_0_BIF_1_HWDATA[21]\, HWDATA(20) => 
        \Fabric_Master1_0_BIF_1_HWDATA[20]\, HWDATA(19) => 
        \Fabric_Master1_0_BIF_1_HWDATA[19]\, HWDATA(18) => 
        \Fabric_Master1_0_BIF_1_HWDATA[18]\, HWDATA(17) => 
        \Fabric_Master1_0_BIF_1_HWDATA[17]\, HWDATA(16) => 
        \Fabric_Master1_0_BIF_1_HWDATA[16]\, HWDATA(15) => 
        \Fabric_Master1_0_BIF_1_HWDATA[15]\, HWDATA(14) => 
        \Fabric_Master1_0_BIF_1_HWDATA[14]\, HWDATA(13) => 
        \Fabric_Master1_0_BIF_1_HWDATA[13]\, HWDATA(12) => 
        \Fabric_Master1_0_BIF_1_HWDATA[12]\, HWDATA(11) => 
        \Fabric_Master1_0_BIF_1_HWDATA[11]\, HWDATA(10) => 
        \Fabric_Master1_0_BIF_1_HWDATA[10]\, HWDATA(9) => 
        \Fabric_Master1_0_BIF_1_HWDATA[9]\, HWDATA(8) => 
        \Fabric_Master1_0_BIF_1_HWDATA[8]\, HWDATA(7) => 
        \Fabric_Master1_0_BIF_1_HWDATA[7]\, HWDATA(6) => 
        \Fabric_Master1_0_BIF_1_HWDATA[6]\, HWDATA(5) => 
        \Fabric_Master1_0_BIF_1_HWDATA[5]\, HWDATA(4) => 
        \Fabric_Master1_0_BIF_1_HWDATA[4]\, HWDATA(3) => 
        \Fabric_Master1_0_BIF_1_HWDATA[3]\, HWDATA(2) => 
        \Fabric_Master1_0_BIF_1_HWDATA[2]\, HWDATA(1) => 
        \Fabric_Master1_0_BIF_1_HWDATA[1]\, HWDATA(0) => 
        \Fabric_Master1_0_BIF_1_HWDATA[0]\, HADDR(31) => 
        \Fabric_Master1_0_BIF_1_HADDR[31]\, HADDR(30) => 
        \Fabric_Master1_0_BIF_1_HADDR[30]\, HADDR(29) => 
        \Fabric_Master1_0_BIF_1_HADDR[29]\, HADDR(28) => 
        \Fabric_Master1_0_BIF_1_HADDR[28]\, HADDR(27) => 
        \Fabric_Master1_0_BIF_1_HADDR[27]\, HADDR(26) => 
        \Fabric_Master1_0_BIF_1_HADDR[26]\, HADDR(25) => 
        \Fabric_Master1_0_BIF_1_HADDR[25]\, HADDR(24) => 
        \Fabric_Master1_0_BIF_1_HADDR[24]\, HADDR(23) => 
        \Fabric_Master1_0_BIF_1_HADDR[23]\, HADDR(22) => 
        \Fabric_Master1_0_BIF_1_HADDR[22]\, HADDR(21) => 
        \Fabric_Master1_0_BIF_1_HADDR[21]\, HADDR(20) => 
        \Fabric_Master1_0_BIF_1_HADDR[20]\, HADDR(19) => 
        \Fabric_Master1_0_BIF_1_HADDR[19]\, HADDR(18) => 
        \Fabric_Master1_0_BIF_1_HADDR[18]\, HADDR(17) => 
        \Fabric_Master1_0_BIF_1_HADDR[17]\, HADDR(16) => 
        \Fabric_Master1_0_BIF_1_HADDR[16]\, HADDR(15) => 
        \Fabric_Master1_0_BIF_1_HADDR[15]\, HADDR(14) => 
        \Fabric_Master1_0_BIF_1_HADDR[14]\, HADDR(13) => 
        \Fabric_Master1_0_BIF_1_HADDR[13]\, HADDR(12) => 
        \Fabric_Master1_0_BIF_1_HADDR[12]\, HADDR(11) => 
        \Fabric_Master1_0_BIF_1_HADDR[11]\, HADDR(10) => 
        \Fabric_Master1_0_BIF_1_HADDR[10]\, HADDR(9) => 
        \Fabric_Master1_0_BIF_1_HADDR[9]\, HADDR(8) => 
        \Fabric_Master1_0_BIF_1_HADDR[8]\, HADDR(7) => 
        \Fabric_Master1_0_BIF_1_HADDR[7]\, HADDR(6) => 
        \Fabric_Master1_0_BIF_1_HADDR[6]\, HADDR(5) => 
        \Fabric_Master1_0_BIF_1_HADDR[5]\, HADDR(4) => 
        \Fabric_Master1_0_BIF_1_HADDR[4]\, HADDR(3) => 
        \Fabric_Master1_0_BIF_1_HADDR[3]\, HADDR(2) => 
        \Fabric_Master1_0_BIF_1_HADDR[2]\, HADDR(1) => 
        \Fabric_Master1_0_BIF_1_HADDR[1]\, HADDR(0) => 
        \Fabric_Master1_0_BIF_1_HADDR[0]\, HRDATA(31) => 
        GND_net_1, HRDATA(30) => GND_net_1, HRDATA(29) => 
        GND_net_1, HRDATA(28) => GND_net_1, HRDATA(27) => 
        GND_net_1, HRDATA(26) => GND_net_1, HRDATA(25) => 
        GND_net_1, HRDATA(24) => GND_net_1, HRDATA(23) => 
        GND_net_1, HRDATA(22) => GND_net_1, HRDATA(21) => 
        GND_net_1, HRDATA(20) => GND_net_1, HRDATA(19) => 
        GND_net_1, HRDATA(18) => GND_net_1, HRDATA(17) => 
        GND_net_1, HRDATA(16) => GND_net_1, HRDATA(15) => 
        GND_net_1, HRDATA(14) => GND_net_1, HRDATA(13) => 
        GND_net_1, HRDATA(12) => GND_net_1, HRDATA(11) => 
        GND_net_1, HRDATA(10) => GND_net_1, HRDATA(9) => 
        GND_net_1, HRDATA(8) => GND_net_1, HRDATA(7) => GND_net_1, 
        HRDATA(6) => GND_net_1, HRDATA(5) => GND_net_1, HRDATA(4)
         => GND_net_1, HRDATA(3) => GND_net_1, HRDATA(2) => 
        GND_net_1, HRDATA(1) => GND_net_1, HRDATA(0) => GND_net_1, 
        RESET_N => AHB_Bus_Matrix_sb_0_MSS_READY, HCLK => 
        AHB_Bus_Matrix_sb_0_FIC_0_CLK, HWRITE => 
        Fabric_Master1_0_BIF_1_HWRITE, HMASTLOCK => OPEN, HREADY
         => OPEN, HSEL => Fabric_Master1_0_BIF_1_HSELx, HREADYOUT
         => Fabric_Master1_0_BIF_1_HREADYOUT, HRESP => GND_net_1, 
        INT1 => Fabric_Master1_0_INT1, MASTER1_START => 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F, MASTER1_STOP => 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F);
    
    AND2_0 : AND2
      port map(A => Fabric_Master1_0_INT1, B => 
        Fabric_Master2_0_INT2, Y => AND2_0_Y);
    
    Fabric_Master2_0 : Fabric_Master2
      port map(HTRANS(1) => \Fabric_Master2_0_BIF_1_HTRANS[1]\, 
        HTRANS(0) => nc1, HSIZE(1) => 
        \Fabric_Master2_0_BIF_1_HSIZE[1]\, HSIZE(0) => 
        \Fabric_Master2_0_BIF_1_HSIZE[0]\, HWDATA(31) => 
        \Fabric_Master2_0_BIF_1_HWDATA[31]\, HWDATA(30) => 
        \Fabric_Master2_0_BIF_1_HWDATA[30]\, HWDATA(29) => 
        \Fabric_Master2_0_BIF_1_HWDATA[29]\, HWDATA(28) => 
        \Fabric_Master2_0_BIF_1_HWDATA[28]\, HWDATA(27) => 
        \Fabric_Master2_0_BIF_1_HWDATA[27]\, HWDATA(26) => 
        \Fabric_Master2_0_BIF_1_HWDATA[26]\, HWDATA(25) => 
        \Fabric_Master2_0_BIF_1_HWDATA[25]\, HWDATA(24) => 
        \Fabric_Master2_0_BIF_1_HWDATA[24]\, HWDATA(23) => 
        \Fabric_Master2_0_BIF_1_HWDATA[23]\, HWDATA(22) => 
        \Fabric_Master2_0_BIF_1_HWDATA[22]\, HWDATA(21) => 
        \Fabric_Master2_0_BIF_1_HWDATA[21]\, HWDATA(20) => 
        \Fabric_Master2_0_BIF_1_HWDATA[20]\, HWDATA(19) => 
        \Fabric_Master2_0_BIF_1_HWDATA[19]\, HWDATA(18) => 
        \Fabric_Master2_0_BIF_1_HWDATA[18]\, HWDATA(17) => 
        \Fabric_Master2_0_BIF_1_HWDATA[17]\, HWDATA(16) => 
        \Fabric_Master2_0_BIF_1_HWDATA[16]\, HWDATA(15) => 
        \Fabric_Master2_0_BIF_1_HWDATA[15]\, HWDATA(14) => 
        \Fabric_Master2_0_BIF_1_HWDATA[14]\, HWDATA(13) => 
        \Fabric_Master2_0_BIF_1_HWDATA[13]\, HWDATA(12) => 
        \Fabric_Master2_0_BIF_1_HWDATA[12]\, HWDATA(11) => 
        \Fabric_Master2_0_BIF_1_HWDATA[11]\, HWDATA(10) => 
        \Fabric_Master2_0_BIF_1_HWDATA[10]\, HWDATA(9) => 
        \Fabric_Master2_0_BIF_1_HWDATA[9]\, HWDATA(8) => 
        \Fabric_Master2_0_BIF_1_HWDATA[8]\, HWDATA(7) => 
        \Fabric_Master2_0_BIF_1_HWDATA[7]\, HWDATA(6) => 
        \Fabric_Master2_0_BIF_1_HWDATA[6]\, HWDATA(5) => 
        \Fabric_Master2_0_BIF_1_HWDATA[5]\, HWDATA(4) => 
        \Fabric_Master2_0_BIF_1_HWDATA[4]\, HWDATA(3) => 
        \Fabric_Master2_0_BIF_1_HWDATA[3]\, HWDATA(2) => 
        \Fabric_Master2_0_BIF_1_HWDATA[2]\, HWDATA(1) => 
        \Fabric_Master2_0_BIF_1_HWDATA[1]\, HWDATA(0) => 
        \Fabric_Master2_0_BIF_1_HWDATA[0]\, HADDR(31) => 
        \Fabric_Master2_0_BIF_1_HADDR[31]\, HADDR(30) => 
        \Fabric_Master2_0_BIF_1_HADDR[30]\, HADDR(29) => 
        \Fabric_Master2_0_BIF_1_HADDR[29]\, HADDR(28) => 
        \Fabric_Master2_0_BIF_1_HADDR[28]\, HADDR(27) => 
        \Fabric_Master2_0_BIF_1_HADDR[27]\, HADDR(26) => 
        \Fabric_Master2_0_BIF_1_HADDR[26]\, HADDR(25) => 
        \Fabric_Master2_0_BIF_1_HADDR[25]\, HADDR(24) => 
        \Fabric_Master2_0_BIF_1_HADDR[24]\, HADDR(23) => 
        \Fabric_Master2_0_BIF_1_HADDR[23]\, HADDR(22) => 
        \Fabric_Master2_0_BIF_1_HADDR[22]\, HADDR(21) => 
        \Fabric_Master2_0_BIF_1_HADDR[21]\, HADDR(20) => 
        \Fabric_Master2_0_BIF_1_HADDR[20]\, HADDR(19) => 
        \Fabric_Master2_0_BIF_1_HADDR[19]\, HADDR(18) => 
        \Fabric_Master2_0_BIF_1_HADDR[18]\, HADDR(17) => 
        \Fabric_Master2_0_BIF_1_HADDR[17]\, HADDR(16) => 
        \Fabric_Master2_0_BIF_1_HADDR[16]\, HADDR(15) => 
        \Fabric_Master2_0_BIF_1_HADDR[15]\, HADDR(14) => 
        \Fabric_Master2_0_BIF_1_HADDR[14]\, HADDR(13) => 
        \Fabric_Master2_0_BIF_1_HADDR[13]\, HADDR(12) => 
        \Fabric_Master2_0_BIF_1_HADDR[12]\, HADDR(11) => 
        \Fabric_Master2_0_BIF_1_HADDR[11]\, HADDR(10) => 
        \Fabric_Master2_0_BIF_1_HADDR[10]\, HADDR(9) => 
        \Fabric_Master2_0_BIF_1_HADDR[9]\, HADDR(8) => 
        \Fabric_Master2_0_BIF_1_HADDR[8]\, HADDR(7) => 
        \Fabric_Master2_0_BIF_1_HADDR[7]\, HADDR(6) => 
        \Fabric_Master2_0_BIF_1_HADDR[6]\, HADDR(5) => 
        \Fabric_Master2_0_BIF_1_HADDR[5]\, HADDR(4) => 
        \Fabric_Master2_0_BIF_1_HADDR[4]\, HADDR(3) => 
        \Fabric_Master2_0_BIF_1_HADDR[3]\, HADDR(2) => 
        \Fabric_Master2_0_BIF_1_HADDR[2]\, HADDR(1) => 
        \Fabric_Master2_0_BIF_1_HADDR[1]\, HADDR(0) => 
        \Fabric_Master2_0_BIF_1_HADDR[0]\, HRDATA(31) => 
        GND_net_1, HRDATA(30) => GND_net_1, HRDATA(29) => 
        GND_net_1, HRDATA(28) => GND_net_1, HRDATA(27) => 
        GND_net_1, HRDATA(26) => GND_net_1, HRDATA(25) => 
        GND_net_1, HRDATA(24) => GND_net_1, HRDATA(23) => 
        GND_net_1, HRDATA(22) => GND_net_1, HRDATA(21) => 
        GND_net_1, HRDATA(20) => GND_net_1, HRDATA(19) => 
        GND_net_1, HRDATA(18) => GND_net_1, HRDATA(17) => 
        GND_net_1, HRDATA(16) => GND_net_1, HRDATA(15) => 
        GND_net_1, HRDATA(14) => GND_net_1, HRDATA(13) => 
        GND_net_1, HRDATA(12) => GND_net_1, HRDATA(11) => 
        GND_net_1, HRDATA(10) => GND_net_1, HRDATA(9) => 
        GND_net_1, HRDATA(8) => GND_net_1, HRDATA(7) => GND_net_1, 
        HRDATA(6) => GND_net_1, HRDATA(5) => GND_net_1, HRDATA(4)
         => GND_net_1, HRDATA(3) => GND_net_1, HRDATA(2) => 
        GND_net_1, HRDATA(1) => GND_net_1, HRDATA(0) => GND_net_1, 
        RESET_N => AHB_Bus_Matrix_sb_0_MSS_READY, HCLK => 
        AHB_Bus_Matrix_sb_0_FIC_1_CLK, HWRITE => 
        Fabric_Master2_0_BIF_1_HWRITE, HMASTLOCK => OPEN, HREADY
         => OPEN, HSEL => Fabric_Master2_0_BIF_1_HSELx, HREADYOUT
         => Fabric_Master2_0_BIF_1_HREADYOUT, HRESP => GND_net_1, 
        INT2 => Fabric_Master2_0_INT2, MASTER2_START => 
        AHB_Bus_Matrix_sb_0_GPIO_0_M2F, MASTER2_STOP => 
        AHB_Bus_Matrix_sb_0_GPIO_2_M2F);
    

end DEF_ARCH; 
