`

    #Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
    #install: C:\Microsemi\Libero_SoC_v11.7\Synplify
    #OS: Windows 7 6.1
    #Hostname: W764-ONTEDDHUS1

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : AHB_Bus_Matrix.vhd(17) | Top entity is set to AHB_Bus_Matrix.
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\CCC_0\AHB_Bus_Matrix_sb_CCC_0_FCCC.vhd changed - recompiling
    File C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS_syn.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp_pcie_hotreset.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master1.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master2.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\FABOSC_0\AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\AHB_Bus_Matrix_sb.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix\AHB_Bus_Matrix.vhd changed - recompiling
    VHDL syntax check successful!
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\CCC_0\AHB_Bus_Matrix_sb_CCC_0_FCCC.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS_syn.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\FABOSC_0\AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\AHB_Bus_Matrix_sb.vhd changed - recompiling
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix\AHB_Bus_Matrix.vhd changed - recompiling
    @N:CD630 : AHB_Bus_Matrix.vhd(17) | Synthesizing work.ahb_bus_matrix.rtl
    @N:CD630 : Fabric_Master2.vhd(28) | Synthesizing work.fabric_master2.fabric_master2
    @N:CD231 : Fabric_Master2.vhd(59) | Using onehot encoding for type ahb_master_states (idle="1000000")
    @W:CG296 : Fabric_Master2.vhd(171) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : Fabric_Master2.vhd(177) | Referenced variable ahb_states is not in sensitivity list
    @W:CD638 : Fabric_Master2.vhd(74) | Signal hready_int is undriven
    @W:CD638 : Fabric_Master2.vhd(88) | Signal cout_clear is undriven
    Post processing for work.fabric_master2.fabric_master2
    @W:CL169 : Fabric_Master2.vhd(106) | Pruning register HREADY_Int1_2
    @A:CL282 : Fabric_Master2.vhd(233) | Feedback mux created for signal HSEL -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @N:CD630 : Fabric_Master1.vhd(27) | Synthesizing work.fabric_master1.fabric_master1
    @N:CD231 : Fabric_Master1.vhd(56) | Using onehot encoding for type ahb_master_states (idle="1000000")
    @W:CG296 : Fabric_Master1.vhd(161) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : Fabric_Master1.vhd(167) | Referenced variable ahb_states is not in sensitivity list
    Post processing for work.fabric_master1.fabric_master1
    @W:CL169 : Fabric_Master1.vhd(100) | Pruning register HREADY_Int1_2
    @A:CL282 : Fabric_Master1.vhd(223) | Feedback mux created for signal HSEL -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @N:CD630 : smartfusion2.vhd(191) | Synthesizing smartfusion2.and2.syn_black_box
    Post processing for smartfusion2.and2.syn_black_box
    @N:CD630 : AHB_Bus_Matrix_sb.vhd(17) | Synthesizing work.ahb_bus_matrix_sb.rtl
    @N:CD630 : smartfusion2.vhd(786) | Synthesizing smartfusion2.sysreset.syn_black_box
    Post processing for smartfusion2.sysreset.syn_black_box
    @N:CD630 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(8) | Synthesizing work.ahb_bus_matrix_sb_fabosc_0_osc.def_arch
    @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box
    Post processing for smartfusion2.clkint.syn_black_box
    @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch
    Post processing for work.rcosc_25_50mhz.def_arch
    @N:CD630 : osc_comps.vhd(79) | Synthesizing work.rcosc_25_50mhz_fab.def_arch
    Post processing for work.rcosc_25_50mhz_fab.def_arch
    Post processing for work.ahb_bus_matrix_sb_fabosc_0_osc.def_arch
    @W:CL240 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @N:CD630 : coreresetp.vhd(27) | Synthesizing work.coreresetp.rtl
    @W:CD434 : coreresetp.vhd(477) | Signal soft_ext_reset_out in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(478) | Signal soft_reset_f2m in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(479) | Signal soft_m3_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(480) | Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(481) | Signal soft_fddr_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(482) | Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(483) | Signal soft_sdif0_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(484) | Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(485) | Signal soft_sdif1_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(486) | Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(487) | Signal soft_sdif2_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(488) | Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(489) | Signal soft_sdif3_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(490) | Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(491) | Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process
    Post processing for work.coreresetp.rtl
    @W:CL169 : coreresetp.vhd(1519) | Pruning register count_ddr_2(13 downto 0)
    @W:CL169 : coreresetp.vhd(1495) | Pruning register count_sdif3_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1471) | Pruning register count_sdif2_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1447) | Pruning register count_sdif1_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1423) | Pruning register count_sdif0_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_q1_2
    @W:CL169 : coreresetp.vhd(1311) | Pruning register count_sdif3_enable_3
    @W:CL169 : coreresetp.vhd(1252) | Pruning register count_sdif2_enable_3
    @W:CL169 : coreresetp.vhd(1193) | Pruning register count_sdif1_enable_3
    @W:CL169 : coreresetp.vhd(1134) | Pruning register count_sdif0_enable_3
    @W:CL169 : coreresetp.vhd(1059) | Pruning register count_ddr_enable_3
    @N:CL177 : coreresetp.vhd(1331) | Sharing sequential element M3_RESET_N_int.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q1.
    @W:CL190 : coreresetp.vhd(1376) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.vhd(1059) | Pruning register release_ext_reset
    @W:CL169 : coreresetp.vhd(1376) | Pruning register EXT_RESET_OUT_int
    @W:CL169 : coreresetp.vhd(1376) | Pruning register sm2_state(2 downto 0)
    @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_q1
    @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_clk_base
    @N:CD630 : AHB_Bus_Matrix_sb_CCC_0_FCCC.vhd(8) | Synthesizing work.ahb_bus_matrix_sb_ccc_0_fccc.def_arch
    @N:CD630 : smartfusion2.vhd(794) | Synthesizing smartfusion2.ccc.syn_black_box
    Post processing for smartfusion2.ccc.syn_black_box
    @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    Post processing for work.ahb_bus_matrix_sb_ccc_0_fccc.def_arch
    @N:CD630 : AHB_Bus_Matrix_sb_MSS.vhd(17) | Synthesizing work.ahb_bus_matrix_sb_mss.rtl
    @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box
    Post processing for smartfusion2.inbuf.syn_black_box
    @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box
    Post processing for smartfusion2.tribuff.syn_black_box
    @N:CD630 : AHB_Bus_Matrix_sb_MSS_syn.vhd(10) | Synthesizing work.mss_120.def_arch
    Post processing for work.mss_120.def_arch
    Post processing for work.ahb_bus_matrix_sb_mss.rtl
    Post processing for work.ahb_bus_matrix_sb.rtl
    Post processing for work.ahb_bus_matrix.rtl
    @W:CL247 : AHB_Bus_Matrix_sb_MSS.vhd(26) | Input port bit 0 of fic_0_ahb_s_htrans(1 downto 0) is unused
    @W:CL247 : AHB_Bus_Matrix_sb_MSS.vhd(34) | Input port bit 0 of fic_1_ahb_s_htrans(1 downto 0) is unused
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q2.
    @N:CL201 : coreresetp.vhd(1311) | Trying to extract state machine for register sdif3_state
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1252) | Trying to extract state machine for register sdif2_state
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1193) | Trying to extract state machine for register sdif1_state
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1134) | Trying to extract state machine for register sdif0_state
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1059) | Trying to extract state machine for register sm0_state
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : coreresetp.vhd(96) | Input CLK_LTSSM is unused
    @W:CL159 : coreresetp.vhd(123) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(126) | Input SDIF0_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(135) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(139) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(143) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(157) | Input SDIF0_PSEL is unused
    @W:CL159 : coreresetp.vhd(158) | Input SDIF0_PWRITE is unused
    @W:CL159 : coreresetp.vhd(159) | Input SDIF0_PRDATA is unused
    @W:CL159 : coreresetp.vhd(160) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.vhd(161) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.vhd(162) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.vhd(163) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.vhd(164) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.vhd(165) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.vhd(166) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.vhd(167) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.vhd(168) | Input SDIF3_PRDATA is unused
    @W:CL159 : coreresetp.vhd(174) | Input SOFT_EXT_RESET_OUT is unused
    @W:CL159 : coreresetp.vhd(175) | Input SOFT_RESET_F2M is unused
    @W:CL159 : coreresetp.vhd(176) | Input SOFT_M3_RESET is unused
    @W:CL159 : coreresetp.vhd(177) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(178) | Input SOFT_FDDR_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(179) | Input SOFT_SDIF0_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(180) | Input SOFT_SDIF0_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(181) | Input SOFT_SDIF1_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(182) | Input SOFT_SDIF1_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(183) | Input SOFT_SDIF2_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(184) | Input SOFT_SDIF2_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(185) | Input SOFT_SDIF3_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(186) | Input SOFT_SDIF3_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(190) | Input SOFT_SDIF0_0_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(191) | Input SOFT_SDIF0_1_CORE_RESET is unused
    @W:CL159 : AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd(10) | Input XTL is unused
    @W:CL159 : Fabric_Master1.vhd(40) | Input HRESP is unused
    @W:CL159 : Fabric_Master1.vhd(41) | Input HRDATA is unused
    @W:CL159 : Fabric_Master2.vhd(41) | Input HRESP is unused
    @W:CL159 : Fabric_Master2.vhd(42) | Input HRDATA is unused

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 87MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 17 10:28:22 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 17 10:28:23 2016

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 17 10:28:23 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    File D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\synthesis\synwork\AHB_Bus_Matrix_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 17 10:28:24 2016

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: AHB_Bus_Matrix_scck.rpt
    Printing clock  summary report in "D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\synthesis\AHB_Bus_Matrix_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 108MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)

    @W:BN132 : coreresetp.vhd(1059) | Removing sequential instance AHB_Bus_Matrix_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance AHB_Bus_Matrix_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance sm0_state[0:6] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1495) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1471) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1447) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1423) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1519) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    syn_allowed_resources : blockrams=236  set on top level netlist AHB_Bus_Matrix

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)

    @S |Clock Summary
    *****************

    Start                                                   Requested     Requested     Clock        Clock
    Clock                                                   Frequency     Period        Type         Group
    --------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    System                                                  100.0 MHz     10.000        system       system_clkgroup
    ====================================================================================================================

    @W:MT530 : fabric_master2.vhd(233) | Found inferred clock AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 179 sequential elements including Fabric_Master2_0.HADDR_TEMP[31:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : ahb_bus_matrix_sb_mss.vhd(939) | Found inferred clock AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 191 sequential elements including AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\synthesis\AHB_Bus_Matrix.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 17 10:28:25 2016

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @W:MO129 : coreresetp.vhd(781) | Sequential instance AHB_Bus_Matrix_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @W:MO129 : coreresetp.vhd(781) | Sequential instance AHB_Bus_Matrix_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO129 : coreresetp.vhd(1331) | Sequential instance AHB_Bus_Matrix_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @N: : fabric_master1.vhd(223) | Found counter in view:work.Fabric_Master1(fabric_master1) inst HWRITE_DATA_TEMP[31:0]
    @N: : fabric_master1.vhd(163) | Found counter in view:work.Fabric_Master1(fabric_master1) inst Recount[31:0]
    @N: : fabric_master1.vhd(223) | Found counter in view:work.Fabric_Master1(fabric_master1) inst clock_count[31:0]
    @N: : fabric_master1.vhd(144) | Found counter in view:work.Fabric_Master1(fabric_master1) inst count_Temp1[31:0]
    @N:FX404 : fabric_master1.vhd(235) | Found addmux in view:work.Fabric_Master1(fabric_master1) inst HADDR_TEMP_7[31:0] from un1_HADDR_TEMP[31:0]
    @N:BN362 : fabric_master1.vhd(223) | Removing sequential instance HTRANS[0] of view:PrimLib.dffr(prim) in hierarchy view:work.Fabric_Master1(fabric_master1) because there are no references to its outputs
    @N: : fabric_master2.vhd(233) | Found counter in view:work.Fabric_Master2(fabric_master2) inst HWRITE_DATA_TEMP[31:0]
    @N: : fabric_master2.vhd(173) | Found counter in view:work.Fabric_Master2(fabric_master2) inst Recount[31:0]
    @N: : fabric_master2.vhd(233) | Found counter in view:work.Fabric_Master2(fabric_master2) inst clock_count[31:0]
    @N: : fabric_master2.vhd(153) | Found counter in view:work.Fabric_Master2(fabric_master2) inst count_Temp1[31:0]
    @N:FX404 : fabric_master2.vhd(245) | Found addmux in view:work.Fabric_Master2(fabric_master2) inst HADDR_TEMP_6[31:0] from un1_HADDR_TEMP[31:0]
    @N:BN362 : fabric_master2.vhd(233) | Removing sequential instance HTRANS[0] of view:PrimLib.dffr(prim) in hierarchy view:work.Fabric_Master2(fabric_master2) because there are no references to its outputs
    @A:BN291 : fabric_master2.vhd(233) | Boundary register HTRANS[0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		     0.16ns		 674 /       365
       2		0h:00m:00s		     0.16ns		 669 /       365
    @N:FP130 :  | Promoting Net AHB_Bus_Matrix_sb_0_MSS_READY on CLKINT  I_1
    @N:FP130 :  | Promoting Net un1_reset_n_2_i on CLKINT  I_134
    @N:FP130 :  | Promoting Net un1_reset_n_2_i on CLKINT  I_138

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 151MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 151MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    2 non-gated/non-generated clock tree(s) driving 366 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ===================================================== Non-Gated/Non-Generated Clocks =====================================================
    Clock Tree ID     Driving Element                        Drive Element Type     Fanout     Sample Instance
    ------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        AHB_Bus_Matrix_sb_0.CCC_0.GL0_INST     CLKINT                 188        AHB_Bus_Matrix_sb_0.CORERESETP_0.RESET_N_M2F_q1
    ClockId0002        AHB_Bus_Matrix_sb_0.CCC_0.GL1_INST     CLKINT                 178        Fabric_Master2_0.ahb_states[0]
    ==========================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 121MB peak: 151MB)

    Writing Analyst data base D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\synthesis\synwork\AHB_Bus_Matrix_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 151MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    J-2015.03M-SP1-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 151MB)

    @W:MT246 : ahb_bus_matrix_sb_ccc_0_fccc.vhd(110) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:AHB_Bus_Matrix_sb_0.CCC_0.GL0_net"

    @W:MT420 :  | Found inferred clock AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:AHB_Bus_Matrix_sb_0.CCC_0.GL1_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Feb 17 10:28:27 2016
    #

    Top view:               AHB_Bus_Matrix
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 1.080

                                                            Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                          Frequency     Frequency     Period        Period        Slack     Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     112.1 MHz     10.000        8.920         1.080     inferred     Inferred_clkgroup_1
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     100.0 MHz     147.8 MHz     10.000        6.766         3.234     inferred     Inferred_clkgroup_0
    System                                                  100.0 MHz     895.2 MHz     10.000        1.117         8.883     system       system_clkgroup
    ==========================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                             Ending                                               |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                               System                                               |  10.000      8.883  |  No paths    -      |  No paths    -      |  No paths    -
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock  AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  10.000      3.234  |  No paths    -      |  No paths    -      |  No paths    -
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock  AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock  AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock  AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.080  |  No paths    -      |  No paths    -      |  No paths    -
    ================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                   Starting                                                                                                                             Arrival
    Instance                                                       Reference                                               Type        Pin                         Net                                  Time        Slack
                                                                   Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_120     F_FM0_READYOUT              Fabric_Master1_0_BIF_1_HREADYOUT     4.776       1.080
    AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_120     CAN_TXBUS_MGPIO2A_H2F_B     AHB_Bus_Matrix_sb_0_GPIO_2_M2F       3.470       2.547
    AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_120     I2C1_SDA_MGPIO0A_H2F_B      AHB_Bus_Matrix_sb_0_GPIO_0_M2F       3.522       3.267
    Fabric_Master1_0.ahb_states[3]                                 AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           ahb_states[3]                        0.087       3.312
    Fabric_Master1_0.clock_count[12]                               AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           clock_count[12]                      0.087       3.699
    Fabric_Master1_0.ahb_states[1]                                 AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           ahb_states[1]                        0.087       3.709
    Fabric_Master1_0.clock_count[24]                               AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           clock_count[24]                      0.087       3.777
    Fabric_Master1_0.clock_count[7]                                AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           clock_count[7]                       0.087       3.797
    Fabric_Master1_0.clock_count[13]                               AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           clock_count[13]                      0.087       3.800
    Fabric_Master1_0.ahb_states[2]                                 AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                           ahb_states[2]                        0.087       3.810
    =====================================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                             Starting                                                                                       Required
    Instance                                 Reference                                               Type     Pin     Net                   Time         Slack
                                             Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------
    Fabric_Master1_0.HWRITE_DATA_TEMP[0]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[1]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[2]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[3]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[4]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[5]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[6]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[7]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[8]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    Fabric_Master1_0.HWRITE_DATA_TEMP[9]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_htrans6_4_i_0     9.662        1.080
    ==========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.338
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.662

        - Propagation time:                      8.583
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     1.080

        Number of logic level(s):                2
        Starting point:                          AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST / F_FM0_READYOUT
        Ending point:                            Fabric_Master1_0.HWRITE_DATA_TEMP[0] / EN
        The start point is clocked by            AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            AHB_Bus_Matrix_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

    Instance / Net                                                             Pin                Pin               Arrival     No. of
    Name                                                           Type        Name               Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_0.AHB_Bus_Matrix_sb_MSS_0.MSS_ADLIB_INST     MSS_120     F_FM0_READYOUT     Out     4.776     4.776       -
    Fabric_Master1_0_BIF_1_HREADYOUT                               Net         -                  -       1.149     -           45
    Fabric_Master1_0.HREADY_flngedge                               CFG2        A                  In      -         5.925       -
    Fabric_Master1_0.HREADY_flngedge                               CFG2        Y                  Out     0.100     6.026       -
    HREADY_flngedge                                                Net         -                  -       1.067     -           35
    Fabric_Master1_0.un1_htrans6_4_1_RNIB5F61                      CFG4        D                  In      -         7.093       -
    Fabric_Master1_0.un1_htrans6_4_1_RNIB5F61                      CFG4        Y                  Out     0.288     7.381       -
    un1_htrans6_4_i_0                                              Net         -                  -       1.202     -           32
    Fabric_Master1_0.HWRITE_DATA_TEMP[0]                           SLE         EN                 In      -         8.583       -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 8.920 is 5.502(61.7%) logic and 3.419(38.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                                                                     Arrival
    Instance                             Reference                                               Type     Pin     Net                 Time        Slack
                                         Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    Fabric_Master2_0.ahb_states[2]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       ahb_states[2]       0.108       3.234
    Fabric_Master2_0.ahb_states[1]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       ahb_states[1]       0.108       3.350
    Fabric_Master2_0.ahb_states[0]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       ahb_states[0]       0.108       3.639
    Fabric_Master2_0.ahb_states[4]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       clock_count         0.108       3.740
    Fabric_Master2_0.ahb_states[5]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       ahb_states[5]       0.108       3.750
    Fabric_Master2_0.ahb_states[3]       AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       ahb_states[3]       0.108       3.983
    Fabric_Master2_0.HREADY_Int0         AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       HREADY_Int0         0.108       4.155
    Fabric_Master2_0.clock_count[28]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       clock_count[28]     0.087       4.177
    Fabric_Master2_0.clock_count[24]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       clock_count[24]     0.087       4.255
    Fabric_Master2_0.clock_count[0]      AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       clock_count[0]      0.087       4.275
    ===================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                        Starting                                                                                      Required
    Instance                            Reference                                               Type     Pin     Net                  Time         Slack
                                        Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    Fabric_Master2_0.HADDR_TEMP[31]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[31]     9.745        3.234
    Fabric_Master2_0.HADDR_TEMP[30]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[30]     9.745        3.250
    Fabric_Master2_0.HADDR_TEMP[29]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[29]     9.745        3.266
    Fabric_Master2_0.HADDR_TEMP[28]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[28]     9.745        3.283
    Fabric_Master2_0.HADDR_TEMP[27]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[27]     9.745        3.299
    Fabric_Master2_0.HADDR_TEMP[26]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[26]     9.745        3.315
    Fabric_Master2_0.HADDR_TEMP[25]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[25]     9.745        3.332
    Fabric_Master2_0.HADDR_TEMP[24]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[24]     9.745        3.348
    Fabric_Master2_0.HADDR_TEMP[23]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[23]     9.745        3.364
    Fabric_Master2_0.HADDR_TEMP[22]     AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       HADDR_TEMP_6[22]     9.745        3.380
    ====================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.745

        - Propagation time:                      6.511
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 3.234

        Number of logic level(s):                33
        Starting point:                          Fabric_Master2_0.ahb_states[2] / Q
        Ending point:                            Fabric_Master2_0.HADDR_TEMP[31] / D
        The start point is clocked by            AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK
        The end   point is clocked by            AHB_Bus_Matrix_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                         Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    Fabric_Master2_0.ahb_states[2]               SLE      Q        Out     0.108     0.108       -
    ahb_states[2]                                Net      -        -       1.651     -           41
    Fabric_Master2_0.htrans9_1                   CFG4     D        In      -         1.760       -
    Fabric_Master2_0.htrans9_1                   CFG4     Y        Out     0.317     2.077       -
    htrans9_1                                    Net      -        -       0.630     -           2
    Fabric_Master2_0.HADDR_TEMP_1_sqmuxa_1_d     CFG4     D        In      -         2.707       -
    Fabric_Master2_0.HADDR_TEMP_1_sqmuxa_1_d     CFG4     Y        Out     0.271     2.978       -
    HADDR_TEMP_1_sqmuxa_1_d                      Net      -        -       0.556     -           1
    Fabric_Master2_0.un1_htrans6_6_3             CFG4     D        In      -         3.534       -
    Fabric_Master2_0.un1_htrans6_6_3             CFG4     Y        Out     0.271     3.805       -
    un1_htrans6_6_3                              Net      -        -       0.556     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_2_0        ARI1     D        In      -         4.361       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_2_0        ARI1     FCO      Out     0.503     4.864       -
    HADDR_TEMP_6_cry_2                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_3          ARI1     FCI      In      -         4.864       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_3          ARI1     FCO      Out     0.016     4.881       -
    HADDR_TEMP_6_cry_3                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_4          ARI1     FCI      In      -         4.881       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_4          ARI1     FCO      Out     0.016     4.897       -
    HADDR_TEMP_6_cry_4                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_5          ARI1     FCI      In      -         4.897       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_5          ARI1     FCO      Out     0.016     4.913       -
    HADDR_TEMP_6_cry_5                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_6          ARI1     FCI      In      -         4.913       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_6          ARI1     FCO      Out     0.016     4.930       -
    HADDR_TEMP_6_cry_6                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_7          ARI1     FCI      In      -         4.930       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_7          ARI1     FCO      Out     0.016     4.946       -
    HADDR_TEMP_6_cry_7                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_8          ARI1     FCI      In      -         4.946       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_8          ARI1     FCO      Out     0.016     4.962       -
    HADDR_TEMP_6_cry_8                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_9          ARI1     FCI      In      -         4.962       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_9          ARI1     FCO      Out     0.016     4.979       -
    HADDR_TEMP_6_cry_9                           Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_10         ARI1     FCI      In      -         4.979       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_10         ARI1     FCO      Out     0.016     4.995       -
    HADDR_TEMP_6_cry_10                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_11         ARI1     FCI      In      -         4.995       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_11         ARI1     FCO      Out     0.016     5.011       -
    HADDR_TEMP_6_cry_11                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_12         ARI1     FCI      In      -         5.011       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_12         ARI1     FCO      Out     0.016     5.027       -
    HADDR_TEMP_6_cry_12                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_13         ARI1     FCI      In      -         5.027       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_13         ARI1     FCO      Out     0.016     5.044       -
    HADDR_TEMP_6_cry_13                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_14         ARI1     FCI      In      -         5.044       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_14         ARI1     FCO      Out     0.016     5.060       -
    HADDR_TEMP_6_cry_14                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_15         ARI1     FCI      In      -         5.060       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_15         ARI1     FCO      Out     0.016     5.076       -
    HADDR_TEMP_6_cry_15                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_16         ARI1     FCI      In      -         5.076       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_16         ARI1     FCO      Out     0.016     5.093       -
    HADDR_TEMP_6_cry_16                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_17         ARI1     FCI      In      -         5.093       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_17         ARI1     FCO      Out     0.016     5.109       -
    HADDR_TEMP_6_cry_17                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_18         ARI1     FCI      In      -         5.109       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_18         ARI1     FCO      Out     0.016     5.125       -
    HADDR_TEMP_6_cry_18                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_19         ARI1     FCI      In      -         5.125       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_19         ARI1     FCO      Out     0.016     5.142       -
    HADDR_TEMP_6_cry_19                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_20         ARI1     FCI      In      -         5.142       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_20         ARI1     FCO      Out     0.016     5.158       -
    HADDR_TEMP_6_cry_20                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_21         ARI1     FCI      In      -         5.158       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_21         ARI1     FCO      Out     0.016     5.174       -
    HADDR_TEMP_6_cry_21                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_22         ARI1     FCI      In      -         5.174       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_22         ARI1     FCO      Out     0.016     5.191       -
    HADDR_TEMP_6_cry_22                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_23         ARI1     FCI      In      -         5.191       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_23         ARI1     FCO      Out     0.016     5.207       -
    HADDR_TEMP_6_cry_23                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_24         ARI1     FCI      In      -         5.207       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_24         ARI1     FCO      Out     0.016     5.223       -
    HADDR_TEMP_6_cry_24                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_25         ARI1     FCI      In      -         5.223       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_25         ARI1     FCO      Out     0.016     5.239       -
    HADDR_TEMP_6_cry_25                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_26         ARI1     FCI      In      -         5.239       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_26         ARI1     FCO      Out     0.016     5.256       -
    HADDR_TEMP_6_cry_26                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_27         ARI1     FCI      In      -         5.256       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_27         ARI1     FCO      Out     0.016     5.272       -
    HADDR_TEMP_6_cry_27                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_28         ARI1     FCI      In      -         5.272       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_28         ARI1     FCO      Out     0.016     5.288       -
    HADDR_TEMP_6_cry_28                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_29         ARI1     FCI      In      -         5.288       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_29         ARI1     FCO      Out     0.016     5.305       -
    HADDR_TEMP_6_cry_29                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_cry_30         ARI1     FCI      In      -         5.305       -
    Fabric_Master2_0.HADDR_TEMP_6_cry_30         ARI1     FCO      Out     0.016     5.321       -
    HADDR_TEMP_6_cry_30                          Net      -        -       0.000     -           1
    Fabric_Master2_0.HADDR_TEMP_6_s_31           ARI1     FCI      In      -         5.321       -
    Fabric_Master2_0.HADDR_TEMP_6_s_31           ARI1     S        Out     0.073     5.394       -
    HADDR_TEMP_6[31]                             Net      -        -       1.117     -           1
    Fabric_Master2_0.HADDR_TEMP[31]              SLE      D        In      -         6.511       -
    =======================================================================================================
    Total path delay (propagation time + setup) of 6.766 is 2.257(33.4%) logic and 4.510(66.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                      Starting                                                                                           Arrival
    Instance                                          Reference     Type               Pin        Net                                                    Time        Slack
                                                      Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       8.883
    ======================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                           Starting                                                                                         Required
    Instance                               Reference     Type     Pin                Net                                                    Time         Slack
                                           Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_0.CCC_0.CCC_INST     System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       8.883
    ==========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         10.000

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 8.883

        Number of logic level(s):                0
        Starting point:                          AHB_Bus_Matrix_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
        Ending point:                            AHB_Bus_Matrix_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                            Pin                Pin               Arrival     No. of
    Name                                                   Type               Name               Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------
    AHB_Bus_Matrix_sb_0.FABOSC_0.I_RCOSC_25_50MHZ          RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -
    FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       1.117     -           1
    AHB_Bus_Matrix_sb_0.CCC_0.CCC_INST                     CCC                RCOSC_25_50MHZ     In      -         1.117       -
    =====================================================================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 151MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 151MB)

    ---------------------------------------
    Resource Usage Report for AHB_Bus_Matrix

    Mapping to part: m2s150tfc1152std
    Cell usage:
    AND2            1 use
    CCC             1 use
    CLKINT          5 uses
    MSS_120         1 use
    RCOSC_25_50MHZ  1 use
    SYSRESET        1 use
    CFG1           2 uses
    CFG2           53 uses
    CFG3           25 uses
    CFG4           263 uses

    Carry primitives used for arithmetic functions:
    ARI1           320 uses

    Sequential Cells:
    SLE            365 uses

    DSP Blocks:    0

    I/O ports: 3
    I/O primitives: 2
    INBUF          1 use
    TRIBUFF        1 use

    Global Clock Buffers: 5

    Total LUTs:    663

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  365 + 0 + 0 + 0 = 365;
    Total number of LUTs after P&R:  663 + 0 + 0 + 0 = 663;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 51MB peak: 151MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Wed Feb 17 10:28:27 2016

    ###########################################################]

`