@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix\AHB_Bus_Matrix.vhd":17:7:17:20|Top entity is set to AHB_Bus_Matrix.
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix\AHB_Bus_Matrix.vhd":17:7:17:20|Synthesizing work.ahb_bus_matrix.rtl 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master2.vhd":28:7:28:20|Synthesizing work.fabric_master2.fabric_master2 
@N: CD231 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master2.vhd":59:23:59:24|Using onehot encoding for type ahb_master_states (idle="1000000")
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master1.vhd":27:7:27:20|Synthesizing work.fabric_master1.fabric_master1 
@N: CD231 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\hdl\Fabric_Master1.vhd":56:23:56:24|Using onehot encoding for type ahb_master_states (idle="1000000")
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":191:10:191:13|Synthesizing smartfusion2.and2.syn_black_box 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\AHB_Bus_Matrix_sb.vhd":17:7:17:23|Synthesizing work.ahb_bus_matrix_sb.rtl 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":786:10:786:17|Synthesizing smartfusion2.sysreset.syn_black_box 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\FABOSC_0\AHB_Bus_Matrix_sb_FABOSC_0_OSC.vhd":8:7:8:36|Synthesizing work.ahb_bus_matrix_sb_fabosc_0_osc.def_arch 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":79:7:79:24|Synthesizing work.rcosc_25_50mhz_fab.def_arch 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":27:7:27:16|Synthesizing work.coreresetp.rtl 
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q1.
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb\CCC_0\AHB_Bus_Matrix_sb_CCC_0_FCCC.vhd":8:7:8:34|Synthesizing work.ahb_bus_matrix_sb_ccc_0_fccc.def_arch 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":794:10:794:12|Synthesizing smartfusion2.ccc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS.vhd":17:7:17:27|Synthesizing work.ahb_bus_matrix_sb_mss.rtl 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":403:10:403:14|Synthesizing smartfusion2.inbuf.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":423:10:423:16|Synthesizing smartfusion2.tribuff.syn_black_box 
@N: CD630 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\work\AHB_Bus_Matrix_sb_MSS\AHB_Bus_Matrix_sb_MSS_syn.vhd":10:7:10:13|Synthesizing work.mss_120.def_arch 
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q2.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL201 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\Libero11.7\AC388\M2S_AC388_DF\AHB_Bus_Matrix\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Trying to extract state machine for register sm0_state
@N|Running in 64-bit mode

