#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-KUMARJ #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v" @I:"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\define.h" @I::"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v" Verilog syntax check successful! Selecting top level module ddc @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000100000 out_width=32'b00000000000000000000000000100001 datatype=48'b011101010110111001110011011010010110011101101110 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000100000 Generated name = synBusAdapter_32s_33s_unsign_0s_0s_0s_0s_0s_SS_32s @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000001100 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000001101 outfrac=32'b00000000000000000000000000001010 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010001 Generated name = synBusAdapter_17s_12s_signed_0s_13s_10s_5s_0s_SS_17s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000001100 infrac=32'b00000000000000000000000000001101 outfrac=32'b00000000000000000000000000001010 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000100 outputIntWidth=32'b00000000000000000000000000000010 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000011111 shiftLeftAmount=32'b11111111111111111111111111111101 ShiftOutputWidth=32'b00000000000000000000000000011100 Generated name = synBusSatRnd_Z1 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000100000 out_width=32'b00000000000000000000000000001100 datatype=48'b011101010110111001110011011010010110011101101110 preshift=32'b00000000000000000000000000010100 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000110100 Generated name = synBusAdapter_32s_12s_unsign_20s_0s_0s_0s_0s_SS_52s @W:CG107 : SynLib.v(161) | Extending unsized constant with leading x/z beyond 32 bits @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000010001 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_17s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000010001 Generated name = singleDelayWithEnableGeneric_17s @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000001100 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_12s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000001100 Generated name = singleDelayWithEnableGeneric_12s @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000001100 out_width=32'b00000000000000000000000000001101 datatype=48'b011101010110111001110011011010010110011101101110 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000001100 Generated name = synBusAdapter_12s_13s_unsign_0s_0s_0s_0s_0s_SS_12s @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000001101 out_width=32'b00000000000000000000000000001110 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b11111111111111111111111111111111 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000001110 Generated name = synBusAdapter_13s_14s_signed_4294967295s_0s_0s_0s_0s_SS_14s_Z2 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000001110 out_width=32'b00000000000000000000000000001101 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000001110 Generated name = synBusAdapter_14s_13s_signed_0s_0s_0s_0s_0s_SS_14s @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010010 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010010 Generated name = synBusAdapter_18s_17s_signed_0s_0s_0s_0s_0s_SS_18s @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000000001 delaylength=32'b00000000000000000000000000001010 Generated name = synDelayWithEnable_1s_1s_10s @N:CG364 : SynLib.v(621) | Synthesizing module synDelayWithEnableGeneric preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000000001 delaylength=32'b00000000000000000000000000001010 decompRegs=32'b00000000000000000000000000000010 decompThresholdMin=32'b00000000000000000000000000001001 ramThreshold=32'b00000000000000000000000001000100 forceRAMThreshold=32'b00000000000000000000111110100000 cntWidth=32'b00000000000000000000000000000100 decompThresholdBW=32'b00000000000000000000000001000100 delayNRLen=32'b00000000000000000000000000000110 resetType=48'b011000010111001101111001011011100110001101101000 Generated name = synDelayWithEnableGeneric_Z3 @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_0_ @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_1_ @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_2_ @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_3_ @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_4_ @W:CG133 : SynLib.v(643) | No assignment to delayLineClip_5_ @W:CG133 : SynLib.v(644) | No assignment to regsL_0_ @W:CG133 : SynLib.v(644) | No assignment to regsL_1_ @W:CG133 : SynLib.v(645) | No assignment to regsR_0_ @W:CG133 : SynLib.v(645) | No assignment to regsR_1_ @W:CG133 : SynLib.v(646) | No assignment to cnt @W:CG133 : SynLib.v(647) | No assignment to resetExpired @W:CG133 : SynLib.v(648) | No assignment to cntDone @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010101 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010101 Generated name = synBusAdapter_17s_17s_signed_0s_21s_13s_5s_0s_SS_21s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010101 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010101 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000101000 shiftLeftAmount=32'b11111111111111111111111111111000 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z4 @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000001111 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_15s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000001111 Generated name = singleDelayWithEnableGeneric_15s @N:CG364 : ddc.v(322) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9 @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010010 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000001101 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000101 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b0 rounded=32'b00000000000000000000000000000000 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100101 shiftLeftAmount=32'b00000000000000000000000000000000 ShiftOutputWidth=32'b00000000000000000000000000100101 Generated name = synBusSatRnd_Z5 @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010000 out_width=32'b00000000000000000000000000001111 infrac=32'b00000000000000000000000000001101 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000011 outputIntWidth=32'b00000000000000000000000000000010 doRnd=1'b0 rounded=32'b00000000000000000000000000000000 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100001 shiftLeftAmount=32'b00000000000000000000000000000000 ShiftOutputWidth=32'b00000000000000000000000000100001 Generated name = synBusSatRnd_Z6 @W:CG360 : ddc.v(352) | No assignment to wire N_x_in_0_515 @W:CG360 : ddc.v(353) | No assignment to wire N_y_in_0_516 @W:CG360 : ddc.v(354) | No assignment to wire N_z_in_0_517 @W:CG360 : ddc.v(355) | No assignment to wire N_x_out_1_518 @W:CG360 : ddc.v(356) | No assignment to wire N_y_out_1_519 @W:CG360 : ddc.v(357) | No assignment to wire N_z_out_1_520 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010100 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010100 Generated name = synBusAdapter_17s_17s_signed_0s_20s_13s_5s_0s_SS_20s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010100 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010100 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100111 shiftLeftAmount=32'b11111111111111111111111111111001 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z7 @N:CG364 : ddc.v(491) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8 @W:CG360 : ddc.v(521) | No assignment to wire N_x_in_0_521 @W:CG360 : ddc.v(522) | No assignment to wire N_y_in_0_522 @W:CG360 : ddc.v(523) | No assignment to wire N_z_in_0_523 @W:CG360 : ddc.v(524) | No assignment to wire N_x_out_1_524 @W:CG360 : ddc.v(525) | No assignment to wire N_y_out_1_525 @W:CG360 : ddc.v(526) | No assignment to wire N_z_out_1_526 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010011 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010011 Generated name = synBusAdapter_17s_17s_signed_0s_19s_13s_5s_0s_SS_19s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010011 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010011 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100110 shiftLeftAmount=32'b11111111111111111111111111111010 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z8 @N:CG364 : ddc.v(660) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7 @W:CG360 : ddc.v(690) | No assignment to wire N_x_in_0_527 @W:CG360 : ddc.v(691) | No assignment to wire N_y_in_0_528 @W:CG360 : ddc.v(692) | No assignment to wire N_z_in_0_529 @W:CG360 : ddc.v(693) | No assignment to wire N_x_out_1_530 @W:CG360 : ddc.v(694) | No assignment to wire N_y_out_1_531 @W:CG360 : ddc.v(695) | No assignment to wire N_z_out_1_532 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010010 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010010 Generated name = synBusAdapter_17s_17s_signed_0s_18s_13s_5s_0s_SS_18s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010010 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010010 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100101 shiftLeftAmount=32'b11111111111111111111111111111011 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z9 @N:CG364 : ddc.v(829) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6 @W:CG360 : ddc.v(859) | No assignment to wire N_x_in_0_533 @W:CG360 : ddc.v(860) | No assignment to wire N_y_in_0_534 @W:CG360 : ddc.v(861) | No assignment to wire N_z_in_0_535 @W:CG360 : ddc.v(862) | No assignment to wire N_x_out_1_536 @W:CG360 : ddc.v(863) | No assignment to wire N_y_out_1_537 @W:CG360 : ddc.v(864) | No assignment to wire N_z_out_1_538 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010001 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010001 Generated name = synBusAdapter_17s_17s_signed_0s_17s_13s_5s_0s_SS_17s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010001 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100100 shiftLeftAmount=32'b11111111111111111111111111111100 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z10 @N:CG364 : ddc.v(998) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5 @W:CG360 : ddc.v(1028) | No assignment to wire N_x_in_0_539 @W:CG360 : ddc.v(1029) | No assignment to wire N_y_in_0_540 @W:CG360 : ddc.v(1030) | No assignment to wire N_z_in_0_541 @W:CG360 : ddc.v(1031) | No assignment to wire N_x_out_1_542 @W:CG360 : ddc.v(1032) | No assignment to wire N_y_out_1_543 @W:CG360 : ddc.v(1033) | No assignment to wire N_z_out_1_544 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010000 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010001 Generated name = synBusAdapter_17s_17s_signed_0s_16s_13s_5s_0s_SS_17s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010000 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000001 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100100 shiftLeftAmount=32'b11111111111111111111111111111101 ShiftOutputWidth=32'b00000000000000000000000000100001 Generated name = synBusSatRnd_Z11 @N:CG364 : ddc.v(1167) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4 @W:CG360 : ddc.v(1197) | No assignment to wire N_x_in_0_545 @W:CG360 : ddc.v(1198) | No assignment to wire N_y_in_0_546 @W:CG360 : ddc.v(1199) | No assignment to wire N_z_in_0_547 @W:CG360 : ddc.v(1200) | No assignment to wire N_x_out_1_548 @W:CG360 : ddc.v(1201) | No assignment to wire N_y_out_1_549 @W:CG360 : ddc.v(1202) | No assignment to wire N_z_out_1_550 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000001111 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010001 Generated name = synBusAdapter_17s_17s_signed_0s_15s_13s_5s_0s_SS_17s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000001111 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000010 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100100 shiftLeftAmount=32'b11111111111111111111111111111110 ShiftOutputWidth=32'b00000000000000000000000000100010 Generated name = synBusSatRnd_Z12 @N:CG364 : ddc.v(1336) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3 @W:CG360 : ddc.v(1366) | No assignment to wire N_x_in_0_551 @W:CG360 : ddc.v(1367) | No assignment to wire N_y_in_0_552 @W:CG360 : ddc.v(1368) | No assignment to wire N_z_in_0_553 @W:CG360 : ddc.v(1369) | No assignment to wire N_x_out_1_554 @W:CG360 : ddc.v(1370) | No assignment to wire N_y_out_1_555 @W:CG360 : ddc.v(1371) | No assignment to wire N_z_out_1_556 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000001110 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010001 Generated name = synBusAdapter_17s_17s_signed_0s_14s_13s_5s_0s_SS_17s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000001110 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000011 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000100100 shiftLeftAmount=32'b11111111111111111111111111111111 ShiftOutputWidth=32'b00000000000000000000000000100011 Generated name = synBusSatRnd_Z13 @N:CG364 : ddc.v(1505) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2 @W:CG360 : ddc.v(1535) | No assignment to wire N_x_in_0_557 @W:CG360 : ddc.v(1536) | No assignment to wire N_y_in_0_558 @W:CG360 : ddc.v(1537) | No assignment to wire N_z_in_0_559 @W:CG360 : ddc.v(1538) | No assignment to wire N_x_out_1_560 @W:CG360 : ddc.v(1539) | No assignment to wire N_y_out_1_561 @W:CG360 : ddc.v(1540) | No assignment to wire N_z_out_1_562 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000011000 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000011000 Generated name = synBusAdapter_17s_17s_signed_0s_24s_13s_5s_0s_SS_24s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000011000 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000011000 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000101011 shiftLeftAmount=32'b11111111111111111111111111110101 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z14 @N:CG364 : ddc.v(1674) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12 @W:CG360 : ddc.v(1704) | No assignment to wire N_x_in_0_563 @W:CG360 : ddc.v(1705) | No assignment to wire N_y_in_0_564 @W:CG360 : ddc.v(1706) | No assignment to wire N_z_in_0_565 @W:CG360 : ddc.v(1707) | No assignment to wire N_x_out_1_566 @W:CG360 : ddc.v(1708) | No assignment to wire N_y_out_1_567 @W:CG360 : ddc.v(1709) | No assignment to wire N_z_out_1_568 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010111 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010111 Generated name = synBusAdapter_17s_17s_signed_0s_23s_13s_5s_0s_SS_23s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010111 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010111 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000101010 shiftLeftAmount=32'b11111111111111111111111111110110 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z15 @N:CG364 : ddc.v(1843) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11 @W:CG360 : ddc.v(1873) | No assignment to wire N_x_in_0_569 @W:CG360 : ddc.v(1874) | No assignment to wire N_y_in_0_570 @W:CG360 : ddc.v(1875) | No assignment to wire N_z_in_0_571 @W:CG360 : ddc.v(1876) | No assignment to wire N_x_out_1_572 @W:CG360 : ddc.v(1877) | No assignment to wire N_y_out_1_573 @W:CG360 : ddc.v(1878) | No assignment to wire N_z_out_1_574 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000010110 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000010110 Generated name = synBusAdapter_17s_17s_signed_0s_22s_13s_5s_0s_SS_22s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000010110 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000010110 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000101001 shiftLeftAmount=32'b11111111111111111111111111110111 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z16 @N:CG364 : ddc.v(2012) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10 @W:CG360 : ddc.v(2042) | No assignment to wire N_x_in_0_575 @W:CG360 : ddc.v(2043) | No assignment to wire N_y_in_0_576 @W:CG360 : ddc.v(2044) | No assignment to wire N_z_in_0_577 @W:CG360 : ddc.v(2045) | No assignment to wire N_x_out_1_578 @W:CG360 : ddc.v(2046) | No assignment to wire N_y_out_1_579 @W:CG360 : ddc.v(2047) | No assignment to wire N_z_out_1_580 @N:CG364 : ddc.v(2181) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1 @W:CG360 : ddc.v(2203) | No assignment to wire N_z_in_0_581 @W:CG360 : ddc.v(2204) | No assignment to wire N_x_out_1_582 @W:CG360 : ddc.v(2205) | No assignment to wire N_y_out_1_583 @W:CG360 : ddc.v(2206) | No assignment to wire N_z_out_1_584 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000010001 out_width=32'b00000000000000000000000000010001 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000011001 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000011001 Generated name = synBusAdapter_17s_17s_signed_0s_25s_13s_5s_0s_SS_25s @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000011001 out_width=32'b00000000000000000000000000010001 infrac=32'b00000000000000000000000000011001 outfrac=32'b00000000000000000000000000001101 round=32'b00000000000000000000000000000101 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000000000 outputIntWidth=32'b00000000000000000000000000000100 doRnd=1'b1 rounded=32'b00000000000000000000000000000001 doSat=1'b0 maximumWidth=32'b00000000000000000000000000101100 shiftLeftAmount=32'b11111111111111111111111111110100 ShiftOutputWidth=32'b00000000000000000000000000100000 Generated name = synBusSatRnd_Z17 @N:CG364 : ddc.v(2246) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13 @W:CG360 : ddc.v(2270) | No assignment to wire N_x_in_0_585 @W:CG360 : ddc.v(2271) | No assignment to wire N_y_in_0_586 @W:CG360 : ddc.v(2272) | No assignment to wire N_z_in_0_587 @W:CG360 : ddc.v(2273) | No assignment to wire N_x_out_1_588 @W:CG360 : ddc.v(2274) | No assignment to wire N_y_out_1_589 @N:CG364 : ddc.v(2387) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1 @W:CG360 : ddc.v(2434) | No assignment to wire N_z_in_0_590 @W:CG360 : ddc.v(2435) | No assignment to wire N_x_out_1_591 @W:CG360 : ddc.v(2436) | No assignment to wire N_y_out_1_592 @N:CG364 : ddc.v(2573) | Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage @N:CG364 : SynLib.v(1920) | Synthesizing module synNegate bitwidth=32'b00000000000000000000000000010010 Generated name = synNegate_18s @W:CG360 : ddc.v(2601) | No assignment to wire N_GlobalEnable1_0_593 @W:CG360 : ddc.v(2602) | No assignment to wire N_z_in_0_594 @W:CG360 : ddc.v(2603) | No assignment to wire N_x_out_1_595 @W:CG360 : ddc.v(2604) | No assignment to wire N_y_out_1_596 @N:CG364 : ddc.v(2765) | Synthesizing module DDS_SinCos_CORDIC_SinCos @W:CG360 : ddc.v(2779) | No assignment to wire N_GlobalEnable1_0_597 @W:CG360 : ddc.v(2780) | No assignment to wire N_theta_0_598 @W:CG360 : ddc.v(2781) | No assignment to wire N_sin_1_599 @W:CG360 : ddc.v(2782) | No assignment to wire N_cos_1_600 @N:CG364 : ddc.v(2818) | Synthesizing module DDS_SinCos @W:CG360 : ddc.v(2836) | No assignment to wire N_GlobalEnable1_0_601 @W:CG360 : ddc.v(2837) | No assignment to wire N_phasein_0_602 @W:CG360 : ddc.v(2838) | No assignment to wire N_sin_1_603 @W:CG360 : ddc.v(2839) | No assignment to wire N_cos_1_604 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000100010 out_width=32'b00000000000000000000000000100000 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000100010 Generated name = synBusAdapter_34s_32s_signed_0s_0s_0s_0s_0s_SS_34s @N:CG364 : ddc.v(2931) | Synthesizing module DDS_PhaseGenerator @N:CG364 : SynLib.v(1428) | Synthesizing module synAccumulator bitwidth=32'b00000000000000000000000000100001 datatype=48'b011100110110100101100111011011100110010101100100 opr=32'b01101001011011100110001101110010 Generated name = synAccumulator_33s_signed_incr @W:CG133 : SynLib.v(1437) | No assignment to accU @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000100001 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_33s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000100001 Generated name = singleDelayWithEnableGeneric_33s @N:CG364 : ddc.v(2915) | Synthesizing module synDDS_PhaseGenerator_shrp1 @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000100000 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_32s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000100000 Generated name = singleDelayWithEnableGeneric_32s @N:CG364 : ddc.v(2899) | Synthesizing module synDDS_PhaseGenerator_shrp2 @W:CG360 : ddc.v(2947) | No assignment to wire N_freq_0_605 @W:CG360 : ddc.v(2948) | No assignment to wire N_pout_1_606 @N:CG364 : ddc.v(3198) | Synthesizing module DDS @W:CG360 : ddc.v(3212) | No assignment to wire N_GlobalEnable1_0_607 @W:CG360 : ddc.v(3213) | No assignment to wire N_freq_0_608 @W:CG360 : ddc.v(3214) | No assignment to wire N_sin_1_609 @W:CG360 : ddc.v(3215) | No assignment to wire N_cos_1_610 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000001110 out_width=32'b00000000000000000000000000101100 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000001110 Generated name = synBusAdapter_14s_44s_signed_0s_0s_0s_0s_0s_SS_14s @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000101100 out_width=32'b00000000000000000000000000001110 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000011100 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000001001000 Generated name = synBusAdapter_44s_14s_signed_28s_0s_0s_0s_0s_SS_72s @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000001110 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_14s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000001110 Generated name = singleDelayWithEnableGeneric_14s @N:CG364 : ddc.v(3076) | Synthesizing module CIC_I_I1 @N:CG364 : SynLib.v(326) | Synthesizing module synBusSatRnd inp_width=32'b00000000000000000000000000101101 out_width=32'b00000000000000000000000000101100 infrac=32'b00000000000000000000000000001011 outfrac=32'b00000000000000000000000000001011 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 datatype=16'b0101001101010011 inputIntWidth=32'b00000000000000000000000000100010 outputIntWidth=32'b00000000000000000000000000100001 doRnd=1'b0 rounded=32'b00000000000000000000000000000000 doSat=1'b0 maximumWidth=32'b00000000000000000000000001011011 shiftLeftAmount=32'b00000000000000000000000000000000 ShiftOutputWidth=32'b00000000000000000000000001011011 Generated name = synBusSatRnd_Z18 @N:CG364 : SynLib.v(906) | Synthesizing module synDelayWithEnable preferRAMImpl=32'b00000000000000000000000000000001 bitwidth=32'b00000000000000000000000000101100 delaylength=32'b00000000000000000000000000000001 Generated name = synDelayWithEnable_1s_44s_1s @N:CG364 : SynLib.v(600) | Synthesizing module singleDelayWithEnableGeneric bitwidth=32'b00000000000000000000000000101100 Generated name = singleDelayWithEnableGeneric_44s @N:CG364 : ddc.v(3060) | Synthesizing module synCIC_I_I1_Delay @W:CG360 : ddc.v(3086) | No assignment to wire N_x_0_641 @W:CG360 : ddc.v(3087) | No assignment to wire N_y_1_642 @N:CG364 : ddc.v(3145) | Synthesizing module CIC_I_C1 @N:CG364 : ddc.v(3129) | Synthesizing module synCIC_I_C1_Delay @W:CG360 : ddc.v(3155) | No assignment to wire N_x_0_651 @W:CG360 : ddc.v(3156) | No assignment to wire N_y_1_652 @N:CG364 : ddc.v(3248) | Synthesizing module CIC_I @W:CG360 : ddc.v(3272) | No assignment to wire N_x_0_653 @W:CG360 : ddc.v(3273) | No assignment to wire N_y_1_654 @N:CG364 : SynLib.v(117) | Synthesizing module synBusAdapter inp_width=32'b00000000000000000000000000001111 out_width=32'b00000000000000000000000000001110 datatype=48'b011100110110100101100111011011100110010101100100 preshift=32'b00000000000000000000000000000000 infrac=32'b00000000000000000000000000000000 outfrac=32'b00000000000000000000000000000000 round=32'b00000000000000000000000000000000 sat=32'b00000000000000000000000000000000 saType=16'b0101001101010011 tmpInpWidth=32'b00000000000000000000000000001111 Generated name = synBusAdapter_15s_14s_signed_0s_0s_0s_0s_0s_SS_15s @N:CG364 : SynLib.v(2508) | Synthesizing module synDownsampleSimple bitwidth=32'b00000000000000000000000000001110 Generated name = synDownsampleSimple_14s @W:CG133 : SynLib.v(2513) | No assignment to outreg @N:CG364 : ddc.v(3383) | Synthesizing module ddc @N:CG364 : ddc.v(178) | Synthesizing module CFIR_I_PolyphaseFIR_1 inpBitWidth=32'b00000000000000000000000000001110 inpFrac=32'b00000000000000000000000000001101 coefBitWidth=32'b00000000000000000000000000001001 coefFrac=32'b00000000000000000000000000001000 dpBitWidth=32'b00000000000000000000000000001111 dpFrac=32'b00000000000000000000000000001101 outBitWidth=32'b00000000000000000000000000001111 tapLen=32'b00000000000000000000000000011000 extraLatency=32'b00000000000000000000000000000000 uniTap=32'b00000000000000000000000000001010 Generated name = CFIR_I_PolyphaseFIR_1_14s_13s_9s_8s_15s_13s_15s_24s_0s_10s @N:CG364 : ddc.v(15) | Synthesizing module CFIR_I_PolyphaseFIR_0 inpBitWidth=32'b00000000000000000000000000001110 inpFrac=32'b00000000000000000000000000001101 coefBitWidth=32'b00000000000000000000000000001001 coefFrac=32'b00000000000000000000000000001000 dpBitWidth=32'b00000000000000000000000000001111 dpFrac=32'b00000000000000000000000000001101 outBitWidth=32'b00000000000000000000000000001111 tapLen=32'b00000000000000000000000000011001 extraLatency=32'b00000000000000000000000000000000 uniTap=32'b00000000000000000000000000001010 Generated name = CFIR_I_PolyphaseFIR_0_14s_13s_9s_8s_15s_13s_15s_25s_0s_10s @W:CL279 : ddc.v(110) | Pruning register bits 14 to 8 of inner_floop.mem_23_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 9 of inner_floop.mem_22_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 10 of inner_floop.mem_21_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 11 of inner_floop.mem_20_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 12 of inner_floop.mem_19_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 12 of inner_floop.mem_18_[14:0] @W:CL279 : ddc.v(110) | Pruning register bits 14 to 13 of inner_floop.mem_17_[14:0] @W:CL260 : ddc.v(110) | Pruning register bit 14 of inner_floop.mem_16_[14:0] @W:CL279 : ddc.v(272) | Pruning register bits 14 to 8 of inner_floop.mem_22_[14:0] @W:CL279 : ddc.v(272) | Pruning register bits 14 to 10 of inner_floop.mem_21_[14:0] @W:CL279 : ddc.v(272) | Pruning register bits 14 to 11 of inner_floop.mem_20_[14:0] @W:CL279 : ddc.v(272) | Pruning register bits 14 to 12 of inner_floop.mem_19_[14:0] @W:CL279 : ddc.v(272) | Pruning register bits 14 to 13 of inner_floop.mem_18_[14:0] @W:CL260 : ddc.v(272) | Pruning register bit 14 of inner_floop.mem_17_[14:0] @W:CL247 : SynLib.v(129) | Input port bit 14 of inp[14:0] is unused @W:CL247 : SynLib.v(334) | Input port bit 44 of inp[44:0] is unused @W:CL246 : SynLib.v(129) | Input port bits 43 to 42 of inp[43:0] are unused @W:CL246 : SynLib.v(129) | Input port bits 27 to 0 of inp[43:0] are unused @W:CL246 : SynLib.v(129) | Input port bits 33 to 32 of inp[33:0] are unused @W:CL246 : ddc.v(2252) | Input port bits 13 to 0 of z_in[14:0] are unused @W:CL159 : ddc.v(2247) | Input clk is unused @W:CL159 : ddc.v(2248) | Input GlobalEnable1 is unused @W:CL159 : ddc.v(2249) | Input GlobalReset is unused @W:CL159 : ddc.v(1844) | Input clk is unused @W:CL159 : ddc.v(1845) | Input GlobalEnable1 is unused @W:CL159 : ddc.v(1846) | Input GlobalReset is unused @W:CL159 : ddc.v(1675) | Input clk is unused @W:CL159 : ddc.v(1676) | Input GlobalEnable1 is unused @W:CL159 : ddc.v(1677) | Input GlobalReset is unused @W:CL247 : SynLib.v(334) | Input port bit 15 of inp[15:0] is unused @W:CL247 : SynLib.v(334) | Input port bit 17 of inp[17:0] is unused @N:CL135 : SynLib.v(762) | Found seqShift GenBlock.asynch_implementation.RegisterStyle.delayline, depth=10, width=1 @W:CL247 : SynLib.v(129) | Input port bit 17 of inp[17:0] is unused @W:CL247 : SynLib.v(129) | Input port bit 13 of inp[13:0] is unused @W:CL246 : SynLib.v(129) | Input port bits 19 to 0 of inp[31:0] are unused @W:CL247 : SynLib.v(334) | Input port bit 15 of inp[16:0] is unused At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 83MB peak: 112MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Mar 03 15:15:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 03 15:15:19 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Mar 03 15:15:19 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 03 15:15:20 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\synthesis.fdc Linked File: ddc_scck.rpt Printing clock summary report in "E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\synthesis\ddc_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) syn_allowed_resources : blockrams=69,dsps=72 set on top level netlist ddc Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 156MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------- clk 40.0 MHz 25.000 declared default_clkgroup clkDiv64 0.6 MHz 1600.000 declared default_clkgroup clkDiv128 0.3 MHz 3200.000 declared default_clkgroup ======================================================================= Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\synthesis\ddc.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 156MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 03 15:15:21 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Available hyper_sources - for debug and ip models None Found @W:BN132 : ddc.v(3276) | Removing sequential instance myCIC_I.DownsampleCounterclkDrate64[5:0], because it is equivalent to instance myCIC_Q.DownsampleCounterclkDrate64[5:0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un7_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un7_enDs[0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un6_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un6_enDs[0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un10_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un10_enDs[0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un9_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un9_enDs[0] @W:BN132 : ddc.v(3279) | Removing user instance myCIC_I.dcntProc1_64_proc.DownsampleCounterclkDrate64_4[5:0], because it is equivalent to instance myCIC_Q.dcntProc1_64_proc.DownsampleCounterclkDrate64_4[5:0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un8_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un8_enDs[0] @W:BN132 : ddc.v(3312) | Removing user instance myCIC_I.Rate_block.un11_enDs[0], because it is equivalent to instance myCIC_Q.Rate_block.un11_enDs[0] Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 148MB) @N: : ddc.v(3276) | Found counter in view:work.ddc(verilog) inst myCIC_Q.DownsampleCounterclkDrate64[5:0] @N:BN362 : synlib.v(607) | Removing sequential instance NoName of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_0 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_1 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_2 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_3 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_4 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_5 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_6 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_7 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_8 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_9 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_10 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_11 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_12 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_13 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_14 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_15 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_16 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_17 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_18 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_19 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_20 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_21 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_22 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_23 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_24 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_25 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_26 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_27 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_28 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_29 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_30 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_31 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_32 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_33 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_34 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_35 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_36 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_37 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_38 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_39 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_40 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_41 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_42 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_43 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_44 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_45 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_46 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_47 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_48 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_49 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_50 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_51 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_52 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_53 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_54 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_55 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_56 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_57 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_58 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_59 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_60 of view:PrimLib.dffr(prim) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[0] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[4] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[5] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[6] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[7] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[8] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[9] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[10] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[11] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[12] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[13] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[14] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[15] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[16] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[17] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[18] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myPhaseGenerator.shrp2_block\.myshrp2.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[19] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS(verilog) because there are no references to its outputs @W:MO129 : synlib.v(607) | Sequential instance myDDS.myPhaseGenerator.shrp1_block.myshrp1.Delay0_block.GenBlock.genblk1.theDelay.outreg[32] reduced to a combinational gate by constant propagation @N:BN362 : synlib.v(607) | Removing sequential instance Delay2_block.GenBlock\.genblk1\.theDelay.outreg[15] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS_SinCos(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance Delay1_block.GenBlock\.genblk1\.theDelay.outreg[15] of view:PrimLib.dffr(prim) in hierarchy view:work.DDS_SinCos(verilog) because there are no references to its outputs @N:FX404 : synlib.v(396) | Found addmux in view:work.DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1(verilog) inst myCORDIC_stg2.Convert2.genblk4\.Convert.rndOutput[16:0] from myCORDIC_stg2.Convert2.genblk4\.Convert.un82_rndOutput[16:0] @N:FX404 : synlib.v(396) | Found addmux in view:work.DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1(verilog) inst myCORDIC_stg2.Convert1.genblk4\.Convert.rndOutput[16:0] from myCORDIC_stg2.Convert1.genblk4\.Convert.un82_rndOutput[16:0] @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay3_block.GenBlock.genblk1.theDelay.outreg[0] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[4] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[7] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[10] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[11] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[13] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[14] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[15] reduced to a combinational gate by constant propagation @W:MO129 : synlib.v(607) | Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[16] reduced to a combinational gate by constant propagation @W:BN132 : synlib.v(607) | Removing instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[16], because it is equivalent to instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[4] @W:BN132 : synlib.v(607) | Removing instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[15], because it is equivalent to instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[4] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 153MB) @N:BN362 : synlib.v(607) | Removing sequential instance NoName_92 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_93 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_94 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_95 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_96 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_97 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_98 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_99 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_100 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_101 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_102 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_103 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_104 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_105 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_106 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_107 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_108 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_109 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_110 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_111 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_112 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_113 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_114 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_115 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_116 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_117 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_118 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_119 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_120 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_121 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_122 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_61 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_62 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_63 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_64 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_65 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_66 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_67 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_68 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_69 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_70 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_71 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_72 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_73 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_74 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_75 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_76 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_77 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_78 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_79 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_80 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_81 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_82 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_83 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_84 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_85 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_86 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_87 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_88 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_89 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_90 in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance NoName_91 in hierarchy view:work.ddc(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 162MB peak: 162MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 164MB) @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_0_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_0_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_0_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_0_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @W:FX665 : ddc.v(272) | Removing instance CFIR_I_PolyphaseFIR_1_block�myCFIR_I_PolyphaseFIR_1.inner_floop�mem_22_[7] because it is equivalent to instance CFIR_I_PolyphaseFIR_1_block�myCFIR_I_PolyphaseFIR_1.inner_floop�mem_22_[6] @W:FX665 : ddc.v(110) | Removing instance CFIR_I_PolyphaseFIR_0_block�myCFIR_I_PolyphaseFIR_0.inner_floop�mem_23_[7] because it is equivalent to instance CFIR_I_PolyphaseFIR_0_block�myCFIR_I_PolyphaseFIR_0.inner_floop�mem_23_[6] @W:FX665 : ddc.v(272) | Removing instance CFIR_Q_PolyphaseFIR_1_block�myCFIR_Q_PolyphaseFIR_1.inner_floop�mem_22_[7] because it is equivalent to instance CFIR_Q_PolyphaseFIR_1_block�myCFIR_Q_PolyphaseFIR_1.inner_floop�mem_22_[6] @W:FX665 : ddc.v(110) | Removing instance CFIR_Q_PolyphaseFIR_0_block�myCFIR_Q_PolyphaseFIR_0.inner_floop�mem_23_[7] because it is equivalent to instance CFIR_Q_PolyphaseFIR_0_block�myCFIR_Q_PolyphaseFIR_0.inner_floop�mem_23_[6] @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_1_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_1_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC4.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC4.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC4.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC4.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_1_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_1_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_2_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_2_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC3.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC3.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC3.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC3.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_2_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_2_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_3_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_3_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC2.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC2.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC2.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC2.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_3_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_3_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_4_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_4_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_4_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_4_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_5_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_5_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_5_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_5_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_6_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_6_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_6_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_7_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_7_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_7_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_7_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_8_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_8_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_8_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_8_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_9_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_9_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_9_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_9_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_10_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_10_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_10_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_10_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_11_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_11_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_11_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_11_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_12_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_12_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_12_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_12_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_13_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_13_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_13_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_13_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_14_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_14_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_14_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_14_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_Q_PolyphaseFIR_0_block\.myCFIR_Q_PolyphaseFIR_0.inner_floop\.mem_15_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(110) | Removing sequential instance CFIR_I_PolyphaseFIR_0_block\.myCFIR_I_PolyphaseFIR_0.inner_floop\.mem_15_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_15_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_15_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_16_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs @N:BN362 : ddc.v(272) | Removing sequential instance CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_16_[14] in hierarchy view:work.ddc(verilog) because there are no references to its outputs Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 163MB peak: 164MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 163MB peak: 164MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 164MB) @N:BN362 : synlib.v(1452) | Removing sequential instance myDDS.myPhaseGenerator.Acc_p_block\.Acc_p.AccumulatorGen\.genblk1\.accS[32] in hierarchy view:work.ddc(verilog) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 163MB peak: 164MB) Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 160MB peak: 164MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -0.41ns 3383 / 2918 2 0h:00m:05s -0.41ns 3383 / 2918 @N:FX271 : synlib.v(607) | Instance "myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg10.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[16]" with 7 loads replicated 1 times to improve timing @N:FX271 : synlib.v(607) | Instance "myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg10.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[16]" with 7 loads replicated 1 times to improve timing Timing driven replication report Added 2 Registers via timing driven replication Added 0 LUTs via timing driven replication 3 0h:00m:06s -0.13ns 3377 / 2920 4 0h:00m:06s -0.13ns 3377 / 2920 @N:FP130 : | Promoting Net GlobalReset_c on CLKINT I_1430 @N:FP130 : | Promoting Net clkDiv128_c on CLKINT I_1431 @N:FP130 : | Promoting Net clk_c on CLKINT I_1432 @N:FP130 : | Promoting Net clkDiv64_c on CLKINT I_1433 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 162MB peak: 173MB) @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[42] of view:ACG4.SLE(PRIM) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @A:BN291 : synlib.v(607) | Boundary register myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[42] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[43] of view:ACG4.SLE(PRIM) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @A:BN291 : synlib.v(607) | Boundary register myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[43] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[42] of view:ACG4.SLE(PRIM) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @A:BN291 : synlib.v(607) | Boundary register myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[42] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : synlib.v(607) | Removing sequential instance myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[43] of view:ACG4.SLE(PRIM) in hierarchy view:work.ddc(verilog) because there are no references to its outputs @A:BN291 : synlib.v(607) | Boundary register myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[43] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 169MB peak: 173MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 2916 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ======================================== Non-Gated/Non-Generated Clocks ======================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------- ClockId0001 clkDiv128 clock definition on port 1290 I_out_block.med[10] ClockId0002 clk clock definition on port 1149 Freq_block.med[0] ClockId0003 clkDiv64 clock definition on port 477 DownsampleCounterclkDiv64Drate2[0] ================================================================================================================ ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 123MB peak: 173MB) Writing Analyst data base E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\synthesis\synwork\ddc_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 162MB peak: 173MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 163MB peak: 173MB) Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 164MB peak: 173MB) Found clock clk with period 25.00ns Found clock clkDiv128 with period 3200.00ns Found clock clkDiv64 with period 1600.00ns @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Mar 03 15:15:37 2016 # Top view: ddc Requested Frequency: 0.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\synthesis.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 10.979 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------- clk 40.0 MHz 71.3 MHz 25.000 14.021 10.979 declared default_clkgroup clkDiv64 0.6 MHz 1.7 MHz 1600.000 576.096 1591.135 declared default_clkgroup clkDiv128 0.3 MHz 73.0 MHz 3200.000 13.705 3191.683 declared default_clkgroup ===================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- clk clk | 25.000 10.979 | No paths - | No paths - | No paths - clk clkDiv64 | 25.000 15.999 | No paths - | No paths - | No paths - clkDiv64 clkDiv64 | 1600.000 1591.135 | No paths - | No paths - | No paths - clkDiv64 clkDiv128 | 1600.000 1593.147 | No paths - | No paths - | No paths - clkDiv128 clkDiv128 | 3200.000 3191.683 | No paths - | No paths - | No paths - =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------ myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[16] clk SLE Q N_6[16] 0.108 10.979 myDDS.mySinCos.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[16] clk SLE Q N_7[16] 0.108 10.979 myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[3] clk SLE Q N_6[3] 0.108 11.176 myDDS.mySinCos.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[3] clk SLE Q N_7[3] 0.108 11.176 myDDS.mySinCos.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[4] clk SLE Q N_7[4] 0.108 11.192 myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[4] clk SLE Q N_6[4] 0.108 11.192 myDDS.mySinCos.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[0] clk SLE Q N_7[0] 0.108 11.207 myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[0] clk SLE Q N_6[0] 0.108 11.207 myDDS.mySinCos.Delay2_block.GenBlock\.genblk1\.theDelay.outreg[5] clk SLE Q N_7[5] 0.108 11.208 myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[5] clk SLE Q N_6[5] 0.108 11.208 ==================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- myCIC_Q.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] clk SLE D N_7[43] 24.745 10.979 myCIC_I.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] clk SLE D N_7[43] 24.745 10.979 myCIC_I.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] clk SLE D N_7[42] 24.745 11.227 myCIC_Q.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[42] clk SLE D N_7[42] 24.745 11.227 myCIC_I.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[41] clk SLE D N_7[41] 24.745 11.237 myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[41] clk SLE D N_7[41] 24.745 11.237 myCIC_Q.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[41] clk SLE D N_7[41] 24.745 11.237 myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[41] clk SLE D N_7[41] 24.745 11.237 myCIC_I.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[40] clk SLE D N_7[40] 24.745 11.253 myCIC_Q.Rate_block\.dsDelay_block.GenBlock\.genblk1\.theDelay.outreg[40] clk SLE D N_7[40] 24.745 11.253 ================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.745 - Propagation time: 13.766 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 10.979 Number of logic level(s): 59 Starting point: myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[16] / Q Ending point: myCIC_Q.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] / D The start point is clocked by clk [rising] on pin CLK The end point is clocked by clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------- myDDS.mySinCos.Delay1_block.GenBlock\.genblk1\.theDelay.outreg[16] SLE Q Out 0.108 0.108 - N_6[16] Net - - 0.733 - 3 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_0 ARI1 B In - 0.841 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_0 ARI1 FCO Out 0.201 1.042 - un1_inp_cry_0 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_1 ARI1 FCI In - 1.042 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_1 ARI1 FCO Out 0.016 1.058 - un1_inp_cry_1 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_2 ARI1 FCI In - 1.058 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_2 ARI1 FCO Out 0.016 1.075 - un1_inp_cry_2 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_3 ARI1 FCI In - 1.075 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_3 ARI1 FCO Out 0.016 1.091 - un1_inp_cry_3 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_4 ARI1 FCI In - 1.091 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_4 ARI1 FCO Out 0.016 1.107 - un1_inp_cry_4 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_5 ARI1 FCI In - 1.107 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_5 ARI1 FCO Out 0.016 1.123 - un1_inp_cry_5 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_6 ARI1 FCI In - 1.123 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_6 ARI1 FCO Out 0.016 1.140 - un1_inp_cry_6 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_7 ARI1 FCI In - 1.140 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_7 ARI1 FCO Out 0.016 1.156 - un1_inp_cry_7 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_8 ARI1 FCI In - 1.156 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_8 ARI1 FCO Out 0.016 1.172 - un1_inp_cry_8 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_9 ARI1 FCI In - 1.172 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_9 ARI1 FCO Out 0.016 1.189 - un1_inp_cry_9 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_10 ARI1 FCI In - 1.189 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_10 ARI1 FCO Out 0.016 1.205 - un1_inp_cry_10 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_11 ARI1 FCI In - 1.205 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_11 ARI1 FCO Out 0.016 1.221 - un1_inp_cry_11 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_12 ARI1 FCI In - 1.221 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_12 ARI1 FCO Out 0.016 1.238 - un1_inp_cry_12 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_13 ARI1 FCI In - 1.238 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_cry_13 ARI1 FCO Out 0.016 1.254 - un1_inp_cry_13 Net - - 0.000 - 1 myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_s_14 ARI1 FCI In - 1.254 - myDDS.mySinCos.Convert3.genblk4\.Convert.un1_inp_s_14 ARI1 S Out 0.073 1.327 - N_3[11] Net - - 1.134 - 7 tmpOut_4_mulonly_0[19:0] MACC B[11] In - 2.461 - tmpOut_4_mulonly_0[19:0] MACC P[11] Out 2.470 4.931 - tmpOut_4[11] Net - - 1.117 - 1 myCIC_Q.myI1.tmpOutPre_cry_5 ARI1 B In - 6.048 - myCIC_Q.myI1.tmpOutPre_cry_5 ARI1 FCO Out 0.201 6.248 - tmpOutPre_cry_5 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_6 ARI1 FCI In - 6.248 - myCIC_Q.myI1.tmpOutPre_cry_6 ARI1 FCO Out 0.016 6.265 - tmpOutPre_cry_6 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_7 ARI1 FCI In - 6.265 - myCIC_Q.myI1.tmpOutPre_cry_7 ARI1 FCO Out 0.016 6.281 - tmpOutPre_cry_7 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_8 ARI1 FCI In - 6.281 - myCIC_Q.myI1.tmpOutPre_cry_8 ARI1 FCO Out 0.016 6.297 - tmpOutPre_cry_8 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_9 ARI1 FCI In - 6.297 - myCIC_Q.myI1.tmpOutPre_cry_9 ARI1 FCO Out 0.016 6.314 - tmpOutPre_cry_9 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_10 ARI1 FCI In - 6.314 - myCIC_Q.myI1.tmpOutPre_cry_10 ARI1 FCO Out 0.016 6.330 - tmpOutPre_cry_10 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_11 ARI1 FCI In - 6.330 - myCIC_Q.myI1.tmpOutPre_cry_11 ARI1 FCO Out 0.016 6.346 - tmpOutPre_cry_11 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_12 ARI1 FCI In - 6.346 - myCIC_Q.myI1.tmpOutPre_cry_12 ARI1 FCO Out 0.016 6.362 - tmpOutPre_cry_12 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_13 ARI1 FCI In - 6.362 - myCIC_Q.myI1.tmpOutPre_cry_13 ARI1 FCO Out 0.016 6.379 - tmpOutPre_cry_13 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_14 ARI1 FCI In - 6.379 - myCIC_Q.myI1.tmpOutPre_cry_14 ARI1 FCO Out 0.016 6.395 - tmpOutPre_cry_14 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_15 ARI1 FCI In - 6.395 - myCIC_Q.myI1.tmpOutPre_cry_15 ARI1 FCO Out 0.016 6.411 - tmpOutPre_cry_15 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_16 ARI1 FCI In - 6.411 - myCIC_Q.myI1.tmpOutPre_cry_16 ARI1 FCO Out 0.016 6.428 - tmpOutPre_cry_16 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_17 ARI1 FCI In - 6.428 - myCIC_Q.myI1.tmpOutPre_cry_17 ARI1 FCO Out 0.016 6.444 - tmpOutPre_cry_17 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_18 ARI1 FCI In - 6.444 - myCIC_Q.myI1.tmpOutPre_cry_18 ARI1 FCO Out 0.016 6.460 - tmpOutPre_cry_18 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_19 ARI1 FCI In - 6.460 - myCIC_Q.myI1.tmpOutPre_cry_19 ARI1 FCO Out 0.016 6.476 - tmpOutPre_cry_19 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_20 ARI1 FCI In - 6.476 - myCIC_Q.myI1.tmpOutPre_cry_20 ARI1 FCO Out 0.016 6.493 - tmpOutPre_cry_20 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_21 ARI1 FCI In - 6.493 - myCIC_Q.myI1.tmpOutPre_cry_21 ARI1 FCO Out 0.016 6.509 - tmpOutPre_cry_21 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_22 ARI1 FCI In - 6.509 - myCIC_Q.myI1.tmpOutPre_cry_22 ARI1 FCO Out 0.016 6.525 - tmpOutPre_cry_22 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_23 ARI1 FCI In - 6.525 - myCIC_Q.myI1.tmpOutPre_cry_23 ARI1 FCO Out 0.016 6.542 - tmpOutPre_cry_23 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_24 ARI1 FCI In - 6.542 - myCIC_Q.myI1.tmpOutPre_cry_24 ARI1 FCO Out 0.016 6.558 - tmpOutPre_cry_24 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_25 ARI1 FCI In - 6.558 - myCIC_Q.myI1.tmpOutPre_cry_25 ARI1 FCO Out 0.016 6.574 - tmpOutPre_cry_25 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_26 ARI1 FCI In - 6.574 - myCIC_Q.myI1.tmpOutPre_cry_26 ARI1 FCO Out 0.016 6.591 - tmpOutPre_cry_26 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_27 ARI1 FCI In - 6.591 - myCIC_Q.myI1.tmpOutPre_cry_27 ARI1 FCO Out 0.016 6.607 - tmpOutPre_cry_27 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_28 ARI1 FCI In - 6.607 - myCIC_Q.myI1.tmpOutPre_cry_28 ARI1 FCO Out 0.016 6.623 - tmpOutPre_cry_28 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_29 ARI1 FCI In - 6.623 - myCIC_Q.myI1.tmpOutPre_cry_29 ARI1 FCO Out 0.016 6.640 - tmpOutPre_cry_29 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_30 ARI1 FCI In - 6.640 - myCIC_Q.myI1.tmpOutPre_cry_30 ARI1 FCO Out 0.016 6.656 - tmpOutPre_cry_30 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_31 ARI1 FCI In - 6.656 - myCIC_Q.myI1.tmpOutPre_cry_31 ARI1 FCO Out 0.016 6.672 - tmpOutPre_cry_31 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_32 ARI1 FCI In - 6.672 - myCIC_Q.myI1.tmpOutPre_cry_32 ARI1 FCO Out 0.016 6.688 - tmpOutPre_cry_32 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_33 ARI1 FCI In - 6.688 - myCIC_Q.myI1.tmpOutPre_cry_33 ARI1 FCO Out 0.016 6.705 - tmpOutPre_cry_33 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_34 ARI1 FCI In - 6.705 - myCIC_Q.myI1.tmpOutPre_cry_34 ARI1 FCO Out 0.016 6.721 - tmpOutPre_cry_34 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_35 ARI1 FCI In - 6.721 - myCIC_Q.myI1.tmpOutPre_cry_35 ARI1 FCO Out 0.016 6.737 - tmpOutPre_cry_35 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_36 ARI1 FCI In - 6.737 - myCIC_Q.myI1.tmpOutPre_cry_36 ARI1 FCO Out 0.016 6.754 - tmpOutPre_cry_36 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_37 ARI1 FCI In - 6.754 - myCIC_Q.myI1.tmpOutPre_cry_37 ARI1 FCO Out 0.016 6.770 - tmpOutPre_cry_37 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_38 ARI1 FCI In - 6.770 - myCIC_Q.myI1.tmpOutPre_cry_38 ARI1 FCO Out 0.016 6.786 - tmpOutPre_cry_38 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_39 ARI1 FCI In - 6.786 - myCIC_Q.myI1.tmpOutPre_cry_39 ARI1 FCO Out 0.016 6.803 - tmpOutPre_cry_39 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_40 ARI1 FCI In - 6.803 - myCIC_Q.myI1.tmpOutPre_cry_40 ARI1 FCO Out 0.016 6.819 - tmpOutPre_cry_40 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_41 ARI1 FCI In - 6.819 - myCIC_Q.myI1.tmpOutPre_cry_41 ARI1 FCO Out 0.016 6.835 - tmpOutPre_cry_41 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_cry_42 ARI1 FCI In - 6.835 - myCIC_Q.myI1.tmpOutPre_cry_42 ARI1 FCO Out 0.016 6.851 - tmpOutPre_cry_42 Net - - 0.000 - 1 myCIC_Q.myI1.tmpOutPre_s_43 ARI1 FCI In - 6.851 - myCIC_Q.myI1.tmpOutPre_s_43 ARI1 S Out 0.073 6.924 - N_3[43] Net - - 1.123 - 2 myCIC_Q.myI2.tmpOutPre_s_43 ARI1 B In - 8.047 - myCIC_Q.myI2.tmpOutPre_s_43 ARI1 S Out 0.308 8.355 - N_4[43] Net - - 1.123 - 2 myCIC_Q.myI3.tmpOutPre_s_43 ARI1 B In - 9.479 - myCIC_Q.myI3.tmpOutPre_s_43 ARI1 S Out 0.308 9.787 - N_5[43] Net - - 1.123 - 2 myCIC_Q.myI4.tmpOutPre_s_43 ARI1 B In - 10.910 - myCIC_Q.myI4.tmpOutPre_s_43 ARI1 S Out 0.308 11.218 - N_6[43] Net - - 1.123 - 2 myCIC_Q.myI5.tmpOutPre_s_43 ARI1 B In - 12.341 - myCIC_Q.myI5.tmpOutPre_s_43 ARI1 S Out 0.308 12.649 - N_7[43] Net - - 1.117 - 1 myCIC_Q.myI5.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[43] SLE D In - 13.766 - ============================================================================================================================================================= Total path delay (propagation time + setup) of 14.021 is 5.428(38.7%) logic and 8.593(61.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: clkDiv64 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------- myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[0] clkDiv64 SLE Q outBuf0[0] 0.087 1591.135 myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[0] clkDiv64 SLE Q outBuf0[0] 0.087 1591.135 myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[1] clkDiv64 SLE Q outBuf0[1] 0.087 1591.344 myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[1] clkDiv64 SLE Q outBuf0[1] 0.087 1591.344 myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[2] clkDiv64 SLE Q outBuf0[2] 0.087 1591.360 myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[2] clkDiv64 SLE Q outBuf0[2] 0.087 1591.360 myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[3] clkDiv64 SLE Q outBuf0[3] 0.087 1591.377 myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[3] clkDiv64 SLE Q outBuf0[3] 0.087 1591.377 myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[4] clkDiv64 SLE Q outBuf0[4] 0.087 1591.393 myCIC_I.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[4] clkDiv64 SLE Q outBuf0[4] 0.087 1591.393 =================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------ myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[13] clkDiv64 SLE D N_14[13] 1599.745 1591.135 myCIC_I.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[13] clkDiv64 SLE D N_14[13] 1599.745 1591.135 myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[12] clkDiv64 SLE D N_14[12] 1599.745 1591.405 myCIC_I.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[12] clkDiv64 SLE D N_14[12] 1599.745 1591.405 myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[11] clkDiv64 SLE D N_14[11] 1599.745 1591.421 myCIC_I.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[11] clkDiv64 SLE D N_14[11] 1599.745 1591.421 myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[10] clkDiv64 SLE D N_14[10] 1599.745 1591.438 myCIC_I.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[10] clkDiv64 SLE D N_14[10] 1599.745 1591.438 myCIC_I.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[9] clkDiv64 SLE D N_14[9] 1599.745 1591.454 myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[9] clkDiv64 SLE D N_14[9] 1599.745 1591.454 ==================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1600.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 1599.745 - Propagation time: 8.610 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1591.135 Number of logic level(s): 46 Starting point: myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[0] / Q Ending point: myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[13] / D The start point is clocked by clkDiv64 [rising] on pin CLK The end point is clocked by clkDiv64 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- myCIC_Q.myC1.Delay_syn_block\.myDelay_syn.Delay0_block.GenBlock\.genblk1\.theDelay.outreg[0] SLE Q Out 0.087 0.087 - outBuf0[0] Net - - 0.778 - 4 myCIC_Q.myC1.tmpOutPre_cry_0 ARI1 B In - 0.865 - myCIC_Q.myC1.tmpOutPre_cry_0 ARI1 FCO Out 0.178 1.043 - tmpOutPre_cry_0 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_1 ARI1 FCI In - 1.043 - myCIC_Q.myC1.tmpOutPre_cry_1 ARI1 FCO Out 0.016 1.060 - tmpOutPre_cry_1 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_2 ARI1 FCI In - 1.060 - myCIC_Q.myC1.tmpOutPre_cry_2 ARI1 FCO Out 0.016 1.076 - tmpOutPre_cry_2 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_3 ARI1 FCI In - 1.076 - myCIC_Q.myC1.tmpOutPre_cry_3 ARI1 FCO Out 0.016 1.092 - tmpOutPre_cry_3 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_4 ARI1 FCI In - 1.092 - myCIC_Q.myC1.tmpOutPre_cry_4 ARI1 FCO Out 0.016 1.108 - tmpOutPre_cry_4 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_5 ARI1 FCI In - 1.108 - myCIC_Q.myC1.tmpOutPre_cry_5 ARI1 FCO Out 0.016 1.125 - tmpOutPre_cry_5 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_6 ARI1 FCI In - 1.125 - myCIC_Q.myC1.tmpOutPre_cry_6 ARI1 FCO Out 0.016 1.141 - tmpOutPre_cry_6 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_7 ARI1 FCI In - 1.141 - myCIC_Q.myC1.tmpOutPre_cry_7 ARI1 FCO Out 0.016 1.157 - tmpOutPre_cry_7 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_8 ARI1 FCI In - 1.157 - myCIC_Q.myC1.tmpOutPre_cry_8 ARI1 FCO Out 0.016 1.174 - tmpOutPre_cry_8 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_9 ARI1 FCI In - 1.174 - myCIC_Q.myC1.tmpOutPre_cry_9 ARI1 FCO Out 0.016 1.190 - tmpOutPre_cry_9 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_10 ARI1 FCI In - 1.190 - myCIC_Q.myC1.tmpOutPre_cry_10 ARI1 FCO Out 0.016 1.206 - tmpOutPre_cry_10 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_11 ARI1 FCI In - 1.206 - myCIC_Q.myC1.tmpOutPre_cry_11 ARI1 FCO Out 0.016 1.222 - tmpOutPre_cry_11 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_12 ARI1 FCI In - 1.222 - myCIC_Q.myC1.tmpOutPre_cry_12 ARI1 FCO Out 0.016 1.239 - tmpOutPre_cry_12 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_13 ARI1 FCI In - 1.239 - myCIC_Q.myC1.tmpOutPre_cry_13 ARI1 FCO Out 0.016 1.255 - tmpOutPre_cry_13 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_14 ARI1 FCI In - 1.255 - myCIC_Q.myC1.tmpOutPre_cry_14 ARI1 FCO Out 0.016 1.271 - tmpOutPre_cry_14 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_15 ARI1 FCI In - 1.271 - myCIC_Q.myC1.tmpOutPre_cry_15 ARI1 FCO Out 0.016 1.288 - tmpOutPre_cry_15 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_16 ARI1 FCI In - 1.288 - myCIC_Q.myC1.tmpOutPre_cry_16 ARI1 FCO Out 0.016 1.304 - tmpOutPre_cry_16 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_17 ARI1 FCI In - 1.304 - myCIC_Q.myC1.tmpOutPre_cry_17 ARI1 FCO Out 0.016 1.320 - tmpOutPre_cry_17 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_18 ARI1 FCI In - 1.320 - myCIC_Q.myC1.tmpOutPre_cry_18 ARI1 FCO Out 0.016 1.337 - tmpOutPre_cry_18 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_19 ARI1 FCI In - 1.337 - myCIC_Q.myC1.tmpOutPre_cry_19 ARI1 FCO Out 0.016 1.353 - tmpOutPre_cry_19 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_20 ARI1 FCI In - 1.353 - myCIC_Q.myC1.tmpOutPre_cry_20 ARI1 FCO Out 0.016 1.369 - tmpOutPre_cry_20 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_21 ARI1 FCI In - 1.369 - myCIC_Q.myC1.tmpOutPre_cry_21 ARI1 FCO Out 0.016 1.386 - tmpOutPre_cry_21 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_22 ARI1 FCI In - 1.386 - myCIC_Q.myC1.tmpOutPre_cry_22 ARI1 FCO Out 0.016 1.402 - tmpOutPre_cry_22 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_23 ARI1 FCI In - 1.402 - myCIC_Q.myC1.tmpOutPre_cry_23 ARI1 FCO Out 0.016 1.418 - tmpOutPre_cry_23 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_24 ARI1 FCI In - 1.418 - myCIC_Q.myC1.tmpOutPre_cry_24 ARI1 FCO Out 0.016 1.434 - tmpOutPre_cry_24 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_25 ARI1 FCI In - 1.434 - myCIC_Q.myC1.tmpOutPre_cry_25 ARI1 FCO Out 0.016 1.451 - tmpOutPre_cry_25 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_26 ARI1 FCI In - 1.451 - myCIC_Q.myC1.tmpOutPre_cry_26 ARI1 FCO Out 0.016 1.467 - tmpOutPre_cry_26 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_27 ARI1 FCI In - 1.467 - myCIC_Q.myC1.tmpOutPre_cry_27 ARI1 FCO Out 0.016 1.483 - tmpOutPre_cry_27 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_28 ARI1 FCI In - 1.483 - myCIC_Q.myC1.tmpOutPre_cry_28 ARI1 FCO Out 0.016 1.500 - tmpOutPre_cry_28 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_29 ARI1 FCI In - 1.500 - myCIC_Q.myC1.tmpOutPre_cry_29 ARI1 FCO Out 0.016 1.516 - tmpOutPre_cry_29 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_30 ARI1 FCI In - 1.516 - myCIC_Q.myC1.tmpOutPre_cry_30 ARI1 FCO Out 0.016 1.532 - tmpOutPre_cry_30 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_31 ARI1 FCI In - 1.532 - myCIC_Q.myC1.tmpOutPre_cry_31 ARI1 FCO Out 0.016 1.549 - tmpOutPre_cry_31 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_32 ARI1 FCI In - 1.549 - myCIC_Q.myC1.tmpOutPre_cry_32 ARI1 FCO Out 0.016 1.565 - tmpOutPre_cry_32 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_33 ARI1 FCI In - 1.565 - myCIC_Q.myC1.tmpOutPre_cry_33 ARI1 FCO Out 0.016 1.581 - tmpOutPre_cry_33 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_34 ARI1 FCI In - 1.581 - myCIC_Q.myC1.tmpOutPre_cry_34 ARI1 FCO Out 0.016 1.597 - tmpOutPre_cry_34 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_35 ARI1 FCI In - 1.597 - myCIC_Q.myC1.tmpOutPre_cry_35 ARI1 FCO Out 0.016 1.614 - tmpOutPre_cry_35 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_36 ARI1 FCI In - 1.614 - myCIC_Q.myC1.tmpOutPre_cry_36 ARI1 FCO Out 0.016 1.630 - tmpOutPre_cry_36 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_37 ARI1 FCI In - 1.630 - myCIC_Q.myC1.tmpOutPre_cry_37 ARI1 FCO Out 0.016 1.646 - tmpOutPre_cry_37 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_38 ARI1 FCI In - 1.646 - myCIC_Q.myC1.tmpOutPre_cry_38 ARI1 FCO Out 0.016 1.663 - tmpOutPre_cry_38 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_39 ARI1 FCI In - 1.663 - myCIC_Q.myC1.tmpOutPre_cry_39 ARI1 FCO Out 0.016 1.679 - tmpOutPre_cry_39 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_cry_40 ARI1 FCI In - 1.679 - myCIC_Q.myC1.tmpOutPre_cry_40 ARI1 FCO Out 0.016 1.695 - tmpOutPre_cry_40 Net - - 0.000 - 1 myCIC_Q.myC1.tmpOutPre_s_41 ARI1 FCI In - 1.695 - myCIC_Q.myC1.tmpOutPre_s_41 ARI1 S Out 0.073 1.768 - N_9[41] Net - - 1.123 - 2 myCIC_Q.myC2.tmpOutPre_s_41 ARI1 B In - 2.891 - myCIC_Q.myC2.tmpOutPre_s_41 ARI1 S Out 0.308 3.199 - N_10[41] Net - - 1.123 - 2 myCIC_Q.myC3.tmpOutPre_s_41 ARI1 B In - 4.322 - myCIC_Q.myC3.tmpOutPre_s_41 ARI1 S Out 0.308 4.630 - N_11[41] Net - - 1.123 - 2 myCIC_Q.myC4.tmpOutPre_s_41 ARI1 B In - 5.753 - myCIC_Q.myC4.tmpOutPre_s_41 ARI1 S Out 0.308 6.061 - N_12[41] Net - - 1.123 - 2 myCIC_Q.myC5.tmpOutPre_s_41 ARI1 B In - 7.184 - myCIC_Q.myC5.tmpOutPre_s_41 ARI1 S Out 0.308 7.493 - N_14[13] Net - - 1.117 - 1 myCIC_Q.Delay_RG1_block.GenBlock\.genblk1\.theDelay.outreg[13] SLE D In - 8.610 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 8.865 is 2.478(28.0%) logic and 6.387(72.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: clkDiv128 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------- Downsample_RG1.outp_ds[13] clkDiv128 SLE Q N_Downsample_RG1_1_355[13] 0.087 3191.683 Downsample_RG3.outp_ds[13] clkDiv128 SLE Q N_Downsample_RG3_1_360[13] 0.087 3191.683 Downsample_RG3.outp_ds[0] clkDiv128 SLE Q N_Downsample_RG3_1_360[0] 0.087 3191.687 Downsample_RG1.outp_ds[0] clkDiv128 SLE Q N_Downsample_RG1_1_355[0] 0.087 3191.687 Downsample_RG3.outp_ds[1] clkDiv128 SLE Q N_Downsample_RG3_1_360[1] 0.087 3191.704 Downsample_RG1.outp_ds[1] clkDiv128 SLE Q N_Downsample_RG1_1_355[1] 0.087 3191.704 Downsample_RG3.outp_ds[2] clkDiv128 SLE Q N_Downsample_RG3_1_360[2] 0.087 3191.720 Downsample_RG1.outp_ds[2] clkDiv128 SLE Q N_Downsample_RG1_1_355[2] 0.087 3191.720 Downsample_RG1.outp_ds[3] clkDiv128 SLE Q N_Downsample_RG1_1_355[3] 0.087 3191.736 Downsample_RG3.outp_ds[3] clkDiv128 SLE Q N_Downsample_RG3_1_360[3] 0.087 3191.736 ================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_6_[13] clkDiv128 SLE D un125_mem_s_13_S 3199.745 3191.683 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[13] clkDiv128 SLE D un125_mem_s_13_S_0 3199.745 3191.683 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_15_[13] clkDiv128 SLE D un278_mem_s_13_S_0 3199.745 3191.683 CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_15_[13] clkDiv128 SLE D un278_mem_s_13_S 3199.745 3191.683 CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_6_[12] clkDiv128 SLE D un125_mem_cry_12_S 3199.745 3191.704 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[12] clkDiv128 SLE D un125_mem_cry_12_S_0 3199.745 3191.704 CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_15_[12] clkDiv128 SLE D un278_mem_cry_12_S 3199.745 3191.704 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_15_[12] clkDiv128 SLE D un278_mem_cry_12_S_0 3199.745 3191.704 CFIR_I_PolyphaseFIR_1_block\.myCFIR_I_PolyphaseFIR_1.inner_floop\.mem_6_[11] clkDiv128 SLE D un125_mem_cry_11_S 3199.745 3191.720 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[11] clkDiv128 SLE D un125_mem_cry_11_S_0 3199.745 3191.720 =============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3200.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 3199.745 - Propagation time: 8.062 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3191.683 Number of logic level(s): 3 Starting point: Downsample_RG1.outp_ds[13] / Q Ending point: CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[13] / D The start point is clocked by clkDiv128 [rising] on pin CLK The end point is clocked by clkDiv128 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------- Downsample_RG1.outp_ds[13] SLE Q Out 0.087 0.087 - N_Downsample_RG1_1_355[13] Net - - 1.321 - 64 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.un1_inp_3_mulonly_0[16:0] MACC A[13] In - 1.408 - CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.un1_inp_3_mulonly_0[16:0] MACC P[16] Out 2.586 3.994 - P_9[16] Net - - 1.137 - 10 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.multBufs1pre\[6\]\.multBufs1pre\[6\]_s_17 ARI1 B In - 5.131 - CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.multBufs1pre\[6\]\.multBufs1pre\[6\]_s_17 ARI1 S Out 0.308 5.439 - multBufs1pre\[6\][17] Net - - 1.137 - 10 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.un125_mem_s_13 ARI1 C In - 6.576 - CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.un125_mem_s_13 ARI1 S Out 0.369 6.945 - un125_mem_s_13_S_0 Net - - 1.117 - 1 CFIR_Q_PolyphaseFIR_1_block\.myCFIR_Q_PolyphaseFIR_1.inner_floop\.mem_6_[13] SLE D In - 8.062 - ============================================================================================================================================================== Total path delay (propagation time + setup) of 8.317 is 3.606(43.4%) logic and 4.711(56.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 164MB peak: 173MB) Finished timing report (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 164MB peak: 173MB) --------------------------------------- Resource Usage Report for ddc Mapping to part: m2gl050tfbga896std Cell usage: CLKINT 4 uses CFG1 25 uses CFG2 9 uses CFG3 31 uses CFG4 1 use Carry primitives used for arithmetic functions: ARI1 3334 uses Sequential Cells: SLE 2916 uses DSP Blocks: 22 MACC: 22 Mults I/O ports: 74 I/O primitives: 74 INBUF 46 uses OUTBUF 28 uses Global Clock Buffers: 4 Total LUTs: 3400 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 792; LUTs = 792; Total number of SLEs after P&R: 2916 + 0 + 0 + 792 = 3708; Total number of LUTs after P&R: 3400 + 0 + 0 + 792 = 4192; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 61MB peak: 173MB) Process took 0h:00m:26s realtime, 0h:00m:26s cputime # Thu Mar 03 15:15:47 2016 ###########################################################]