| Project Settings |
|---|
| Project Name | ddc_syn | Implementation Name | synthesis |
| Top Module | work.ddc | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
93 |
191 |
0 |
- |
0m:03s |
- |
3/3/2016
2:53:43 PM |
| (premap) | Complete |
3 |
0 |
0 |
0m:00s |
0m:00s |
156MB |
3/3/2016
2:53:45 PM |
| (fpga_mapper) | Complete |
253 |
24 |
0 |
0m:25s |
0m:25s |
173MB |
3/3/2016
2:54:11 PM |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 3/3/2016
2:53:44 PM |
| Area Summary |
|---|
| |
| Carry Cells | 3334 |
Sequential Cells | 2916 |
| DSP Blocks (MACC)
(dsp_used) | 22 |
I/O Cells | 74 |
| Global Clock Buffers | 4 |
LUTs
(total_luts) | 3400 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| clk | 40.0 MHz | 70.1 MHz | 10.736 |
| clkDiv64 | 0.6 MHz | 1.7 MHz | 1590.892 |
| clkDiv128 | 0.3 MHz | 73.0 MHz | 3191.683 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 3 / 0 |
| |
|