@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN225 |Writing default property annotation file E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\synthesis\ddc.sap.
