@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3748:7:3748:15|Signal n_x_0_653 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3749:7:3749:15|Signal n_y_1_654 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3562:7:3562:15|Signal n_x_0_651 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3563:7:3563:15|Signal n_y_1_652 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3454:7:3454:15|Signal n_x_0_641 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3455:7:3455:15|Signal n_y_1_642 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3646:7:3646:27|Signal n_globalenable1_0_607 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3647:7:3647:18|Signal n_freq_0_608 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3648:7:3648:17|Signal n_sin_1_609 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3649:7:3649:17|Signal n_cos_1_610 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3282:7:3282:18|Signal n_freq_0_605 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3283:7:3283:18|Signal n_pout_1_606 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":3431:7:3431:10|Signal accu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":3434:7:3434:13|Signal addoutu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3087:7:3087:27|Signal n_globalenable1_0_601 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3088:7:3088:21|Signal n_phasein_0_602 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3089:7:3089:17|Signal n_sin_1_603 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3090:7:3090:17|Signal n_cos_1_604 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3000:7:3000:27|Signal n_globalenable1_0_597 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3001:7:3001:19|Signal n_theta_0_598 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3002:7:3002:17|Signal n_sin_1_599 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3003:7:3003:17|Signal n_cos_1_600 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2823:7:2823:27|Signal n_globalenable1_0_593 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2824:7:2824:18|Signal n_z_in_0_594 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2825:7:2825:19|Signal n_x_out_1_595 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2826:7:2826:19|Signal n_y_out_1_596 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2581:7:2581:18|Signal n_z_in_0_590 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2582:7:2582:19|Signal n_x_out_1_591 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2583:7:2583:19|Signal n_y_out_1_592 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2256:7:2256:18|Signal n_x_in_0_585 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2257:7:2257:18|Signal n_y_in_0_586 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2258:7:2258:18|Signal n_z_in_0_587 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2259:7:2259:19|Signal n_x_out_1_588 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2260:7:2260:19|Signal n_y_out_1_589 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2162:7:2162:18|Signal n_z_in_0_581 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2163:7:2163:19|Signal n_x_out_1_582 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2164:7:2164:19|Signal n_y_out_1_583 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2165:7:2165:19|Signal n_z_out_1_584 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1997:7:1997:18|Signal n_x_in_0_575 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1998:7:1998:18|Signal n_y_in_0_576 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1999:7:1999:18|Signal n_z_in_0_577 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2000:7:2000:19|Signal n_x_out_1_578 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2001:7:2001:19|Signal n_y_out_1_579 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2002:7:2002:19|Signal n_z_out_1_580 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1827:7:1827:18|Signal n_x_in_0_569 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1828:7:1828:18|Signal n_y_in_0_570 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1829:7:1829:18|Signal n_z_in_0_571 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1830:7:1830:19|Signal n_x_out_1_572 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1831:7:1831:19|Signal n_y_out_1_573 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1832:7:1832:19|Signal n_z_out_1_574 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1657:7:1657:18|Signal n_x_in_0_563 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1658:7:1658:18|Signal n_y_in_0_564 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1659:7:1659:18|Signal n_z_in_0_565 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1660:7:1660:19|Signal n_x_out_1_566 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1661:7:1661:19|Signal n_y_out_1_567 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1662:7:1662:19|Signal n_z_out_1_568 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1484:7:1484:18|Signal n_x_in_0_557 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1485:7:1485:18|Signal n_y_in_0_558 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1486:7:1486:18|Signal n_z_in_0_559 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1487:7:1487:19|Signal n_x_out_1_560 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1488:7:1488:19|Signal n_y_out_1_561 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1489:7:1489:19|Signal n_z_out_1_562 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1311:7:1311:18|Signal n_x_in_0_551 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1312:7:1312:18|Signal n_y_in_0_552 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1313:7:1313:18|Signal n_z_in_0_553 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1314:7:1314:19|Signal n_x_out_1_554 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1315:7:1315:19|Signal n_y_out_1_555 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1316:7:1316:19|Signal n_z_out_1_556 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1138:7:1138:18|Signal n_x_in_0_545 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1139:7:1139:18|Signal n_y_in_0_546 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1140:7:1140:18|Signal n_z_in_0_547 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1141:7:1141:19|Signal n_x_out_1_548 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1142:7:1142:19|Signal n_y_out_1_549 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1143:7:1143:19|Signal n_z_out_1_550 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":965:7:965:18|Signal n_x_in_0_539 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":966:7:966:18|Signal n_y_in_0_540 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":967:7:967:18|Signal n_z_in_0_541 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":968:7:968:19|Signal n_x_out_1_542 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":969:7:969:19|Signal n_y_out_1_543 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":970:7:970:19|Signal n_z_out_1_544 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":792:7:792:18|Signal n_x_in_0_533 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":793:7:793:18|Signal n_y_in_0_534 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":794:7:794:18|Signal n_z_in_0_535 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":795:7:795:19|Signal n_x_out_1_536 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":796:7:796:19|Signal n_y_out_1_537 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":797:7:797:19|Signal n_z_out_1_538 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":619:7:619:18|Signal n_x_in_0_527 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":620:7:620:18|Signal n_y_in_0_528 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":621:7:621:18|Signal n_z_in_0_529 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":622:7:622:19|Signal n_x_out_1_530 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":623:7:623:19|Signal n_y_out_1_531 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":624:7:624:19|Signal n_z_out_1_532 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":446:7:446:18|Signal n_x_in_0_521 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":447:7:447:18|Signal n_y_in_0_522 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":448:7:448:18|Signal n_z_in_0_523 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":449:7:449:19|Signal n_x_out_1_524 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":450:7:450:19|Signal n_y_out_1_525 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":451:7:451:19|Signal n_z_out_1_526 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":273:7:273:18|Signal n_x_in_0_515 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":274:7:274:18|Signal n_y_in_0_516 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":275:7:275:18|Signal n_z_in_0_517 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":276:7:276:19|Signal n_x_out_1_518 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":277:7:277:19|Signal n_y_out_1_519 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":278:7:278:19|Signal n_z_out_1_520 is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2407:7:2407:19|Signal delaylineclip is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2408:7:2408:11|Signal regsl is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2408:14:2408:18|Signal regsr is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2409:7:2409:9|Signal cnt is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2410:7:2410:18|Signal resetexpired is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2411:7:2411:13|Signal cntdone is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1976:7:1976:10|Signal inps is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1979:7:1979:17|Signal shiftedinps is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1976:7:1976:10|Signal inps is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1979:7:1979:17|Signal shiftedinps is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1977:7:1977:10|Signal inpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1980:7:1980:17|Signal shiftedinpu is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1976:7:1976:10|Signal inps is undriven 
@W: CD638 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1979:7:1979:17|Signal shiftedinps is undriven 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1566:4:1566:6|Input port bit 15 of inp(16 downto 0) is unused 
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bits 19 to 0 of inp(31 downto 0) are unused 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bit 13 of inp(13 downto 0) is unused 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bit 17 of inp(17 downto 0) is unused 
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1622:2:1622:4|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1623:2:1623:14|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1624:2:1624:12|Input GlobalReset is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1792:2:1792:4|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1793:2:1793:14|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1794:2:1794:12|Input GlobalReset is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1566:4:1566:6|Input port bit 17 of inp(17 downto 0) is unused 
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2232:2:2232:5|Input port bits 13 to 0 of z_in(14 downto 0) are unused 
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2227:2:2227:4|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2228:2:2228:14|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2229:2:2229:12|Input GlobalReset is unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bits 33 to 32 of inp(33 downto 0) are unused 
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bits 43 to 42 of inp(43 downto 0) are unused 
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bits 27 to 0 of inp(43 downto 0) are unused 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1566:4:1566:6|Input port bit 44 of inp(44 downto 0) is unused 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1566:4:1566:6|Input port bit 15 of inp(15 downto 0) is unused 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1952:2:1952:4|Input port bit 14 of inp(14 downto 0) is unused 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bits 14 to 8 of mem_22(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bits 14 to 10 of mem_21(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bits 14 to 11 of mem_20(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bits 14 to 12 of mem_19(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bits 14 to 13 of mem_18(14 downto 0)  
@W: CL260 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":205:6:205:7|Pruning register bit 14 of mem_17(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 8 of mem_23(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 9 of mem_22(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 10 of mem_21(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 11 of mem_20(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 12 of mem_19(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 12 of mem_18(14 downto 0)  
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bits 14 to 13 of mem_17(14 downto 0)  
@W: CL260 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":88:6:88:7|Pruning register bit 14 of mem_16(14 downto 0)  

