@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3911:7:3911:9|Top entity is set to ddc.
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3911:7:3911:9|Synthesizing work.ddc.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":22:7:22:27|Synthesizing work.cfir_i_polyphasefir_0.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":4929:7:4929:25|Synthesizing work.syndownsamplesimple.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":139:7:139:27|Synthesizing work.cfir_i_polyphasefir_1.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3698:7:3698:11|Synthesizing work.cic_i.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3530:7:3530:14|Synthesizing work.cic_i_c1.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3498:7:3498:23|Synthesizing work.syncic_i_c1_delay.struct 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3422:7:3422:14|Synthesizing work.cic_i_i1.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3390:7:3390:23|Synthesizing work.syncic_i_i1_delay.struct 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3606:7:3606:9|Synthesizing work.dds.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3229:7:3229:24|Synthesizing work.dds_phasegenerator.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3166:7:3166:33|Synthesizing work.syndds_phasegenerator_shrp2.struct 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3197:7:3197:33|Synthesizing work.syndds_phasegenerator_shrp1.struct 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":3414:7:3414:20|Synthesizing work.synaccumulator.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":3052:7:3052:16|Synthesizing work.dds_sincos.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2969:7:2969:30|Synthesizing work.dds_sincos_cordic_sincos.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2778:7:2778:44|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2361:7:2361:64|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2225:7:2225:77|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg13.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":2133:7:2133:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg1.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1960:7:1960:77|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg10.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1790:7:1790:77|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg11.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1620:7:1620:77|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg12.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1447:7:1447:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg2.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1274:7:1274:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg3.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":1101:7:1101:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg4.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":928:7:928:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg5.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":755:7:755:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg6.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":582:7:582:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg7.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":409:7:409:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg8.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\ddc.vhd":236:7:236:76|Synthesizing work.dds_sincos_cordic_sincos_cordic2_stage_cordic_onequadrant1_cordic_stg9.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":3717:7:3717:15|Synthesizing work.synnegate.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2376:7:2376:31|Synthesizing work.syndelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2603:7:2603:41|Synthesizing work.syndelaywithenable_std_logic_vector.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2275:7:2275:34|Synthesizing work.singledelaywithenablegeneric.structural 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1555:7:1555:18|Synthesizing work.synbussatrnd.behav 
@N: CD630 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":1936:7:1936:19|Synthesizing work.synbusadapter.behav 
@N: CL135 :"E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\VHDL\DDC_top\hdl\SynLib_asynch.vhd":2545:8:2545:9|Found seqShift delayline, depth=10, width=1
@N|Running in 64-bit mode

