# Microsemi Physical design constraints file

# Version: v11.7 11.7.0.119

# Design Name:  

# Input Netlist Format: EDIF 

# Family: IGLOO2 , Die: M2GL050T , Package: 896 FBGA , Speed grade: STD 

# Date generated: Thu Mar 03 15:16:09 2016 


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# IO banks setting
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# Local clock constraints
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# Region constraints
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# I/O constraints
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# Core cell constraints
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