No errors or warnings found.

***** Place and Route Configurations *****

Timing-driven            : ON

Power-driven             : OFF

High-effort              : OFF

Repair min-delay         : ON

Incremental              : OFF

Inter-clock optimization : ON

TDPR scenario            : place_and_route



INFO: No User PDC file(s) was specified.



Running the I/O Bank and Globals Assigner.

Info:  I/O Bank and Globals Assigner identified 0 fixed I/O macros, 74 unfixed I/O macros



I/O Bank and Globals Assigner completed successfully.

Total time spent in I/O Bank and Globals Assigner: 1 seconds




Placer V4.0 - 11.7.0 


Design: ddc                             Started: Thu Mar 03 15:24:19 2016





Initializing Timing-Driven Placement ...


Placing design...


End of placement.


Pre-Placement Runtime        : 3 seconds


Placement Runtime            : 29 seconds





Placer completed successfully.





Design: ddc                             


Finished: Thu Mar 03 15:25:17 2016


Total CPU Time:     00:00:56            Total Elapsed Time: 00:00:58


Total Memory Usage: 567.1 Mbytes


                        o - o - o - o - o - o








Router 


Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddcStarted: Thu Mar 03 15:25:25 2016








Router completed successfully.





Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddc


Finished: Thu Mar 03 15:25:50 2016


Total CPU Time:     00:00:24            Total Elapsed Time: 00:00:25


Total Memory Usage: 1934.8 Mbytes


                        o - o - o - o - o - o





Info: Iteration 1:

  Number of violating paths: 8

  Worst minimum delay slack: -0.036 ns




Router 


Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddcStarted: Thu Mar 03 15:26:18 2016





Loading routing information for ECO mode...


After loading previous routing information: Shorts = 0. Open nets = 16.





Router completed successfully.





Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddc


Finished: Thu Mar 03 15:26:38 2016


Total CPU Time:     00:00:20            Total Elapsed Time: 00:00:20


Total Memory Usage: 1929.7 Mbytes


                        o - o - o - o - o - o





Info: Iteration 2:

  Number of violating paths: 1

  Worst minimum delay slack: -0.011 ns




Router 


Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddcStarted: Thu Mar 03 15:27:06 2016





Loading routing information for ECO mode...


After loading previous routing information: Shorts = 0. Open nets = 2.





Router completed successfully.





Design: E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddc


Finished: Thu Mar 03 15:27:27 2016


Total CPU Time:     00:00:20            Total Elapsed Time: 00:00:21


Total Memory Usage: 1929.7 Mbytes


                        o - o - o - o - o - o





Info: Iteration 3:

  Number of violating paths: 0

  Worst minimum delay slack: 

Resource Usage

+---------------+------+-------+------------+

| Type          | Used | Total | Percentage |

+---------------+------+-------+------------+

| 4LUT          | 4192 | 56340 | 7.44       |

| DFF           | 3688 | 56340 | 6.55       |

| I/O Register  | 0    | 1125  | 0.00       |

| Logic Element | 4566 | 56340 | 8.10       |

+---------------+------+-------+------------+



