<?xml version="1.0" encoding="UTF-8" standalone="no" ?><TCML xmlns="tcml"><Scenario Id="Primary"/><Scenario Id="place_and_route"><clock Id="1"><name>clk</name><period>25</period><waveform>0 12.5</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clk }]</orig_string><macro><type>PORT</type><pattern>clk</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/place_route.sdc</file><line>7</line></origin></clock><clock Id="2"><name>clkDiv64</name><period>1600</period><waveform>0 800</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clkDiv64 }]</orig_string><macro><type>PORT</type><pattern>clkDiv64</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/place_route.sdc</file><line>8</line></origin></clock><clock Id="3"><name>clkDiv128</name><period>3200</period><waveform>0 1600</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clkDiv128 }]</orig_string><macro><type>PORT</type><pattern>clkDiv128</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/place_route.sdc</file><line>9</line></origin></clock></Scenario><Scenario Id="timing_analysis"><clock Id="4"><name>clk</name><period>25</period><waveform>0 12.5</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clk }]</orig_string><macro><type>PORT</type><pattern>clk</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/timing_analysis.sdc</file><line>7</line></origin></clock><clock Id="5"><name>clkDiv64</name><period>1600</period><waveform>0 800</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clkDiv64 }]</orig_string><macro><type>PORT</type><pattern>clkDiv64</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/timing_analysis.sdc</file><line>8</line></origin></clock><clock Id="6"><name>clkDiv128</name><period>3200</period><waveform>0 1600</waveform><source><type>CLOCK_SRC</type><toolcontext>SDC_USER</toolcontext><orig_string>[get_ports { clkDiv128 }]</orig_string><macro><type>PORT</type><pattern>clkDiv128</pattern></macro></source><comment/><origin><file>E:/Libero_11p7_updates/LL_11p6/m2gl_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/designer/ddc/timing_analysis.sdc</file><line>9</line></origin></clock></Scenario></TCML>