set_family {IGLOO2}
read_adl {E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\ddc.adl}
map_netlist
read_sdc {E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\constraint\ddc.sdc}
check_constraints {E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\constraint\placer_sdc_errors.log}
write_sdc -strict {E:\Libero_11p7_updates\LL_11p6\m2gl_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\place_route.sdc}
