| Project Settings |
|---|
| Project Name | demo_syn | Implementation Name | synthesis |
| Top Module | demo | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
48 |
216 |
0 |
- |
0m:01s |
- |
27-04-2016
PM 07:22:49 |
| (premap) | Complete |
94 |
11 |
0 |
0m:00s |
0m:00s |
145MB |
27-04-2016
PM 07:22:52 |
| (fpga_mapper) | Complete |
25 |
29 |
0 |
0m:01s |
0m:01s |
138MB |
27-04-2016
PM 07:22:53 |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 27-04-2016
PM 07:22:51 |
| Area Summary |
|---|
| |
| Carry Cells | 32 |
Sequential Cells | 33 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 4 |
| Global Clock Buffers | 2 |
LUTs
(total_luts) | 61 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| demo_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 276.5 MHz | 6.383 |
| System | 100.0 MHz | 1029.4 MHz | 9.029 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|