@W: MO111 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module demo_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module demo_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module demo_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module demo_sb_FABOSC_0_OSC) 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance demo_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel is always 0, optimizing ...
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance demo_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":50:18:50:22|Removing user instance BLINK_LED_0.LED4_2,  because it is equivalent to instance BLINK_LED_0.LED3_2
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":49:18:49:22|Removing user instance BLINK_LED_0.LED3_2,  because it is equivalent to instance BLINK_LED_0.LED1_2
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":33:0:33:5|Removing sequential instance BLINK_LED_0.LED4,  because it is equivalent to instance BLINK_LED_0.LED3
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":33:0:33:5|Removing sequential instance BLINK_LED_0.LED3,  because it is equivalent to instance BLINK_LED_0.LED1
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":48:18:48:22|Removing user instance BLINK_LED_0.LED2_2,  because it is equivalent to instance BLINK_LED_0.LED1_2
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\sample\demo\hdl\blink1.v":33:0:33:5|Removing sequential instance BLINK_LED_0.LED2,  because it is equivalent to instance BLINK_LED_0.LED1
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] is always 0, optimizing ...
@W: MO161 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[13] is always 1, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[0] is always 0, optimizing ...
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[14] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[10] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[6] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[2] removed due to constant propagation
@W: MT246 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\ccc_0\demo_sb_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock demo_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:demo_sb_0.CCC_0.GL0_net"
