@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS of view:PrimLib.dffre(prim) in hierarchy view:work.demo_sb(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:work.demo_sb(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":496:4:496:9|Removing sequential instance demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_q1 in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":565:4:565:9|Removing sequential instance demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":526:4:526:9|Removing sequential instance demo_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":511:4:511:9|Removing sequential instance demo_sb_0.CORERESETP_0.RESET_N_M2F_clk_base in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":496:4:496:9|Removing sequential instance demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":526:4:526:9|Removing sequential instance demo_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":511:4:511:9|Removing sequential instance demo_sb_0.CORERESETP_0.RESET_N_M2F_q1 in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":545:4:545:9|Removing sequential instance demo_sb_0.CORERESETP_0.mss_ready_state in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":545:4:545:9|Removing sequential instance demo_sb_0.CORERESETP_0.mss_ready_select in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN114 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb\demo_sb.v":788:9:788:20|Removing instance demo_sb_0.SYSRESET_POR of black_box view:ACG4.SYSRESET(PRIM) because there are no references to its outputs 
@N: BN114 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\work\demo_sb_hpms\demo_sb_hpms.v":243:0:243:13|Removing instance demo_sb_0.demo_sb_HPMS_0.MSS_ADLIB_INST of black_box view:work.MSS_010(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance demo_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance demo_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\iap_igl2\010\11.7\sample\demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance demo_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[1] in hierarchy view:work.demo(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net demo_sb_0_FIC_0_LOCK on CLKINT  I_38 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
