#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-DONTHUS1 #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\Debounce.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\AXI_MASTER_TO_SLAVE.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\Controller.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\IAP_INIT.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\IAP_CTRL\IAP_CTRL.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\PCIe_AXI_IF.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\SPI_Erase.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\SPI_PROGRAM.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\IAP\IAP.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\SgCore\TAMPER\2.1.200\tamper_comps.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\LSRAM_TAMPER\TAMPER_0\LSRAM_TAMPER_TAMPER_0_TAMPER.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\LSRAM_TAMPER\TPSRAM_0\LSRAM_TAMPER_TPSRAM_0_TPSRAM.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\Ram_interface.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\LSRAM_TAMPER\LSRAM_TAMPER.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP\SERDES_IF_0\PCIE_IAP_SERDES_IF_0_SERDES_IF_syn.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP\SERDES_IF_0\PCIE_IAP_SERDES_IF_0_SERDES_IF.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP_sb\CCC_0\PCIE_IAP_sb_CCC_0_FCCC.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP_sb_HPMS\PCIE_IAP_sb_HPMS_syn.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP_sb_HPMS\PCIE_IAP_sb_HPMS.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP_sb\PCIE_IAP_sb.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\hdl\HOTRESET.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\acmtable.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\debugblk.v" @I:"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\debugblk.v":"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\support.v" @N:CG334 : debugblk.v(68) | Read directive translate_off @N:CG333 : debugblk.v(745) | Read directive translate_on @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\instructions.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\instructnvm_bb.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\iram512x9_rtl.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\instructram.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram256x8_rtl.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ramblocks.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v" @N:CG334 : coreabc.v(982) | Read directive translate_off @N:CG333 : coreabc.v(984) | Read directive translate_on @N:CG334 : coreabc.v(1379) | Read directive translate_off @N:CG333 : coreabc.v(1423) | Read directive translate_on @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\SERDES_INIT\SERDES_INIT.v" @I::"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\component\work\PCIE_IAP\PCIE_IAP.v" Verilog syntax check successful! Selecting top level module PCIE_IAP @N:CG364 : igloo2.v(126) | Synthesizing module AND2 @N:CG364 : Debounce.v(20) | Synthesizing module DEBOUNCE @N:CG179 : Debounce.v(81) | Removing redundant assignment @N:CG364 : AXI_MASTER_TO_SLAVE.v(21) | Synthesizing module AXI_MASTER_TO_SLAVE ID_BITS=32'b00000000000000000000000000000100 ADDR_WIDTH=32'b00000000000000000000000000100000 Generated name = AXI_MASTER_TO_SLAVE_4s_32s @N:CG364 : Controller.v(23) | Synthesizing module Controller @W:CL271 : Controller.v(244) | Pruning bits 31 to 16 of raddr_int[31:0] -- not in use ... @W:CL271 : Controller.v(133) | Pruning bits 31 to 16 of waddr_int[31:0] -- not in use ... @A:CL282 : Controller.v(244) | Feedback mux created for signal RID[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : Controller.v(133) | Feedback mux created for signal BID[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CG775 : CoreSysServices.v(30) | Found Component IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB @N:CG364 : CoreSysServices_UserIF.v(30) | Synthesizing module CoreSysServices_UserIF SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000001 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = CoreSysServices_UserIF_Z1 @W:CL169 : CoreSysServices_UserIF.v(789) | Pruning register cuhprior_flushdone_d3 @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning register pord_d1 @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning register pord_d2 @W:CL169 : CoreSysServices_UserIF.v(592) | Pruning register custatus_out_en_r @W:CL169 : CoreSysServices_UserIF.v(522) | Pruning register pord_comb_d1 @W:CL207 : CoreSysServices_UserIF.v(719) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL190 : CoreSysServices_UserIF.v(505) | Optimizing register bit hprior_kp_busy_high to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[0] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[2] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[3] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[4] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[5] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[0] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[1] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[3] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[5] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[6] to a constant 0 @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[7] to a constant 0 @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 5 to 2 of uclatchoptions_hold[5:0] @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 0 of uclatchoptions_hold[5:0] @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0] @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 3 of ucmdbyte_req_hold[7:0] @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0] @W:CL169 : CoreSysServices_UserIF.v(505) | Pruning register hprior_kp_busy_high @N:CG364 : igloo2.v(835) | Synthesizing module FLASH_FREEZE @N:CG364 : CoreSysServices_CmdDec.v(30) | Synthesizing module CoreSysServices_CmdDec SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000001 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 C_IDLE=2'b00 C_REQ_PHASE=2'b01 C_RESP_PHASE=2'b10 REQ_IDLE=6'b000000 REQ_WAIT_MEMWR1=6'b000001 REQ_MEMWR_DESC=6'b000010 REQ_WAIT_MEMWR2=6'b000011 REQ_MEMWR_DATA=6'b000100 REQ_PHASE=6'b000101 REQ_FIIC_INT=6'b000111 REQ_POLL_CINT1=6'b001000 REQ_RDCOMM_STATUS1=6'b001001 REQ_WRCOMM_CTRL=6'b001010 REQ_WRCOMM_INT=6'b001011 REQ_WRCOMM_FRM=6'b001100 REQ_WRCOMM_DATA=6'b001101 REQ_POLL_CINT2=6'b001110 REQ_RDCOMM_STATUS2=6'b001111 REQ_WAIT_REG1=6'b010000 REQ_WAIT_REG2=6'b010001 REQ_WAIT_REG3=6'b010010 REQ_WAIT_REG4=6'b010011 REQ_WAIT_REG5=6'b010100 REQ_WAIT_REG6=6'b010101 REQ_WAIT_REG7=6'b010110 REQ_WAIT_REG8=6'b010111 REQ_WAIT_REG9=6'b011000 REQ_RD_INT=6'b011011 REQ_RDCOMM_INT=6'b011100 REQ_WAIT_REG10=6'b100001 REQ_WAIT_REG11=6'b100010 REQ_WAIT_REG12=6'b100011 REQ_WAIT_REG13=6'b100100 REQ_WRCOMM_CTRL2=6'b100101 REQ_WRCOMM_CTRL3=6'b100110 REQ_WRCOMM_CTRL4=6'b100111 REQ_WRCOMM_INT2=6'b101000 REQ_WAIT_MEMWR22=6'b101001 REQ_MEMWR_DATA1=6'b101010 REQ_WAIT_ASYNCRD1=6'b101011 REQ_RDCOMM_ASYNCFRM1=6'b101100 REQ_WAIT_ASYNCRD2=6'b101101 REQ_RDCOMM_ASYNCFRM2=6'b101110 REQ_ASYNC_OUT1=6'b110000 REQ_ASYNC_OUT2=6'b110001 REQ_WAIT_REG14=6'b110010 REQ_WRCOMM_DESC2=6'b110011 REQ_WAIT_REG15=6'b110100 RESP_IDLE=6'b000000 RESP_PHASE=6'b000001 RESP_RDCOMM_STATUS=6'b000011 RESP_RDCOMM_FRM=6'b000100 RESP_RDCOMM_DESC=6'b000101 RESP_RDCOMM_DATA=6'b000110 RESP_WAIT_MEMRD=6'b000111 RESP_MEMRD=6'b001000 RESP_POLL_CINT1=6'b001001 RESP_POLL_CINT4=6'b001100 RESP_REG1=6'b001101 RESP_REG4=6'b010000 RESP_REG5=6'b010001 RESP_REG6=6'b010010 RESP_REG7=6'b010011 RESP_REG8=6'b010100 RESP_REG9=6'b010101 RESP_WRCOMM_CTRL1=6'b010110 RESP_WAIT_REG11=6'b010111 RESP_WRCOMM_CTRL2=6'b011000 RESP_WAIT_REG12=6'b011001 RESP_RDCOMM_STATUS3=6'b011011 RESP_WRCOMM_INT3=6'b100100 RESP_WAIT_REG13=6'b100101 RESP_FIIC_INT=6'b100110 RESP_WAIT_REG14=6'b100111 RESP_WAIT_ASYNCRD1=6'b101000 RESP_RDCOMM_ASYNCFRM1=6'b101001 RESP_ASYNC_OUT1=6'b101100 RESP_WAIT_ASYNCRD3=6'b101110 RESP_RDCOMM_ASYNCFRM3=6'b101111 RESP_ASYNC_OUT3=6'b110000 ASYNCEVENT_POLL_IDLE=4'b0000 ASYNCEVENT_POLL_WAIT=4'b0001 ASYNCEVENT_POLL_CINT=4'b0010 ASYNCEVENT_REG1=4'b0011 ASYNCEVENT_RDCOMM_STATUS=4'b0100 ASYNCEVENT_WAIT_RD1=4'b0101 ASYNCEVENT_RDCOMM_FRM1=4'b0110 ASYNCEVENT_RDCOMM_OUT1=4'b0111 ASYNCEVENT_WAIT=4'b1000 ASYNCEVENT_PHASE=4'b1001 ASYNCEVENT_WAIT_REG11=4'b1010 ASYNCEVENT_WRCOMM_CTRL1=4'b1011 ASYNCEVENT_WAIT_REG13=4'b1100 ASYNCEVENT_FIIC_INT=4'b1101 ASYNCEVENT_WAIT_REG14=4'b1110 ASYNCEVENT_WRCOMM_INT3=4'b1111 COMM_CTRL_REG=32'b01000000000000010110000000000000 COMM_STATUS_REG=32'b01000000000000010110000000000100 COMM_INTEN_REG=32'b01000000000000010110000000001000 COMM_DATA8_REG=32'b01000000000000010110000000010000 COMM_DATA32_REG=32'b01000000000000010110000000010100 COMM_FRM8_REG=32'b01000000000000010110000000011000 COMM_FRM32_REG=32'b01000000000000010110000000011100 Generated name = CoreSysServices_CmdDec_Z2 @N:CG179 : CoreSysServices_CmdDec.v(1912) | Removing redundant assignment @W:CG133 : CoreSysServices_CmdDec.v(418) | No assignment to cfwr_req_d1 @W:CG133 : CoreSysServices_CmdDec.v(436) | No assignment to cfsrc_addr_int @W:CG133 : CoreSysServices_CmdDec.v(437) | No assignment to cfdst_addr_int @W:CG133 : CoreSysServices_CmdDec.v(447) | No assignment to memwr_data @W:CG133 : CoreSysServices_CmdDec.v(470) | No assignment to req_srcreg_addr @W:CG133 : CoreSysServices_CmdDec.v(472) | No assignment to req_srcreg_data @W:CG133 : CoreSysServices_CmdDec.v(512) | No assignment to cuhprior_flushdone_d1 @W:CG360 : CoreSysServices_CmdDec.v(555) | No assignment to wire cfwr_req_int @W:CG360 : CoreSysServices_CmdDec.v(557) | No assignment to wire cfwr_req_c @W:CG360 : CoreSysServices_CmdDec.v(563) | No assignment to wire cfdata_w_o @W:CL168 : CoreSysServices_CmdDec.v(2927) | Pruning instance FLASH_FREEZE_0 -- not in use ... @W:CL169 : CoreSysServices_CmdDec.v(2980) | Pruning register FF_exit @W:CL169 : CoreSysServices_CmdDec.v(2962) | Pruning register FF_exit_led @W:CL169 : CoreSysServices_CmdDec.v(2949) | Pruning register FF_entry_led @W:CL169 : CoreSysServices_CmdDec.v(2939) | Pruning register FF_entry @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning register cunvm_bfr_iapverify_done_d1 @W:CL169 : CoreSysServices_CmdDec.v(2770) | Pruning register latchen_hrdata_r @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning register fiicreg_done_d1 @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning register commctrlreg_done_d1 @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning register commpoll_done_d1 @W:CL169 : CoreSysServices_CmdDec.v(1924) | Pruning register set_puf_getkcnum_r @W:CL169 : CoreSysServices_CmdDec.v(1906) | Pruning register wait_count[2:0] @W:CL169 : CoreSysServices_CmdDec.v(1731) | Pruning register fctrans_done_d2 @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning register pord_d1 @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning register pord_d2 @W:CL169 : CoreSysServices_CmdDec.v(1582) | Pruning register req_phase_active_pulse @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning register resp_data_done_d1 @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning register req_phase_active_d1 @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning register resp_desc_done @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning register resp_frm_done @W:CL169 : CoreSysServices_CmdDec.v(1015) | Pruning register req_desc_done @W:CL271 : CoreSysServices_CmdDec.v(1924) | Pruning bits 31 to 8 of fcdataout_d1[31:0] -- not in use ... @W:CL113 : CoreSysServices_CmdDec.v(2811) | Feedback mux created for signal cutamper_msg[7:0]. @W:CL207 : CoreSysServices_CmdDec.v(2786) | All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization. @N:CL177 : CoreSysServices_CmdDec.v(2461) | Sharing sequential element fcpop_d1. @N:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_fail_valid_r. @N:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_detect_valid_r. @W:CL207 : CoreSysServices_CmdDec.v(1594) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL250 : CoreSysServices_CmdDec.v(2811) | All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_detect_valid to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_fail_valid to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[0] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[2] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[5] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[6] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[8] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[9] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[10] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[11] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[12] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[13] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[14] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[15] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[16] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[17] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[18] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[19] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[20] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[21] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[22] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[23] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[24] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[25] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[26] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[27] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[28] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[30] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[31] to a constant 0 @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 31 of resp_srcreg_addr_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0] @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 15 of resp_srcreg_addr_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0] @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0] @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 2 of resp_srcreg_data_d1[31:0] @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 0 of resp_srcreg_data_d1[31:0] @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning register cutamper_detect_valid @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning register cutamper_fail_valid @N:CG364 : CoreSysServices_FSMCtrl.v(30) | Synthesizing module CoreSysServices_FSMCtrl @W:CG133 : CoreSysServices_FSMCtrl.v(236) | No assignment to rvalid_out_en_d1 @W:CG133 : CoreSysServices_FSMCtrl.v(237) | No assignment to rvalid_out_en_d2 @W:CG360 : CoreSysServices_FSMCtrl.v(245) | No assignment to wire fmhaddr_lat @W:CL169 : CoreSysServices_FSMCtrl.v(952) | Pruning register busreq_prev @W:CL169 : CoreSysServices_FSMCtrl.v(934) | Pruning register pop_d1 @W:CL169 : CoreSysServices_FSMCtrl.v(868) | Pruning register fmhtrans_int2[1:0] @W:CL169 : CoreSysServices_FSMCtrl.v(732) | Pruning register haddr_prev[29:0] @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning register latch_addr_d2 @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning register latch_addr_d3 @W:CL169 : CoreSysServices_FSMCtrl.v(639) | Pruning register latch_addr_d1 @W:CL169 : CoreSysServices_FSMCtrl.v(627) | Pruning register state_prev_clk[3:0] @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[1] to a constant 0 @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[2] to a constant 0 @W:CL190 : CoreSysServices_FSMCtrl.v(853) | Optimizing register bit fmhtrans_int[0] to a constant 0 @W:CL260 : CoreSysServices_FSMCtrl.v(853) | Pruning register bit 0 of fmhtrans_int[1:0] @W:CL279 : CoreSysServices_FSMCtrl.v(293) | Pruning register bits 2 to 1 of fmhburst_d1[2:0] @N:CG364 : CoreSysServices_AHBLMasterIF.v(30) | Synthesizing module CoreSysServices_AHBLMasterIF @N:CG364 : CoreSysServices.v(30) | Synthesizing module IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000001 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES_Z3 @W:CG360 : CoreSysServices.v(259) | No assignment to wire cfburst_len_o @W:CG360 : CoreSysServices.v(265) | No assignment to wire ustatus_resp_o @W:CG360 : CoreSysServices.v(266) | No assignment to wire ubusy_o @W:CG360 : CoreSysServices.v(267) | No assignment to wire udata_en_o @W:CG360 : CoreSysServices.v(268) | No assignment to wire udata_valid_o @W:CG360 : CoreSysServices.v(269) | No assignment to wire udata_r_o @W:CG360 : CoreSysServices.v(275) | No assignment to wire uclatchpord_o @W:CG360 : CoreSysServices.v(281) | No assignment to wire uccrypto_opmode_o @W:CG360 : CoreSysServices.v(304) | No assignment to wire cudata_wen_o @N:CG364 : IAP_INIT.v(23) | Synthesizing module IAP_INIT @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[0] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[1] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[3] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[5] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[6] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_CMDBYTE_REQ[7] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_OPTIONS_MODE[2] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_OPTIONS_MODE[3] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_OPTIONS_MODE[4] to a constant 0 @W:CL190 : IAP_INIT.v(50) | Optimizing register bit SERV_OPTIONS_MODE[5] to a constant 0 @W:CL279 : IAP_INIT.v(50) | Pruning register bits 5 to 2 of SERV_OPTIONS_MODE[5:0] @W:CL279 : IAP_INIT.v(50) | Pruning register bits 7 to 5 of SERV_CMDBYTE_REQ[7:0] @W:CL260 : IAP_INIT.v(50) | Pruning register bit 3 of SERV_CMDBYTE_REQ[7:0] @W:CL279 : IAP_INIT.v(50) | Pruning register bits 1 to 0 of SERV_CMDBYTE_REQ[7:0] @N:CG364 : IAP_CTRL.v(9) | Synthesizing module IAP_CTRL @N:CG364 : PCIe_AXI_IF.v(21) | Synthesizing module PCIe_AXI_IF Xfer_size=6'b010000 Idle_0=3'b000 Idle_1=3'b001 Write_0=3'b010 Write_1=3'b011 Read_0=3'b010 Read_1=3'b011 Read_2=3'b100 Bresp_0=3'b100 Write_2=3'b101 Generated name = PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4 @N:CG179 : PCIe_AXI_IF.v(379) | Removing redundant assignment @W:CG133 : PCIe_AXI_IF.v(84) | No assignment to ddr_wr_st @A:CL282 : PCIe_AXI_IF.v(191) | Feedback mux created for signal burst_cnt[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : PCIe_AXI_IF.v(127) | Optimizing register bit AWSIZE[0] to a constant 1 @W:CL190 : PCIe_AXI_IF.v(127) | Optimizing register bit AWSIZE[1] to a constant 1 @W:CL190 : PCIe_AXI_IF.v(281) | Optimizing register bit ARSIZE[0] to a constant 1 @W:CL190 : PCIe_AXI_IF.v(281) | Optimizing register bit ARSIZE[1] to a constant 1 @W:CL169 : PCIe_AXI_IF.v(281) | Pruning register ARSIZE[1:0] @W:CL169 : PCIe_AXI_IF.v(127) | Pruning register AWSIZE[1:0] @N:CG364 : SPI_Erase.v(20) | Synthesizing module SPI_Erase @W:CL169 : SPI_Erase.v(124) | Pruning register read_byte[3][7:0] @W:CL169 : SPI_Erase.v(124) | Pruning register read_byte[2][7:0] @W:CL169 : SPI_Erase.v(124) | Pruning register read_byte[0][7:0] @W:CL271 : SPI_Erase.v(124) | Pruning bits 7 to 1 of read_byte[1][7:0] -- not in use ... @A:CL282 : SPI_Erase.v(124) | Feedback mux created for signal read_byte[1][0:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : SPI_Erase.v(124) | Optimizing register bit init_idx_cnt[1] to a constant 0 @W:CL260 : SPI_Erase.v(124) | Pruning register bit 1 of init_idx_cnt[2:0] @N:CG364 : SPI_PROGRAM.v(20) | Synthesizing module SPI_PROGRAM @W:CL169 : SPI_PROGRAM.v(133) | Pruning register read_byte[3][7:0] @W:CL169 : SPI_PROGRAM.v(133) | Pruning register read_byte[2][7:0] @W:CL169 : SPI_PROGRAM.v(133) | Pruning register read_byte[0][7:0] @W:CL271 : SPI_PROGRAM.v(133) | Pruning bits 7 to 1 of read_byte[1][7:0] -- not in use ... @A:CL282 : SPI_PROGRAM.v(133) | Feedback mux created for signal read_byte[1][0:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : SPI_PROGRAM.v(133) | Optimizing register bit init_idx_cnt[1] to a constant 0 @W:CL260 : SPI_PROGRAM.v(133) | Pruning register bit 1 of init_idx_cnt[2:0] @N:CG364 : IAP.v(9) | Synthesizing module IAP @N:CG364 : Ram_interface.v(20) | Synthesizing module Ram_intferface @N:CG364 : igloo2.v(376) | Synthesizing module VCC @N:CG364 : tamper_comps.v(1) | Synthesizing module TAMPER @N:CG364 : LSRAM_TAMPER_TAMPER_0_TAMPER.v(5) | Synthesizing module LSRAM_TAMPER_TAMPER_0_TAMPER @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 @N:CG364 : igloo2.v(372) | Synthesizing module GND @N:CG364 : LSRAM_TAMPER_TPSRAM_0_TPSRAM.v(5) | Synthesizing module LSRAM_TAMPER_TPSRAM_0_TPSRAM @N:CG364 : LSRAM_TAMPER.v(9) | Synthesizing module LSRAM_TAMPER @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT @N:CG364 : igloo2.v(727) | Synthesizing module CCC @N:CG364 : PCIE_IAP_sb_CCC_0_FCCC.v(5) | Synthesizing module PCIE_IAP_sb_CCC_0_FCCC @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z5 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z6 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z7 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b10000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_65536_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b1 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b1 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b10000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z8 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z9 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : PCIE_IAP_sb_FABOSC_0_OSC.v(5) | Synthesizing module PCIE_IAP_sb_FABOSC_0_OSC @N:CG364 : PCIE_IAP_sb_HPMS_syn.v(5) | Synthesizing module MSS_010 @N:CG364 : igloo2.v(286) | Synthesizing module BIBUF @N:CG364 : igloo2.v(268) | Synthesizing module INBUF @N:CG364 : igloo2.v(280) | Synthesizing module TRIBUFF @N:CG364 : PCIE_IAP_sb_HPMS.v(9) | Synthesizing module PCIE_IAP_sb_HPMS @N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET @N:CG364 : PCIE_IAP_sb.v(9) | Synthesizing module PCIE_IAP_sb @N:CG364 : igloo2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : PCIE_IAP_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0 @N:CG364 : PCIE_IAP_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module PCIE_IAP_SERDES_IF_0_SERDES_IF @N:CG364 : coreabc.v(46) | Synthesizing module SERDES_INIT_COREABC_0_COREABC FAMILY=32'b00000000000000000000000000011000 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000010000 ICWIDTH=32'b00000000000000000000000000001100 ZRWIDTH=32'b00000000000000000000000000000000 IFWIDTH=32'b00000000000000000000000000000000 IIWIDTH=32'b00000000000000000000000000000001 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000000100 EN_RAM=32'b00000000000000000000000000000001 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000000 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000000 EN_SHL=32'b00000000000000000000000000000000 EN_SHR=32'b00000000000000000000000000000000 EN_CALL=32'b00000000000000000000000000000000 EN_PUSH=32'b00000000000000000000000000000000 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000000 EN_IOWRT=32'b00000000000000000000000000000000 EN_ALURAM=32'b00000000000000000000000000000000 EN_INDIRECT=32'b00000000000000000000000000000000 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000000 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000010101 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000001000000000000 APB_SWIDTH=32'b00000000000000000000000000000100 RAMWIDTH=32'b00000000000000000000000000111010 SYNC_RESET=32'b00000000000000000000000000000000 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = SERDES_INIT_COREABC_0_COREABC_Z10 @N:CG364 : ramblocks.v(25) | Synthesizing module SERDES_INIT_COREABC_0_RAMBLOCKS DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011000 Generated name = SERDES_INIT_COREABC_0_RAMBLOCKS_32s_24s @N:CG364 : ram256x16_rtl.v(20) | Synthesizing module SERDES_INIT_COREABC_0_RAM256X16 @N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16 @W:CG360 : ramblocks.v(38) | No assignment to wire RDW @W:CG360 : ramblocks.v(44) | No assignment to wire RDYY @N:CG364 : instructions.v(26) | Synthesizing module SERDES_INIT_COREABC_0_INSTRUCTIONS AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000100 ICWIDTH=32'b00000000000000000000000000001100 IIWIDTH=32'b00000000000000000000000000000001 IFWIDTH=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000000 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000100 IW=32'b00000000000000000000000000001100 FW=32'b00000000000000000000000000000101 iJUMP=32'b00000000000000000010001000000000 iCALL=32'b00000000000000000010001100000000 iRETURN=32'b00000000000000000010010000000000 iRETISR=32'b00000000000000000010010100000000 iWAIT=32'b00000000000000000010011000000000 iHALT=32'b00000000000000000010011000000000 iINC=32'b00000000000000000000001100000001 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Label_WaitSdifRelease=32'b00000000000000000000000000001010 Label_WaitPcie0PmaReady=32'b00000000000000000000000000010001 Generated name = SERDES_INIT_COREABC_0_INSTRUCTIONS_Z11 @W:CG133 : coreabc.v(686) | No assignment to MULT @W:CG133 : coreabc.v(687) | No assignment to A @W:CG133 : coreabc.v(688) | No assignment to B @W:CG133 : coreabc.v(1348) | No assignment to b @W:CG360 : coreabc.v(227) | No assignment to wire DEBUG1 @W:CG360 : coreabc.v(228) | No assignment to wire DEBUG2 @W:CG360 : coreabc.v(229) | No assignment to wire DEBUGBLK_RESETN @W:CG133 : coreabc.v(255) | No assignment to iii @W:CG133 : coreabc.v(256) | No assignment to RAMDOUTXX @W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr @W:CL169 : coreabc.v(1031) | Pruning register ZREGISTER[0] @W:CL169 : coreabc.v(1031) | Pruning register STKPTR[7:0] @W:CL169 : coreabc.v(1031) | Pruning register GETINST @W:CL169 : coreabc.v(501) | Pruning register UROM.upper_addr[7:0] @W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1031) | All reachable assignments to IO_OUT[0] assign 0, register removed by optimization. @W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @W:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ... @W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0] @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z12 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000000 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000000 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z13 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @W:CL169 : coreresetp.v(676) | Pruning register SDIF0_PERST_N_q1 @W:CL169 : coreresetp.v(676) | Pruning register SDIF0_PERST_N_q2 @W:CL169 : coreresetp.v(676) | Pruning register SDIF0_PERST_N_q3 @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL189 : coreresetp.v(676) | Register bit SDIF0_PERST_N_re is always 0, optimizing ... @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : HOTRESET.v(31) | Synthesizing module HOTRESET @A:CL282 : HOTRESET.v(273) | Feedback mux created for signal HOT_RESET_N_PULSE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CG364 : SERDES_INIT.v(9) | Synthesizing module SERDES_INIT @N:CG364 : PCIE_IAP.v(9) | Synthesizing module PCIE_IAP @N:CL201 : HOTRESET.v(194) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : HOTRESET.v(36) | Input port bit 31 of PRDATA[31:0] is unused @W:CL246 : HOTRESET.v(36) | Input port bits 25 to 0 of PRDATA[31:0] are unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(80) | Input SDIF0_PERST_N is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : ram256x16_rtl.v(23) | Input RESET is unused @N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : coreabc.v(134) | Input PSLVERR_M is unused @W:CL159 : coreabc.v(135) | Input IO_IN is unused @W:CL159 : coreabc.v(138) | Input INTREQ is unused @W:CL159 : coreabc.v(141) | Input INITDATVAL is unused @W:CL159 : coreabc.v(142) | Input INITDONE is unused @W:CL159 : coreabc.v(143) | Input INITADDR is unused @W:CL159 : coreabc.v(144) | Input INITDATA is unused @W:CL159 : coreabc.v(148) | Input PSEL_S is unused @W:CL159 : coreabc.v(149) | Input PENABLE_S is unused @W:CL159 : coreabc.v(150) | Input PWRITE_S is unused @W:CL159 : coreabc.v(151) | Input PADDR_S is unused @W:CL159 : coreabc.v(152) | Input PWDATA_S is unused @W:CL247 : PCIE_IAP_sb_HPMS.v(56) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : PCIE_IAP_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIE_IAP_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : PCIE_IAP_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIE_IAP_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : PCIE_IAP_sb_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @N:CL201 : Ram_interface.v(66) | Trying to extract state machine for register state_tpsram_access Extracted state machine for register state_tpsram_access State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 @W:CL190 : SPI_PROGRAM.v(133) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : SPI_PROGRAM.v(133) | Pruning register bit 0 of HTRANS[1:0] @N:CL201 : SPI_PROGRAM.v(133) | Trying to extract state machine for register ahb_mast_st Extracted state machine for register ahb_mast_st State machine has 18 reachable states with original encodings of: 00000 00001 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 @W:CL279 : SPI_PROGRAM.v(133) | Pruning register bits 31 to 25 of HWDATA[31:0] @W:CL279 : SPI_PROGRAM.v(133) | Pruning register bits 23 to 12 of HWDATA[31:0] @W:CL246 : SPI_PROGRAM.v(40) | Input port bits 31 to 9 of HRDATA[31:0] are unused @W:CL247 : SPI_PROGRAM.v(40) | Input port bit 7 of HRDATA[31:0] is unused @W:CL246 : SPI_PROGRAM.v(40) | Input port bits 5 to 1 of HRDATA[31:0] are unused @W:CL156 : SPI_PROGRAM.v(57) | *Input SPI_Reg_add[24][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_PROGRAM.v(57) | *Input SPI_Reg_add[25][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_PROGRAM.v(56) | *Input SPI_Reg[25][11:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_PROGRAM.v(56) | *Input SPI_Reg[25][24] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL159 : SPI_PROGRAM.v(42) | Input HRESP is unused @W:CL190 : SPI_Erase.v(124) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : SPI_Erase.v(124) | Pruning register bit 0 of HTRANS[1:0] @N:CL201 : SPI_Erase.v(124) | Trying to extract state machine for register ahb_mast_st Extracted state machine for register ahb_mast_st State machine has 10 reachable states with original encodings of: 0000 0100 0101 0110 0111 1000 1001 1010 1011 1110 @W:CL279 : SPI_Erase.v(124) | Pruning register bits 31 to 25 of HWDATA[31:0] @W:CL279 : SPI_Erase.v(124) | Pruning register bits 23 to 12 of HWDATA[31:0] @W:CL246 : SPI_Erase.v(39) | Input port bits 31 to 7 of HRDATA[31:0] are unused @W:CL246 : SPI_Erase.v(39) | Input port bits 5 to 1 of HRDATA[31:0] are unused @W:CL156 : SPI_Erase.v(56) | *Input SPI_Reg_add[23][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_Erase.v(56) | *Input SPI_Reg_add[24][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_Erase.v(55) | *Input SPI_Reg[24][11:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : SPI_Erase.v(55) | *Input SPI_Reg[24][24] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL159 : SPI_Erase.v(41) | Input HRESP is unused @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL134 : PCIe_AXI_IF.v(468) | Found RAM Rdata, depth=256, width=8 @N:CL201 : PCIe_AXI_IF.v(387) | Trying to extract state machine for register axi_fsm_read_state Extracted state machine for register axi_fsm_read_state State machine has 3 reachable states with original encodings of: 000 011 100 @N:CL201 : PCIe_AXI_IF.v(342) | Trying to extract state machine for register araddr_st Extracted state machine for register araddr_st State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : PCIe_AXI_IF.v(281) | Trying to extract state machine for register axi_fsm_ar_state Extracted state machine for register axi_fsm_ar_state State machine has 3 reachable states with original encodings of: 000 001 010 @N:CL201 : PCIe_AXI_IF.v(191) | Trying to extract state machine for register axi_fsm_current_state Extracted state machine for register axi_fsm_current_state State machine has 4 reachable states with original encodings of: 001 010 011 100 @N:CL201 : PCIe_AXI_IF.v(127) | Trying to extract state machine for register axi_fsm_aw_state Extracted state machine for register axi_fsm_aw_state State machine has 3 reachable states with original encodings of: 000 001 010 @W:CL159 : PCIe_AXI_IF.v(56) | Input BID is unused @W:CL159 : PCIe_AXI_IF.v(57) | Input BRESP is unused @W:CL159 : PCIe_AXI_IF.v(58) | Input BVALID is unused @W:CL159 : PCIe_AXI_IF.v(70) | Input RID is unused @W:CL159 : PCIe_AXI_IF.v(72) | Input RRESP is unused @N:CL201 : IAP_INIT.v(50) | Trying to extract state machine for register iap_st Extracted state machine for register iap_st State machine has 3 reachable states with original encodings of: 000 001 010 @W:CL159 : CoreSysServices_AHBLMasterIF.v(72) | Input HCLK is unused @W:CL159 : CoreSysServices_AHBLMasterIF.v(73) | Input HRESETN is unused @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[0] to a constant 0 @W:CL169 : CoreSysServices_FSMCtrl.v(293) | Pruning register fmhburst_d1[0] @N:CL201 : CoreSysServices_FSMCtrl.v(326) | Trying to extract state machine for register curr_state Extracted state machine for register curr_state State machine has 7 reachable states with original encodings of: 0000 0001 0010 0101 1000 1001 1011 @W:CL159 : CoreSysServices_FSMCtrl.v(162) | Input cfwr_req_d is unused @W:CL159 : CoreSysServices_FSMCtrl.v(163) | Input cfrd_req_d is unused @W:CL190 : CoreSysServices_CmdDec.v(997) | Optimizing register bit burstlen_memwr_data_r[31] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[16] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[17] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[18] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[19] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[20] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[21] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[22] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[23] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[24] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[25] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[26] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[27] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[28] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[29] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[30] to a constant 0 @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[31] to a constant 0 @W:CL279 : CoreSysServices_CmdDec.v(1096) | Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0] @W:CL260 : CoreSysServices_CmdDec.v(997) | Pruning register bit 31 of burstlen_memwr_data_r[31:0] @N:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element fcdataout_d1. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_wr_d1[31] to a constant 0 @W:CL260 : CoreSysServices_CmdDec.v(1096) | Pruning register bit 31 of cfburst_len_wr_d1[31:0] @N:CL201 : CoreSysServices_CmdDec.v(3426) | Trying to extract state machine for register asynchevent_curr_state Extracted state machine for register asynchevent_curr_state State machine has 2 reachable states with original encodings of: 0000 1001 @N:CL201 : CoreSysServices_CmdDec.v(3004) | Trying to extract state machine for register resp_curr_state Extracted state machine for register resp_curr_state State machine has 31 reachable states with original encodings of: 000000 000001 000011 000101 000110 000111 001000 001001 001100 001101 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011011 100100 100101 100110 100111 101000 101001 101100 101110 101111 110000 @N:CL201 : CoreSysServices_CmdDec.v(1970) | Trying to extract state machine for register req_curr_state Extracted state machine for register req_curr_state State machine has 37 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 100001 100010 100101 100110 101000 101001 101010 101011 101100 101101 101110 110000 110001 110010 110011 110100 @N:CL201 : CoreSysServices_CmdDec.v(1640) | Trying to extract state machine for register main_curr_state Extracted state machine for register main_curr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL190 : CoreSysServices_CmdDec.v(1895) | Optimizing register bit cfrd_asyncevent_o to a constant 0 @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning register resp_srcreg_addr_d1[30] @W:CL169 : CoreSysServices_CmdDec.v(1895) | Pruning register cfrd_asyncevent_o @W:CL157 : CoreSysServices_CmdDec.v(372) | *Output cutrans_done_o has undriven bits -- simulation mismatch possible. @W:CL159 : CoreSysServices_CmdDec.v(345) | Input ucdata_wvalid_i is unused @W:CL159 : CoreSysServices_CmdDec.v(356) | Input fcpush_i is unused @W:CL159 : CoreSysServices_CmdDec.v(360) | Input clr_req is unused @N:CL135 : CoreSysServices_UserIF.v(772) | Found seqShift zer_new_serv_d1, depth=3, width=1 @W:CL159 : CoreSysServices_UserIF.v(257) | Input cutrans_done_i is unused @W:CL159 : CoreSysServices_UserIF.v(262) | Input cutamper_detect_valid is unused @W:CL159 : CoreSysServices_UserIF.v(263) | Input cutamper_fail_valid is unused @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[0] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[1] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[2] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[3] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[4] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[5] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[6] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[7] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[8] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[9] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[10] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[11] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[12] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[13] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[14] to a constant 0 @W:CL190 : Controller.v(339) | Optimizing register bit SPI_ERASE_ADDR[15] to a constant 0 @W:CL279 : Controller.v(339) | Pruning register bits 15 to 0 of SPI_ERASE_ADDR[23:0] @N:CL201 : Controller.v(483) | Trying to extract state machine for register iap_state Extracted state machine for register iap_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : Controller.v(415) | Trying to extract state machine for register program_state Extracted state machine for register program_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : Controller.v(339) | Trying to extract state machine for register erase_state Extracted state machine for register erase_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL201 : Controller.v(244) | Trying to extract state machine for register rstate Extracted state machine for register rstate State machine has 2 reachable states with original encodings of: 00 01 @N:CL201 : Controller.v(133) | Trying to extract state machine for register wstate Extracted state machine for register wstate State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : Controller.v(29) | Input port bits 31 to 16 of AWADDR[31:0] are unused @W:CL246 : Controller.v(39) | Input port bits 63 to 32 of WDATA[63:0] are unused @W:CL246 : Controller.v(49) | Input port bits 31 to 16 of ARADDR[31:0] are unused @W:CL159 : Controller.v(30) | Input AWLEN is unused @W:CL159 : Controller.v(31) | Input AWSIZE is unused @W:CL159 : Controller.v(32) | Input AWBURST is unused @W:CL159 : Controller.v(33) | Input AWLOCK is unused @W:CL159 : Controller.v(34) | Input AWCACHE is unused @W:CL159 : Controller.v(35) | Input AWPROT is unused @W:CL159 : Controller.v(38) | Input WID is unused @W:CL159 : Controller.v(40) | Input WSTRB is unused @W:CL159 : Controller.v(50) | Input ARLEN is unused @W:CL159 : Controller.v(51) | Input ARSIZE is unused @W:CL159 : Controller.v(52) | Input ARBURST is unused @W:CL159 : Controller.v(53) | Input ARLOCK is unused @W:CL159 : Controller.v(54) | Input ARCACHE is unused @W:CL159 : Controller.v(55) | Input ARPROT is unused At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 123MB peak: 147MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Wed Apr 27 18:33:24 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 88MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 18:33:24 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime # Wed Apr 27 18:33:24 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\bin64\syn_nfilter.exe changed - recompiling File D:\PCIE\IAP_IGL2\010\PCIE_IAP_igl2_1\synthesis\synwork\PCIE_IAP_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 18:33:27 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: PCIE_IAP_scck.rpt Printing clock summary report in "D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\synthesis\PCIE_IAP_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 141MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 141MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 141MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 141MB) @W:BN132 : controller.v(244) | Removing sequential instance IAP_0.Controller_0.RVALID, because it is equivalent to instance IAP_0.Controller_0.RLAST @W:BN132 : iap_init.v(50) | Removing sequential instance IAP_0.IAP_CTRL_0.IAP_INIT_0.SERV_CMDBYTE_REQ_1[4], because it is equivalent to instance IAP_0.IAP_CTRL_0.IAP_INIT_0.SERV_CMDBYTE_REQ_1[2] @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : ram_interface.v(66) | Removing sequential instance o_led_tpsram_test_complete of view:PrimLib.dffse(prim) in hierarchy view:work.Ram_intferface(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(546) | Removing sequential instance FIC_2_APB_M_PSLVERR of view:PrimLib.dffre(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coresysservices_userif.v(566) | Removing sequential instance utamper_msg_valid of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z1(verilog) because there are no references to its outputs @N:BN362 : coresysservices_userif.v(552) | Removing sequential instance utamper_msg[7:0] of view:PrimLib.dffre(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z1(verilog) because there are no references to its outputs @N:BN362 : coresysservices_userif.v(416) | Removing sequential instance ucmd_error of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z1(verilog) because there are no references to its outputs @N:BN362 : coresysservices_fsmctrl.v(305) | Removing sequential instance clr_req of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance sm0_state[6:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1388) | Removing sequential instance RESET_N_F2M_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coresysservices_userif.v(439) | Removing sequential instance udata_wrdy_d2 of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z1(verilog) because there are no references to its outputs @N:BN362 : coresysservices_fsmctrl.v(838) | Removing sequential instance fmhsel_o of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2461) | Removing sequential instance cudata_wrdy_o of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1485) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1517) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1549) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1581) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1613) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2733) | Removing sequential instance cudata_rvalid_o of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z7_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z7_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=21 set on top level netlist PCIE_IAP Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 168MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------------------------------------- PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 System 100.0 MHz 10.000 system system_clkgroup =========================================================================================================================== @W:MT530 : hotreset.v(194) | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock which controls 41 sequential elements including SERDES_INIT_0.HOTRESET_0.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1485) | Found inferred clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including SERDES_INIT_0.CoreResetP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : ram_interface.v(66) | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 416 sequential elements including LSRAM_TAMPER_0.Ram_intferface_0.next_data[7:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : debounce.v(70) | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 2561 sequential elements including DEBOUNCE_0.INTERRUPT. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\synthesis\PCIE_IAP.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 168MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 18:33:28 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB) @W:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o on net cutrans_done_o has its enable tied to GND (module CoreSysServices_CmdDec_Z2) @W:MO111 : | Tristate driver cutrans_done_o_t on net cutrans_done_o has its enable tied to GND (module IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES_Z3) @W:MO111 : pcie_iap_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) @W:MO111 : pcie_iap_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) @W:MO111 : pcie_iap_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) @W:MO111 : pcie_iap_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) @W:MO171 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM\.INSTR_MUXC reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(511) | Sequential instance SERDES_INIT_0.CoreResetP_0.RESET_N_M2F_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(511) | Sequential instance SERDES_INIT_0.CoreResetP_0.RESET_N_M2F_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIE_IAP_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIE_IAP_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance PCIE_IAP_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : coresysservices_userif.v(772) | Sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_UserIF.cuhprior_flushdone_d1[0] reduced to a combinational gate by constant propagation @N:BN362 : coreresetp.v(545) | Removing sequential instance mss_ready_select of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(545) | Removing sequential instance mss_ready_state of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z13(verilog) because there are no references to its outputs @W:BN132 : coreresetp.v(898) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(912) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(856) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sm0_areset_n_rcosc_q1, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(912) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif3_areset_n_rcosc, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc @W:BN132 : coreresetp.v(898) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif2_areset_n_rcosc, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc @W:BN132 : coreresetp.v(884) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc @W:BN132 : coreresetp.v(1581) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif3_core, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled @W:BN132 : coreresetp.v(1549) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif2_core, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled @W:BN132 : coreresetp.v(1517) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif1_core, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled @W:BN132 : coreresetp.v(1646) | Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif2_core_q1, because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.release_sdif1_core_q1 Available hyper_sources - for debug and ip models None Found @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[42:41] mapped in logic. @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[42:41] mapped in logic. @N:MO106 : instructions.v(79) | Found ROM, 'INSTRUCTION_1[42:41]', 19 words by 2 bits @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[35:25] mapped in logic. @N:MO106 : instructions.v(79) | Found ROM, 'INSTRUCTION_1[35:25]', 29 words by 11 bits @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[23:22] mapped in logic. @N:MO106 : instructions.v(79) | Found ROM, 'INSTRUCTION_1[23:22]', 22 words by 2 bits @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[17:13] mapped in logic. @N:MO106 : instructions.v(79) | Found ROM, 'INSTRUCTION_1[17:13]', 22 words by 5 bits @N:FA239 : instructions.v(79) | ROM INSTRUCTION_1[4:1] mapped in logic. @N:MO106 : instructions.v(79) | Found ROM, 'INSTRUCTION_1[4:1]', 29 words by 4 bits @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance resp_srcreg_data_d1[7] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[4] of view:PrimLib.dffre(prim) in hierarchy view:work.IAP_CTRL(verilog) because there are no references to its outputs Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 154MB) @N: : debounce.v(53) | Found counter in view:work.DEBOUNCE(verilog) inst q_reg[15:0] Encoding state machine erase_state[4:0] (view:work.Controller(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine iap_state[3:0] (view:work.Controller(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : controller.v(483) | No possible illegal states for state machine iap_state[3:0],safe FSM implementation is disabled Encoding state machine program_state[3:0] (view:work.Controller(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : controller.v(415) | No possible illegal states for state machine program_state[3:0],safe FSM implementation is disabled Encoding state machine wstate[2:0] (view:work.Controller(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine rstate[1:0] (view:work.Controller(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : controller.v(244) | No possible illegal states for state machine rstate[1:0],safe FSM implementation is disabled @N: : controller.v(339) | Found counter in view:work.Controller(verilog) inst SPI_ERASE_ADDR_1[23:16] @N: : controller.v(339) | Found counter in view:work.Controller(verilog) inst erase_cnt[8:0] @N:FX404 : controller.v(430) | Found addmux in view:work.Controller(verilog) inst SPI_PROG_ADDR_7[23:0] from un1_SPI_PROG_ADDR[23:0] @W:MO160 : controller.v(287) | Register bit RDATA[63] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[62] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[61] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[60] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[59] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[58] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[57] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[56] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[55] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[54] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[53] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[52] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[51] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[50] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[49] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[48] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[47] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[46] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[45] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[44] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[43] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[42] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[41] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[40] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[39] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[38] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[37] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[36] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[35] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[34] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[33] is always 0, optimizing ... @W:MO160 : controller.v(287) | Register bit RDATA[32] is always 0, optimizing ... @N:MF179 : | Found 9 bit by 9 bit '==' comparator, 'SPI_ERASE_STRT16' @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[5] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[4] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[3] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[2] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[7] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[6] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[5] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[3] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[1] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[0] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[5] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[4] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[3] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[2] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[7] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[6] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[5] is always 0, optimizing ... @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[3] is always 0, optimizing ... Encoding state machine resp_curr_state[30:0] (view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | No possible illegal states for state machine asynchevent_curr_state[1:0],safe FSM implementation is disabled Encoding state machine req_curr_state[36:0] (view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 Encoding state machine main_curr_state[2:0] (view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: : coresysservices_cmddec.v(2481) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) inst desc_datasel_cntr[31:0] @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[8] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[9] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[10] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[11] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[12] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[13] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[14] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[15] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[16] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[17] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[18] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[19] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[20] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[21] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[22] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[23] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[24] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[25] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[26] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[27] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[28] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[29] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[30] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[31] of view:PrimLib.dffr(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) because there are no references to its outputs @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[31] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[30] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[28] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[27] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[26] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[25] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[24] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[23] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[22] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[21] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[20] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[19] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[18] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[17] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[16] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[14] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[13] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[7] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[6] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[5] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[4] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[3] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[2] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[1] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[0] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[30] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[29] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[28] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[27] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[26] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[25] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[24] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[23] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[22] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[21] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[20] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[19] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[18] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[17] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[16] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[14] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[13] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[7] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[6] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[5] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[1] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[31] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[30] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[28] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[27] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[26] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[25] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[24] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[23] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[22] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[21] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[20] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[19] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[18] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[17] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[16] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[14] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[13] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[31] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[28] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[27] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[26] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[25] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[24] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[23] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[22] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[21] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[20] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[19] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[18] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[17] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[7] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[6] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[5] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[1] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[0] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[14] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[13] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[1] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[31] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[28] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[27] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[26] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[25] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[24] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[23] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[22] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[21] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[20] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[19] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[18] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[17] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[15] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[12] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[11] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[10] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[9] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[8] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[7] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[6] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[5] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[1] is always 0, optimizing ... @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[0] is always 0, optimizing ... Encoding state machine curr_state[6:0] (view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n of view:PrimLib.dffse(prim) in hierarchy view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) because there are no references to its outputs @N: : coresysservices_fsmctrl.v(760) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) inst word_count[31:0] @W:MO160 : coresysservices_fsmctrl.v(679) | Register bit cfrd_asyncevent_d1 is always 0, optimizing ... Encoding state machine iap_st[2:0] (view:work.IAP_INIT(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 Encoding state machine axi_fsm_current_state[3:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)) original code -> new code 001 -> 00 010 -> 01 011 -> 10 100 -> 11 @N:MO225 : pcie_axi_if.v(191) | No possible illegal states for state machine axi_fsm_current_state[3:0],safe FSM implementation is disabled Encoding state machine axi_fsm_ar_state[2:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 Encoding state machine axi_fsm_read_state[2:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)) original code -> new code 000 -> 00 011 -> 01 100 -> 10 Encoding state machine axi_fsm_aw_state[2:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 Encoding state machine araddr_st[2:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:FX403 : | Property "block_ram" or "no_rw_check" found for RAM Rdata[15:0] with specified coding style. Inferring block RAM. @W:FX107 : | No read/write conflict check. Possible simulation mismatch! @N:MF707 : | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata[15:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)). @N:FX403 : | Property "block_ram" or "no_rw_check" found for RAM Rdata[15:0] with specified coding style. Inferring block RAM. @W:FX107 : | No read/write conflict check. Possible simulation mismatch! @N:MF707 : | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata[15:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)). @N:FX403 : | Property "block_ram" or "no_rw_check" found for RAM Rdata[15:0] with specified coding style. Inferring block RAM. @W:FX107 : | No read/write conflict check. Possible simulation mismatch! @N:MF707 : | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata[15:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)). @N:FX403 : | Property "block_ram" or "no_rw_check" found for RAM Rdata[15:0] with specified coding style. Inferring block RAM. @W:FX107 : | No read/write conflict check. Possible simulation mismatch! @N:MF707 : | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata[15:0] (view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog)). @N: : pcie_axi_if.v(191) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst WDATA_int[7:0] @N: : pcie_axi_if.v(191) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst data_cnt[5:0] @N: : pcie_axi_if.v(281) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst raddr_cnt[8:0] @N: : pcie_axi_if.v(387) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst rburst_cnt[5:0] @N: : pcie_axi_if.v(127) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst waddr_cnt[5:0] @N: : pcie_axi_if.v(445) | Found counter in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst rdata_cnt[8:0] @N:FX404 : pcie_axi_if.v(351) | Found addmux in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst ARADDR_int_9[31:0] from un1_ARADDR_int[31:0] @N:FX404 : pcie_axi_if.v(141) | Found addmux in view:work.PCIe_AXI_IF_16s_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z4(verilog) inst AWADDR_int_5[31:0] from un1_AWADDR_int[31:0] @W:MO160 : pcie_axi_if.v(281) | Register bit ARBURST[1] is always 0, optimizing ... @W:MO161 : pcie_axi_if.v(281) | Register bit ARBURST[0] is always 1, optimizing ... @W:MO160 : pcie_axi_if.v(127) | Register bit AWBURST[1] is always 0, optimizing ... @W:MO161 : pcie_axi_if.v(127) | Register bit AWBURST[0] is always 1, optimizing ... Encoding state machine ahb_mast_st[9:0] (view:work.SPI_Erase(verilog)) original code -> new code 0000 -> 0000000001 0100 -> 0000000010 0101 -> 0000000100 0110 -> 0000001000 0111 -> 0000010000 1000 -> 0000100000 1001 -> 0001000000 1010 -> 0010000000 1011 -> 0100000000 1110 -> 1000000000 @N: : spi_erase.v(124) | Found counter in view:work.SPI_Erase(verilog) inst reg_count[5:0] @W:MO160 : spi_erase.v(124) | Register bit HADDR[31] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[29] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[28] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[27] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[26] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[25] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[24] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[23] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[22] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[21] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[20] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[19] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[18] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[17] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[16] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[15] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[14] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[13] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[11] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[10] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[9] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[8] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[7] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[6] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[1] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HADDR[0] is always 0, optimizing ... @W:MO160 : spi_erase.v(124) | Register bit HWDATA_1[11] is always 0, optimizing ... Encoding state machine ahb_mast_st[17:0] (view:work.SPI_PROGRAM(verilog)) original code -> new code 00000 -> 000000000000000001 00001 -> 000000000000000010 00011 -> 000000000000000100 00100 -> 000000000000001000 00101 -> 000000000000010000 00110 -> 000000000000100000 00111 -> 000000000001000000 01000 -> 000000000010000000 01001 -> 000000000100000000 01010 -> 000000001000000000 01011 -> 000000010000000000 01100 -> 000000100000000000 01101 -> 000001000000000000 01110 -> 000010000000000000 01111 -> 000100000000000000 10000 -> 001000000000000000 10001 -> 010000000000000000 10010 -> 100000000000000000 @N: : spi_program.v(133) | Found counter in view:work.SPI_PROGRAM(verilog) inst data_cnt[9:0] @N: : spi_program.v(133) | Found counter in view:work.SPI_PROGRAM(verilog) inst data_address_int[7:0] @N: : spi_program.v(133) | Found counter in view:work.SPI_PROGRAM(verilog) inst reg_count[5:0] @W:MO160 : spi_program.v(133) | Register bit HADDR[31] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[29] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[28] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[27] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[26] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[25] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[24] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[23] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[22] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[21] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[20] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[19] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[18] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[17] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[16] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[15] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[14] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[13] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[11] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[10] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[9] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[8] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[7] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[6] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[1] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HADDR[0] is always 0, optimizing ... @W:MO160 : spi_program.v(133) | Register bit HWDATA_1[11] is always 0, optimizing ... Encoding state machine state_tpsram_access_1[5:0] (view:work.Ram_intferface(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 @N: : ram_interface.v(66) | Found counter in view:work.Ram_intferface(verilog) inst next_data[7:0] @N: : ram_interface.v(66) | Found counter in view:work.Ram_intferface(verilog) inst expected_data[7:0] @N: : ram_interface.v(66) | Found counter in view:work.Ram_intferface(verilog) inst counter[15:0] @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_IAP_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_IAP_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_IAP_sb(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z7_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[15] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[11] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[7] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[14] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[10] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[6] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[2] removed due to constant propagation Encoding state machine ICYCLE[3:0] (view:work.SERDES_INIT_COREABC_0_COREABC_Z10(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1031) | No possible illegal states for state machine ICYCLE[3:0],safe FSM implementation is disabled @N: : coreabc.v(1031) | Found counter in view:work.SERDES_INIT_COREABC_0_COREABC_Z10(verilog) inst SMADDR[11:0] @W:MO129 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[8] reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[10] reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[11] reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[14] reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(484) | Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_SCMD[2] reduced to a combinational gate by constant propagation @W:FX107 : ram256x16_rtl.v(32) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : ram256x16_rtl.v(32) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for UG3\.UR32\.UR0.RAM[15:0] (view:work.SERDES_INIT_COREABC_0_RAMBLOCKS_32s_24s(verilog)). @W:FX107 : ram256x16_rtl.v(32) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : ram256x16_rtl.v(32) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for UG3\.UR_xhdl12.RAM[15:0] (view:work.SERDES_INIT_COREABC_0_RAMBLOCKS_32s_24s(verilog)). Encoding state machine state[2:0] (view:work.CoreConfigP_Z12(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ... Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z13(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z13(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z13(verilog) inst count_sdif0[12:0] Encoding state machine state[3:0] (view:work.HOTRESET(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : hotreset.v(194) | No possible illegal states for state machine state[3:0],safe FSM implementation is disabled @N: : hotreset.v(250) | Found counter in view:work.HOTRESET(verilog) inst count[6:0] @N:BN362 : coresysservices_cmddec.v(1924) | Removing sequential instance CORESYSSERVICES_0.U_CmdDec.memwr_data_addr_r[29] in hierarchy view:work.IAP_CTRL(verilog) because there are no references to its outputs @N:BN362 : coresysservices_fsmctrl.v(780) | Removing sequential instance CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[0] in hierarchy view:work.IAP_CTRL(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CoreConfigP_0.paddr[10] in hierarchy view:work.SERDES_INIT(verilog) because there are no references to its outputs @A:BN291 : coreconfigp.v(255) | Boundary register CoreConfigP_0.paddr[10] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[0] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[0] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 186MB) @N:BN362 : coresysservices_cmddec.v(2668) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2668) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[6] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[0] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[5] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[8] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[9] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[10] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[11] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[12] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[13] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[14] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[15] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[0] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[2] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[3] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[4] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1970) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_curr_state[26] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(229) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[11] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(229) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[1] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_defaultslavesm.v(64) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_2.default_slave_sm.defSlaveSMCurrentState in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coreahblite_defaultslavesm.v(64) | Removing sequential instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_1.default_slave_sm.defSlaveSMCurrentState in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 179MB peak: 186MB) @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[13] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[3] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[4] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[2] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[4] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[3] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[4] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(580) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.set_puf_getkcnum in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 168MB peak: 186MB) @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[10] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : coresysservices_cmddec.v(1970) | Removing sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_curr_state[27] in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 169MB peak: 186MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 177MB peak: 186MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 176MB peak: 186MB) @N:FA239 : coresysservices_cmddec.v(1466) | ROM IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[3:0] mapped in logic. @N:FA239 : coresysservices_cmddec.v(1466) | ROM IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[3:0] mapped in logic. @N:MO106 : coresysservices_cmddec.v(1466) | Found ROM, 'IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[3:0]', 8 words by 4 bits Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 176MB peak: 186MB) Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 201MB peak: 248MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:13s -0.25ns 2335 / 1317 2 0h:00m:13s -0.25ns 2252 / 1317 3 0h:00m:13s -0.25ns 2252 / 1317 @N:FX271 : coreahblite_masterstage.v(625) | Instance "PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel" with 42 loads replicated 2 times to improve timing @N:FX271 : coresysservices_userif.v(653) | Instance "IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[2]" with 34 loads replicated 2 times to improve timing @N:FX271 : coresysservices_fsmctrl.v(326) | Instance "IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.curr_state[0]" with 39 loads replicated 3 times to improve timing Timing driven replication report Added 7 Registers via timing driven replication Added 7 LUTs via timing driven replication @N:BN362 : | Removing sequential instance IAP_0.PCIe_AXI_IF_0.Rdata_2_Rdata_0_0_en in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance IAP_0.PCIe_AXI_IF_0.Rdata_1_Rdata_0_0_en in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance IAP_0.PCIe_AXI_IF_0.Rdata_0_Rdata_0_0_en in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance IAP_0.PCIe_AXI_IF_0.Rdata_Rdata_0_0_en in hierarchy view:work.PCIE_IAP(verilog) because there are no references to its outputs @N:FP130 : | Promoting Net PCIE_IAP_sb_0_POWER_ON_RESET_N on CLKINT I_440 @N:FP130 : | Promoting Net SERDES_INIT_0_APB_S_PRESET_N on CLKINT I_441 @N:FP130 : | Promoting Net un1_PCIE_IAP_sb_0_5 on CLKINT I_442 @N:FP130 : | Promoting Net SERDES_INIT_0.HOTRESET_0.reset_n_clk_ltssm on CLKINT I_443 @N:FP130 : | Promoting Net SERDES_INIT_0.CoreResetP_0.sm0_areset_n_clk_base on CLKINT I_444 @N:FP130 : | Promoting Net SERDES_INIT_0.CoreResetP_0.sm0_areset_n_rcosc on CLKINT I_445 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 205MB peak: 248MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 208MB peak: 248MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 1361 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================================================= Non-Gated/Non-Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 PCIE_IAP_sb_0.CCC_0.GL0_INST CLKINT 983 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST ClockId0002 PCIE_IAP_sb_0.CCC_0.GL1_INST CLKINT 317 SERDES_IF_0.SERDESIF_INST ClockId0003 PCIE_IAP_sb_0.CCC_0.GL2_INST CLKINT 39 SERDES_INIT_0.HOTRESET_0.count[6] ClockId0004 PCIE_IAP_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 22 SERDES_INIT_0.HOTRESET_0.counter[0] ========================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 163MB peak: 248MB) Writing Analyst data base D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\synthesis\synwork\PCIE_IAP_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 198MB peak: 248MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 199MB peak: 248MB) Start final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 193MB peak: 248MB) @W:MT246 : pcie_iap_sb_ccc_0_fccc.v(26) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : lsram_tamper_tamper_0_tamper.v(31) | Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL0_net" @W:MT420 : | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL1_net" @W:MT420 : | Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL2_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 27 18:33:47 2016 # Top view: PCIE_IAP Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.554 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 122.0 MHz 10.000 8.200 1.801 inferred Inferred_clkgroup_3 PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 139.3 MHz 10.000 7.180 1.554 inferred Inferred_clkgroup_2 PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock 100.0 MHz 285.9 MHz 10.000 3.497 6.503 inferred Inferred_clkgroup_0 PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 431.2 MHz 10.000 2.319 7.681 inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock | 10.000 6.503 | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.681 | No paths - | No paths - | No paths - PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock System | 10.000 8.934 | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock | 10.000 2.820 | No paths - | 5.000 2.629 | 5.000 1.554 PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 1.801 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 3.086 1.801 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_RESP CoreAHBLite_0_AHBmslave16_HRESP 3.189 2.043 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[21] SERDES_IF_0_AXI_MASTER_WDATA[21] 4.037 2.653 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[25] SERDES_IF_0_AXI_MASTER_WDATA[25] 4.037 2.711 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[27] SERDES_IF_0_AXI_MASTER_WDATA[27] 3.874 2.718 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[24] SERDES_IF_0_AXI_MASTER_WDATA[24] 4.036 2.765 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[19] SERDES_IF_0_AXI_MASTER_WDATA[19] 3.903 2.787 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_RDATA[17] CoreAHBLite_0_AHBmslave16_HRDATA[17] 3.490 2.801 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_RDATA[11] CoreAHBLite_0_AHBmslave16_HRDATA[11] 3.403 2.820 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDESIF_0 M_WDATA_HWDATA[26] SERDES_IF_0_AXI_MASTER_WDATA[26] 4.033 2.824 ====================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_0[4] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D word_count_lm[4] 9.778 1.801 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_0[0] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D word_count_lm[0] 9.778 1.815 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_0[6] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D word_count_lm[6] 9.778 1.849 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_WDATA[2] N_344_i_0 9.879 1.928 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_WDATA[4] N_342_i_0 9.883 2.043 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_WDATA[7] N_339_i_0 9.823 2.121 PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_WDATA[1] N_345_i_0 9.856 2.152 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count[1] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN word_counte 9.707 2.155 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count[2] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN word_counte 9.707 2.155 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count[5] PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN word_counte 9.707 2.155 ========================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 7.978 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.801 Number of logic level(s): 5 Starting point: PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_0[4] / D The start point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- PCIE_IAP_sb_0.PCIE_IAP_sb_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_READYOUT Out 3.086 3.086 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.996 - 28 PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNI374L5[16] CFG4 D In - 4.082 - PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNI374L5[16] CFG4 Y Out 0.236 4.318 - HREADY_N_3_mux Net - - 1.094 - 43 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_next_state_i_o2_0_c_RNIEH2R5[1] CFG3 C In - 5.412 - IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_next_state_i_o2_0_c_RNIEH2R5[1] CFG3 Y Out 0.177 5.589 - req_next_state_i_o2_0_1_d[1] Net - - 0.590 - 3 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_next_state_i_a6_0_2_RNIMR5E6[1] CFG4 D In - 6.179 - IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_CmdDec.req_next_state_i_a6_0_2_RNIMR5E6[1] CFG4 Y Out 0.284 6.462 - r_N_3_mux Net - - 0.622 - 4 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_lm_0_RNO[4] CFG4 B In - 7.084 - IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_lm_0_RNO[4] CFG4 Y Out 0.129 7.213 - word_count_5[4] Net - - 0.483 - 1 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_lm_0[4] CFG3 B In - 7.697 - IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_lm_0[4] CFG3 Y Out 0.143 7.840 - word_count_lm[4] Net - - 0.138 - 1 IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_fsm_ctrl.word_count_0[4] SLE D In - 7.978 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 8.200 is 4.277(52.2%) logic and 3.923(47.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.CoreConfigP_0.psel PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE Q psel 0.094 1.554 SERDES_INIT_0.CoreConfigP_0.state[1] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE Q state[1] 0.076 2.629 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PRDATA[7] SERDES_INIT_0_SDIF0_APBmslave_PRDATA[7] 5.613 2.820 SERDES_INIT_0.CoreConfigP_0.SDIF0_PENABLE PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE Q SERDES_INIT_0_SDIF0_APBmslave_PENABLE 0.094 3.288 SERDES_INIT_0.CoreConfigP_0.paddr[15] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE Q paddr[15] 0.076 3.293 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PRDATA[4] SERDES_INIT_0_SDIF0_APBmslave_PRDATA[4] 5.198 3.294 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PRDATA[0] SERDES_INIT_0_SDIF0_APBmslave_PRDATA[0] 5.118 3.315 SERDES_INIT_0.CoreConfigP_0.paddr[4] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE Q SERDES_INIT_0_SDIF0_APBmslave_PADDR[4] 0.094 3.316 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PRDATA[1] SERDES_INIT_0_SDIF0_APBmslave_PRDATA[1] 5.053 3.380 SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PRDATA[2] SERDES_INIT_0_SDIF0_APBmslave_PRDATA[2] 5.094 3.398 ============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SERDES_IF_0.SERDESIF_INST PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SERDESIF_0 APB_PSEL SERDES_INIT_0_SDIF0_APBmslave_PSELx 3.487 1.554 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[0] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[1] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[2] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[3] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[4] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[5] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[6] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[7] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 SERDES_INIT_0.CoreConfigP_0.soft_reset_reg[8] PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock SLE EN soft_reset_reg6 4.707 2.084 ========================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.513 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.487 - Propagation time: 1.933 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.554 Number of logic level(s): 1 Starting point: SERDES_INIT_0.CoreConfigP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock [falling] on pin CLK The end point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.CoreConfigP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.708 - 5 SERDES_INIT_0.CoreConfigP_0.R_SDIF0_PSEL_1_0_a2_0_a2 CFG2 A In - 0.802 - SERDES_INIT_0.CoreConfigP_0.R_SDIF0_PSEL_1_0_a2_0_a2 CFG2 Y Out 0.076 0.878 - SERDES_INIT_0_SDIF0_APBmslave_PSELx Net - - 1.055 - 34 SERDES_IF_0.SERDESIF_INST SERDESIF_0 APB_PSEL In - 1.933 - ============================================================================================================================= Total path delay (propagation time + setup) of 3.446 is 1.683(48.8%) logic and 1.763(51.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.HOTRESET_0.state[1] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q counte 0.094 6.503 SERDES_INIT_0.HOTRESET_0.count[0] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[0] 0.094 7.100 SERDES_INIT_0.HOTRESET_0.count[6] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[6] 0.094 7.100 SERDES_INIT_0.HOTRESET_0.count[1] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[1] 0.094 7.168 SERDES_INIT_0.HOTRESET_0.count[2] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[2] 0.076 7.213 SERDES_INIT_0.HOTRESET_0.count[4] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[4] 0.076 7.244 SERDES_INIT_0.HOTRESET_0.count[5] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[5] 0.094 7.275 SERDES_INIT_0.HOTRESET_0.state[0] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count 0.094 7.527 SERDES_INIT_0.HOTRESET_0.count[3] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q count[3] 0.094 7.805 SERDES_INIT_0.HOTRESET_0.LTSSM_HotReset_entry_p PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE Q LTSSM_HotReset_entry_p 0.076 7.976 =================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.HOTRESET_0.hot_reset_n_ltssm PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE EN un1_hot_reset_n_ltssm_0_sqmuxa_1_0_0 9.707 6.503 SERDES_INIT_0.HOTRESET_0.l2_detected_n PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE EN un1_hot_reset_n_ltssm_0_sqmuxa_0_0 9.707 6.571 SERDES_INIT_0.HOTRESET_0.state[1] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D N_148_i_0 9.778 6.631 SERDES_INIT_0.HOTRESET_0.state[0] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D N_146_i_0 9.778 6.738 SERDES_INIT_0.HOTRESET_0.count[6] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[6] 9.778 7.527 SERDES_INIT_0.HOTRESET_0.count[5] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[5] 9.778 7.541 SERDES_INIT_0.HOTRESET_0.count[4] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[4] 9.778 7.555 SERDES_INIT_0.HOTRESET_0.count[3] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[3] 9.778 7.569 SERDES_INIT_0.HOTRESET_0.count[0] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[0] 9.778 7.582 SERDES_INIT_0.HOTRESET_0.count[1] PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock SLE D count_s[1] 9.778 7.582 ============================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.707 - Propagation time: 3.204 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 6.503 Number of logic level(s): 3 Starting point: SERDES_INIT_0.HOTRESET_0.state[1] / Q Ending point: SERDES_INIT_0.HOTRESET_0.hot_reset_n_ltssm / EN The start point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK The end point is clocked by PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.HOTRESET_0.state[1] SLE Q Out 0.094 0.094 - counte Net - - 1.223 - 14 SERDES_INIT_0.HOTRESET_0.state_ns_i_0_a3_1_4[1] CFG3 B In - 1.318 - SERDES_INIT_0.HOTRESET_0.state_ns_i_0_a3_1_4[1] CFG3 Y Out 0.143 1.460 - state_ns_i_0_a3_1_4[1] Net - - 0.483 - 1 SERDES_INIT_0.HOTRESET_0.state_ns_i_0_a3_1[1] CFG4 D In - 1.944 - SERDES_INIT_0.HOTRESET_0.state_ns_i_0_a3_1[1] CFG4 Y Out 0.250 2.194 - N_13 Net - - 0.622 - 4 SERDES_INIT_0.HOTRESET_0.un1_hot_reset_n_ltssm_0_sqmuxa_1_0_0 CFG4 D In - 2.816 - SERDES_INIT_0.HOTRESET_0.un1_hot_reset_n_ltssm_0_sqmuxa_1_0_0 CFG4 Y Out 0.250 3.066 - un1_hot_reset_n_ltssm_0_sqmuxa_1_0_0 Net - - 0.138 - 1 SERDES_INIT_0.HOTRESET_0.hot_reset_n_ltssm SLE EN In - 3.204 - ============================================================================================================================ Total path delay (propagation time + setup) of 3.497 is 1.031(29.5%) logic and 2.466(70.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------ SERDES_INIT_0.CoreResetP_0.count_sdif0[0] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[0] 0.094 7.681 SERDES_INIT_0.CoreResetP_0.count_sdif0[1] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[1] 0.094 7.746 SERDES_INIT_0.CoreResetP_0.count_sdif0[2] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[2] 0.094 7.760 SERDES_INIT_0.CoreResetP_0.count_sdif0[3] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[3] 0.094 7.774 SERDES_INIT_0.CoreResetP_0.count_sdif0[4] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[4] 0.094 7.789 SERDES_INIT_0.CoreResetP_0.count_sdif0[5] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[5] 0.094 7.803 SERDES_INIT_0.CoreResetP_0.count_sdif0[6] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[6] 0.094 7.817 SERDES_INIT_0.CoreResetP_0.count_sdif0[7] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[7] 0.094 7.831 SERDES_INIT_0.CoreResetP_0.count_sdif0[8] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[8] 0.094 7.845 SERDES_INIT_0.CoreResetP_0.count_sdif0[9] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[9] 0.094 7.858 ================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.CoreResetP_0.count_sdif0[12] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[12] 9.778 7.681 SERDES_INIT_0.CoreResetP_0.count_sdif0[11] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[11] 9.778 7.695 SERDES_INIT_0.CoreResetP_0.count_sdif0[10] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[10] 9.778 7.709 SERDES_INIT_0.CoreResetP_0.count_sdif0[9] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[9] 9.778 7.723 SERDES_INIT_0.CoreResetP_0.count_sdif0[8] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[8] 9.778 7.738 SERDES_INIT_0.CoreResetP_0.count_sdif0[7] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[7] 9.778 7.752 SERDES_INIT_0.CoreResetP_0.count_sdif0[6] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[6] 9.778 7.766 SERDES_INIT_0.CoreResetP_0.count_sdif0[5] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[5] 9.778 7.780 SERDES_INIT_0.CoreResetP_0.count_sdif0[4] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[4] 9.778 7.795 SERDES_INIT_0.CoreResetP_0.count_sdif0[3] PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[3] 9.778 7.809 ======================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.097 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.681 Number of logic level(s): 13 Starting point: SERDES_INIT_0.CoreResetP_0.count_sdif0[0] / Q Ending point: SERDES_INIT_0.CoreResetP_0.count_sdif0[12] / D The start point is clocked by PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- SERDES_INIT_0.CoreResetP_0.count_sdif0[0] SLE Q Out 0.094 0.094 - count_sdif0[0] Net - - 0.637 - 3 SERDES_INIT_0.CoreResetP_0.count_sdif0_s_433 ARI1 B In - 0.732 - SERDES_INIT_0.CoreResetP_0.count_sdif0_s_433 ARI1 FCO Out 0.174 0.906 - count_sdif0_s_433_FCO Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[1] ARI1 FCI In - 0.906 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[1] ARI1 FCO Out 0.014 0.920 - count_sdif0_cry[1] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[2] ARI1 FCI In - 0.920 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[2] ARI1 FCO Out 0.014 0.935 - count_sdif0_cry[2] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[3] ARI1 FCI In - 0.935 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[3] ARI1 FCO Out 0.014 0.949 - count_sdif0_cry[3] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[4] ARI1 FCI In - 0.949 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[4] ARI1 FCO Out 0.014 0.963 - count_sdif0_cry[4] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[5] ARI1 FCI In - 0.963 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[5] ARI1 FCO Out 0.014 0.977 - count_sdif0_cry[5] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[6] ARI1 FCI In - 0.977 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[6] ARI1 FCO Out 0.014 0.991 - count_sdif0_cry[6] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[7] ARI1 FCI In - 0.991 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[7] ARI1 FCO Out 0.014 1.006 - count_sdif0_cry[7] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[8] ARI1 FCI In - 1.006 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[8] ARI1 FCO Out 0.014 1.020 - count_sdif0_cry[8] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[9] ARI1 FCI In - 1.020 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[9] ARI1 FCO Out 0.014 1.034 - count_sdif0_cry[9] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[10] ARI1 FCI In - 1.034 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[10] ARI1 FCO Out 0.014 1.048 - count_sdif0_cry[10] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[11] ARI1 FCI In - 1.048 - SERDES_INIT_0.CoreResetP_0.count_sdif0_cry[11] ARI1 FCO Out 0.014 1.062 - count_sdif0_cry[11] Net - - 0.000 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0_s[12] ARI1 FCI In - 1.062 - SERDES_INIT_0.CoreResetP_0.count_sdif0_s[12] ARI1 S Out 0.063 1.126 - count_sdif0_s[12] Net - - 0.971 - 1 SERDES_INIT_0.CoreResetP_0.count_sdif0[12] SLE D In - 2.097 - ============================================================================================================= Total path delay (propagation time + setup) of 2.319 is 0.710(30.6%) logic and 1.609(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 193MB peak: 248MB) Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 193MB peak: 248MB) --------------------------------------- Resource Usage Report for PCIE_IAP Mapping to part: m2gl010tfbga484-1 Cell usage: AND2 1 use CCC 1 use CLKINT 10 uses MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_0 1 use SYSRESET 1 use TAMPER 1 use CFG1 18 uses CFG2 396 uses CFG3 456 uses CFG4 1045 uses Carry primitives used for arithmetic functions: ARI1 357 uses Sequential Cells: SLE 1324 uses DSP Blocks: 0 I/O ports: 36 I/O primitives: 18 BIBUF 2 uses INBUF 6 uses INBUF_DIFF 1 use OUTBUF 8 uses TRIBUFF 1 use Global Clock Buffers: 10 RAM/ROM usage summary Block Rams (RAM1K18) : 5 Block Rams (RAM64x18) : 8 Total LUTs: 2272 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 288; LUTs = 288; RAM1K18 Interface Logic : SLEs = 180; LUTs = 180; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 1324 + 288 + 180 + 0 = 1792; Total number of LUTs after P&R: 2272 + 288 + 180 + 0 = 2740; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 60MB peak: 248MB) Process took 0h:00m:18s realtime, 0h:00m:17s cputime # Wed Apr 27 18:33:47 2016 ###########################################################]