@W: MO111 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":372:29:372:42|Tristate driver cutrans_done_o on net cutrans_done_o has its enable tied to GND (module CoreSysServices_CmdDec_Z2) 
@W: MO111 :|Tristate driver cutrans_done_o_t on net cutrans_done_o has its enable tied to GND (module IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES_Z3) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\pcie_iap_sb\fabosc_0\pcie_iap_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\pcie_iap_sb\fabosc_0\pcie_iap_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\pcie_iap_sb\fabosc_0\pcie_iap_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\pcie_iap_sb\fabosc_0\pcie_iap_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIE_IAP_sb_FABOSC_0_OSC) 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM\.INSTR_MUXC reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":511:4:511:9|Sequential instance SERDES_INIT_0.CoreResetP_0.RESET_N_M2F_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":511:4:511:9|Sequential instance SERDES_INIT_0.CoreResetP_0.RESET_N_M2F_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SERDES_INIT_0.CoreResetP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIE_IAP_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIE_IAP_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance PCIE_IAP_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":772:3:772:8|Sequential instance IAP_0.IAP_CTRL_0.CORESYSSERVICES_0.U_UserIF.cuhprior_flushdone_d1[0] reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.sdif1_areset_n_rcosc,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif3_core,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif2_core,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif1_core,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.ddr_settled
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance SERDES_INIT_0.CoreResetP_0.release_sdif2_core_q1,  because it is equivalent to instance SERDES_INIT_0.CoreResetP_0.release_sdif1_core_q1
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[63] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[62] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[61] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[60] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[59] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[58] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[57] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[56] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[55] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[54] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[53] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[52] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[51] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[50] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[49] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[48] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[47] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[46] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[45] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[44] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[43] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[42] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[41] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[40] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[39] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[38] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[37] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[36] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[35] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[34] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[33] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\controller.v":287:0:287:5|Register bit RDATA[32] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":696:3:696:8|Register bit CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_userif.v":653:3:653:8|Register bit CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[30] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1924:3:1924:8|Register bit memwr_data_addr_r[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[30] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[29] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memwr_data_r[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[30] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":2668:3:2668:8|Register bit cfdatain_d1[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1303:3:1303:8|Register bit cfsrc_addr_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":997:3:997:8|Register bit burstlen_memrd_data_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_cmddec.v":1255:3:1255:8|Register bit cfdst_addr_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coresysservices\3.1.101\rtl\vlog\core\coresysservices_fsmctrl.v":679:2:679:7|Register bit cfrd_asyncevent_d1 is always 0, optimizing ...
@W: FX107 :|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :|No read/write conflict check. Possible simulation mismatch!
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\pcie_axi_if.v":281:0:281:5|Register bit ARBURST[1] is always 0, optimizing ...
@W: MO161 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\pcie_axi_if.v":281:0:281:5|Register bit ARBURST[0] is always 1, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\pcie_axi_if.v":127:0:127:5|Register bit AWBURST[1] is always 0, optimizing ...
@W: MO161 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\pcie_axi_if.v":127:0:127:5|Register bit AWBURST[0] is always 1, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[29] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HADDR[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_erase.v":124:0:124:5|Register bit HWDATA_1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[29] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HADDR[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\hdl\spi_program.v":133:0:133:5|Register bit HWDATA_1[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] is always 0, optimizing ...
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[14] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[10] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[6] removed due to constant propagation
@W: MO197 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[2] removed due to constant propagation
@W: MO129 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[8] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[10] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[11] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_ADDR[14] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance SERDES_INIT_0.COREABC_0.UROM.INSTR_SCMD[2] reduced to a combinational gate by constant propagation
@W: FX107 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\serdes_init\coreabc_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|No read/write conflict check. Possible simulation mismatch!
@W: MO160 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit paddr[16] is always 0, optimizing ...
@W: MT246 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\pcie_iap_sb\ccc_0\pcie_iap_sb_ccc_0_fccc.v":26:36:26:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"d:\pcie\iap_igl2\010\11.7\pcie_iap_igl2\component\work\lsram_tamper\tamper_0\lsram_tamper_tamper_0_tamper.v":31:11:31:21|Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
@W: MT420 |Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL0_net"
@W: MT420 |Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL1_net"
@W: MT420 |Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIE_IAP_sb_0.CCC_0.GL2_net"
