#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP_igl2\synthesis\run_options.txt
#--  Written on Wed Apr 27 18:33:18 2016


#project files
add_file -include "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/support.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/Debounce.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/AXI_MASTER_TO_SLAVE.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/Controller.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/IAP_INIT.v"
add_file -verilog -lib CORESYSSERVICES_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_AHBLMasterIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_CmdDec.v"
add_file -verilog -lib CORESYSSERVICES_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_FSMCtrl.v"
add_file -verilog -lib CORESYSSERVICES_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_UserIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP_CTRL/CORESYSSERVICES_0/rtl/vlog/core/CoreSysServices.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP_CTRL/IAP_CTRL.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/PCIe_AXI_IF.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_Erase.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_PROGRAM.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP/IAP.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/SgCore/TAMPER/2.1.200/tamper_comps.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TAMPER_0/LSRAM_TAMPER_TAMPER_0_TAMPER.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TPSRAM_0/LSRAM_TAMPER_TPSRAM_0_TPSRAM.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/Ram_interface.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/LSRAM_TAMPER.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP/SERDES_IF_0/PCIE_IAP_SERDES_IF_0_SERDES_IF_syn.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP/SERDES_IF_0/PCIE_IAP_SERDES_IF_0_SERDES_IF.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/CCC_0/PCIE_IAP_sb_CCC_0_FCCC.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/FABOSC_0/PCIE_IAP_sb_FABOSC_0_OSC.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb_HPMS/PCIE_IAP_sb_HPMS_syn.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb_HPMS/PCIE_IAP_sb_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/PCIE_IAP_sb.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/HOTRESET.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/acmtable.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/debugblk.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/instructions.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/instructnvm_bb.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/iram512x9_rtl.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/instructram.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/ram128x8_smartfusion2.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/ram256x16_rtl.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/ram256x8_rtl.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/ramblocks.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/coreabc.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/SERDES_INIT.v"
add_file -verilog "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP/PCIE_IAP.v"
add_file -include "D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core/support.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "PCIE_IAP"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./PCIE_IAP.edn"
impl -active "synthesis"
