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R8
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R15
R5
r1
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8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP/IAP.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP/IAP.v
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r1
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R3
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8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP_CTRL/IAP_CTRL.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP_CTRL/IAP_CTRL.v
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r1
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31
R18
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/IAP_CTRL/IAP_CTRL.v|
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R7
R8
n@i@a@p_@c@t@r@l
vIAP_INIT
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R3
w1430233728
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/IAP_INIT.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/IAP_INIT.v
R9
R5
r1
!s85 0
31
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/IAP_INIT.v|
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R7
R8
n@i@a@p_@i@n@i@t
vLSRAM_TAMPER
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R2
R3
w1428235516
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/LSRAM_TAMPER.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/LSRAM_TAMPER.v
L0 9
R5
r1
!s85 0
31
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!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/LSRAM_TAMPER.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/LSRAM_TAMPER.v|
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R7
R8
n@l@s@r@a@m_@t@a@m@p@e@r
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R17
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R2
R3
w1428235510
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TAMPER_0/LSRAM_TAMPER_TAMPER_0_TAMPER.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TAMPER_0/LSRAM_TAMPER_TAMPER_0_TAMPER.v
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r1
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31
R18
!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TAMPER_0/LSRAM_TAMPER_TAMPER_0_TAMPER.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TAMPER_0/LSRAM_TAMPER_TAMPER_0_TAMPER.v|
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R7
R8
n@l@s@r@a@m_@t@a@m@p@e@r_@t@a@m@p@e@r_0_@t@a@m@p@e@r
vLSRAM_TAMPER_TPSRAM_0_TPSRAM
R17
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R2
R3
w1428235515
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TPSRAM_0/LSRAM_TAMPER_TPSRAM_0_TPSRAM.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TPSRAM_0/LSRAM_TAMPER_TPSRAM_0_TPSRAM.v
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R5
r1
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31
R18
!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TPSRAM_0/LSRAM_TAMPER_TPSRAM_0_TPSRAM.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/LSRAM_TAMPER/TPSRAM_0/LSRAM_TAMPER_TPSRAM_0_TPSRAM.v|
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R7
R8
n@l@s@r@a@m_@t@a@m@p@e@r_@t@p@s@r@a@m_0_@t@p@s@r@a@m
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FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/PCIe_AXI_IF.v
R4
R5
r1
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31
R18
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/PCIe_AXI_IF.v|
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R2
R3
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FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP/PCIE_IAP.v
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r1
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31
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP/PCIE_IAP.v|
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R10
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R2
R3
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FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/PCIE_IAP_sb.v
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r1
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31
R11
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/PCIE_IAP_sb.v|
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R2
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FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/CCC_0/PCIE_IAP_sb_CCC_0_FCCC.v
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31
R20
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/CCC_0/PCIE_IAP_sb_CCC_0_FCCC.v|
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R2
R3
R23
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/FABOSC_0/PCIE_IAP_sb_FABOSC_0_OSC.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/FABOSC_0/PCIE_IAP_sb_FABOSC_0_OSC.v
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r1
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R20
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!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb/FABOSC_0/PCIE_IAP_sb_FABOSC_0_OSC.v|
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R7
R8
n@p@c@i@e_@i@a@p_sb_@f@a@b@o@s@c_0_@o@s@c
vPCIE_IAP_sb_HPMS
R19
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FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/PCIE_IAP_sb_HPMS/PCIE_IAP_sb_HPMS.v
L0 9
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R18
!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_Erase.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_Erase.v|
!s101 -O0
!i113 1
R7
R8
n@s@p@i_@erase
vSPI_PROGRAM
R17
!i10b 1
!s100 lS9jDh@m^T_2JH;c5YV:b1
I:D1fa;dYz=ZHXJBW5Y:Gh2
R2
R3
w1418851790
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_PROGRAM.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_PROGRAM.v
R16
R5
r1
!s85 0
31
R18
!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_PROGRAM.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/hdl/SPI_PROGRAM.v|
!s101 -O0
!i113 1
R7
R8
n@s@p@i_@p@r@o@g@r@a@m
vtestbench
R21
!i10b 1
!s100 i[g=O>V56HX:zjW>2j<Yn0
IP0n0Qk995>UVf:fXeEh[G1
R2
R3
w1418852092
8D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus/testbench.v
FD:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus/testbench.v
R4
R5
r1
!s85 0
31
R22
!s107 D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus/testbench.v|
!s90 -reportprogress|300|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core|+incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus|-work|presynth|D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus/testbench.v|
!s101 -O0
!i113 1
R7
!s92 +incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/component/work/SERDES_INIT/COREABC_0/rtl/vlog/core +incdir+D:/PCIE/IAP_IGL2/010/11.7/PCIE_IAP_igl2/stimulus -work presynth -O0
