| Project Settings |
|---|
| Project Name | PCIE_IAP_syn | Implementation Name | synthesis |
| Top Module | PCIE_IAP | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
129 |
585 |
0 |
- |
0m:07s |
- |
27-04-2016
PM 07:54:19 |
| (premap) | Complete |
120 |
14 |
0 |
0m:01s |
0m:01s |
168MB |
27-04-2016
PM 07:54:23 |
| (fpga_mapper) | Complete |
127 |
320 |
0 |
0m:17s |
0m:17s |
247MB |
27-04-2016
PM 07:54:41 |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 27-04-2016
PM 07:54:21 |
| Area Summary |
|---|
| |
| Carry Cells | 322 |
Sequential Cells | 1248 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 18 |
| Global Clock Buffers | 10 |
Block Rams (RAM1K18)
(v_ram) | 4 |
| Block Rams (RAM64x18)
(v_ram) | 8 |
LUTs
(total_luts) | 2144 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 119.6 MHz | 1.641 |
| PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock | 100.0 MHz | 138.2 MHz | 1.522 |
| PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock | 100.0 MHz | 285.9 MHz | 6.503 |
| PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 431.2 MHz | 7.681 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 4 / 0 |
| |
|