@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\hdl\controller.v":244:0:244:5|Removing sequential instance IAP_0.Controller_0.RVALID,  because it is equivalent to instance IAP_0.Controller_0.RLAST
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\hdl\iap_init.v":50:0:50:5|Removing sequential instance IAP_0.IAP_CTRL_0.IAP_INIT_0.SERV_CMDBYTE_REQ_1[4],  because it is equivalent to instance IAP_0.IAP_CTRL_0.IAP_INIT_0.SERV_CMDBYTE_REQ_1[2]
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance PCIE_IAP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT530 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\hdl\hotreset.v":194:4:194:9|Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL2_net_inferred_clock which controls 41 sequential elements including SERDES_INIT_0.HOTRESET_0.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock PCIE_IAP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including SERDES_INIT_0.CoreResetP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\component\work\pcie_iap\serdes_if_0\pcie_iap_serdes_if_0_serdes_if.v":215:52:215:64|Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 348 sequential elements including SERDES_IF_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\pcie\iap_igl2\010\11.7\pcie_iap\hdl\debounce.v":70:1:70:6|Found inferred clock PCIE_IAP_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 2561 sequential elements including DEBOUNCE_0.INTERRUPT. This clock has no specified timing constraint which may adversely impact design performance. 
