@W: CL271 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":244:0:244:5|Pruning bits 31 to 16 of raddr_int[31:0] -- not in use ...
@W: CL271 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":133:0:133:5|Pruning bits 31 to 16 of waddr_int[31:0] -- not in use ...
@W: CG775 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":30:7:30:48|Found Component IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":789:3:789:8|Pruning register cuhprior_flushdone_d3 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning register pord_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning register pord_d2 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":592:3:592:8|Pruning register custatus_out_en_r 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":522:3:522:8|Pruning register pord_comb_d1 
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":719:3:719:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Optimizing register bit hprior_kp_busy_high to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[2] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[3] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[4] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[1] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[3] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[6] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[7] to a constant 0
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 5 to 2 of uclatchoptions_hold[5:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 0 of uclatchoptions_hold[5:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 3 of ucmdbyte_req_hold[7:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Pruning register hprior_kp_busy_high 
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":418:30:418:40|No assignment to cfwr_req_d1
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":436:30:436:43|No assignment to cfsrc_addr_int
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":437:30:437:43|No assignment to cfdst_addr_int
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":447:30:447:39|No assignment to memwr_data
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":470:30:470:44|No assignment to req_srcreg_addr
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":472:30:472:44|No assignment to req_srcreg_data
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":512:30:512:50|No assignment to cuhprior_flushdone_d1
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":555:30:555:41|No assignment to wire cfwr_req_int
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":557:30:557:39|No assignment to wire cfwr_req_c
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":563:30:563:39|No assignment to wire cfdata_w_o
@W: CL168 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2927:16:2927:29|Pruning instance FLASH_FREEZE_0 -- not in use ...
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2980:3:2980:8|Pruning register FF_exit 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2962:3:2962:8|Pruning register FF_exit_led 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2949:3:2949:8|Pruning register FF_entry_led 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2939:3:2939:8|Pruning register FF_entry 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register cunvm_bfr_iapverify_done_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2770:3:2770:8|Pruning register latchen_hrdata_r 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning register fiicreg_done_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning register commctrlreg_done_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning register commpoll_done_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning register set_puf_getkcnum_r 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1906:3:1906:8|Pruning register wait_count[2:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1731:3:1731:8|Pruning register fctrans_done_d2 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning register pord_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning register pord_d2 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1582:3:1582:8|Pruning register req_phase_active_pulse 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning register resp_data_done_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning register req_phase_active_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning register resp_desc_done 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning register resp_frm_done 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1015:3:1015:8|Pruning register req_desc_done 
@W: CL271 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning bits 31 to 8 of fcdataout_d1[31:0] -- not in use ...
@W: CL113 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|Feedback mux created for signal cutamper_msg[7:0].
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2786:3:2786:8|All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization.
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1594:3:1594:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL250 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_detect_valid to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_fail_valid to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[2] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[6] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[8] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[9] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[10] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[11] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[12] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[13] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[14] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[15] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[16] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[17] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[18] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[19] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[20] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[21] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[22] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[23] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[24] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[25] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[26] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[27] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[28] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[30] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[31] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 31 of resp_srcreg_addr_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 15 of resp_srcreg_addr_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 2 of resp_srcreg_data_d1[31:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 0 of resp_srcreg_data_d1[31:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning register cutamper_detect_valid 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning register cutamper_fail_valid 
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":236:21:236:36|No assignment to rvalid_out_en_d1
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":237:21:237:36|No assignment to rvalid_out_en_d2
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":245:21:245:31|No assignment to wire fmhaddr_lat
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":952:3:952:8|Pruning register busreq_prev 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":934:6:934:11|Pruning register pop_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":868:5:868:10|Pruning register fmhtrans_int2[1:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":732:3:732:8|Pruning register haddr_prev[29:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning register latch_addr_d2 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning register latch_addr_d3 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":639:2:639:7|Pruning register latch_addr_d1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":627:2:627:7|Pruning register state_prev_clk[3:0] 
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[1] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[2] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Optimizing register bit fmhtrans_int[0] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Pruning register bit 0 of fmhtrans_int[1:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning register bits 2 to 1 of fmhburst_d1[2:0] 
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":259:29:259:41|No assignment to wire cfburst_len_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":265:29:265:42|No assignment to wire ustatus_resp_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":266:29:266:35|No assignment to wire ubusy_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":267:29:267:38|No assignment to wire udata_en_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":268:29:268:41|No assignment to wire udata_valid_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":269:29:269:37|No assignment to wire udata_r_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":275:29:275:41|No assignment to wire uclatchpord_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":281:29:281:45|No assignment to wire uccrypto_opmode_o
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":304:29:304:40|No assignment to wire cudata_wen_o
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[1] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[3] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[6] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_CMDBYTE_REQ[7] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_OPTIONS_MODE[2] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_OPTIONS_MODE[3] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_OPTIONS_MODE[4] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Optimizing register bit SERV_OPTIONS_MODE[5] to a constant 0
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Pruning register bits 5 to 2 of SERV_OPTIONS_MODE[5:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Pruning register bits 7 to 5 of SERV_CMDBYTE_REQ[7:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Pruning register bit 3 of SERV_CMDBYTE_REQ[7:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Pruning register bits 1 to 0 of SERV_CMDBYTE_REQ[7:0] 
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":84:13:84:21|No assignment to ddr_wr_st
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":127:0:127:5|Optimizing register bit AWSIZE[0] to a constant 1
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":127:0:127:5|Optimizing register bit AWSIZE[1] to a constant 1
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":281:0:281:5|Optimizing register bit ARSIZE[0] to a constant 1
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":281:0:281:5|Optimizing register bit ARSIZE[1] to a constant 1
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":281:0:281:5|Pruning register ARSIZE[1:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":127:0:127:5|Pruning register AWSIZE[1:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register read_byte[3][7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register read_byte[2][7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register read_byte[0][7:0] 
@W: CL271 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning bits 7 to 1 of read_byte[1][7:0] -- not in use ...
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Optimizing register bit init_idx_cnt[1] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register bit 1 of init_idx_cnt[2:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register read_byte[3][7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register read_byte[2][7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register read_byte[0][7:0] 
@W: CL271 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning bits 7 to 1 of read_byte[1][7:0] -- not in use ...
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Optimizing register bit init_idx_cnt[1] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register bit 1 of init_idx_cnt[2:0] 
@W: CG775 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning register count_sdif0[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning register count_sdif0_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ramblocks.v":38:23:38:25|No assignment to wire RDW
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ramblocks.v":44:15:44:18|No assignment to wire RDYY
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":686:34:686:37|No assignment to MULT
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":687:34:687:34|No assignment to A
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":688:34:688:34|No assignment to B
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1348:16:1348:16|No assignment to b
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":227:9:227:14|No assignment to wire DEBUG1
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":228:9:228:14|No assignment to wire DEBUG2
@W: CG360 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":229:9:229:23|No assignment to wire DEBUGBLK_RESETN
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":255:12:255:14|No assignment to iii
@W: CG133 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":256:25:256:33|No assignment to RAMDOUTXX
@W: CG134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":260:14:260:21|No assignment to bit 12 of ins_addr
@W: CG134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":260:14:260:21|No assignment to bit 13 of ins_addr
@W: CG134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":260:14:260:21|No assignment to bit 14 of ins_addr
@W: CG134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":260:14:260:21|No assignment to bit 15 of ins_addr
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|Pruning register ZREGISTER[0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|Pruning register STKPTR[7:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|Pruning register GETINST 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":501:12:501:17|Pruning register UROM.upper_addr[7:0] 
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|All reachable assignments to ISR assign 0, register removed by optimization.
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|All reachable assignments to IO_OUT[0] assign 0, register removed by optimization.
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|All reachable assignments to DOISR assign 0, register removed by optimization.
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":808:4:808:9|All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W: CL207 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":808:4:808:9|All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W: CL189 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":484:12:484:17|Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ...
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":484:12:484:17|Pruning register bit 4 of UROM.INSTR_SLOT[4:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Pruning register SDIF0_PERST_N_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Pruning register SDIF0_PERST_N_q2 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Pruning register SDIF0_PERST_N_q3 
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL189 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Register bit SDIF0_PERST_N_re is always 0, optimizing ...
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\HOTRESET.v":36:24:36:29|Input port bit 31 of PRDATA[31:0] is unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\HOTRESET.v":36:24:36:29|Input port bits 25 to 0 of PRDATA[31:0] are unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":80:20:80:32|Input SDIF0_PERST_N is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":23:10:23:14|Input RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":134:10:134:18|Input PSLVERR_M is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":135:26:135:30|Input IO_IN is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":138:10:138:15|Input INTREQ is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":141:10:141:19|Input INITDATVAL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":142:10:142:17|Input INITDONE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":143:27:143:34|Input INITADDR is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":144:15:144:22|Input INITDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":148:11:148:16|Input PSEL_S is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":149:11:149:19|Input PENABLE_S is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":150:11:150:18|Input PWRITE_S is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":151:28:151:34|Input PADDR_S is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":152:28:152:35|Input PWDATA_S is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb_HPMS\PCIE_IAP_sb_HPMS.v":56:14:56:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL157 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":107:20:107:37|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":108:20:108:33|Input SOFT_RESET_F2M is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":109:20:109:32|Input SOFT_M3_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":110:20:110:49|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":111:20:111:39|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":112:20:112:39|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":113:20:113:40|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":114:20:114:39|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":115:20:115:40|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":116:20:116:39|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":117:20:117:40|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":118:20:118:39|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":119:20:119:40|Input SOFT_SDIF3_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":123:20:123:42|Input SOFT_SDIF0_0_CORE_RESET is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":124:20:124:42|Input SOFT_SDIF0_1_CORE_RESET is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":123:15:123:23|Input HBURST_M0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":124:15:124:22|Input HPROT_M0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":134:15:134:23|Input HBURST_M1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":135:15:135:22|Input HPROT_M1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":145:15:145:23|Input HBURST_M2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":146:15:146:22|Input HPROT_M2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":156:15:156:23|Input HBURST_M3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":157:15:157:22|Input HPROT_M3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":69:18:69:26|Input HWDATA_M3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":73:18:73:26|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":74:13:74:24|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":75:13:75:20|Input HRESP_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":84:18:84:26|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":85:13:85:24|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":86:13:86:20|Input HRESP_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":95:18:95:26|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":96:13:96:24|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":97:13:97:20|Input HRESP_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":106:18:106:26|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":107:13:107:24|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":108:13:108:20|Input HRESP_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":117:18:117:26|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":118:13:118:24|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":119:13:119:20|Input HRESP_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":128:18:128:26|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":129:13:129:24|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":130:13:130:20|Input HRESP_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":139:18:139:26|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":140:13:140:24|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":141:13:141:20|Input HRESP_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":150:18:150:26|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":151:13:151:24|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":152:13:152:20|Input HRESP_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":161:18:161:26|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":162:13:162:24|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":163:13:163:20|Input HRESP_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":172:18:172:26|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":173:13:173:24|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":174:13:174:20|Input HRESP_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":183:18:183:27|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":184:13:184:25|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":185:13:185:21|Input HRESP_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":194:18:194:27|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":195:13:195:25|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":196:13:196:21|Input HRESP_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":205:18:205:27|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":206:13:206:25|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":207:13:207:21|Input HRESP_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":216:18:216:27|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":217:13:217:25|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":218:13:218:21|Input HRESP_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":227:18:227:27|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":228:13:228:25|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":229:13:229:21|Input HRESP_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":238:18:238:27|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":239:13:239:25|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":240:13:240:21|Input HRESP_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input SDATAREADY is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input SHRESP is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S16 is unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register bit 0 of HTRANS[1:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register bits 31 to 25 of HWDATA[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Pruning register bits 23 to 12 of HWDATA[31:0] 
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":40:23:40:28|Input port bits 31 to 9 of HRDATA[31:0] are unused
@W: CL247 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":40:23:40:28|Input port bit 7 of HRDATA[31:0] is unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":40:23:40:28|Input port bits 5 to 1 of HRDATA[31:0] are unused
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":57:12:57:22|*Input SPI_Reg_add[24][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":57:12:57:22|*Input SPI_Reg_add[25][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":56:12:56:18|*Input SPI_Reg[25][11:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":56:12:56:18|*Input SPI_Reg[25][24] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":42:21:42:25|Input HRESP is unused
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register bit 0 of HTRANS[1:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register bits 31 to 25 of HWDATA[31:0] 
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Pruning register bits 23 to 12 of HWDATA[31:0] 
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":39:23:39:28|Input port bits 31 to 7 of HRDATA[31:0] are unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":39:23:39:28|Input port bits 5 to 1 of HRDATA[31:0] are unused
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":56:12:56:22|*Input SPI_Reg_add[23][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":56:12:56:22|*Input SPI_Reg_add[24][31:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":55:12:55:18|*Input SPI_Reg[24][11:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":55:12:55:18|*Input SPI_Reg[24][24] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":41:21:41:25|Input HRESP is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":56:22:56:24|Input BID is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":57:21:57:25|Input BRESP is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":58:21:58:26|Input BVALID is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":70:26:70:28|Input RID is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":72:26:72:30|Input RRESP is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":72:28:72:31|Input HCLK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":73:28:73:34|Input HRESETN is unused
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[0] to a constant 0
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning register fmhburst_d1[0] 
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":162:21:162:30|Input cfwr_req_d is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":163:21:163:30|Input cfrd_req_d is unused
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Optimizing register bit burstlen_memwr_data_r[31] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[16] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[17] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[18] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[19] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[20] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[21] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[22] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[23] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[24] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[25] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[26] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[27] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[28] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[29] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[30] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[31] to a constant 0
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0] 
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Pruning register bit 31 of burstlen_memwr_data_r[31:0] 
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_wr_d1[31] to a constant 0
@W: CL260 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bit 31 of cfburst_len_wr_d1[31:0] 
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Optimizing register bit cfrd_asyncevent_o to a constant 0
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register resp_srcreg_addr_d1[30] 
@W: CL169 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Pruning register cfrd_asyncevent_o 
@W: CL157 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":372:29:372:42|*Output cutrans_done_o has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":345:17:345:31|Input ucdata_wvalid_i is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":356:17:356:24|Input fcpush_i is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":360:17:360:23|Input clr_req is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":257:28:257:41|Input cutrans_done_i is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":262:28:262:48|Input cutamper_detect_valid is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":263:28:263:46|Input cutamper_fail_valid is unused
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[0] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[1] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[2] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[3] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[4] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[5] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[6] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[7] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[8] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[9] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[10] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[11] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[12] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[13] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[14] to a constant 0
@W: CL190 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Optimizing register bit SPI_ERASE_ADDR[15] to a constant 0
@W: CL279 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Pruning register bits 15 to 0 of SPI_ERASE_ADDR[23:0] 
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":29:23:29:28|Input port bits 31 to 16 of AWADDR[31:0] are unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":39:32:39:36|Input port bits 63 to 32 of WDATA[63:0] are unused
@W: CL246 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":49:23:49:28|Input port bits 31 to 16 of ARADDR[31:0] are unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":30:32:30:36|Input AWLEN is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":31:32:31:37|Input AWSIZE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":32:32:32:38|Input AWBURST is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":33:32:33:37|Input AWLOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":34:32:34:38|Input AWCACHE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":35:32:35:37|Input AWPROT is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":38:25:38:27|Input WID is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":40:32:40:36|Input WSTRB is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":50:32:50:36|Input ARLEN is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":51:32:51:37|Input ARSIZE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":52:32:52:38|Input ARBURST is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":53:32:53:37|Input ARLOCK is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":54:32:54:38|Input ARCACHE is unused
@W: CL159 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":55:32:55:37|Input ARPROT is unused

