@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG334 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\debugblk.v":68:17:68:29|Read directive translate_off 
@N: CG333 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\debugblk.v":745:17:745:28|Read directive translate_on 
@N: CG334 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":982:21:982:33|Read directive translate_off 
@N: CG333 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":984:21:984:32|Read directive translate_on 
@N: CG334 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1379:17:1379:29|Read directive translate_off 
@N: CG333 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1423:17:1423:28|Read directive translate_on 
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":126:7:126:10|Synthesizing module AND2
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Debounce.v":20:8:20:15|Synthesizing module DEBOUNCE
@N: CG179 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Debounce.v":81:18:81:26|Removing redundant assignment
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\AXI_MASTER_TO_SLAVE.v":21:7:21:25|Synthesizing module AXI_MASTER_TO_SLAVE
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":23:7:23:16|Synthesizing module Controller
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":30:7:30:28|Synthesizing module CoreSysServices_UserIF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":835:7:835:18|Synthesizing module FLASH_FREEZE
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":30:7:30:28|Synthesizing module CoreSysServices_CmdDec
@N: CG179 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1912:26:1912:35|Removing redundant assignment
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Sharing sequential element fcpop_d1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_fail_valid_r.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_detect_valid_r.
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":30:7:30:29|Synthesizing module CoreSysServices_FSMCtrl
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":30:7:30:34|Synthesizing module CoreSysServices_AHBLMasterIF
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":30:7:30:48|Synthesizing module IAP_CTRL_CORESYSSERVICES_0_CORESYSSERVICES
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":23:7:23:14|Synthesizing module IAP_INIT
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP_CTRL\IAP_CTRL.v":9:7:9:14|Synthesizing module IAP_CTRL
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":21:7:21:17|Synthesizing module PCIe_AXI_IF
@N: CG179 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":379:23:379:32|Removing redundant assignment
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":20:7:20:15|Synthesizing module SPI_Erase
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":20:7:20:17|Synthesizing module SPI_PROGRAM
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\IAP\IAP.v":9:7:9:9|Synthesizing module IAP
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\CCC_0\PCIE_IAP_sb_CCC_0_FCCC.v":5:7:5:28|Synthesizing module PCIE_IAP_sb_CCC_0_FCCC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\FABOSC_0\PCIE_IAP_sb_FABOSC_0_OSC.v":5:7:5:30|Synthesizing module PCIE_IAP_sb_FABOSC_0_OSC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb_HPMS\PCIE_IAP_sb_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":280:7:280:13|Synthesizing module TRIBUFF
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb_HPMS\PCIE_IAP_sb_HPMS.v":9:7:9:22|Synthesizing module PCIE_IAP_sb_HPMS
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP_sb\PCIE_IAP_sb.v":9:7:9:17|Synthesizing module PCIE_IAP_sb
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v":320:7:320:16|Synthesizing module INBUF_DIFF
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP\SERDES_IF_0\PCIE_IAP_SERDES_IF_0_SERDES_IF_syn.v":5:7:5:16|Synthesizing module SERDESIF_0
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP\SERDES_IF_0\PCIE_IAP_SERDES_IF_0_SERDES_IF.v":5:7:5:36|Synthesizing module PCIE_IAP_SERDES_IF_0_SERDES_IF
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":46:7:46:35|Synthesizing module SERDES_INIT_COREABC_0_COREABC
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ramblocks.v":25:7:25:37|Synthesizing module SERDES_INIT_COREABC_0_RAMBLOCKS
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":20:7:20:37|Synthesizing module SERDES_INIT_COREABC_0_RAM256X16
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Found RAM RAM, depth=256, width=16
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\instructions.v":26:7:26:40|Synthesizing module SERDES_INIT_COREABC_0_INSTRUCTIONS
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\HOTRESET.v":31:7:31:14|Synthesizing module HOTRESET
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\SERDES_INIT.v":9:7:9:17|Synthesizing module SERDES_INIT
@N: CG364 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\PCIE_IAP\PCIE_IAP.v":9:7:9:14|Synthesizing module PCIE_IAP
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\HOTRESET.v":194:4:194:9|Trying to extract state machine for register state
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\work\SERDES_INIT\COREABC_0\rtl\vlog\core\coreabc.v":1031:4:1031:9|Trying to extract state machine for register ICYCLE
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_PROGRAM.v":133:0:133:5|Trying to extract state machine for register ahb_mast_st
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\SPI_Erase.v":124:0:124:5|Trying to extract state machine for register ahb_mast_st
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL134 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":468:0:468:5|Found RAM Rdata, depth=256, width=8
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":387:0:387:5|Trying to extract state machine for register axi_fsm_read_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":342:0:342:5|Trying to extract state machine for register araddr_st
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":281:0:281:5|Trying to extract state machine for register axi_fsm_ar_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":191:0:191:5|Trying to extract state machine for register axi_fsm_current_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\PCIe_AXI_IF.v":127:0:127:5|Trying to extract state machine for register axi_fsm_aw_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\IAP_INIT.v":50:0:50:5|Trying to extract state machine for register iap_st
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":326:3:326:8|Trying to extract state machine for register curr_state
@N: CL177 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element fcdataout_d1.
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":3426:3:3426:8|Trying to extract state machine for register asynchevent_curr_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":3004:3:3004:8|Trying to extract state machine for register resp_curr_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1970:3:1970:8|Trying to extract state machine for register req_curr_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1640:3:1640:8|Trying to extract state machine for register main_curr_state
@N: CL135 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":772:3:772:8|Found seqShift zer_new_serv_d1, depth=3, width=1
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":483:0:483:5|Trying to extract state machine for register iap_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":415:0:415:5|Trying to extract state machine for register program_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":339:0:339:5|Trying to extract state machine for register erase_state
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":244:0:244:5|Trying to extract state machine for register rstate
@N: CL201 :"D:\PCIE\IAP_IGL2\010\11.7\PCIE_IAP\hdl\Controller.v":133:0:133:5|Trying to extract state machine for register wstate
@N|Running in 64-bit mode

