#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
#install: D:\Microsemi\Libero_SoC_v11.7\Synplify
#OS: Windows 7 6.1
#Hostname: W764D-ATHULDEEP

#Implementation: synthesis

Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v"
@I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v"
@I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v"
@I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v"
@I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\acmtable.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\debugblk.v"
@I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\debugblk.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\support.v"
@N:CG334 : debugblk.v(68) | Read directive translate_off 
@N:CG333 : debugblk.v(745) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\instructions.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\instructnvm_bb.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\iram512x9_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\instructram.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\ram256x16_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\ram256x8_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\ramblocks.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\COREABC_0\rtl\vlog\core\coreabc.v"
@N:CG334 : coreabc.v(982) | Read directive translate_off 
@N:CG333 : coreabc.v(984) | Read directive translate_on 
@N:CG334 : coreabc.v(1379) | Read directive translate_off 
@N:CG333 : coreabc.v(1423) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxi.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxo.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxi.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxo.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\peanx_sync.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_peanx_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\r10b8b.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pcs.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petbm.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petcr.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\t8b10b.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petex_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_tbi.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_core.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\rx4096x36.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_clkrst.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_hst.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_fab.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_sys.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_fab.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_sys.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_wtm.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v"
@I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\include.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsm_sysreg.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mahbe_dual.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mmcxwol.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecrc.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perfn_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\permc_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petfn_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petmc_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac_core.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecar.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pehst.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemgt.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_ladd.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_linc.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sadd.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinc.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinchd.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sincnf.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_store.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_mem2p.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_2flp.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_hstinf.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rfp.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rtc.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_tfp.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\si_sal.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_pulse.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tx2048x40.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\CoreTSE_top.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\CORETSE_0\rtl\vlog\core_obfuscated\CoreTSE.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\FCCC_0\Igloo2_1000BaseT_sb_FCCC_0_FCCC.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\SERDES_IF_0\Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF_syn.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\SERDES_IF_0\Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb_sb\CCC_0\Igloo2_1000BaseT_sb_sb_CCC_0_FCCC.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb_sb\FABOSC_0\Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb_sb_HPMS\Igloo2_1000BaseT_sb_sb_HPMS_syn.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb_sb_HPMS\Igloo2_1000BaseT_sb_sb_HPMS.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb_sb\Igloo2_1000BaseT_sb_sb.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\LSRAM_MTX_MRX\TPSRAM_0\LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\hdl\coretse_if_0.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\LSRAM_MTX_MRX\LSRAM_MTX_MRX.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_sb\Igloo2_1000BaseT_sb.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\acmtable.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\debugblk.v"
@I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\debugblk.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\support.v"
@N:CG334 : debugblk.v(68) | Read directive translate_off 
@N:CG333 : debugblk.v(745) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\instructions.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\instructnvm_bb.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\iram512x9_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\instructram.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\ram256x16_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\ram256x8_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\ramblocks.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\COREABC_0\rtl\vlog\core\coreabc.v"
@N:CG334 : coreabc.v(982) | Read directive translate_off 
@N:CG333 : coreabc.v(984) | Read directive translate_on 
@N:CG334 : coreabc.v(1379) | Read directive translate_off 
@N:CG333 : coreabc.v(1423) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\SERDESIF_0_INIT_0test\SERDESIF_0_INIT_0test.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\acmtable.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\debugblk.v"
@I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\debugblk.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\support.v"
@N:CG334 : debugblk.v(68) | Read directive translate_off 
@N:CG333 : debugblk.v(745) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\instructions.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\instructnvm_bb.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\iram512x9_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\instructram.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\ram256x8_rtl.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\ramblocks.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\COREABC_0\rtl\vlog\core\coreabc.v"
@N:CG334 : coreabc.v(982) | Read directive translate_off 
@N:CG333 : coreabc.v(984) | Read directive translate_on 
@N:CG334 : coreabc.v(1379) | Read directive translate_off 
@N:CG333 : coreabc.v(1423) | Read directive translate_on 
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\CORETSE_0\rtl\vlog\core_obfuscated\CoreTSE.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\FCCC_0\Test_1000BaseT_FCCC_0_FCCC.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\SERDES_IF\Test_1000BaseT_SERDES_IF_SERDES_IF.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Test_1000BaseT\Test_1000BaseT.v"
@I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\component\work\Igloo2_1000BaseT_Top\Igloo2_1000BaseT_Top.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module Igloo2_1000BaseT_Top
@N:CG364 : igloo2.v(126) | Synthesizing module AND2

@N:CG364 : igloo2.v(286) | Synthesizing module BIBUF

@N:CG364 : coreabc.v(46) | Synthesizing module Igloo2_1000BaseT_sb_COREABC_0_COREABC

	FAMILY=32'b00000000000000000000000000011000
	APB_AWIDTH=32'b00000000000000000000000000010000
	APB_DWIDTH=32'b00000000000000000000000000100000
	APB_SDEPTH=32'b00000000000000000000000000010000
	ICWIDTH=32'b00000000000000000000000000001011
	ZRWIDTH=32'b00000000000000000000000000010000
	IFWIDTH=32'b00000000000000000000000000000001
	IIWIDTH=32'b00000000000000000000000000000001
	IOWIDTH=32'b00000000000000000000000000000001
	STWIDTH=32'b00000000000000000000000000001000
	EN_RAM=32'b00000000000000000000000000000001
	EN_AND=32'b00000000000000000000000000000001
	EN_XOR=32'b00000000000000000000000000000001
	EN_OR=32'b00000000000000000000000000000001
	EN_ADD=32'b00000000000000000000000000000001
	EN_INC=32'b00000000000000000000000000000001
	EN_SHL=32'b00000000000000000000000000000001
	EN_SHR=32'b00000000000000000000000000000001
	EN_CALL=32'b00000000000000000000000000000001
	EN_PUSH=32'b00000000000000000000000000000001
	EN_MULT=32'b00000000000000000000000000000000
	EN_ACM=32'b00000000000000000000000000000000
	EN_DATAM=32'b00000000000000000000000000000010
	EN_INT=32'b00000000000000000000000000000000
	EN_IOREAD=32'b00000000000000000000000000000001
	EN_IOWRT=32'b00000000000000000000000000000001
	EN_ALURAM=32'b00000000000000000000000000000001
	EN_INDIRECT=32'b00000000000000000000000000000001
	ISRADDR=32'b00000000000000000000000000000001
	DEBUG=32'b00000000000000000000000000000000
	INSMODE=32'b00000000000000000000000000000000
	INITWIDTH=32'b00000000000000000000000000001011
	TESTMODE=32'b00000000000000000000000000000000
	ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001
	IMEM_APB_ACCESS=32'b00000000000000000000000000000000
	UNIQ_STRING_LENGTH=32'b00000000000000000000000000011101
	MAX_NVMDWIDTH=32'b00000000000000000000000000100000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	IRWIDTH=32'b00000000000000000000000000100000
	ICDEPTH=32'b00000000000000000000100000000000
	APB_SWIDTH=32'b00000000000000000000000000000100
	RAMWIDTH=32'b00000000000000000000000000111010
	SYNC_RESET=32'b00000000000000000000000000000000
	CYCLE0=2'b00
	CYCLE1=2'b01
	CYCLE2=2'b10
	CYCLE3=2'b11
   Generated name = Igloo2_1000BaseT_sb_COREABC_0_COREABC_Z1

@N:CG364 : ramblocks.v(25) | Synthesizing module Igloo2_1000BaseT_sb_COREABC_0_RAMBLOCKS

	DWIDTH=32'b00000000000000000000000000100000
	FAMILY=32'b00000000000000000000000000011000
   Generated name = Igloo2_1000BaseT_sb_COREABC_0_RAMBLOCKS_32s_24s

@N:CG364 : ram256x16_rtl.v(20) | Synthesizing module Igloo2_1000BaseT_sb_COREABC_0_RAM256X16

@N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16
@W:CG360 : ramblocks.v(38) | No assignment to wire RDW

@W:CG360 : ramblocks.v(44) | No assignment to wire RDYY

@N:CG364 : instructions.v(26) | Synthesizing module Igloo2_1000BaseT_sb_COREABC_0_INSTRUCTIONS

	AWIDTH=32'b00000000000000000000000000010000
	DWIDTH=32'b00000000000000000000000000100000
	SWIDTH=32'b00000000000000000000000000000100
	ICWIDTH=32'b00000000000000000000000000001011
	IIWIDTH=32'b00000000000000000000000000000001
	IFWIDTH=32'b00000000000000000000000000000001
	IWWIDTH=32'b00000000000000000000000000111010
	EN_MULT=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000001
	TESTMODE=32'b00000000000000000000000000000000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	AW=32'b00000000000000000000000000010000
	DW=32'b00000000000000000000000000100000
	SW=32'b00000000000000000000000000000100
	IW=32'b00000000000000000000000000001011
	FW=32'b00000000000000000000000000000101
	iJUMP=32'b00000000000000000010001000000001
	iCALL=32'b00000000000000000010001100000001
	iRETURN=32'b00000000000000000010010000000001
	iRETISR=32'b00000000000000000010010100000001
	iWAIT=32'b00000000000000000010011000000001
	iHALT=32'b00000000000000000010011000000001
	iINC=32'b00000000000000000000001100000000
	iACM_CTRLSTAT=8'b00000000
	iACM_ADDR_ADDR=8'b00000100
	iACM_DATA_ADDR=8'b00001000
	iADC_CTRL2_HI_ADDR=8'b00010000
	iADC_STAT_HI_ADDR=8'b00100000
	Sym_MDIO_STAT_REG=32'b00000000000000000000000000110100
	Sym_TSE_MACFG1_REG=32'b00000000000000000000000000000000
	Sym_TSE_MACFG2_REG=32'b00000000000000000000000000000100
	Label_read_phy_status=32'b00000000000000000000000000011011
	Label_delay_loop=32'b00000000000000000000000000011111
	Label_Delay_loop_phy14=32'b00000000000000000000000000100000
	Label_MDIO_wait_status=32'b00000000000000000000000000101010
	Label_Status_reg_p0=32'b00000000000000000000000000101010
   Generated name = Igloo2_1000BaseT_sb_COREABC_0_INSTRUCTIONS_Z2

@W:CG133 : coreabc.v(686) | No assignment to MULT
@W:CG133 : coreabc.v(687) | No assignment to A
@W:CG133 : coreabc.v(688) | No assignment to B
@W:CG360 : coreabc.v(227) | No assignment to wire DEBUG1

@W:CG360 : coreabc.v(228) | No assignment to wire DEBUG2

@W:CG360 : coreabc.v(229) | No assignment to wire DEBUGBLK_RESETN

@W:CG133 : coreabc.v(255) | No assignment to iii
@W:CG133 : coreabc.v(256) | No assignment to RAMDOUTXX
@W:CG134 : coreabc.v(260) | No assignment to bit 11 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr
@W:CL169 : coreabc.v(1031) | Pruning register GETINST 

@W:CL169 : coreabc.v(501) | Pruning register UROM.upper_addr[7:0] 

@W:CL208 : coreabc.v(1031) | All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ...
@W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0] 

@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3

@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	IADDR_OPTION=32'b00000000000000000000000000010001
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	MADDR_BITS=6'b011100
	UPR_NIBBLE_POSN=4'b1000
	FAMILY=32'b00000000000000000000000000011000
	SYNC_RESET=32'b00000000000000000000000000000000
	IADDR_NOTINUSE=32'b00000000000000000000000000000000
	IADDR_EXTERNAL=32'b00000000000000000000000000000001
	IADDR_SLOT0=32'b00000000000000000000000000000010
	IADDR_SLOT1=32'b00000000000000000000000000000011
	IADDR_SLOT2=32'b00000000000000000000000000000100
	IADDR_SLOT3=32'b00000000000000000000000000000101
	IADDR_SLOT4=32'b00000000000000000000000000000110
	IADDR_SLOT5=32'b00000000000000000000000000000111
	IADDR_SLOT6=32'b00000000000000000000000000001000
	IADDR_SLOT7=32'b00000000000000000000000000001001
	IADDR_SLOT8=32'b00000000000000000000000000001010
	IADDR_SLOT9=32'b00000000000000000000000000001011
	IADDR_SLOT10=32'b00000000000000000000000000001100
	IADDR_SLOT11=32'b00000000000000000000000000001101
	IADDR_SLOT12=32'b00000000000000000000000000001110
	IADDR_SLOT13=32'b00000000000000000000000000001111
	IADDR_SLOT14=32'b00000000000000000000000000010000
	IADDR_SLOT15=32'b00000000000000000000000000010001
	SL0=16'b0000000000000001
	SL1=16'b0000000000000000
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b1000000000000000
	SC=16'b0000000000000000
	SC_qual=16'b0000000000000000
   Generated name = CoreAPB3_Z3

@N:CG364 : coreapb3_iaddr_reg.v(21) | Synthesizing module coreapb3_iaddr_reg

	SYNC_RESET=32'b00000000000000000000000000000000
	APB_DWIDTH=6'b100000
	MADDR_BITS=6'b011100
   Generated name = coreapb3_iaddr_reg_0s_32_28

@N:CG364 : decoder.v(6) | Synthesizing module decoder

@N:CG364 : tsm_sysreg.v(4) | Synthesizing module tsm_sysreg

	CORETSEoII=32'b00000000000000000000000000000001
	CORETSEii=32'b00000000000000000000000000000000
   Generated name = tsm_sysreg_1s_0s

@N:CG364 : mahbe_dual.v(6) | Synthesizing module mahbe_dual

	CORETSEii=32'b00000000000000000000000000000000
	CORETSEoII=32'b00000000000000000000000000000001
   Generated name = mahbe_dual_0s_1s

@W:CL169 : mahbe_dual.v(282) | Pruning register CORETSEI00l 

@N:CG364 : amcxtfif_fab.v(6) | Synthesizing module amcxtfif_fab

	TABITS=32'b00000000000000000000000000001011
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSElOoI=11'b00000000000
	CORETSElO0I=12'b000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = amcxtfif_fab_11s_32s_2s_0_0_1s

@N:CG364 : amcxtfif_sys.v(6) | Synthesizing module amcxtfif_sys

	TABITS=32'b00000000000000000000000000001011
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSEii=32'b00000000000000000000000000000000
	CORETSElO0I=12'b000000000000
	CORETSEoooI=14'b00000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = amcxtfif_sys_11s_32s_2s_0s_0_0_1s

@W:CL271 : amcxtfif_sys.v(1656) | Pruning bits 1 to 0 of CORETSEIIiI[13:0] -- not in use ...

@W:CL271 : amcxtfif_sys.v(1475) | Pruning bits 13 to 2 of CORETSElIiI[13:0] -- not in use ...

@W:CL271 : amcxtfif_sys.v(1447) | Pruning bits 1 to 0 of CORETSEOIiI[13:0] -- not in use ...

@W:CL271 : amcxtfif_sys.v(1380) | Pruning bits 1 to 0 of CORETSEiOiI[13:0] -- not in use ...

@W:CL265 : amcxtfif_sys.v(1609) | Pruning bit 38 of CORETSEOliI[39:0] -- not in use ...

@N:CG364 : amcxrfif_fab.v(6) | Synthesizing module amcxrfif_fab

	RABITS=32'b00000000000000000000000000001100
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSElO0I=13'b0000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = amcxrfif_fab_12s_32s_2s_0_1s

@N:CG179 : amcxrfif_fab.v(971) | Removing redundant assignment
@N:CG179 : amcxrfif_fab.v(977) | Removing redundant assignment
@N:CG179 : amcxrfif_fab.v(983) | Removing redundant assignment
@N:CG179 : amcxrfif_fab.v(989) | Removing redundant assignment
@N:CG179 : amcxrfif_fab.v(995) | Removing redundant assignment
@W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[36] to a constant 0
@W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[37] to a constant 0
@W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[38] to a constant 0
@W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[39] to a constant 0
@W:CL279 : amcxrfif_fab.v(1581) | Pruning register bits 39 to 36 of CORETSEOIOI[39:0] 

@W:CL169 : amcxrfif_fab.v(1022) | Pruning register CORETSEiI0I 

@N:CG364 : amcxrfif_sys.v(6) | Synthesizing module amcxrfif_sys

	CORETSEii=32'b00000000000000000000000000000000
	RABITS=32'b00000000000000000000000000001100
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSEIo0I=14'b00000000000000
	CORETSElo0I=13'b0000000000000
	CORETSElO0I=15'b000000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s

@N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module amcxtfif_wtm

	RABITS=32'b00000000000000000000000000001100
	CORETSEO0II=32'b00000000000000000000000000000001
	CORETSElOoI=12'b000000000000
	CORETSElO0I=13'b0000000000000
   Generated name = amcxtfif_wtm_12s_1s_0_0

@N:CG364 : amcxfif_hst.v(6) | Synthesizing module amcxfif_hst

	TABITS=32'b00000000000000000000000000001011
	RABITS=32'b00000000000000000000000000001100
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSEO0II=32'b00000000000000000000000000000001
	CORETSEIoII=13'b0000000000000
	CORETSEloII=4'b0000
	CORETSEooII=19'b0000000000000000000
	CORETSEioII=12'b111111111111
	CORETSEOiII=12'b111111111111
	CORETSEIiII=14'b00000000000000
	CORETSEliII=4'b0000
	CORETSEoiII=3'b000
	CORETSEiiII=18'b000000000000000000
	CORETSEOOlI=13'b1111111111111
	CORETSEIOlI=13'b1111111111111
	CORETSElOlI=12'b111111111111
   Generated name = amcxfif_hst_Z4

@W:CG360 : amcxfif_hst.v(904) | No assignment to wire CORETSEO0lI

@N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module amcxfif_clkrst

@N:CG364 : amcxfif.v(6) | Synthesizing module amcxfif

	TABITS=32'b00000000000000000000000000001011
	RABITS=32'b00000000000000000000000000001100
	CORETSEii1=32'b00000000000000000000000000100000
	CORETSEOOo=32'b00000000000000000000000000000010
	CORETSEii=32'b00000000000000000000000000000000
   Generated name = amcxfif_11s_12s_32s_2s_0s

@N:CG364 : petmc_top.v(6) | Synthesizing module petmc_top

@N:CG364 : pecrc.v(6) | Synthesizing module pecrc

@N:CG364 : petfn_top.v(6) | Synthesizing module petfn_top

	CORETSEOOI=32'b00000000000000000000000000000000
	CORETSEIOI=1'b0
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = petfn_top_0s_0_1s

@N:CG179 : petfn_top.v(9933) | Removing redundant assignment
@N:CG179 : petfn_top.v(9993) | Removing redundant assignment
@W:CG133 : petfn_top.v(418) | No assignment to CORETSEO1oOI
@W:CG360 : petfn_top.v(421) | No assignment to wire CORETSEI1oOI

@W:CG360 : petfn_top.v(445) | No assignment to wire CORETSEOo0OI

@W:CG133 : petfn_top.v(586) | No assignment to CORETSEOiiOI
@W:CG360 : petfn_top.v(956) | No assignment to wire CORETSEliIII

@W:CL169 : petfn_top.v(4062) | Pruning register CORETSEIoiOI[15:0] 

@W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[5] to a constant 0
@W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[6] to a constant 0
@W:CL279 : petfn_top.v(3748) | Pruning register bits 6 to 5 of CORETSEOoOII[6:0] 

@N:CG364 : perfn_top.v(6) | Synthesizing module perfn_top

	CORETSEii=32'b00000000000000000000000000000000
	CORETSEIOI=1'b0
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = perfn_top_0s_0_1s

@W:CG360 : perfn_top.v(343) | No assignment to wire CORETSEol0i

@W:CG360 : perfn_top.v(650) | No assignment to wire CORETSEIioi

@W:CG133 : perfn_top.v(653) | No assignment to CORETSElioi
@N:CG364 : permc_top.v(6) | Synthesizing module permc_top

@N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module pe_mcxmac_core

	CORETSEIOI=1'b0
	CORETSEii=32'b00000000000000000000000000000000
	CORETSEOOI=32'b00000000000000000000000000000000
   Generated name = pe_mcxmac_core_0_0s_0s

@N:CG364 : pemgt.v(6) | Synthesizing module pemgt

@N:CG364 : pehst.v(6) | Synthesizing module pehst

@W:CG133 : pehst.v(613) | No assignment to CORETSEooI1
@W:CG133 : pehst.v(709) | No assignment to CORETSEioI1
@W:CG133 : pehst.v(714) | No assignment to CORETSEOiI1
@W:CG133 : pehst.v(716) | No assignment to CORETSEIiI1
@W:CL169 : pehst.v(1969) | Pruning register CORETSEo0i1 

@W:CL169 : pehst.v(1939) | Pruning register CORETSEl0i1 

@W:CL169 : pehst.v(1909) | Pruning register CORETSEI0i1 

@N:CG364 : pecar.v(6) | Synthesizing module pecar

@N:CG364 : pe_mcxmac.v(6) | Synthesizing module pe_mcxmac

	CORETSEIOI=1'b0
	CORETSEOOI=32'b00000000000000000000000000000000
	CORETSEii=32'b00000000000000000000000000000000
   Generated name = pe_mcxmac_0_0s_0s

@W:CG360 : pe_mcxmac.v(676) | No assignment to wire CORETSEOii0

@W:CG360 : pe_mcxmac.v(679) | No assignment to wire CORETSEI0I0

@W:CG360 : pe_mcxmac.v(682) | No assignment to wire CORETSEl0I0

@N:CG364 : tsmac_top.v(4) | Synthesizing module tsmac_top

	TABITS=32'b00000000000000000000000000001011
	RABITS=32'b00000000000000000000000000001100
	MDIO_PHYID=32'b00000000000000000000000000010010
	CORETSEIi=32'b00000000000000000000000000000001
	CORETSEli=32'b00000000000000000000000000000001
	CORETSEoi=32'b00000000000000000000000000000001
	CORETSEii=32'b00000000000000000000000000000000
	CORETSEOOI=32'b00000000000000000000000000000000
	CORETSEIOI=32'b00000000000000000000000000000000
	CORETSElOI=32'b00000000000000000000000000000001
	CORETSEoOI=32'b00000000000000000000000000000010
	CORETSEiOI=32'b00000000000000000000000000000001
	CORETSEOII=32'b00000000000000000000000000000010
	CORETSEIII=32'b00000000000000000000000000010010
	CORETSElII=32'b00000000000000000000000000010010
	CORETSEiII=32'b00000000000000000000000000000101
	CORETSEOlI=32'b00000000000000000000000000000101
	CORETSEoII=32'b00000000000000000000000000000001
   Generated name = tsmac_top_Z5

@N:CG364 : sib_sync_pulse.v(5) | Synthesizing module sib_sync_pulse

@N:CG364 : sib_sync_2flp.v(5) | Synthesizing module sib_sync_2flp

	CORETSEoO01I=32'b00000000000000000000000000000001
	CORETSEiO01I=32'b00000000000000000000000000000000
   Generated name = sib_sync_2flp_1s_0s

@W:CG133 : sib_sync_2flp.v(62) | No assignment to CORETSEii1I
@N:CG364 : pemstat_cntrl.v(6) | Synthesizing module pemstat_cntrl

@W:CG360 : pemstat_cntrl.v(108) | No assignment to wire CORETSEi00o

@W:CG360 : pemstat_cntrl.v(110) | No assignment to wire CORETSEO10o

@W:CG133 : pemstat_cntrl.v(113) | No assignment to CORETSEI10o
@W:CG133 : pemstat_cntrl.v(115) | No assignment to CORETSEl10o
@W:CG133 : pemstat_cntrl.v(124) | No assignment to CORETSEi11I
@W:CG133 : pemstat_cntrl.v(126) | No assignment to CORETSEIo0o
@N:CG364 : pemstat_linc.v(6) | Synthesizing module pemstat_linc

@N:CG179 : pemstat_linc.v(183) | Removing redundant assignment
@N:CG179 : pemstat_linc.v(255) | Removing redundant assignment
@N:CG364 : pemstat_ladd.v(6) | Synthesizing module pemstat_ladd

@N:CG179 : pemstat_ladd.v(338) | Removing redundant assignment
@N:CG364 : pemstat_sinc.v(6) | Synthesizing module pemstat_sinc

@N:CG179 : pemstat_sinc.v(183) | Removing redundant assignment
@N:CG179 : pemstat_sinc.v(255) | Removing redundant assignment
@N:CG364 : pemstat_sinchd.v(6) | Synthesizing module pemstat_sinchd

@N:CG179 : pemstat_sinchd.v(183) | Removing redundant assignment
@N:CG179 : pemstat_sinchd.v(255) | Removing redundant assignment
@N:CG364 : pemstat_sadd.v(6) | Synthesizing module pemstat_sadd

@N:CG179 : pemstat_sadd.v(201) | Removing redundant assignment
@N:CG179 : pemstat_sadd.v(278) | Removing redundant assignment
@N:CG364 : pemstat_sincnf.v(6) | Synthesizing module pemstat_sincnf

@N:CG179 : pemstat_sincnf.v(183) | Removing redundant assignment
@N:CG179 : pemstat_sincnf.v(255) | Removing redundant assignment
@N:CG364 : pemstat_store.v(6) | Synthesizing module pemstat_store

@N:CG364 : pemstat_eim.v(6) | Synthesizing module pemstat_eim

@N:CG364 : pemstat.v(6) | Synthesizing module pemstat

@N:CG364 : mmcxwol.v(6) | Synthesizing module mmcxwol

@N:CG364 : si_sal.v(4) | Synthesizing module si_sal

@N:CG179 : si_sal.v(886) | Removing redundant assignment
@W:CG360 : tsmac_top.v(149) | No assignment to wire CORETSElI0

@W:CG360 : tsmac_top.v(151) | No assignment to wire CORETSEoI0

@W:CG360 : tsmac_top.v(153) | No assignment to wire CORETSEiI0

@W:CG360 : tsmac_top.v(155) | No assignment to wire CORETSEOl0

@W:CG360 : tsmac_top.v(157) | No assignment to wire CORETSEIl0

@N:CG364 : tx2048x40.v(6) | Synthesizing module tx2048x40

	TABITS=32'b00000000000000000000000000001011
	CORETSEO0II=32'b00000000000000000000000000000001
	CORETSEI1I1I=32'b00000000000000000000000000000001
	CORETSEl1I1I=32'b00000000000000000000000000000100
   Generated name = tx2048x40_11s_1s_1s_4s

@N:CL134 : tx2048x40.v(131) | Found RAM CORETSEi1I1I, depth=2048, width=40
@N:CG364 : rx4096x36.v(6) | Synthesizing module rx4096x36

	RABITS=32'b00000000000000000000000000001100
	CORETSEO0II=32'b00000000000000000000000000000001
	CORETSEI1I1I=32'b00000000000000000000000000000001
	CORETSEl1I1I=32'b00000000000000000000000000000100
   Generated name = rx4096x36_12s_1s_1s_4s

@N:CL134 : rx4096x36.v(131) | Found RAM CORETSEi1I1I, depth=4096, width=36
@N:CG364 : CoreTSE_top.v(2) | Synthesizing module CoreTSE_TOP

	GMII_TBI=32'b00000000000000000000000000000001
	TABITS=32'b00000000000000000000000000001011
	RABITS=32'b00000000000000000000000000001100
	SAL=32'b00000000000000000000000000000001
	WOL=32'b00000000000000000000000000000001
	STATS=32'b00000000000000000000000000000001
	MDIO_PHYID=32'b00000000000000000000000000010010
   Generated name = CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s

@N:CG364 : msgmii_clkrst.v(7) | Synthesizing module msgmii_clkrst

@N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module msgmii_cnvtxi

@W:CL169 : msgmii_cnvtxi.v(319) | Pruning register CORETSEloil[3:0] 

@N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module msgmii_cnvtxo

@N:CG364 : t8b10b.v(6) | Synthesizing module t8b10b

@N:CG364 : petex_top.v(6) | Synthesizing module petex_top

	CORETSEIOI=32'b00000000000000000000000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = petex_top_0s_1s

@N:CG179 : petex_top.v(2036) | Removing redundant assignment
@W:CL169 : petex_top.v(639) | Pruning register CORETSEII0OI 

@N:CG364 : perex_pma.v(6) | Synthesizing module perex_pma

@W:CL169 : perex_pma.v(1536) | Pruning register CORETSEOili 

@W:CL169 : perex_pma.v(1506) | Pruning register CORETSEioli 

@W:CL169 : perex_pma.v(1476) | Pruning register CORETSEooli 

@N:CG364 : r10b8b.v(6) | Synthesizing module r10b8b

@N:CG364 : perex_pcs.v(6) | Synthesizing module perex_pcs

	CORETSEIOI=32'b00000000000000000000000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = perex_pcs_0s_1s

@W:CL169 : perex_pcs.v(4065) | Pruning register CORETSEiOli 

@W:CL169 : perex_pcs.v(4010) | Pruning register CORETSElOli 

@W:CL169 : perex_pcs.v(3869) | Pruning register CORETSEliIi 

@W:CL265 : perex_pcs.v(1203) | Pruning bit 3 of CORETSEilio[3:0] -- not in use ...

@W:CL265 : perex_pcs.v(1203) | Pruning bit 1 of CORETSEilio[3:0] -- not in use ...

@N:CL177 : perex_pcs.v(3570) | Sharing sequential element CORETSEIoIi.
@N:CG364 : peanx_sync.v(6) | Synthesizing module peanx_sync

@N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module msgmii_peanx_top

@W:CL169 : msgmii_peanx_top.v(3015) | Pruning register CORETSElO10 

@W:CL265 : msgmii_peanx_top.v(2937) | Pruning bit 14 of CORETSEOO10[15:0] -- not in use ...

@W:CL265 : msgmii_peanx_top.v(2345) | Pruning bit 14 of CORETSEO000[15:0] -- not in use ...

@N:CL177 : msgmii_peanx_top.v(2271) | Sharing sequential element CORETSEiI00.
@N:CG364 : petbm.v(6) | Synthesizing module petbm

	CORETSEIOI=32'b00000000000000000000000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = petbm_0s_1s

@W:CL169 : petbm.v(2461) | Pruning register CORETSEl1lOI 

@N:CG364 : petcr.v(7) | Synthesizing module petcr

@N:CL177 : petcr.v(329) | Sharing sequential element CORETSEOO11.
@N:CL177 : petcr.v(470) | Sharing sequential element CORETSEOO0OI.
@N:CG364 : msgmii_tbi.v(6) | Synthesizing module msgmii_tbi

	CORETSEIOI=32'b00000000000000000000000000000000
	CORETSEO0II=32'b00000000000000000000000000000001
   Generated name = msgmii_tbi_0s_1s

@W:CG360 : msgmii_tbi.v(387) | No assignment to wire CORETSEI010

@N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module msgmii_cnvrxi

@W:CL169 : msgmii_cnvrxi.v(416) | Pruning register CORETSEOool[1:0] 

@N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module msgmii_cnvrxo

@N:CG364 : msgmii_core.v(6) | Synthesizing module msgmii_core

	CORETSEIOI=32'b00000000000000000000000000000000
	MDIO_PHYID=32'b00000000000000000000000000010010
   Generated name = msgmii_core_0s_18s

@W:CG781 : CoreTSE_top.v(861) | Undriven input CORETSElO0 on instance CORETSEIlI, tying to 0
@W:CG781 : CoreTSE_top.v(865) | Undriven input CORETSEoO0 on instance CORETSEIlI, tying to 0
@W:CG781 : CoreTSE_top.v(869) | Undriven input CORETSEiO0 on instance CORETSEIlI, tying to 0
@W:CG781 : CoreTSE_top.v(873) | Undriven input CORETSEOI0 on instance CORETSEIlI, tying to 0
@W:CG781 : CoreTSE_top.v(877) | Undriven input CORETSEII0 on instance CORETSEIlI, tying to 0
@W:CG781 : CoreTSE_top.v(901) | Undriven input CORETSEll0 on instance CORETSEIlI, tying to 0
@W:CG360 : CoreTSE_top.v(78) | No assignment to wire TXD

@W:CG360 : CoreTSE_top.v(80) | No assignment to wire TXEN

@W:CG360 : CoreTSE_top.v(82) | No assignment to wire TXER

@N:CG364 : CoreTSE.v(2) | Synthesizing module Igloo2_1000BaseT_sb_CORETSE_0_CORETSE

	FAMILY=32'b00000000000000000000000000010011
	GMII_TBI=32'b00000000000000000000000000000001
	SAL=32'b00000000000000000000000000000001
	WOL=32'b00000000000000000000000000000001
	STATS=32'b00000000000000000000000000000001
	MDIO_PHYID=32'b00000000000000000000000000010010
	PACKET_SIZE=32'b00000000000000000000000000001011
   Generated name = Igloo2_1000BaseT_sb_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s

@N:CG364 : igloo2.v(362) | Synthesizing module CLKINT

@N:CG364 : igloo2.v(376) | Synthesizing module VCC

@N:CG364 : igloo2.v(372) | Synthesizing module GND

@N:CG364 : igloo2.v(727) | Synthesizing module CCC

@N:CG364 : Igloo2_1000BaseT_sb_FCCC_0_FCCC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_FCCC_0_FCCC

@N:CG364 : igloo2.v(268) | Synthesizing module INBUF

@N:CG364 : Igloo2_1000BaseT_sb_sb_CCC_0_FCCC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_sb_CCC_0_FCCC

@N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster

	DATA_LOCATION=32'b00000000000000111110100000000000
	ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000
	ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
	S7=32'b00000000000000000000000000000111
	S8=32'b00000000000000000000000000001000
	S9=32'b00000000000000000000000000001001
	S10=32'b00000000000000000000000000001010
	S11=32'b00000000000000000000000000001011
	S12=32'b00000000000000000000000000001100
	S13=32'b00000000000000000000000000001101
	S14=32'b00000000000000000000000000001110
	S15=32'b00000000000000000000000000001111
	S16=32'b00000000000000000000000000010000
	S17=32'b00000000000000000000000000010001
	S18=32'b00000000000000000000000000010010
	S19=32'b00000000000000000000000000010011
	S20=32'b00000000000000000000000000010100
	S21=32'b00000000000000000000000000010101
	S22=32'b00000000000000000000000000010110
	P0=32'b00000000000000000000000000100000
	P1=32'b00000000000000000000000000100001
	P2=32'b00000000000000000000000000100010
	P3=32'b00000000000000000000000000100011
	P4=32'b00000000000000000000000000100100
	P5=32'b00000000000000000000000000100101
	P6=32'b00000000000000000000000000100110
	OP_COPY=7'b0000000
	OP_POLL=7'b0000010
	OP_LOAD=7'b0000011
	OP_STORE=7'b0000100
	OP_AND=7'b0000101
	OP_OR=7'b0000110
   Generated name = CoreConfigMaster_Z6

@W:CL190 : coreconfigmaster.v(723) | Optimizing register bit HTRANS[0] to a constant 0
@W:CL260 : coreconfigmaster.v(723) | Pruning register bit 0 of HTRANS[1:0] 

@W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z7

@N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM

	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	HRESPEXTEND=1'b1
   Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1

@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0

@N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState.
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z8

@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0

@N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState.
@N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER

	SYNC_RESET=32'b00000000000000000000000000000000
	M0EXTEND=4'b0000
	M0DONE=4'b0001
	M0LOCK=4'b0010
	M0LOCKEXTEND=4'b0011
	M1EXTEND=4'b0100
	M1DONE=4'b0101
	M1LOCK=4'b0110
	M1LOCKEXTEND=4'b0111
	M2EXTEND=4'b1000
	M2DONE=4'b1001
	M2LOCK=4'b1010
	M2LOCKEXTEND=4'b1011
	M3EXTEND=4'b1100
	M3DONE=4'b1101
	M3LOCK=4'b1110
	M3LOCKEXTEND=4'b1111
	MASTER_0=4'b0001
	MASTER_1=4'b0010
	MASTER_2=4'b0100
	MASTER_3=4'b1000
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVEARBITER_Z9

@N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE

	SYNC_RESET=32'b00000000000000000000000000000000
	TRN_IDLE=1'b0
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0

@N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s

@N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite

	FAMILY=6'b011000
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	SYNC_RESET=32'b00000000000000000000000000000000
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z10

@N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000001
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000001
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z11

@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000001
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000001
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z12

@N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset

@W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] 

@W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] 

@W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] 

@W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc 

@W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable 

@W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable 

@W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable 

@W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable 

@N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset 

@W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int 

@W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base 

@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC

@N:CG364 : Igloo2_1000BaseT_sb_sb_HPMS_syn.v(5) | Synthesizing module MSS_010

@N:CG364 : Igloo2_1000BaseT_sb_sb_HPMS.v(9) | Synthesizing module Igloo2_1000BaseT_sb_sb_HPMS

@N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET

@N:CG364 : Igloo2_1000BaseT_sb_sb.v(9) | Synthesizing module Igloo2_1000BaseT_sb_sb

@N:CG364 : coretse_if_0.v(18) | Synthesizing module coretse_if

@A:CL282 : coretse_if_0.v(140) | Feedback mux created for signal bytes_valid_rx[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A:CL282 : coretse_if_0.v(140) | Feedback mux created for signal WDATA[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A:CL282 : coretse_if_0.v(53) | Feedback mux created for signal MTXDAT[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18

@N:CG364 : LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v(5) | Synthesizing module LSRAM_MTX_MRX_TPSRAM_0_TPSRAM

@N:CG364 : LSRAM_MTX_MRX.v(9) | Synthesizing module LSRAM_MTX_MRX

@N:CG364 : igloo2.v(320) | Synthesizing module INBUF_DIFF

@N:CG364 : Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0

@N:CG364 : Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF

@N:CG364 : Igloo2_1000BaseT_sb.v(9) | Synthesizing module Igloo2_1000BaseT_sb

@N:CG364 : coreabc.v(46) | Synthesizing module Test_1000BaseT_COREABC_0_COREABC

	FAMILY=32'b00000000000000000000000000011000
	APB_AWIDTH=32'b00000000000000000000000000010000
	APB_DWIDTH=32'b00000000000000000000000000100000
	APB_SDEPTH=32'b00000000000000000000000000010000
	ICWIDTH=32'b00000000000000000000000000001011
	ZRWIDTH=32'b00000000000000000000000000010000
	IFWIDTH=32'b00000000000000000000000000000001
	IIWIDTH=32'b00000000000000000000000000000001
	IOWIDTH=32'b00000000000000000000000000000001
	STWIDTH=32'b00000000000000000000000000001000
	EN_RAM=32'b00000000000000000000000000000001
	EN_AND=32'b00000000000000000000000000000001
	EN_XOR=32'b00000000000000000000000000000001
	EN_OR=32'b00000000000000000000000000000001
	EN_ADD=32'b00000000000000000000000000000001
	EN_INC=32'b00000000000000000000000000000001
	EN_SHL=32'b00000000000000000000000000000001
	EN_SHR=32'b00000000000000000000000000000001
	EN_CALL=32'b00000000000000000000000000000001
	EN_PUSH=32'b00000000000000000000000000000001
	EN_MULT=32'b00000000000000000000000000000000
	EN_ACM=32'b00000000000000000000000000000000
	EN_DATAM=32'b00000000000000000000000000000010
	EN_INT=32'b00000000000000000000000000000000
	EN_IOREAD=32'b00000000000000000000000000000001
	EN_IOWRT=32'b00000000000000000000000000000001
	EN_ALURAM=32'b00000000000000000000000000000001
	EN_INDIRECT=32'b00000000000000000000000000000001
	ISRADDR=32'b00000000000000000000000000000001
	DEBUG=32'b00000000000000000000000000000000
	INSMODE=32'b00000000000000000000000000000000
	INITWIDTH=32'b00000000000000000000000000001011
	TESTMODE=32'b00000000000000000000000000000000
	ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001
	IMEM_APB_ACCESS=32'b00000000000000000000000000000000
	UNIQ_STRING_LENGTH=32'b00000000000000000000000000011000
	MAX_NVMDWIDTH=32'b00000000000000000000000000100000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	IRWIDTH=32'b00000000000000000000000000100000
	ICDEPTH=32'b00000000000000000000100000000000
	APB_SWIDTH=32'b00000000000000000000000000000100
	RAMWIDTH=32'b00000000000000000000000000111010
	SYNC_RESET=32'b00000000000000000000000000000000
	CYCLE0=2'b00
	CYCLE1=2'b01
	CYCLE2=2'b10
	CYCLE3=2'b11
   Generated name = Test_1000BaseT_COREABC_0_COREABC_Z13

@N:CG364 : ramblocks.v(25) | Synthesizing module Test_1000BaseT_COREABC_0_RAMBLOCKS

	DWIDTH=32'b00000000000000000000000000100000
	FAMILY=32'b00000000000000000000000000011000
   Generated name = Test_1000BaseT_COREABC_0_RAMBLOCKS_32s_24s

@N:CG364 : ram256x16_rtl.v(20) | Synthesizing module Test_1000BaseT_COREABC_0_RAM256X16

@N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16
@W:CG360 : ramblocks.v(38) | No assignment to wire RDW

@W:CG360 : ramblocks.v(44) | No assignment to wire RDYY

@N:CG364 : instructions.v(26) | Synthesizing module Test_1000BaseT_COREABC_0_INSTRUCTIONS

	AWIDTH=32'b00000000000000000000000000010000
	DWIDTH=32'b00000000000000000000000000100000
	SWIDTH=32'b00000000000000000000000000000100
	ICWIDTH=32'b00000000000000000000000000001011
	IIWIDTH=32'b00000000000000000000000000000001
	IFWIDTH=32'b00000000000000000000000000000001
	IWWIDTH=32'b00000000000000000000000000111010
	EN_MULT=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000001
	TESTMODE=32'b00000000000000000000000000000000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	AW=32'b00000000000000000000000000010000
	DW=32'b00000000000000000000000000100000
	SW=32'b00000000000000000000000000000100
	IW=32'b00000000000000000000000000001011
	FW=32'b00000000000000000000000000000101
	iJUMP=32'b00000000000000000010001000000001
	iCALL=32'b00000000000000000010001100000001
	iRETURN=32'b00000000000000000010010000000001
	iRETISR=32'b00000000000000000010010100000001
	iWAIT=32'b00000000000000000010011000000001
	iHALT=32'b00000000000000000010011000000001
	iINC=32'b00000000000000000000001100000000
	iACM_CTRLSTAT=8'b00000000
	iACM_ADDR_ADDR=8'b00000100
	iACM_DATA_ADDR=8'b00001000
	iADC_CTRL2_HI_ADDR=8'b00010000
	iADC_STAT_HI_ADDR=8'b00100000
	Sym_MDIO_STAT_REG=32'b00000000000000000000000000110100
	Sym_TSE_MACFG1_REG=32'b00000000000000000000000000000000
	Sym_TSE_MACFG2_REG=32'b00000000000000000000000000000100
	Label_read_phy_status=32'b00000000000000000000000000011011
	Label_delay_loop=32'b00000000000000000000000000011111
	Label_Delay_loop_phy14=32'b00000000000000000000000000100000
	Label_MDIO_wait_status=32'b00000000000000000000000000101010
	Label_Status_reg_p0=32'b00000000000000000000000000101010
   Generated name = Test_1000BaseT_COREABC_0_INSTRUCTIONS_Z14

@W:CG133 : coreabc.v(686) | No assignment to MULT
@W:CG133 : coreabc.v(687) | No assignment to A
@W:CG133 : coreabc.v(688) | No assignment to B
@W:CG360 : coreabc.v(227) | No assignment to wire DEBUG1

@W:CG360 : coreabc.v(228) | No assignment to wire DEBUG2

@W:CG360 : coreabc.v(229) | No assignment to wire DEBUGBLK_RESETN

@W:CG133 : coreabc.v(255) | No assignment to iii
@W:CG133 : coreabc.v(256) | No assignment to RAMDOUTXX
@W:CG134 : coreabc.v(260) | No assignment to bit 11 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr
@W:CL169 : coreabc.v(1031) | Pruning register GETINST 

@W:CL169 : coreabc.v(501) | Pruning register UROM.upper_addr[7:0] 

@W:CL208 : coreabc.v(1031) | All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ...
@W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0] 

@N:CG364 : CoreTSE.v(2) | Synthesizing module Test_1000BaseT_CORETSE_0_CORETSE

	FAMILY=32'b00000000000000000000000000010011
	GMII_TBI=32'b00000000000000000000000000000001
	SAL=32'b00000000000000000000000000000001
	WOL=32'b00000000000000000000000000000001
	STATS=32'b00000000000000000000000000000001
	MDIO_PHYID=32'b00000000000000000000000000010010
	PACKET_SIZE=32'b00000000000000000000000000001011
   Generated name = Test_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s

@N:CG364 : Test_1000BaseT_FCCC_0_FCCC.v(5) | Synthesizing module Test_1000BaseT_FCCC_0_FCCC

@N:CG364 : Test_1000BaseT_SERDES_IF_SERDES_IF.v(5) | Synthesizing module Test_1000BaseT_SERDES_IF_SERDES_IF

@N:CG364 : coreabc.v(46) | Synthesizing module SERDESIF_0_INIT_0test_COREABC_0_COREABC

	FAMILY=32'b00000000000000000000000000011000
	APB_AWIDTH=32'b00000000000000000000000000010000
	APB_DWIDTH=32'b00000000000000000000000000100000
	APB_SDEPTH=32'b00000000000000000000000000010000
	ICWIDTH=32'b00000000000000000000000000001100
	ZRWIDTH=32'b00000000000000000000000000000000
	IFWIDTH=32'b00000000000000000000000000000000
	IIWIDTH=32'b00000000000000000000000000000001
	IOWIDTH=32'b00000000000000000000000000000001
	STWIDTH=32'b00000000000000000000000000000100
	EN_RAM=32'b00000000000000000000000000000001
	EN_AND=32'b00000000000000000000000000000001
	EN_XOR=32'b00000000000000000000000000000000
	EN_OR=32'b00000000000000000000000000000001
	EN_ADD=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000000
	EN_SHL=32'b00000000000000000000000000000000
	EN_SHR=32'b00000000000000000000000000000000
	EN_CALL=32'b00000000000000000000000000000000
	EN_PUSH=32'b00000000000000000000000000000000
	EN_MULT=32'b00000000000000000000000000000000
	EN_ACM=32'b00000000000000000000000000000000
	EN_DATAM=32'b00000000000000000000000000000010
	EN_INT=32'b00000000000000000000000000000000
	EN_IOREAD=32'b00000000000000000000000000000000
	EN_IOWRT=32'b00000000000000000000000000000000
	EN_ALURAM=32'b00000000000000000000000000000000
	EN_INDIRECT=32'b00000000000000000000000000000000
	ISRADDR=32'b00000000000000000000000000000001
	DEBUG=32'b00000000000000000000000000000000
	INSMODE=32'b00000000000000000000000000000000
	INITWIDTH=32'b00000000000000000000000000001011
	TESTMODE=32'b00000000000000000000000000000000
	ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001
	IMEM_APB_ACCESS=32'b00000000000000000000000000000000
	UNIQ_STRING_LENGTH=32'b00000000000000000000000000011011
	MAX_NVMDWIDTH=32'b00000000000000000000000000100000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	IRWIDTH=32'b00000000000000000000000000100000
	ICDEPTH=32'b00000000000000000001000000000000
	APB_SWIDTH=32'b00000000000000000000000000000100
	RAMWIDTH=32'b00000000000000000000000000111010
	SYNC_RESET=32'b00000000000000000000000000000000
	CYCLE0=2'b00
	CYCLE1=2'b01
	CYCLE2=2'b10
	CYCLE3=2'b11
   Generated name = SERDESIF_0_INIT_0test_COREABC_0_COREABC_Z15

@N:CG364 : ramblocks.v(25) | Synthesizing module SERDESIF_0_INIT_0test_COREABC_0_RAMBLOCKS

	DWIDTH=32'b00000000000000000000000000100000
	FAMILY=32'b00000000000000000000000000011000
   Generated name = SERDESIF_0_INIT_0test_COREABC_0_RAMBLOCKS_32s_24s

@N:CG364 : ram256x16_rtl.v(20) | Synthesizing module SERDESIF_0_INIT_0test_COREABC_0_RAM256X16

@N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16
@W:CG360 : ramblocks.v(38) | No assignment to wire RDW

@W:CG360 : ramblocks.v(44) | No assignment to wire RDYY

@N:CG364 : instructions.v(26) | Synthesizing module SERDESIF_0_INIT_0test_COREABC_0_INSTRUCTIONS

	AWIDTH=32'b00000000000000000000000000010000
	DWIDTH=32'b00000000000000000000000000100000
	SWIDTH=32'b00000000000000000000000000000100
	ICWIDTH=32'b00000000000000000000000000001100
	IIWIDTH=32'b00000000000000000000000000000001
	IFWIDTH=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	EN_MULT=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000000
	TESTMODE=32'b00000000000000000000000000000000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	AW=32'b00000000000000000000000000010000
	DW=32'b00000000000000000000000000100000
	SW=32'b00000000000000000000000000000100
	IW=32'b00000000000000000000000000001100
	FW=32'b00000000000000000000000000000101
	iJUMP=32'b00000000000000000010001000000000
	iCALL=32'b00000000000000000010001100000000
	iRETURN=32'b00000000000000000010010000000000
	iRETISR=32'b00000000000000000010010100000000
	iWAIT=32'b00000000000000000010011000000000
	iHALT=32'b00000000000000000010011000000000
	iINC=32'b00000000000000000000001100000001
	iACM_CTRLSTAT=8'b00000000
	iACM_ADDR_ADDR=8'b00000100
	iACM_DATA_ADDR=8'b00001000
	iADC_CTRL2_HI_ADDR=8'b00010000
	iADC_STAT_HI_ADDR=8'b00100000
	Label_WaitSdifRelease=32'b00000000000000000000000000010011
   Generated name = SERDESIF_0_INIT_0test_COREABC_0_INSTRUCTIONS_Z16

@W:CG133 : coreabc.v(686) | No assignment to MULT
@W:CG133 : coreabc.v(687) | No assignment to A
@W:CG133 : coreabc.v(688) | No assignment to B
@W:CG133 : coreabc.v(1348) | No assignment to b
@W:CG360 : coreabc.v(227) | No assignment to wire DEBUG1

@W:CG360 : coreabc.v(228) | No assignment to wire DEBUG2

@W:CG360 : coreabc.v(229) | No assignment to wire DEBUGBLK_RESETN

@W:CG133 : coreabc.v(255) | No assignment to iii
@W:CG133 : coreabc.v(256) | No assignment to RAMDOUTXX
@W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr
@W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr
@W:CL169 : coreabc.v(1031) | Pruning register ZREGISTER[0] 

@W:CL169 : coreabc.v(1031) | Pruning register STKPTR[7:0] 

@W:CL169 : coreabc.v(1031) | Pruning register GETINST 

@W:CL169 : coreabc.v(501) | Pruning register UROM.upper_addr[7:0] 

@W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to IO_OUT[0] assign 0, register removed by optimization.
@W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ...
@W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0] 

@N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000001
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z17

@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000001
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000001
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z18

@W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] 

@W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] 

@W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] 

@W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc 

@W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable 

@W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable 

@W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable 

@W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable 

@N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
@N:CG364 : SERDESIF_0_INIT_0test.v(9) | Synthesizing module SERDESIF_0_INIT_0test

@N:CG364 : Test_1000BaseT.v(9) | Synthesizing module Test_1000BaseT

@N:CG364 : Igloo2_1000BaseT_Top.v(9) | Synthesizing module Igloo2_1000BaseT_Top

@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
@N:CL201 : coreresetp.v(1433) | Trying to extract state machine for register sm2_state
Extracted state machine for register sm2_state
State machine has 2 reachable states with original encodings of:
   000
   001
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
@W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
@W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
@W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
@W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
@W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
@W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
@W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
@W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
@W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
@W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
@W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
@W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
@W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
@N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL159 : ram256x16_rtl.v(23) | Input RESET is unused
@N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : coreabc.v(134) | Input PSLVERR_M is unused
@W:CL159 : coreabc.v(135) | Input IO_IN is unused
@W:CL159 : coreabc.v(138) | Input INTREQ is unused
@W:CL159 : coreabc.v(141) | Input INITDATVAL is unused
@W:CL159 : coreabc.v(142) | Input INITDONE is unused
@W:CL159 : coreabc.v(143) | Input INITADDR is unused
@W:CL159 : coreabc.v(144) | Input INITDATA is unused
@W:CL159 : coreabc.v(148) | Input PSEL_S is unused
@W:CL159 : coreabc.v(149) | Input PENABLE_S is unused
@W:CL159 : coreabc.v(150) | Input PWRITE_S is unused
@W:CL159 : coreabc.v(151) | Input PADDR_S is unused
@W:CL159 : coreabc.v(152) | Input PWDATA_S is unused
@W:CL156 : Test_1000BaseT_SERDES_IF_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL159 : ram256x16_rtl.v(23) | Input RESET is unused
@N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : coreabc.v(134) | Input PSLVERR_M is unused
@W:CL159 : coreabc.v(138) | Input INTREQ is unused
@W:CL159 : coreabc.v(141) | Input INITDATVAL is unused
@W:CL159 : coreabc.v(142) | Input INITDONE is unused
@W:CL159 : coreabc.v(143) | Input INITADDR is unused
@W:CL159 : coreabc.v(144) | Input INITDATA is unused
@W:CL159 : coreabc.v(148) | Input PSEL_S is unused
@W:CL159 : coreabc.v(149) | Input PENABLE_S is unused
@W:CL159 : coreabc.v(150) | Input PWRITE_S is unused
@W:CL159 : coreabc.v(151) | Input PADDR_S is unused
@W:CL159 : coreabc.v(152) | Input PWDATA_S is unused
@W:CL156 : Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@N:CL201 : coretse_if_0.v(140) | Trying to extract state machine for register rx_st
Extracted state machine for register rx_st
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   100
@N:CL201 : coretse_if_0.v(53) | Trying to extract state machine for register tx_st
Extracted state machine for register tx_st
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@W:CL247 : Igloo2_1000BaseT_sb_sb_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

@W:CL157 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W:CL157 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W:CL159 : Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC.v(14) | Input XTL is unused
@N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused

@W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused

@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
@W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
@W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
@W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
@W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
@W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
@W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
@W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
@W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
@W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
@N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused

@W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused

@W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused

@W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused

@W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused

@W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused

@W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused

@W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused

@W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused

@W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused

@W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused

@W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused

@W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused

@W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused

@W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused

@W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused

@W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused

@W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused

@W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused

@W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused

@W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused

@W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused
@W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused
@W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused
@W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused
@W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused
@W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused
@W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused
@W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused
@W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused
@W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused
@W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused
@W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused
@W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused
@W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused
@W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused
@W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused
@N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused
@W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused
@W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused
@W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused
@W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused
@W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused
@W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused
@W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused

@W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused

@W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused
@W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused
@W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused
@N:CL201 : coreconfigmaster.v(723) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 29 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   100000
   100001
   100010
   100011
   100100
   100101
   100110
@N:CL177 : petcr.v(343) | Sharing sequential element CORETSEIO11.
@N:CL177 : petcr.v(484) | Sharing sequential element CORETSEIO0OI.
@W:CL190 : petbm.v(669) | Optimizing register bit CORETSEllIOI[5] to a constant 0
@W:CL260 : petbm.v(669) | Pruning register bit 5 of CORETSEllIOI[5:0] 

@N:CL201 : msgmii_peanx_top.v(3347) | Trying to extract state machine for register CORETSElI10
@W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSEIII0[15:0] is unused

@W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSEIII0[15:0] is unused

@N:CL201 : perex_pcs.v(4633) | Trying to extract state machine for register CORETSEi1O0
Extracted state machine for register CORETSEi1O0
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL157 : CoreTSE_top.v(78) | *Output TXD has undriven bits -- simulation mismatch possible.
@W:CL157 : CoreTSE_top.v(80) | *Output TXEN has undriven bits -- simulation mismatch possible.
@W:CL157 : CoreTSE_top.v(82) | *Output TXER has undriven bits -- simulation mismatch possible.
@W:CL159 : CoreTSE_top.v(89) | Input RXD is unused
@W:CL159 : CoreTSE_top.v(91) | Input RXDV is unused
@W:CL159 : CoreTSE_top.v(93) | Input RXER is unused
@W:CL159 : CoreTSE_top.v(95) | Input CRS is unused
@W:CL159 : CoreTSE_top.v(97) | Input COL is unused
@W:CL246 : pemstat_eim.v(151) | Input port bits 24 to 20 of CORETSEOiIo[31:0] are unused

@W:CL247 : pemstat_store.v(176) | Input port bit 31 of CORETSEl00o[31:0] is unused

@W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused

@W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused

@W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused

@W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused

@W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSEl00o[30:0] are unused

@W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSEl00o[30:0] are unused

@W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSEo0o[30:0] is unused

@W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSEo0o[30:0] are unused

@W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSElio0[51:0] are unused

@W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSElio0[51:0] are unused

@W:CL159 : sib_sync_2flp.v(24) | Input CORETSEoI01I is unused
@W:CL159 : sib_sync_2flp.v(26) | Input CORETSEiI01I is unused
@W:CL246 : tsmac_top.v(175) | Input port bits 31 to 10 of CORETSEiiI[31:0] are unused

@W:CL246 : tsmac_top.v(175) | Input port bits 1 to 0 of CORETSEiiI[31:0] are unused

@W:CL157 : tsmac_top.v(149) | *Output CORETSElI0 has undriven bits -- simulation mismatch possible.
@W:CL157 : tsmac_top.v(151) | *Output CORETSEoI0 has undriven bits -- simulation mismatch possible.
@W:CL157 : tsmac_top.v(153) | *Output CORETSEiI0 has undriven bits -- simulation mismatch possible.
@W:CL157 : tsmac_top.v(155) | *Output CORETSEOl0 has undriven bits -- simulation mismatch possible.
@W:CL157 : tsmac_top.v(157) | *Output CORETSEIl0 has undriven bits -- simulation mismatch possible.
@W:CL159 : tsmac_top.v(139) | Input CORETSElO0 is unused
@W:CL159 : tsmac_top.v(141) | Input CORETSEoO0 is unused
@W:CL159 : tsmac_top.v(143) | Input CORETSEiO0 is unused
@W:CL159 : tsmac_top.v(145) | Input CORETSEOI0 is unused
@W:CL159 : tsmac_top.v(147) | Input CORETSEII0 is unused
@W:CL159 : pecar.v(120) | Input CORETSEoIo is unused
@W:CL159 : pecar.v(130) | Input CORETSEolo is unused
@W:CL159 : pecar.v(143) | Input CORETSEoOo is unused
@A:CL153 : pehst.v(613) | *Unassigned bits of CORETSEooI1 are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : pehst.v(709) | *Unassigned bits of CORETSEioI1 are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : pehst.v(714) | *Unassigned bits of CORETSEOiI1 are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : pehst.v(716) | *Unassigned bits of CORETSEIiI1 are referenced and tied to 0 -- simulation mismatch possible.
@W:CL159 : pehst.v(198) | Input CORETSEOoo0 is unused
@N:CL201 : pemgt.v(547) | Trying to extract state machine for register CORETSEi1i1
Extracted state machine for register CORETSEi1i1
State machine has 32 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11101
   11110
   11111
@W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSEl110[1:0] is unused

@W:CL138 : perfn_top.v(3373) | Removing register 'CORETSEOOi0' because it is only assigned 0 or its original value.
@N:CL201 : perfn_top.v(5127) | Trying to extract state machine for register CORETSEo0o
@W:CL246 : perfn_top.v(142) | Input port bits 1 to 0 of CORETSEIoO1[7:0] are unused

@N:CL135 : petfn_top.v(6206) | Found seqShift CORETSEOIlII, depth=3, width=8
@N:CL135 : petfn_top.v(7121) | Found seqShift CORETSEIllII, depth=4, width=1
@N:CL135 : petfn_top.v(6988) | Found seqShift CORETSEiIlII, depth=4, width=1
@N:CL135 : petfn_top.v(7239) | Found seqShift CORETSEollII, depth=4, width=1
@N:CL135 : petfn_top.v(2644) | Found seqShift CORETSEl1iOI, depth=3, width=1
@N:CL135 : petfn_top.v(2813) | Found seqShift CORETSEOOOII, depth=3, width=4
@N:CL135 : petfn_top.v(8329) | Found seqShift CORETSEl01, depth=3, width=1
@N:CL135 : petfn_top.v(7634) | Found seqShift CORETSEI01, depth=4, width=1
@N:CL201 : petfn_top.v(10298) | Trying to extract state machine for register CORETSElio0
@W:CL246 : petfn_top.v(214) | Input port bits 1 to 0 of CORETSEI0O1[6:0] are unused

@W:CL246 : petfn_top.v(216) | Input port bits 1 to 0 of CORETSEl0O1[6:0] are unused

@W:CL246 : petfn_top.v(218) | Input port bits 1 to 0 of CORETSEo0O1[6:0] are unused

@W:CL246 : petfn_top.v(226) | Input port bits 9 to 6 of CORETSEi0O1[9:0] are unused

@W:CL159 : petfn_top.v(326) | Input CORETSEO1i0 is unused
@W:CL159 : petfn_top.v(329) | Input CORETSEI1i0 is unused
@W:CL159 : petfn_top.v(337) | Input CORETSEl1i0 is unused
@W:CL159 : petfn_top.v(340) | Input CORETSEo1i0 is unused
@W:CL159 : petfn_top.v(351) | Input CORETSEi1i0 is unused
@W:CL159 : petfn_top.v(343) | Input CORETSEOoi0 is unused
@W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSEl110[1:0] is unused

@W:CL159 : amcxfif_hst.v(232) | Input CORETSEiOOI is unused
@N:CL201 : amcxtfif_wtm.v(268) | Trying to extract state machine for register CORETSEooiI
Extracted state machine for register CORETSEooiI
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL246 : amcxrfif_sys.v(234) | Input port bits 39 to 36 of CORETSEOOII[39:0] are unused

@N:CL135 : amcxrfif_fab.v(1079) | Found seqShift CORETSEioi, depth=3, width=1
@N:CL201 : amcxrfif_fab.v(588) | Trying to extract state machine for register CORETSEO10I
Extracted state machine for register CORETSEO10I
State machine has 5 reachable states with original encodings of:
   0000
   1000
   1100
   1110
   1111
@W:CL247 : amcxrfif_fab.v(123) | Input port bit 12 of CORETSEIOII[13:0] is unused

@N:CL201 : amcxtfif_sys.v(804) | Trying to extract state machine for register CORETSEiooI
Extracted state machine for register CORETSEiooI
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL246 : coreapb3_iaddr_reg.v(39) | Input port bits 31 to 24 of PADDR[31:0] are unused

@W:CL159 : coreapb3.v(72) | Input IADDR is unused
@W:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused
@W:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused
@W:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused
@W:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(122) | Input PREADYS1 is unused
@W:CL159 : coreapb3.v(123) | Input PREADYS2 is unused
@W:CL159 : coreapb3.v(124) | Input PREADYS3 is unused
@W:CL159 : coreapb3.v(125) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(126) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(127) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(128) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(129) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(130) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(131) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(132) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(133) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(134) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(135) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(136) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused
@W:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused
@W:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused
@W:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused
@W:CL159 : ram256x16_rtl.v(23) | Input RESET is unused
@N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : coreabc.v(134) | Input PSLVERR_M is unused
@W:CL159 : coreabc.v(138) | Input INTREQ is unused
@W:CL159 : coreabc.v(141) | Input INITDATVAL is unused
@W:CL159 : coreabc.v(142) | Input INITDONE is unused
@W:CL159 : coreabc.v(143) | Input INITADDR is unused
@W:CL159 : coreabc.v(144) | Input INITDATA is unused
@W:CL159 : coreabc.v(148) | Input PSEL_S is unused
@W:CL159 : coreabc.v(149) | Input PENABLE_S is unused
@W:CL159 : coreabc.v(150) | Input PWRITE_S is unused
@W:CL159 : coreabc.v(151) | Input PADDR_S is unused
@W:CL159 : coreabc.v(152) | Input PWDATA_S is unused

At c_ver Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 156MB peak: 173MB)

Process took 0h:00m:09s realtime, 0h:00m:09s cputime
# Fri Nov 25 18:39:37 2016

###########################################################]
Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
@N: :  | Running in 64-bit mode 
File D:\DATA\CORETSE _MSSMAC\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\CoreTSE_loopback_demo\synthesis\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 100MB peak: 100MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Nov 25 18:39:39 2016

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 4MB peak: 4MB)

Process took 0h:00m:11s realtime, 0h:00m:11s cputime
# Fri Nov 25 18:39:39 2016

###########################################################]
Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
@N: :  | Running in 64-bit mode 
File D:\DATA\CORETSE _MSSMAC\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\CoreTSE_loopback_demo\synthesis\synwork\Igloo2_1000BaseT_Top_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 116MB peak: 117MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Nov 25 18:39:41 2016

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03M-SP1-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\designer\Igloo2_1000BaseT_Top\synthesis.fdc
@L: D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\synthesis\Igloo2_1000BaseT_Top_scck.rpt 
Printing clock  summary report in "D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\synthesis\Igloo2_1000BaseT_Top_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 167MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 167MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 167MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 167MB)

@W:BN132 : petmc_top.v(2012) | Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEoio0,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEiIl1
@W:BN132 : petfn_top.v(4500) | Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElIIII,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEllo
@W:BN132 : petfn_top.v(6138) | Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOl0OI,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIll1
@W:BN132 : perfn_top.v(3332) | Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiio0,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEOioi
@W:BN132 : permc_top.v(1848) | Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEIoOOI,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSElol1
@W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@N:BN362 : pemgt.v(2195) | Removing sequential instance CORETSEIoI1 of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt_0(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreabc.v(1031) | Removing sequential instance IO_OUT[0] of view:PrimLib.dffre(prim) in hierarchy view:work.Igloo2_1000BaseT_sb_COREABC_0_COREABC_Z1(verilog) because there are no references to its outputs 
@N:BN362 : pemgt.v(2195) | Removing sequential instance CORETSEIoI1 of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt_1(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(546) | Removing sequential instance FIC_2_APB_M_PSLVERR of view:PrimLib.dffre(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z17(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreabc.v(1031) | Removing sequential instance IO_OUT[0] of view:PrimLib.dffre(prim) in hierarchy view:work.Test_1000BaseT_COREABC_0_COREABC_Z13(verilog) because there are no references to its outputs 
@N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_1_0(verilog) because there are no references to its outputs 
@N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_0_0(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_1_1(verilog) because there are no references to its outputs 
@N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1433) | Removing sequential instance EXT_RESET_OUT_int of view:PrimLib.dffse(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1388) | Removing sequential instance RESET_N_F2M_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(630) | Removing sequential instance CORETSEli01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(683) | Removing sequential instance CORETSEIO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEoi11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEIOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_core.v(251) | Removing sequential instance CORETSEIi1[9:0] of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_core_0s_18s_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(630) | Removing sequential instance CORETSEli01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(683) | Removing sequential instance CORETSEIO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEoi11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEIOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_core.v(251) | Removing sequential instance CORETSEIi1[9:0] of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_core_0s_18s_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : pemgt.v(2657) | Removing sequential instance CORETSEl0Io of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(616) | Removing sequential instance CORETSEIi01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(669) | Removing sequential instance CORETSEOO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEli11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEOOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(420) | Removing sequential instance CORETSEI001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(471) | Removing sequential instance CORETSEO101 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1055) | Removing sequential instance CORETSEo111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(250) | Removing sequential instance CORETSEIIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_0(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(289) | Removing sequential instance CORETSEoIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : pemgt.v(2657) | Removing sequential instance CORETSEl0Io of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(616) | Removing sequential instance CORETSEIi01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(669) | Removing sequential instance CORETSEOO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEli11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEOOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(420) | Removing sequential instance CORETSEI001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(471) | Removing sequential instance CORETSEO101 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1055) | Removing sequential instance CORETSEo111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(250) | Removing sequential instance CORETSEIIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_1(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(289) | Removing sequential instance CORETSEoIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1433) | Removing sequential instance sm2_state[1:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(406) | Removing sequential instance CORETSEO001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(457) | Removing sequential instance CORETSEi001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1041) | Removing sequential instance CORETSEl111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEIo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEio11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(237) | Removing sequential instance CORETSEOIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_0(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(276) | Removing sequential instance CORETSElIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_0(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(991) | Removing sequential instance CORETSEl0l of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(406) | Removing sequential instance CORETSEO001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(457) | Removing sequential instance CORETSEi001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1041) | Removing sequential instance CORETSEl111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEIo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEio11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(237) | Removing sequential instance CORETSEOIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_1(verilog) because there are no references to its outputs 
@N:BN362 : msgmii_clkrst.v(276) | Removing sequential instance CORETSElIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(991) | Removing sequential instance CORETSEl0l of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_1(verilog) because there are no references to its outputs 
@N:BN362 : mahbe_dual.v(282) | Removing sequential instance CORETSEl0Ol of view:PrimLib.dffse(prim) in hierarchy view:work.mahbe_dual_0s_1s_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEOo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEoo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_0(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : mahbe_dual.v(282) | Removing sequential instance CORETSEl0Ol of view:PrimLib.dffse(prim) in hierarchy view:work.mahbe_dual_0s_1s_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEOo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEoo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEO00l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s_0(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEil0l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s_0(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(1037) | Removing sequential instance CORETSEIo11I[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.tsm_sysreg_1s_0s_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEO00l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s_1(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEil0l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s_1(verilog) because there are no references to its outputs 
@N:BN362 : tsm_sysreg.v(1037) | Removing sequential instance CORETSEIo11I[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.tsm_sysreg_1s_0s_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z18(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(1025) | Removing sequential instance CORETSEl0oI[10:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_0(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(1073) | Removing sequential instance CORETSEo0oI[11:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_0(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(1025) | Removing sequential instance CORETSEl0oI[10:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_1(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(1073) | Removing sequential instance CORETSEo0oI[11:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_1(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(939) | Removing sequential instance CORETSEO0oI of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_0(verilog) because there are no references to its outputs 
@N:BN362 : amcxtfif_fab.v(939) | Removing sequential instance CORETSEO0oI of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog) because there are no references to its outputs 
@W:MT462 : test_1000baset_serdes_if_serdes_if.v(98) | Net Test_1000BaseT_0.SERDES_IF.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W:MT462 : igloo2_1000baset_sb_serdes_if_0_serdes_if.v(98) | Net Igloo2_1000BaseT_0.SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
syn_allowed_resources : blockrams=21  set on top level netlist Igloo2_1000BaseT_Top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 223MB)



@S |Clock Summary
*****************

Start                                                                          Requested     Requested     Clock        Clock               
Clock                                                                          Frequency     Period        Type         Group               
--------------------------------------------------------------------------------------------------------------------------------------------
Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL0_net_inferred_clock                         100.0 MHz     10.000        inferred     Inferred_clkgroup_10
Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL1_net_inferred_clock                         100.0 MHz     10.000        inferred     Inferred_clkgroup_11
Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF|EPCS_3_TX_CLK_inferred_clock         100.0 MHz     10.000        inferred     Inferred_clkgroup_9 
Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL0_net_inferred_clock                       100.0 MHz     10.000        inferred     Inferred_clkgroup_6 
Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL1_net_inferred_clock                       100.0 MHz     10.000        inferred     Inferred_clkgroup_1 
Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL3_net_inferred_clock                       100.0 MHz     10.000        inferred     Inferred_clkgroup_8 
Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0 
Igloo2_1000BaseT_sb_sb_HPMS|FIC_2_APB_M_PCLK_inferred_clock                    100.0 MHz     10.000        inferred     Inferred_clkgroup_7 
System                                                                         100.0 MHz     10.000        system       system_clkgroup     
Test_1000BaseT_FCCC_0_FCCC|GL0_net_inferred_clock                              100.0 MHz     10.000        inferred     Inferred_clkgroup_3 
Test_1000BaseT_FCCC_0_FCCC|GL1_net_inferred_clock                              100.0 MHz     10.000        inferred     Inferred_clkgroup_4 
Test_1000BaseT_SERDES_IF_SERDES_IF|EPCS_3_TX_CLK_inferred_clock                100.0 MHz     10.000        inferred     Inferred_clkgroup_2 
pemgt_0|CORETSEOo1_inferred_clock                                              100.0 MHz     10.000        inferred     Inferred_clkgroup_12
pemgt_1|CORETSEOo1_inferred_clock                                              100.0 MHz     10.000        inferred     Inferred_clkgroup_5 
============================================================================================================================================

@W:MT532 : msgmii_clkrst.v(354) | Found signal identified as System clock which controls 6 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEI0O0.CORETSEiO1.  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W:MT530 : coreresetp.v(1485) | Found inferred clock Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 382 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : coreresetp.v(1485) | Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 30 sequential elements including Test_1000BaseT_0.SERDESIF_0_INIT.CoreResetP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : amcxtfif_sys.v(665) | Found inferred clock Test_1000BaseT_SERDES_IF_SERDES_IF|EPCS_3_TX_CLK_inferred_clock which controls 1790 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSElioI. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : perex_pma.v(987) | Found inferred clock Test_1000BaseT_FCCC_0_FCCC|GL0_net_inferred_clock which controls 410 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEOO0i[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : perex_pma.v(127) | Found inferred clock Test_1000BaseT_FCCC_0_FCCC|GL1_net_inferred_clock which controls 12 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : pemgt.v(1863) | Found inferred clock pemgt_1|CORETSEOo1_inferred_clock which controls 290 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIOIo[7:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : ram256x16_rtl.v(32) | Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 5357 sequential elements including Igloo2_1000BaseT_0.COREABC_0.URAM\.UR.UG3\.UR_xhdl12.RD[15:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : coreconfigp.v(447) | Found inferred clock Igloo2_1000BaseT_sb_sb_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : coreresetp_pcie_hotreset.v(179) | Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL3_net_inferred_clock which controls 37 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : amcxtfif_sys.v(665) | Found inferred clock Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF|EPCS_3_TX_CLK_inferred_clock which controls 1790 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSElioI. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : perex_pma.v(987) | Found inferred clock Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL0_net_inferred_clock which controls 410 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEOO0i[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : perex_pma.v(127) | Found inferred clock Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL1_net_inferred_clock which controls 12 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : pemgt.v(1863) | Found inferred clock pemgt_0|CORETSEOo1_inferred_clock which controls 290 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIOIo[7:0]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\simulation\simulation\CoreTSE_loopback_demo\synthesis\Igloo2_1000BaseT_Top.sap. 
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 133MB peak: 223MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Nov 25 18:39:45 2016

###########################################################]
Map & Optimize Report