@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\petmc_top.v":2012:0:2012:5|Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEoio0,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEiIl1
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\petfn_top.v":4500:0:4500:5|Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElIIII,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEllo
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\petfn_top.v":6138:0:6138:5|Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOl0OI,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIll1
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\perfn_top.v":3332:0:3332:5|Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiio0,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEOioi
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\permc_top.v":1848:0:1848:5|Removing sequential instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEIoOOI,  because it is equivalent to instance Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSElol1
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT462 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\work\test_1000baset\serdes_if\test_1000baset_serdes_if_serdes_if.v":98:15:98:32|Net Test_1000BaseT_0.SERDES_IF.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\work\igloo2_1000baset_sb\serdes_if_0\igloo2_1000baset_sb_serdes_if_0_serdes_if.v":98:15:98:32|Net Igloo2_1000BaseT_0.SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT532 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v":354:0:354:5|Found signal identified as System clock which controls 6 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEI0O0.CORETSEiO1.  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock Igloo2_1000BaseT_sb_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 382 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 30 sequential elements including Test_1000BaseT_0.SERDESIF_0_INIT.CoreResetP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_sys.v":665:0:665:5|Found inferred clock Test_1000BaseT_SERDES_IF_SERDES_IF|EPCS_3_TX_CLK_inferred_clock which controls 1790 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSElioI. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v":987:0:987:5|Found inferred clock Test_1000BaseT_FCCC_0_FCCC|GL0_net_inferred_clock which controls 410 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEOO0i[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v":127:0:127:5|Found inferred clock Test_1000BaseT_FCCC_0_FCCC|GL1_net_inferred_clock which controls 12 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemgt.v":1863:0:1863:5|Found inferred clock pemgt_1|CORETSEOo1_inferred_clock which controls 290 sequential elements including Test_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIOIo[7:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\work\igloo2_1000baset_sb\coreabc_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 5357 sequential elements including Igloo2_1000BaseT_0.COREABC_0.URAM\.UR.UG3\.UR_xhdl12.RD[15:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock Igloo2_1000BaseT_sb_sb_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Found inferred clock Igloo2_1000BaseT_sb_sb_CCC_0_FCCC|GL3_net_inferred_clock which controls 37 sequential elements including Igloo2_1000BaseT_0.Igloo2_1000BaseT_sb_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_sys.v":665:0:665:5|Found inferred clock Igloo2_1000BaseT_sb_SERDES_IF_0_SERDES_IF|EPCS_3_TX_CLK_inferred_clock which controls 1790 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSElioI. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v":987:0:987:5|Found inferred clock Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL0_net_inferred_clock which controls 410 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEOO0i[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v":127:0:127:5|Found inferred clock Igloo2_1000BaseT_sb_FCCC_0_FCCC|GL1_net_inferred_clock which controls 12 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\simulation\simulation\coretse_loopback_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemgt.v":1863:0:1863:5|Found inferred clock pemgt_0|CORETSEOo1_inferred_clock which controls 290 sequential elements including Igloo2_1000BaseT_0.CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIOIo[7:0]. This clock has no specified timing constraint which may adversely impact design performance. 
