#Build: Synplify Pro (R) R-2020.09M-SP1-1, Build 100R, Feb 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I52881 # Fri Jun 4 09:49:53 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys HDL Compiler, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Verilog Compiler, Version comp202009synp2, Build 147R, Built Mar 17 2021 10:14:42, @ @N: : | Running in 64-bit mode @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\generic\igloo2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\CCC_0\Igloo2_1000BaseT_sb_CCC_0_FCCC.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\FABOSC_0\Igloo2_1000BaseT_sb_FABOSC_0_OSC.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb_HPMS\Igloo2_1000BaseT_sb_HPMS_syn.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb_HPMS\Igloo2_1000BaseT_sb_HPMS.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\Igloo2_1000BaseT_sb.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\LSRAM_MTX_MRX\TPSRAM_0\LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\hdl\coretse_if.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\LSRAM_MTX_MRX\LSRAM_MTX_MRX.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\debugblk.v" (library work) @I:"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\debugblk.v":"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\support.v" (library work) @N:CG334 : debugblk.v(68) | Read directive translate_off. @N:CG333 : debugblk.v(745) | Read directive translate_on. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\instructions.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\ram256x8_rtl.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\ramblocks.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\acmtable.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\instructnvm_bb.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v" (library work) @N:CG334 : iram512x9_rtl.v(57) | Read directive translate_off. @N:CG333 : iram512x9_rtl.v(65) | Read directive translate_on. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\instructram.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\COREABC_0\rtl\vlog\core\coreabc.v" (library work) @N:CG334 : coreabc.v(992) | Read directive translate_off. @N:CG333 : coreabc.v(994) | Read directive translate_on. @N:CG334 : coreabc.v(1389) | Read directive translate_off. @N:CG333 : coreabc.v(1433) | Read directive translate_on. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\r10b8b.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pcs.v" (library work) @W:CG1337 : perex_pcs.v(616) | Net CORETSEi0li is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petbm.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\peanx_sync.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_peanx_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petcr.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\t8b10b.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petex_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_tbi.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxi.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxo.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxi.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxo.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_core.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_clkrst.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_wtm.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_hst.v" (library work) @W:CG1337 : amcxfif_hst.v(2279) | Net CORETSEIO0I is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_fab.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_sys.v" (library work) @W:CG1337 : amcxrfif_sys.v(1585) | Net CORETSEIOoI is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_fab.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_sys.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecrc.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perfn_top.v" (library work) @W:CG1337 : perfn_top.v(2362) | Net CORETSEo0ii is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petfn_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\permc_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petmc_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac_core.v" (library work) @W:CG1337 : pe_mcxmac_core.v(1230) | Net CORETSElil1 is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecar.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pehst.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemgt.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac.v" (library work) @W:CG1337 : pe_mcxmac.v(978) | Net CORETSEI0I1 is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v" (library work) @I:"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v":"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\include.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsm_sysreg.v" (library work) @W:CG1337 : tsm_sysreg.v(352) | Net CORETSEOIo1I is not declared. @W:CG1337 : tsm_sysreg.v(372) | Net CORETSEIIo1I is not declared. @W:CG1337 : tsm_sysreg.v(392) | Net CORETSElIo1I is not declared. @W:CG1337 : tsm_sysreg.v(412) | Net CORETSEoIo1I is not declared. @W:CG1337 : tsm_sysreg.v(432) | Net CORETSEiIo1I is not declared. @W:CG1337 : tsm_sysreg.v(452) | Net CORETSEOlo1I is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mahbe_dual.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mmcxwol.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_ladd.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_linc.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sadd.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinchd.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sincnf.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinc.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_store.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_mem2p.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_2flp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_top.v" (library work) @W:CG1337 : sib_fifo_top.v(227) | Net CORETSEIO01I is not declared. @W:CG1337 : sib_fifo_top.v(468) | Net CORETSEol01I is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_hstinf.v" (library work) @W:CG1337 : ptp_hstinf.v(1596) | Net CORETSElOolI is not declared. @W:CG1337 : ptp_hstinf.v(1604) | Net CORETSEoOolI is not declared. @W:CG1337 : ptp_hstinf.v(1612) | Net CORETSEiOolI is not declared. @W:CG1337 : ptp_hstinf.v(1671) | Net CORETSEOIolI is not declared. @W:CG1337 : ptp_hstinf.v(1679) | Net CORETSEIIolI is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rfp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rtc.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_tfp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_top.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\si_sal.v" (library work) @W:CG1337 : si_sal.v(890) | Net CORETSEIll1I is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_pulse.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v" (library work) @W:CG1337 : tsmac_top.v(2416) | Net CORETSEoio1I is not declared. @W:CG1337 : tsmac_top.v(2423) | Net CORETSEiio1I is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tx2048x40.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\rx4096x36.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\CoreTSE_top.v" (library work) @W:CG1337 : CoreTSE_top.v(1048) | Net CORETSEl00 is not declared. @W:CG1337 : CoreTSE_top.v(1261) | Net CORETSEl00 is not declared. @W:CG1337 : CoreTSE_top.v(1291) | Net CORETSEoi1 is not declared. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\CORETSE_0\rtl\vlog\core_obfuscated\CoreTSE.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\FCCC_0\top_FCCC_0_FCCC.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\SERDES_IF_0\top_SERDES_IF_0_SERDES_IF_syn.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\SERDES_IF_0\top_SERDES_IF_0_SERDES_IF.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : igloo2.v(126) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 115MB peak: 115MB) @N:CG364 : igloo2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 115MB peak: 115MB) @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 115MB peak: 115MB) @N:CG364 : coreabc.v(46) | Synthesizing module top_COREABC_0_COREABC in library work. FAMILY=32'b00000000000000000000000000011000 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000010000 ICWIDTH=32'b00000000000000000000000000001011 ZRWIDTH=32'b00000000000000000000000000010000 IFWIDTH=32'b00000000000000000000000000000001 IIWIDTH=32'b00000000000000000000000000000001 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000001000 EN_RAM=32'b00000000000000000000000000000001 EN_RAM_ECC=32'b00000000000000000000000000000000 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000001 EN_INDIRECT=32'b00000000000000000000000000000001 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000011010 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000000100000000000 APB_SWIDTH=32'b00000000000000000000000000000100 RAMWIDTH=32'b00000000000000000000000000111010 SYNC_RESET=32'b00000000000000000000000000000000 ZRWIDTH_ZR=32'b00000000000000000000000000010000 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = top_COREABC_0_COREABC_Z1 @N:CG364 : ramblocks.v(25) | Synthesizing module top_COREABC_0_RAMBLOCKS in library work. EN_RAM_ECC=32'b00000000000000000000000000000000 DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011000 Generated name = top_COREABC_0_RAMBLOCKS_0s_32s_24s @N:CG364 : ram256x16_rtl.v(20) | Synthesizing module top_COREABC_0_RAM256X16 in library work. Running optimization stage 1 on top_COREABC_0_RAM256X16 ....... @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[0][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[1][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[2][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[3][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[4][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[5][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[6][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[7][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[8][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[9][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[10][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[11][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[12][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[13][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[14][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[15][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[16][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[17][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[18][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[19][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[20][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[21][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[22][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[23][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[24][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[25][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[26][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[27][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[28][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[29][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[30][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[31][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[32][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[33][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[34][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[35][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[36][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[37][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[38][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[39][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[40][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[41][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[42][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[43][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[44][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[45][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[46][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[47][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[48][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[49][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[50][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[51][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[52][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[53][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[54][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[55][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[56][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[57][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[58][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[59][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[60][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[61][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[62][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[63][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[64][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[65][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[66][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[67][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[68][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[69][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[70][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[71][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[72][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[73][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[74][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[75][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[76][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[77][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[78][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[79][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[80][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[81][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[82][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[83][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[84][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[85][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[86][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[87][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[88][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[89][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[90][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[91][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[92][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[93][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[94][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[95][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[96][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[97][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[98][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[99][15:0]. Make sure that there are no unused intermediate registers. Only the first 100 messages of id 'CL169' are reported. To see all messages use 'report_messages -log C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\synlog\top_compiler.srr -id CL169' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL169} -count unlimited' in the Tcl shell. @N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16 Finished optimization stage 1 on top_COREABC_0_RAM256X16 (CPU Time 0h:00m:00s, Memory Used current: 117MB peak: 118MB) @W:CG360 : ramblocks.v(43) | Removing wire RDW, as there is no assignment to it. @W:CG360 : ramblocks.v(49) | Removing wire RDYY, as there is no assignment to it. Running optimization stage 1 on top_COREABC_0_RAMBLOCKS_0s_32s_24s ....... @W:CL318 : ramblocks.v(40) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : ramblocks.v(41) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on top_COREABC_0_RAMBLOCKS_0s_32s_24s (CPU Time 0h:00m:00s, Memory Used current: 117MB peak: 118MB) @N:CG364 : instructions.v(26) | Synthesizing module top_COREABC_0_INSTRUCTIONS in library work. AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000100 ICWIDTH=32'b00000000000000000000000000001011 IIWIDTH=32'b00000000000000000000000000000001 IFWIDTH=32'b00000000000000000000000000000001 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000100 IW=32'b00000000000000000000000000001011 FW=32'b00000000000000000000000000000101 iJUMP=32'b00000000000000000010001000000001 iCALL=32'b00000000000000000010001100000001 iRETURN=32'b00000000000000000010010000000001 iRETISR=32'b00000000000000000010010100000001 iWAIT=32'b00000000000000000010011000000001 iHALT=32'b00000000000000000010011000000001 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Sym_MDIO_STAT_REG=32'b00000000000000000000000000110100 Sym_TSE_MACFG1_REG=32'b00000000000000000000000000000000 Sym_TSE_MACFG2_REG=32'b00000000000000000000000000000100 Label_read_phy_status=32'b00000000000000000000000000101100 Label_delay_loop=32'b00000000000000000000000000110000 Label_Delay_loop_phy14=32'b00000000000000000000000000110001 Label_MDIO_wait_status=32'b00000000000000000000000000111011 Label_Status_reg_p0=32'b00000000000000000000000000111011 Generated name = top_COREABC_0_INSTRUCTIONS_Z2 Running optimization stage 1 on top_COREABC_0_INSTRUCTIONS_Z2 ....... Finished optimization stage 1 on top_COREABC_0_INSTRUCTIONS_Z2 (CPU Time 0h:00m:00s, Memory Used current: 120MB peak: 121MB) @W:CG133 : coreabc.v(696) | Object MULT is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(697) | Object A is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(698) | Object B is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : coreabc.v(234) | Removing wire DEBUG1, as there is no assignment to it. @W:CG360 : coreabc.v(235) | Removing wire DEBUG2, as there is no assignment to it. @W:CG360 : coreabc.v(236) | Removing wire DEBUGBLK_RESETN, as there is no assignment to it. @W:CG133 : coreabc.v(262) | Object iii is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(263) | Object RAMDOUTXX is declared but not assigned. Either assign a value or remove the declaration. @W:CG134 : coreabc.v(267) | No assignment to bit 11 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 15 of ins_addr Running optimization stage 1 on top_COREABC_0_COREABC_Z1 ....... @W:CL208 : coreabc.v(1041) | All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization. @W:CL207 : coreabc.v(1041) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1041) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @N:CL189 : coreabc.v(494) | Register bit UROM.INSTR_SLOT[4] is always 0. @W:CL260 : coreabc.v(494) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on top_COREABC_0_COREABC_Z1 (CPU Time 0h:00m:00s, Memory Used current: 127MB peak: 128MB) @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 1 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000010001 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b011100 UPR_NIBBLE_POSN=4'b1000 FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b1000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z3 @N:CG364 : coreapb3_iaddr_reg.v(21) | Synthesizing module coreapb3_iaddr_reg in library COREAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 APB_DWIDTH=6'b100000 MADDR_BITS=6'b011100 Generated name = coreapb3_iaddr_reg_0s_32_28 Running optimization stage 1 on coreapb3_iaddr_reg_0s_32_28 ....... Finished optimization stage 1 on coreapb3_iaddr_reg_0s_32_28 (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) Running optimization stage 1 on CoreAPB3_Z3 ....... Finished optimization stage 1 on CoreAPB3_Z3 (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) @N:CG364 : decoder.v(6) | Synthesizing module decoder in library work. Running optimization stage 1 on decoder ....... Finished optimization stage 1 on decoder (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) @N:CG364 : tsm_sysreg.v(4) | Synthesizing module tsm_sysreg in library work. CORETSEoII=32'b00000000000000000000000000000001 CORETSEii=32'b00000000000000000000000000000000 Generated name = tsm_sysreg_1s_0s Running optimization stage 1 on tsm_sysreg_1s_0s ....... Finished optimization stage 1 on tsm_sysreg_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) @N:CG364 : mahbe_dual.v(6) | Synthesizing module mahbe_dual in library work. CORETSEii=32'b00000000000000000000000000000000 CORETSEoII=32'b00000000000000000000000000000001 Generated name = mahbe_dual_0s_1s Running optimization stage 1 on mahbe_dual_0s_1s ....... Finished optimization stage 1 on mahbe_dual_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 128MB) @W:CG168 : amcxfif.v(1037) | Type of parameter CORETSEOOo on the instance CORETSEoIII is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxtfif_fab.v(6) | Synthesizing module amcxtfif_fab in library work. TABITS=32'b00000000000000000000000000001011 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSElOoI=11'b00000000000 CORETSElO0I=12'b000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxtfif_fab_11s_32s_2s_0_0_1s Running optimization stage 1 on amcxtfif_fab_11s_32s_2s_0_0_1s ....... Finished optimization stage 1 on amcxtfif_fab_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 129MB) @W:CG168 : amcxfif.v(1218) | Type of parameter CORETSEOOo on the instance CORETSEiIII is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxtfif_sys.v(6) | Synthesizing module amcxtfif_sys in library work. TABITS=32'b00000000000000000000000000001011 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEii=32'b00000000000000000000000000000000 CORETSElO0I=12'b000000000000 CORETSEoooI=14'b00000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxtfif_sys_11s_32s_2s_0s_0_0_1s Running optimization stage 1 on amcxtfif_sys_11s_32s_2s_0s_0_0_1s ....... @W:CL271 : amcxtfif_sys.v(1656) | Pruning unused bits 1 to 0 of CORETSEIIiI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1475) | Pruning unused bits 13 to 2 of CORETSElIiI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1447) | Pruning unused bits 1 to 0 of CORETSEOIiI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1380) | Pruning unused bits 1 to 0 of CORETSEiOiI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL265 : amcxtfif_sys.v(1609) | Removing unused bit 38 of CORETSEOliI[39:0]. Either assign all bits or reduce the width of the signal. Finished optimization stage 1 on amcxtfif_sys_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 127MB peak: 129MB) @W:CG168 : amcxfif.v(1384) | Type of parameter CORETSEOOo on the instance CORETSEOlII is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxrfif_fab.v(6) | Synthesizing module amcxrfif_fab in library work. RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSElO0I=13'b0000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxrfif_fab_12s_32s_2s_0_1s @N:CG179 : amcxrfif_fab.v(971) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(977) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(983) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(989) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(995) | Removing redundant assignment. Running optimization stage 1 on amcxrfif_fab_12s_32s_2s_0_1s ....... @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[36] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[37] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[38] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[39] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : amcxrfif_fab.v(1581) | Pruning register bits 39 to 36 of CORETSEOIOI[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 1 on amcxrfif_fab_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 127MB peak: 129MB) @W:CG168 : amcxfif.v(1520) | Type of parameter CORETSEOOo on the instance CORETSEIlII is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxrfif_sys.v(6) | Synthesizing module amcxrfif_sys in library work. CORETSEii=32'b00000000000000000000000000000000 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEIo0I=14'b00000000000000 CORETSElo0I=13'b0000000000000 CORETSElO0I=15'b000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s Running optimization stage 1 on amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s ....... Finished optimization stage 1 on amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 132MB) @N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module amcxtfif_wtm in library work. RABITS=32'b00000000000000000000000000001100 CORETSEO0II=32'b00000000000000000000000000000001 CORETSElOoI=12'b000000000000 CORETSElO0I=13'b0000000000000 Generated name = amcxtfif_wtm_12s_1s_0_0 Running optimization stage 1 on amcxtfif_wtm_12s_1s_0_0 ....... Finished optimization stage 1 on amcxtfif_wtm_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 132MB) @W:CG168 : amcxfif.v(1832) | Type of parameter CORETSEOOo on the instance CORETSEolII is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxfif_hst.v(6) | Synthesizing module amcxfif_hst in library work. TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEIoII=13'b0000000000000 CORETSEloII=4'b0000 CORETSEooII=19'b0000000000000000000 CORETSEioII=12'b111111111111 CORETSEOiII=12'b111111111111 CORETSEIiII=14'b00000000000000 CORETSEliII=4'b0000 CORETSEoiII=3'b000 CORETSEiiII=18'b000000000000000000 CORETSEOOlI=13'b1111111111111 CORETSEIOlI=13'b1111111111111 CORETSElOlI=12'b111111111111 Generated name = amcxfif_hst_Z4 @W:CG360 : amcxfif_hst.v(904) | Removing wire CORETSEO0lI, as there is no assignment to it. Running optimization stage 1 on amcxfif_hst_Z4 ....... Finished optimization stage 1 on amcxfif_hst_Z4 (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 132MB) @N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module amcxfif_clkrst in library work. Running optimization stage 1 on amcxfif_clkrst ....... Finished optimization stage 1 on amcxfif_clkrst (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 132MB) @N:CG364 : amcxfif.v(6) | Synthesizing module amcxfif in library work. TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEii=32'b00000000000000000000000000000000 Generated name = amcxfif_11s_12s_32s_2s_0s Running optimization stage 1 on amcxfif_11s_12s_32s_2s_0s ....... Finished optimization stage 1 on amcxfif_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 132MB) @N:CG364 : petmc_top.v(6) | Synthesizing module petmc_top in library work. Running optimization stage 1 on petmc_top ....... Finished optimization stage 1 on petmc_top (CPU Time 0h:00m:00s, Memory Used current: 128MB peak: 132MB) @N:CG364 : pecrc.v(6) | Synthesizing module pecrc in library work. Running optimization stage 1 on pecrc ....... Finished optimization stage 1 on pecrc (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 132MB) @N:CG364 : petfn_top.v(6) | Synthesizing module petfn_top in library work. CORETSEOOI=32'b00000000000000000000000000000000 CORETSEIOI=1'b0 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petfn_top_0s_0_1s @N:CG179 : petfn_top.v(9933) | Removing redundant assignment. @N:CG179 : petfn_top.v(9993) | Removing redundant assignment. @W:CG133 : petfn_top.v(418) | Object CORETSEO1oOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(421) | Removing wire CORETSEI1oOI, as there is no assignment to it. @W:CG360 : petfn_top.v(445) | Removing wire CORETSEOo0OI, as there is no assignment to it. @W:CG133 : petfn_top.v(586) | Object CORETSEOiiOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(956) | Removing wire CORETSEliIII, as there is no assignment to it. Running optimization stage 1 on petfn_top_0s_0_1s ....... @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : petfn_top.v(3748) | Pruning register bits 6 to 5 of CORETSEOoOII[6:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 1 on petfn_top_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 132MB) @N:CG364 : perfn_top.v(6) | Synthesizing module perfn_top in library work. CORETSEii=32'b00000000000000000000000000000000 CORETSEIOI=1'b0 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = perfn_top_0s_0_1s @W:CG360 : perfn_top.v(343) | Removing wire CORETSEol0i, as there is no assignment to it. @W:CG360 : perfn_top.v(650) | Removing wire CORETSEIioi, as there is no assignment to it. @W:CG133 : perfn_top.v(653) | Object CORETSElioi is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on perfn_top_0s_0_1s ....... Finished optimization stage 1 on perfn_top_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 141MB) @N:CG364 : permc_top.v(6) | Synthesizing module permc_top in library work. Running optimization stage 1 on permc_top ....... Finished optimization stage 1 on permc_top (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module pe_mcxmac_core in library work. CORETSEIOI=1'b0 CORETSEii=32'b00000000000000000000000000000000 CORETSEOOI=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_core_0_0s_0s Running optimization stage 1 on pe_mcxmac_core_0_0s_0s ....... Finished optimization stage 1 on pe_mcxmac_core_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pemgt.v(6) | Synthesizing module pemgt in library work. Running optimization stage 1 on pemgt ....... Finished optimization stage 1 on pemgt (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pehst.v(6) | Synthesizing module pehst in library work. @W:CG133 : pehst.v(613) | Object CORETSEooI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(709) | Object CORETSEioI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(714) | Object CORETSEOiI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(716) | Object CORETSEIiI1 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on pehst ....... Finished optimization stage 1 on pehst (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pecar.v(6) | Synthesizing module pecar in library work. Running optimization stage 1 on pecar ....... Finished optimization stage 1 on pecar (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pe_mcxmac.v(6) | Synthesizing module pe_mcxmac in library work. CORETSEIOI=1'b0 CORETSEOOI=32'b00000000000000000000000000000000 CORETSEii=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_0_0s_0s @W:CG360 : pe_mcxmac.v(676) | Removing wire CORETSEOii0, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(679) | Removing wire CORETSEI0I0, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(682) | Removing wire CORETSEl0I0, as there is no assignment to it. Running optimization stage 1 on pe_mcxmac_0_0s_0s ....... Finished optimization stage 1 on pe_mcxmac_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : tsmac_top.v(4) | Synthesizing module tsmac_top in library work. TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MDIO_PHYID=32'b00000000000000000000000000010010 CORETSEIi=32'b00000000000000000000000000000001 CORETSEli=32'b00000000000000000000000000000001 CORETSEoi=32'b00000000000000000000000000000001 CORETSEii=32'b00000000000000000000000000000000 CORETSEOOI=32'b00000000000000000000000000000000 CORETSEIOI=32'b00000000000000000000000000000000 CORETSElOI=32'b00000000000000000000000000000001 CORETSEoOI=32'b00000000000000000000000000000010 CORETSEiOI=32'b00000000000000000000000000000001 CORETSEOII=32'b00000000000000000000000000000010 CORETSEIII=32'b00000000000000000000000000010010 CORETSElII=32'b00000000000000000000000000010010 CORETSEiII=32'b00000000000000000000000000000101 CORETSEOlI=32'b00000000000000000000000000000101 CORETSEoII=32'b00000000000000000000000000000001 Generated name = tsmac_top_Z5 @N:CG364 : sib_sync_pulse.v(5) | Synthesizing module sib_sync_pulse in library work. @N:CG364 : sib_sync_2flp.v(5) | Synthesizing module sib_sync_2flp in library work. CORETSEoO01I=32'b00000000000000000000000000000001 CORETSEiO01I=32'b00000000000000000000000000000000 Generated name = sib_sync_2flp_1s_0s @W:CG133 : sib_sync_2flp.v(62) | Object CORETSEii1I is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on sib_sync_2flp_1s_0s ....... Finished optimization stage 1 on sib_sync_2flp_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) Running optimization stage 1 on sib_sync_pulse ....... Finished optimization stage 1 on sib_sync_pulse (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : pemstat_cntrl.v(6) | Synthesizing module pemstat_cntrl in library work. @W:CG360 : pemstat_cntrl.v(108) | Removing wire CORETSEi00o, as there is no assignment to it. @W:CG360 : pemstat_cntrl.v(110) | Removing wire CORETSEO10o, as there is no assignment to it. @W:CG133 : pemstat_cntrl.v(113) | Object CORETSEI10o is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(115) | Object CORETSEl10o is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(124) | Object CORETSEi11I is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(126) | Object CORETSEIo0o is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on pemstat_cntrl ....... Finished optimization stage 1 on pemstat_cntrl (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_linc.v(6) | Synthesizing module pemstat_linc in library work. @N:CG179 : pemstat_linc.v(183) | Removing redundant assignment. @N:CG179 : pemstat_linc.v(255) | Removing redundant assignment. Running optimization stage 1 on pemstat_linc ....... Finished optimization stage 1 on pemstat_linc (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_ladd.v(6) | Synthesizing module pemstat_ladd in library work. @N:CG179 : pemstat_ladd.v(338) | Removing redundant assignment. Running optimization stage 1 on pemstat_ladd ....... Finished optimization stage 1 on pemstat_ladd (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_sinc.v(6) | Synthesizing module pemstat_sinc in library work. @N:CG179 : pemstat_sinc.v(183) | Removing redundant assignment. @N:CG179 : pemstat_sinc.v(255) | Removing redundant assignment. Running optimization stage 1 on pemstat_sinc ....... Finished optimization stage 1 on pemstat_sinc (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_sinchd.v(6) | Synthesizing module pemstat_sinchd in library work. @N:CG179 : pemstat_sinchd.v(183) | Removing redundant assignment. @N:CG179 : pemstat_sinchd.v(255) | Removing redundant assignment. Running optimization stage 1 on pemstat_sinchd ....... Finished optimization stage 1 on pemstat_sinchd (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_sadd.v(6) | Synthesizing module pemstat_sadd in library work. @N:CG179 : pemstat_sadd.v(201) | Removing redundant assignment. @N:CG179 : pemstat_sadd.v(278) | Removing redundant assignment. Running optimization stage 1 on pemstat_sadd ....... Finished optimization stage 1 on pemstat_sadd (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_sincnf.v(6) | Synthesizing module pemstat_sincnf in library work. @N:CG179 : pemstat_sincnf.v(183) | Removing redundant assignment. @N:CG179 : pemstat_sincnf.v(255) | Removing redundant assignment. Running optimization stage 1 on pemstat_sincnf ....... Finished optimization stage 1 on pemstat_sincnf (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_store.v(6) | Synthesizing module pemstat_store in library work. Running optimization stage 1 on pemstat_store ....... Finished optimization stage 1 on pemstat_store (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 143MB) @N:CG364 : pemstat_eim.v(6) | Synthesizing module pemstat_eim in library work. Running optimization stage 1 on pemstat_eim ....... Finished optimization stage 1 on pemstat_eim (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 143MB) @N:CG364 : pemstat.v(6) | Synthesizing module pemstat in library work. Running optimization stage 1 on pemstat ....... Finished optimization stage 1 on pemstat (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 143MB) @N:CG364 : mmcxwol.v(6) | Synthesizing module mmcxwol in library work. Running optimization stage 1 on mmcxwol ....... Finished optimization stage 1 on mmcxwol (CPU Time 0h:00m:00s, Memory Used current: 131MB peak: 143MB) @N:CG364 : si_sal.v(4) | Synthesizing module si_sal in library work. @N:CG179 : si_sal.v(886) | Removing redundant assignment. Running optimization stage 1 on si_sal ....... Finished optimization stage 1 on si_sal (CPU Time 0h:00m:00s, Memory Used current: 131MB peak: 143MB) @W:CG360 : tsmac_top.v(149) | Removing wire CORETSElI0, as there is no assignment to it. @W:CG360 : tsmac_top.v(151) | Removing wire CORETSEoI0, as there is no assignment to it. @W:CG360 : tsmac_top.v(153) | Removing wire CORETSEiI0, as there is no assignment to it. @W:CG360 : tsmac_top.v(155) | Removing wire CORETSEOl0, as there is no assignment to it. @W:CG360 : tsmac_top.v(157) | Removing wire CORETSEIl0, as there is no assignment to it. Running optimization stage 1 on tsmac_top_Z5 ....... @W:CL318 : tsmac_top.v(149) | *Output CORETSElI0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(151) | *Output CORETSEoI0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(153) | *Output CORETSEiI0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(155) | *Output CORETSEOl0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(157) | *Output CORETSEIl0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on tsmac_top_Z5 (CPU Time 0h:00m:00s, Memory Used current: 131MB peak: 143MB) @N:CG364 : tx2048x40.v(6) | Synthesizing module tx2048x40 in library work. TABITS=32'b00000000000000000000000000001011 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEI1I1I=32'b00000000000000000000000000000001 CORETSEl1I1I=32'b00000000000000000000000000000100 Generated name = tx2048x40_11s_1s_1s_4s Running optimization stage 1 on tx2048x40_11s_1s_1s_4s ....... @N:CL134 : tx2048x40.v(131) | Found RAM CORETSEi1I1I, depth=2048, width=40 Finished optimization stage 1 on tx2048x40_11s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 143MB) @N:CG364 : rx4096x36.v(6) | Synthesizing module rx4096x36 in library work. RABITS=32'b00000000000000000000000000001100 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEI1I1I=32'b00000000000000000000000000000001 CORETSEl1I1I=32'b00000000000000000000000000000100 Generated name = rx4096x36_12s_1s_1s_4s Running optimization stage 1 on rx4096x36_12s_1s_1s_4s ....... @N:CL134 : rx4096x36.v(131) | Found RAM CORETSEi1I1I, depth=4096, width=36 Finished optimization stage 1 on rx4096x36_12s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 136MB peak: 143MB) @N:CG364 : CoreTSE_top.v(2) | Synthesizing module CoreTSE_TOP in library work. GMII_TBI=32'b00000000000000000000000000000001 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 SAL=32'b00000000000000000000000000000001 WOL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s @N:CG364 : msgmii_clkrst.v(7) | Synthesizing module msgmii_clkrst in library work. Running optimization stage 1 on msgmii_clkrst ....... Finished optimization stage 1 on msgmii_clkrst (CPU Time 0h:00m:00s, Memory Used current: 136MB peak: 143MB) @N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module msgmii_cnvtxi in library work. Running optimization stage 1 on msgmii_cnvtxi ....... Finished optimization stage 1 on msgmii_cnvtxi (CPU Time 0h:00m:00s, Memory Used current: 136MB peak: 143MB) @N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module msgmii_cnvtxo in library work. Running optimization stage 1 on msgmii_cnvtxo ....... Finished optimization stage 1 on msgmii_cnvtxo (CPU Time 0h:00m:00s, Memory Used current: 137MB peak: 143MB) @N:CG364 : t8b10b.v(6) | Synthesizing module t8b10b in library work. Running optimization stage 1 on t8b10b ....... Finished optimization stage 1 on t8b10b (CPU Time 0h:00m:00s, Memory Used current: 137MB peak: 143MB) @N:CG364 : petex_top.v(6) | Synthesizing module petex_top in library work. CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petex_top_0s_1s @N:CG179 : petex_top.v(2036) | Removing redundant assignment. Running optimization stage 1 on petex_top_0s_1s ....... Finished optimization stage 1 on petex_top_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 137MB peak: 143MB) @N:CG364 : perex_pma.v(6) | Synthesizing module perex_pma in library work. Running optimization stage 1 on perex_pma ....... Finished optimization stage 1 on perex_pma (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 143MB) @N:CG364 : r10b8b.v(6) | Synthesizing module r10b8b in library work. Running optimization stage 1 on r10b8b ....... Finished optimization stage 1 on r10b8b (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 143MB) @N:CG364 : perex_pcs.v(6) | Synthesizing module perex_pcs in library work. CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = perex_pcs_0s_1s Running optimization stage 1 on perex_pcs_0s_1s ....... @W:CL265 : perex_pcs.v(1203) | Removing unused bit 3 of CORETSEilio[3:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : perex_pcs.v(1203) | Removing unused bit 1 of CORETSEilio[3:0]. Either assign all bits or reduce the width of the signal. @W:CL177 : perex_pcs.v(3570) | Sharing sequential element CORETSEIoIi. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on perex_pcs_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 143MB) @N:CG364 : peanx_sync.v(6) | Synthesizing module peanx_sync in library work. Running optimization stage 1 on peanx_sync ....... Finished optimization stage 1 on peanx_sync (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 143MB) @N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module msgmii_peanx_top in library work. Running optimization stage 1 on msgmii_peanx_top ....... @W:CL265 : msgmii_peanx_top.v(2937) | Removing unused bit 14 of CORETSEOO10[15:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : msgmii_peanx_top.v(2345) | Removing unused bit 14 of CORETSEO000[15:0]. Either assign all bits or reduce the width of the signal. @W:CL177 : msgmii_peanx_top.v(2271) | Sharing sequential element CORETSEiI00. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on msgmii_peanx_top (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 143MB) @N:CG364 : petbm.v(6) | Synthesizing module petbm in library work. CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petbm_0s_1s Running optimization stage 1 on petbm_0s_1s ....... Finished optimization stage 1 on petbm_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 148MB) @N:CG364 : petcr.v(7) | Synthesizing module petcr in library work. Running optimization stage 1 on petcr ....... @W:CL177 : petcr.v(329) | Sharing sequential element CORETSEOO11. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(470) | Sharing sequential element CORETSEOO0OI. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on petcr (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 148MB) @N:CG364 : msgmii_tbi.v(6) | Synthesizing module msgmii_tbi in library work. CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = msgmii_tbi_0s_1s @W:CG360 : msgmii_tbi.v(387) | Removing wire CORETSEI010, as there is no assignment to it. Running optimization stage 1 on msgmii_tbi_0s_1s ....... Finished optimization stage 1 on msgmii_tbi_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 148MB) @N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module msgmii_cnvrxi in library work. Running optimization stage 1 on msgmii_cnvrxi ....... Finished optimization stage 1 on msgmii_cnvrxi (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module msgmii_cnvrxo in library work. Running optimization stage 1 on msgmii_cnvrxo ....... Finished optimization stage 1 on msgmii_cnvrxo (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : msgmii_core.v(6) | Synthesizing module msgmii_core in library work. CORETSEIOI=32'b00000000000000000000000000000000 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = msgmii_core_0s_18s Running optimization stage 1 on msgmii_core_0s_18s ....... Finished optimization stage 1 on msgmii_core_0s_18s (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @W:CG781 : CoreTSE_top.v(861) | Input CORETSElO0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(865) | Input CORETSEoO0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(869) | Input CORETSEiO0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(873) | Input CORETSEOI0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(877) | Input CORETSEII0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(901) | Input CORETSEll0 on instance CORETSEIlI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG360 : CoreTSE_top.v(78) | Removing wire TXD, as there is no assignment to it. @W:CG360 : CoreTSE_top.v(80) | Removing wire TXEN, as there is no assignment to it. @W:CG360 : CoreTSE_top.v(82) | Removing wire TXER, as there is no assignment to it. Running optimization stage 1 on CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s ....... @W:CL318 : CoreTSE_top.v(78) | *Output TXD has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : CoreTSE_top.v(80) | *Output TXEN has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : CoreTSE_top.v(82) | *Output TXER has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : CoreTSE.v(2) | Synthesizing module top_CORETSE_0_CORETSE in library work. FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 SAL=32'b00000000000000000000000000000001 WOL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 PACKET_SIZE=32'b00000000000000000000000000001011 Generated name = top_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s Running optimization stage 1 on top_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s ....... Finished optimization stage 1 on top_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : igloo2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : igloo2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : igloo2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... Finished optimization stage 1 on CCC (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : top_FCCC_0_FCCC.v(5) | Synthesizing module top_FCCC_0_FCCC in library work. Running optimization stage 1 on top_FCCC_0_FCCC ....... Finished optimization stage 1 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : igloo2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : Igloo2_1000BaseT_sb_CCC_0_FCCC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_CCC_0_FCCC in library work. Running optimization stage 1 on Igloo2_1000BaseT_sb_CCC_0_FCCC ....... Finished optimization stage 1 on Igloo2_1000BaseT_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 148MB) @N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster in library work. DATA_LOCATION=32'b00000000000000111110100000000000 ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000 ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 S7=32'b00000000000000000000000000000111 S8=32'b00000000000000000000000000001000 S9=32'b00000000000000000000000000001001 S10=32'b00000000000000000000000000001010 S11=32'b00000000000000000000000000001011 S12=32'b00000000000000000000000000001100 S13=32'b00000000000000000000000000001101 S14=32'b00000000000000000000000000001110 S15=32'b00000000000000000000000000001111 S16=32'b00000000000000000000000000010000 S17=32'b00000000000000000000000000010001 S18=32'b00000000000000000000000000010010 S19=32'b00000000000000000000000000010011 S20=32'b00000000000000000000000000010100 S21=32'b00000000000000000000000000010101 S22=32'b00000000000000000000000000010110 P0=32'b00000000000000000000000000100000 P1=32'b00000000000000000000000000100001 P2=32'b00000000000000000000000000100010 P3=32'b00000000000000000000000000100011 P4=32'b00000000000000000000000000100100 P5=32'b00000000000000000000000000100101 P6=32'b00000000000000000000000000100110 OP_COPY=7'b0000000 OP_POLL=7'b0000010 OP_LOAD=7'b0000011 OP_STORE=7'b0000100 OP_AND=7'b0000101 OP_OR=7'b0000110 Generated name = CoreConfigMaster_Z6 Running optimization stage 1 on CoreConfigMaster_Z6 ....... @W:CL190 : coreconfigmaster.v(723) | Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : coreconfigmaster.v(723) | Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on CoreConfigMaster_Z6 (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 155MB) @N:CG775 : coreahblite.v(23) | Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB @W:CG168 : coreahblite.v(541) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_matrix4x16.v(2639) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z7 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z7 ....... Finished optimization stage 1 on COREAHBLITE_ADDRDEC_Z7 (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 155MB) @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Finished optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 155MB) @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 155MB) @W:CG168 : coreahblite_matrix4x16.v(2703) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z8 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z8 ....... Finished optimization stage 1 on COREAHBLITE_ADDRDEC_Z8 (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 155MB) @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 155MB) @W:CG168 : coreahblite_matrix4x16.v(2767) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_matrix4x16.v(2831) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z9 Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z9 ....... Finished optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z9 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Finished optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s Running optimization stage 1 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s ....... Finished optimization stage 1 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z10 Running optimization stage 1 on CoreAHBLite_Z10 ....... Finished optimization stage 1 on CoreAHBLite_Z10 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z11 Running optimization stage 1 on CoreConfigP_Z11 ....... Finished optimization stage 1 on CoreConfigP_Z11 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z12 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset in library work. Running optimization stage 1 on coreresetp_pcie_hotreset ....... Finished optimization stage 1 on coreresetp_pcie_hotreset (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) Running optimization stage 1 on CoreResetP_Z12 ....... @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished optimization stage 1 on CoreResetP_Z12 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 1 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... Finished optimization stage 1 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on Igloo2_1000BaseT_sb_FABOSC_0_OSC ....... @W:CL318 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on Igloo2_1000BaseT_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : Igloo2_1000BaseT_sb_HPMS_syn.v(5) | Synthesizing module MSS_010 in library work. Running optimization stage 1 on MSS_010 ....... Finished optimization stage 1 on MSS_010 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : Igloo2_1000BaseT_sb_HPMS.v(9) | Synthesizing module Igloo2_1000BaseT_sb_HPMS in library work. Running optimization stage 1 on Igloo2_1000BaseT_sb_HPMS ....... Finished optimization stage 1 on Igloo2_1000BaseT_sb_HPMS (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : igloo2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... Finished optimization stage 1 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : Igloo2_1000BaseT_sb.v(9) | Synthesizing module Igloo2_1000BaseT_sb in library work. Running optimization stage 1 on Igloo2_1000BaseT_sb ....... Finished optimization stage 1 on Igloo2_1000BaseT_sb (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 155MB) @N:CG364 : coretse_if.v(18) | Synthesizing module coretse_if in library work. Running optimization stage 1 on coretse_if ....... @A:CL282 : coretse_if.v(140) | Feedback mux created for signal bytes_valid_rx[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : coretse_if.v(140) | Feedback mux created for signal WDATA[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : coretse_if.v(53) | Feedback mux created for signal MTXDAT[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. Finished optimization stage 1 on coretse_if (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... Finished optimization stage 1 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v(5) | Synthesizing module LSRAM_MTX_MRX_TPSRAM_0_TPSRAM in library work. Running optimization stage 1 on LSRAM_MTX_MRX_TPSRAM_0_TPSRAM ....... Finished optimization stage 1 on LSRAM_MTX_MRX_TPSRAM_0_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : LSRAM_MTX_MRX.v(9) | Synthesizing module LSRAM_MTX_MRX in library work. Running optimization stage 1 on LSRAM_MTX_MRX ....... Finished optimization stage 1 on LSRAM_MTX_MRX (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : igloo2.v(320) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0 in library work. Running optimization stage 1 on SERDESIF_0 ....... Finished optimization stage 1 on SERDESIF_0 (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module top_SERDES_IF_0_SERDES_IF in library work. Running optimization stage 1 on top_SERDES_IF_0_SERDES_IF ....... Finished optimization stage 1 on top_SERDES_IF_0_SERDES_IF (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on top_SERDES_IF_0_SERDES_IF ....... @W:CL156 : top_SERDES_IF_0_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Finished optimization stage 2 on top_SERDES_IF_0_SERDES_IF (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on SERDESIF_0 ....... Finished optimization stage 2 on SERDESIF_0 (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on LSRAM_MTX_MRX ....... Finished optimization stage 2 on LSRAM_MTX_MRX (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on LSRAM_MTX_MRX_TPSRAM_0_TPSRAM ....... Finished optimization stage 2 on LSRAM_MTX_MRX_TPSRAM_0_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on RAM1K18 ....... Finished optimization stage 2 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 155MB) Running optimization stage 2 on coretse_if ....... @N:CL201 : coretse_if.v(140) | Trying to extract state machine for register rx_st. Extracted state machine for register rx_st State machine has 4 reachable states with original encodings of: 000 001 010 100 @N:CL201 : coretse_if.v(53) | Trying to extract state machine for register tx_st. Extracted state machine for register tx_st State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Finished optimization stage 2 on coretse_if (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on Igloo2_1000BaseT_sb ....... Finished optimization stage 2 on Igloo2_1000BaseT_sb (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on SYSRESET ....... Finished optimization stage 2 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on Igloo2_1000BaseT_sb_HPMS ....... @W:CL247 : Igloo2_1000BaseT_sb_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused Finished optimization stage 2 on Igloo2_1000BaseT_sb_HPMS (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on MSS_010 ....... Finished optimization stage 2 on MSS_010 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on Igloo2_1000BaseT_sb_FABOSC_0_OSC ....... @N:CL159 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Finished optimization stage 2 on Igloo2_1000BaseT_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on RCOSC_25_50MHZ ....... Finished optimization stage 2 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 2 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on coreresetp_pcie_hotreset ....... @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on coreresetp_pcie_hotreset (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on CoreResetP_Z12 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Finished optimization stage 2 on CoreResetP_Z12 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on CoreConfigP_Z11 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 Finished optimization stage 2 on CoreConfigP_Z11 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on CoreAHBLite_Z10 ....... @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. Finished optimization stage 2 on CoreAHBLite_Z10 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s ....... @N:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused. @N:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused. Finished optimization stage 2 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Finished optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z9 ....... @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Finished optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z9 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... @N:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Finished optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z8 ....... Finished optimization stage 2 on COREAHBLITE_ADDRDEC_Z8 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 ....... @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 146MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Finished optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 146MB peak: 155MB) Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z7 ....... Finished optimization stage 2 on COREAHBLITE_ADDRDEC_Z7 (CPU Time 0h:00m:00s, Memory Used current: 146MB peak: 155MB) Running optimization stage 2 on CoreConfigMaster_Z6 ....... @N:CL201 : coreconfigmaster.v(723) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 29 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000110 000111 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 100000 100001 100010 100011 100100 100101 100110 Finished optimization stage 2 on CoreConfigMaster_Z6 (CPU Time 0h:00m:01s, Memory Used current: 159MB peak: 169MB) Running optimization stage 2 on Igloo2_1000BaseT_sb_CCC_0_FCCC ....... Finished optimization stage 2 on Igloo2_1000BaseT_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 159MB peak: 169MB) Running optimization stage 2 on INBUF ....... Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on top_FCCC_0_FCCC ....... Finished optimization stage 2 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on CCC ....... Finished optimization stage 2 on CCC (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on top_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s ....... Finished optimization stage 2 on top_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on msgmii_core_0s_18s ....... Finished optimization stage 2 on msgmii_core_0s_18s (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 169MB) Running optimization stage 2 on msgmii_cnvrxo ....... Finished optimization stage 2 on msgmii_cnvrxo (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 169MB) Running optimization stage 2 on msgmii_cnvrxi ....... Finished optimization stage 2 on msgmii_cnvrxi (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 169MB) Running optimization stage 2 on msgmii_tbi_0s_1s ....... Finished optimization stage 2 on msgmii_tbi_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 169MB) Running optimization stage 2 on petcr ....... @W:CL177 : petcr.v(343) | Sharing sequential element CORETSEIO11. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(484) | Sharing sequential element CORETSEIO0OI. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 2 on petcr (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 169MB) Running optimization stage 2 on petbm_0s_1s ....... @W:CL190 : petbm.v(669) | Optimizing register bit CORETSEllIOI[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : petbm.v(669) | Pruning register bit 5 of CORETSEllIOI[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 2 on petbm_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 169MB) Running optimization stage 2 on msgmii_peanx_top ....... @N:CL201 : msgmii_peanx_top.v(3347) | Trying to extract state machine for register CORETSElI10. @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSEIII0[15:0] is unused @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSEIII0[15:0] is unused Finished optimization stage 2 on msgmii_peanx_top (CPU Time 0h:00m:00s, Memory Used current: 157MB peak: 169MB) Running optimization stage 2 on peanx_sync ....... Finished optimization stage 2 on peanx_sync (CPU Time 0h:00m:00s, Memory Used current: 157MB peak: 169MB) Running optimization stage 2 on perex_pcs_0s_1s ....... @N:CL201 : perex_pcs.v(4633) | Trying to extract state machine for register CORETSEi1O0. Extracted state machine for register CORETSEi1O0 State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on perex_pcs_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 177MB) Running optimization stage 2 on r10b8b ....... Finished optimization stage 2 on r10b8b (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 177MB) Running optimization stage 2 on perex_pma ....... Finished optimization stage 2 on perex_pma (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 177MB) Running optimization stage 2 on petex_top_0s_1s ....... Finished optimization stage 2 on petex_top_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 177MB) Running optimization stage 2 on t8b10b ....... Finished optimization stage 2 on t8b10b (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on msgmii_cnvtxo ....... Finished optimization stage 2 on msgmii_cnvtxo (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on msgmii_cnvtxi ....... Finished optimization stage 2 on msgmii_cnvtxi (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on msgmii_clkrst ....... Finished optimization stage 2 on msgmii_clkrst (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s ....... Finished optimization stage 2 on CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on rx4096x36_12s_1s_1s_4s ....... Finished optimization stage 2 on rx4096x36_12s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on tx2048x40_11s_1s_1s_4s ....... Finished optimization stage 2 on tx2048x40_11s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on si_sal ....... Finished optimization stage 2 on si_sal (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on mmcxwol ....... Finished optimization stage 2 on mmcxwol (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat ....... Finished optimization stage 2 on pemstat (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_eim ....... @W:CL246 : pemstat_eim.v(151) | Input port bits 24 to 20 of CORETSEOiIo[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_eim (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_store ....... @W:CL247 : pemstat_store.v(176) | Input port bit 31 of CORETSEl00o[31:0] is unused Finished optimization stage 2 on pemstat_store (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_sincnf ....... @W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_sincnf (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_sadd ....... @W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_sadd (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_sinchd ....... @W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_sinchd (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_sinc ....... @W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_sinc (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_ladd ....... @W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_ladd (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_linc ....... @W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSEl00o[30:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_linc (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemstat_cntrl ....... @W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSEo0o[30:0] is unused @W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSEo0o[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSElio0[51:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSElio0[51:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on pemstat_cntrl (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on sib_sync_2flp_1s_0s ....... Finished optimization stage 2 on sib_sync_2flp_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on sib_sync_pulse ....... Finished optimization stage 2 on sib_sync_pulse (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on tsmac_top_Z5 ....... @W:CL246 : tsmac_top.v(175) | Input port bits 31 to 10 of CORETSEiiI[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : tsmac_top.v(175) | Input port bits 1 to 0 of CORETSEiiI[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on tsmac_top_Z5 (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pe_mcxmac_0_0s_0s ....... Finished optimization stage 2 on pe_mcxmac_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pecar ....... Finished optimization stage 2 on pecar (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pehst ....... @A:CL153 : pehst.v(613) | *Unassigned bits of CORETSEooI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(709) | *Unassigned bits of CORETSEioI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(714) | *Unassigned bits of CORETSEOiI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(716) | *Unassigned bits of CORETSEIiI1 are referenced and tied to 0 -- simulation mismatch possible. Finished optimization stage 2 on pehst (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pemgt ....... @N:CL201 : pemgt.v(547) | Trying to extract state machine for register CORETSEi1i1. Extracted state machine for register CORETSEi1i1 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Finished optimization stage 2 on pemgt (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on pe_mcxmac_core_0_0s_0s ....... Finished optimization stage 2 on pe_mcxmac_core_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on permc_top ....... @W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSEl110[1:0] is unused Finished optimization stage 2 on permc_top (CPU Time 0h:00m:00s, Memory Used current: 156MB peak: 177MB) Running optimization stage 2 on perfn_top_0s_0_1s ....... @W:CL138 : perfn_top.v(3373) | Removing register 'CORETSEOOi0' because it is only assigned 0 or its original value. @N:CL201 : perfn_top.v(5127) | Trying to extract state machine for register CORETSEo0o. @W:CL246 : perfn_top.v(142) | Input port bits 1 to 0 of CORETSEIoO1[7:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on perfn_top_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 162MB peak: 177MB) Running optimization stage 2 on petfn_top_0s_0_1s ....... @N:CL135 : petfn_top.v(6206) | Found sequential shift CORETSEOIlII with address depth of 3 words and data bit width of 8. @N:CL135 : petfn_top.v(7121) | Found sequential shift CORETSEIllII with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(6988) | Found sequential shift CORETSEiIlII with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(7239) | Found sequential shift CORETSEollII with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(2644) | Found sequential shift CORETSEl1iOI with address depth of 3 words and data bit width of 1. @N:CL135 : petfn_top.v(2813) | Found sequential shift CORETSEOOOII with address depth of 3 words and data bit width of 4. @N:CL135 : petfn_top.v(8329) | Found sequential shift CORETSEl01 with address depth of 3 words and data bit width of 1. @N:CL135 : petfn_top.v(7634) | Found sequential shift CORETSEI01 with address depth of 4 words and data bit width of 1. @N:CL201 : petfn_top.v(10298) | Trying to extract state machine for register CORETSElio0. @W:CL246 : petfn_top.v(214) | Input port bits 1 to 0 of CORETSEI0O1[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(216) | Input port bits 1 to 0 of CORETSEl0O1[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(218) | Input port bits 1 to 0 of CORETSEo0O1[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(226) | Input port bits 9 to 6 of CORETSEi0O1[9:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on petfn_top_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 157MB peak: 177MB) Running optimization stage 2 on pecrc ....... Finished optimization stage 2 on pecrc (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on petmc_top ....... @W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSEl110[1:0] is unused Finished optimization stage 2 on petmc_top (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on amcxfif_11s_12s_32s_2s_0s ....... Finished optimization stage 2 on amcxfif_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on amcxfif_clkrst ....... Finished optimization stage 2 on amcxfif_clkrst (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on amcxfif_hst_Z4 ....... Finished optimization stage 2 on amcxfif_hst_Z4 (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on amcxtfif_wtm_12s_1s_0_0 ....... @N:CL201 : amcxtfif_wtm.v(268) | Trying to extract state machine for register CORETSEooiI. Extracted state machine for register CORETSEooiI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 Finished optimization stage 2 on amcxtfif_wtm_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 177MB) Running optimization stage 2 on amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s ....... @W:CL246 : amcxrfif_sys.v(234) | Input port bits 39 to 36 of CORETSEOOII[39:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 177MB) Running optimization stage 2 on amcxrfif_fab_12s_32s_2s_0_1s ....... @N:CL135 : amcxrfif_fab.v(1079) | Found sequential shift CORETSEioi with address depth of 3 words and data bit width of 1. @N:CL201 : amcxrfif_fab.v(588) | Trying to extract state machine for register CORETSEO10I. Extracted state machine for register CORETSEO10I State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 @W:CL247 : amcxrfif_fab.v(123) | Input port bit 12 of CORETSEIOII[13:0] is unused Finished optimization stage 2 on amcxrfif_fab_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on amcxtfif_sys_11s_32s_2s_0s_0_0_1s ....... @N:CL201 : amcxtfif_sys.v(804) | Trying to extract state machine for register CORETSEiooI. Extracted state machine for register CORETSEiooI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 Finished optimization stage 2 on amcxtfif_sys_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 164MB peak: 177MB) Running optimization stage 2 on amcxtfif_fab_11s_32s_2s_0_0_1s ....... Finished optimization stage 2 on amcxtfif_fab_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on mahbe_dual_0s_1s ....... Finished optimization stage 2 on mahbe_dual_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on tsm_sysreg_1s_0s ....... Finished optimization stage 2 on tsm_sysreg_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on decoder ....... Finished optimization stage 2 on decoder (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on coreapb3_iaddr_reg_0s_32_28 ....... @W:CL246 : coreapb3_iaddr_reg.v(39) | Input port bits 31 to 24 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on coreapb3_iaddr_reg_0s_32_28 (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on CoreAPB3_Z3 ....... Finished optimization stage 2 on CoreAPB3_Z3 (CPU Time 0h:00m:00s, Memory Used current: 161MB peak: 177MB) Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 162MB peak: 177MB) Running optimization stage 2 on top_COREABC_0_INSTRUCTIONS_Z2 ....... Finished optimization stage 2 on top_COREABC_0_INSTRUCTIONS_Z2 (CPU Time 0h:00m:00s, Memory Used current: 162MB peak: 177MB) Running optimization stage 2 on top_COREABC_0_RAM256X16 ....... Finished optimization stage 2 on top_COREABC_0_RAM256X16 (CPU Time 0h:00m:00s, Memory Used current: 162MB peak: 177MB) Running optimization stage 2 on top_COREABC_0_RAMBLOCKS_0s_32s_24s ....... Finished optimization stage 2 on top_COREABC_0_RAMBLOCKS_0s_32s_24s (CPU Time 0h:00m:00s, Memory Used current: 162MB peak: 177MB) Running optimization stage 2 on top_COREABC_0_COREABC_Z1 ....... @N:CL201 : coreabc.v(1041) | Trying to extract state machine for register ICYCLE. Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on top_COREABC_0_COREABC_Z1 (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 177MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 177MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 177MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 177MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:45s; CPU Time elapsed 0h:00m:44s; Memory used current: 166MB peak: 177MB) Process took 0h:00m:45s realtime, 0h:00m:44s cputime Process completed successfully. # Fri Jun 4 09:50:40 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Jun 4 09:50:41 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:45s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:47s realtime, 0h:00m:45s cputime Process completed successfully. # Fri Jun 4 09:50:41 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Jun 4 09:50:43 2021 ###########################################################] Premap Report # Fri Jun 4 09:50:44 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Reading constraint file: C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(12) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(13) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(14) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(15) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 177MB peak: 177MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 179MB) @W:BN132 : petmc_top.v(2012) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEoio0 because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEiIl1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : petfn_top.v(4500) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElIIII because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEllo. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : petfn_top.v(6138) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOl0OI because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIll1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : perfn_top.v(3332) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiio0 because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEOioi. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : permc_top.v(1848) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEIoOOI because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSElol1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3074) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3028) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3350) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2936) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net DB_DETECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net SB_CORRECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(157) | Tristate driver CORETSEIl0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEIl0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(155) | Tristate driver CORETSEOl0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEOl0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(153) | Tristate driver CORETSEiI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEiI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(149) | Tristate driver CORETSElI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSElI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(151) | Tristate driver CORETSEoI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEoI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(78) | Tristate driver TXD_1 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXD_1 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(78) | Tristate driver TXD_2 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXD_2 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(78) | Tristate driver TXD_3 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXD_3 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(695) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance IADDR_REG[31:0] (in view: COREAPB3_LIB.coreapb3_iaddr_reg_0s_32_28(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreapb3.v(508) | Removing instance g_iaddr_reg\.genblk18\.iaddr_reg (in view: COREAPB3_LIB.CoreAPB3_Z3(verilog)) of type view:COREAPB3_LIB.coreapb3_iaddr_reg_0s_32_28(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z8_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z8_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z8_2(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN362 : pemgt.v(2195) | Removing sequential instance CORETSEIoI1 (in view: work.pemgt(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pecar.v(630) | Removing sequential instance CORETSEli01 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(683) | Removing sequential instance CORETSEIO11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEoi11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEIOo1 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I (in view: work.sib_sync_pulse_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I (in view: work.sib_sync_pulse_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because it does not drive other instances. @N:BN362 : pecar.v(616) | Removing sequential instance CORETSEIi01 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(669) | Removing sequential instance CORETSEOO11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEli11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEOOo1 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(420) | Removing sequential instance CORETSEI001 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(471) | Removing sequential instance CORETSEO101 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : msgmii_core.v(251) | Removing sequential instance CORETSEIi1[9:0] (in view: work.msgmii_core_0s_18s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pemgt.v(2657) | Removing sequential instance CORETSEl0Io (in view: work.pemgt(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(406) | Removing sequential instance CORETSEO001 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(457) | Removing sequential instance CORETSEi001 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEIo11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEio11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEOo11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEoo11 (in view: work.pecar(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(991) | Removing sequential instance CORETSEl0l (in view: work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : mahbe_dual.v(282) | Removing sequential instance CORETSEl0Ol (in view: work.mahbe_dual_0s_1s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEO00l[31:0] (in view: work.tsm_sysreg_1s_0s(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEil0l[31:0] (in view: work.tsm_sysreg_1s_0s(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:BN362 : tsm_sysreg.v(1037) | Removing sequential instance CORETSEIo11I[31:0] (in view: work.tsm_sysreg_1s_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(1025) | Removing sequential instance CORETSEl0oI[10:0] (in view: work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(1073) | Removing sequential instance CORETSEo0oI[11:0] (in view: work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(939) | Removing sequential instance CORETSEO0oI (in view: work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=21 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB) @W:MT686 : synthesis.fdc(12) | No path from master pin (-source) to source of clock FCCC_0/GL0 @W:MT686 : synthesis.fdc(13) | No path from master pin (-source) to source of clock FCCC_0/GL1 @W:MT686 : synthesis.fdc(14) | No path from master pin (-source) to source of clock Igloo2_1000BaseT_sb_0/CCC_0/GL0 @W:MT686 : synthesis.fdc(15) | No path from master pin (-source) to source of clock Igloo2_1000BaseT_sb_0/CCC_0/GL3 Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - CLK0_PAD 50.0 MHz 20.000 declared default_clkgroup 0 1 . Igloo2_1000BaseT_sb_0/CCC_0/GL0 50.0 MHz 20.000 generated (from CLK0_PAD) default_clkgroup 2955 1 . Igloo2_1000BaseT_sb_0/CCC_0/GL3 125.0 MHz 8.000 generated (from CLK0_PAD) default_clkgroup 37 0 - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 1790 0 - SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 410 1 . FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 12 0 - Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 111 0 - Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 30 0 - pemgt|CORETSEOo1_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 124 0 - top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 1 ==================================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CLK0_PAD 0 CLK0_PAD(port) - - Igloo2_1000BaseT_sb_0.CCC_0.CLK0_PAD_INST.I(IBUF) Igloo2_1000BaseT_sb_0/CCC_0/GL0 2955 Igloo2_1000BaseT_sb_0.CCC_0.CCC_INST.GL0(CCC) LSRAM_MTX_MRX_0.TPSRAM_0.LSRAM_MTX_MRX_TPSRAM_0_TPSRAM_R0C1.B_CLK - Igloo2_1000BaseT_sb_0.CCC_0.GL0_INST.I(BUFG) Igloo2_1000BaseT_sb_0/CCC_0/GL3 37 Igloo2_1000BaseT_sb_0.CCC_0.CCC_INST.GL3(CCC) Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.psel_q1.C - Igloo2_1000BaseT_sb_0.CCC_0.GL3_INST.I(BUFG) SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 1790 SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1](SERDESIF_0) CORETSE_0.CORETSEO.CORETSEOi[8:0].C - CLKINT_0.I(BUFG) SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0 SERDES_IF_0.SERDESIF_INST.EPCS_RXCLK[1](SERDESIF_0) - - - FCCC_0/GL0 410 FCCC_0.CCC_INST.GL0(CCC) CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEo1ol[15:0].C - FCCC_0.GL0_INST.I(BUFG) FCCC_0/GL1 12 FCCC_0.CCC_INST.GL1(CCC) CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEolo0.CORETSEiolOI.C - FCCC_0.GL1_INST.I(BUFG) Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 111 Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_010) SERDES_IF_0.SERDESIF_INST.APB_CLK - Igloo2_1000BaseT_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 30 Igloo2_1000BaseT_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_enable_q1.C - Igloo2_1000BaseT_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) pemgt|CORETSEOo1_inferred_clock 124 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1.Q[0](dffr) CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiIIOI.C CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIlOo.E CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.un1_CORETSEloi1.I[0](inv) top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 1 SERDES_IF_0.refclk1_inbuf_diff.Y(INBUF_DIFF) SERDES_IF_0.SERDESIF_INST.REFCLK1 - - ======================================================================================================================================================================================================================================================================================================================================================================================================================== @W:MT530 : petbm.v(1502) | Found inferred clock pemgt|CORETSEOo1_inferred_clock which controls 124 sequential elements including CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[15:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : top_serdes_if_0_serdes_if.v(103) | Found inferred clock top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 226MB) Encoding state machine ICYCLE[3:0] (in view: work.top_COREABC_0_COREABC_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.top_COREABC_0_COREABC_Z1(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEiooI[5:0] (in view: work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine CORETSEO10I[4:0] (in view: work.amcxrfif_fab_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 Encoding state machine CORETSEooiI[5:0] (in view: work.amcxtfif_wtm_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine CORETSEi1i1[31:0] (in view: work.pemgt(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 Encoding state machine CORETSEi1O0_1[3:0] (in view: work.perex_pcs_0s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4633) | There are no possible illegal states for state machine CORETSEi1O0_1[3:0] (in view: work.perex_pcs_0s_1s(verilog)); safe FSM implementation is not required. Encoding state machine state[28:0] (in view: work.CoreConfigMaster_Z6(verilog)) original code -> new code 000000 -> 00000000000000000000000000001 000001 -> 00000000000000000000000000010 000010 -> 00000000000000000000000000100 000011 -> 00000000000000000000000001000 000100 -> 00000000000000000000000010000 000101 -> 00000000000000000000000100000 000110 -> 00000000000000000000001000000 000111 -> 00000000000000000000010000000 001001 -> 00000000000000000000100000000 001010 -> 00000000000000000001000000000 001011 -> 00000000000000000010000000000 001100 -> 00000000000000000100000000000 001101 -> 00000000000000001000000000000 001110 -> 00000000000000010000000000000 001111 -> 00000000000000100000000000000 010000 -> 00000000000001000000000000000 010001 -> 00000000000010000000000000000 010010 -> 00000000000100000000000000000 010011 -> 00000000001000000000000000000 010100 -> 00000000010000000000000000000 010101 -> 00000000100000000000000000000 010110 -> 00000001000000000000000000000 100000 -> 00000010000000000000000000000 100001 -> 00000100000000000000000000000 100010 -> 00001000000000000000000000000 100011 -> 00010000000000000000000000000 100100 -> 00100000000000000000000000000 100101 -> 01000000000000000000000000000 100110 -> 10000000000000000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z11(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z12(verilog)); safe FSM implementation is not required. Encoding state machine tx_st[4:0] (in view: work.coretse_if(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine rx_st[3:0] (in view: work.coretse_if(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 100 -> 11 @N:MO225 : coretse_if.v(140) | There are no possible illegal states for state machine rx_st[3:0] (in view: work.coretse_if(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 234MB peak: 247MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 247MB peak: 247MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 144MB peak: 247MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime # Fri Jun 4 09:50:51 2021 ###########################################################] Map & Optimize Report # Fri Jun 4 09:50:51 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 130MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net DB_DETECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net SB_CORRECT (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(157) | Tristate driver CORETSEIl0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEIl0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(155) | Tristate driver CORETSEOl0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEOl0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(153) | Tristate driver CORETSEiI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEiI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(151) | Tristate driver CORETSEoI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSEoI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(149) | Tristate driver CORETSElI0 (in view: work.tsmac_top_Z5(verilog)) on net CORETSElI0 (in view: work.tsmac_top_Z5(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(82) | Tristate driver TXER (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXER (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(80) | Tristate driver TXEN (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXEN (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(78) | Tristate driver TXD_1 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) on net TXD_1 (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : pecar.v(951) | Removing sequential instance CORETSEliI1.CORETSEi011 (in view: work.pe_mcxmac_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(907) | Removing sequential instance CORETSEliI1.CORETSEo011 (in view: work.pe_mcxmac_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : petcr.v(216) | Removing sequential instance CORETSEolo0.CORETSElolOI (in view: work.msgmii_tbi_0s_1s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @W:BN132 : petfn_top.v(9936) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEi1oOI because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOooOI. To keep the instance, apply constraint syn_preserve=1 on the instance. #### START OF SSF LOG MESSAGES #### #### END OF SSF LOG MESSAGES #### @W:FA239 : t8b10b.v(148) | ROM CORETSEII11I[5:0] (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEoI11I[1:0] (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEII11I[5:0] (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSEII11I[5:0] (in view: work.t8b10b(verilog)) with 32 words by 6 bits. @W:FA239 : t8b10b.v(148) | ROM CORETSEoI11I[1:0] (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSEoI11I[1:0] (in view: work.t8b10b(verilog)) with 32 words by 2 bits. @W:FA239 : t8b10b.v(148) | ROM CORETSElI11I (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSElI11I (in view: work.t8b10b(verilog)) with 32 words by 1 bit. @W:FA239 : t8b10b.v(148) | ROM CORETSEiiO1I (in view: work.t8b10b(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSEiiO1I (in view: work.t8b10b(verilog)) with 32 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEo0I1I (in view: work.r10b8b_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEl0I1I (in view: work.r10b8b_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(1950) | ROM CORETSEoII1I[2:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSEoII1I[2:0] (in view: work.r10b8b_1(verilog)) with 12 words by 3 bits. @W:FA239 : r10b8b.v(1950) | ROM CORETSEOlI1I (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSEOlI1I (in view: work.r10b8b_1(verilog)) with 12 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEOII1I[2:0] (in view: work.r10b8b_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_1(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_1(verilog)) with 46 words by 2 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1950) | ROM CORETSEoII1I[3:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSEoII1I[3:0] (in view: work.r10b8b_0(verilog)) with 12 words by 4 bits. @W:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEo0I1I (in view: work.r10b8b_0(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEl0I1I (in view: work.r10b8b_0(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEOII1I[2:0] (in view: work.r10b8b_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEIOI1I[2:0] (in view: work.r10b8b_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEiOI1I[1:0] (in view: work.r10b8b_0(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM CORETSEOOI1I[1:0] (in view: work.r10b8b_0(verilog)) with 46 words by 2 bits. @N:BN362 : pemgt.v(2142) | Removing sequential instance CORETSEOoI1[4:0] (in view: work.pemgt(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : msgmii_cnvtxo.v(414) | Removing sequential instance CORETSEll1 (in view: work.msgmii_cnvtxo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 204MB peak: 204MB) Encoding state machine ICYCLE[3:0] (in view: work.top_COREABC_0_COREABC_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.top_COREABC_0_COREABC_Z1(verilog)); safe FSM implementation is not required. @N:FX106 : ram256x16_rtl.v(32) | Using block RAM for single-port RAM @W:FX107 : ram256x16_rtl.v(32) | RAM UG3\.UR32\.UR0.RAM[31:0] (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:BN362 : ram256x16_rtl.v(32) | Removing sequential instance UG3\.UR32\.UR0.RD[31:0] (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : ram256x16_rtl.v(32) | Removing sequential instance UG3\.UR32\.UR0.RD_ret_31[31:0] (in view: work.top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:FX403 : rx4096x36.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSEoo0.CORETSEi1I1I[35:0] with specified coding style. Inferring block RAM. @W:FX107 : rx4096x36.v(131) | RAM CORETSEoo0.CORETSEi1I1I[35:0] (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : tx2048x40.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSEO10.CORETSEi1I1I[39:0] with specified coding style. Inferring block RAM. @W:FX107 : tx2048x40.v(131) | RAM CORETSEO10.CORETSEi1I1I[39:0] (in view: work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MF179 : amcxtfif_fab.v(762) | Found 11 by 11 bit equality operator ('==') un3_CORETSEiO1I (in view: work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog)) Encoding state machine CORETSEiooI[5:0] (in view: work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MF179 : amcxtfif_sys.v(2069) | Found 12 by 12 bit equality operator ('==') un1_CORETSEoOiI (in view: work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog)) Encoding state machine CORETSEO10I[4:0] (in view: work.amcxrfif_fab_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : amcxrfif_fab.v(497) | Found 13 by 13 bit equality operator ('==') un4_CORETSEoO0I (in view: work.amcxrfif_fab_12s_32s_2s_0_1s(verilog)) @N:MO231 : amcxrfif_sys.v(1963) | Found counter in view:work.amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s(verilog) instance CORETSEO11I[13:0] @N:MF179 : amcxrfif_sys.v(1281) | Found 12 by 12 bit equality operator ('==') un3_CORETSEiO1I (in view: work.amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s(verilog)) Encoding state machine CORETSEooiI[5:0] (in view: work.amcxtfif_wtm_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MO231 : amcxtfif_wtm.v(524) | Found counter in view:work.amcxtfif_wtm_12s_1s_0_0(verilog) instance CORETSEioiI[15:0] @N:MF179 : | Found 17 by 17 bit equality operator ('==') un13_CORETSEO00II (in view: work.petfn_top_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(9617) | Found 16 by 16 bit equality operator ('==') un19_CORETSEO00II (in view: work.petfn_top_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(5110) | Found 10 by 10 bit equality operator ('==') CORETSEi0III (in view: work.petfn_top_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(4272) | Found 16 by 16 bit equality operator ('==') un3_CORETSEIOIII (in view: work.petfn_top_0s_0_1s(verilog)) @N:MO231 : perfn_top.v(2477) | Found counter in view:work.perfn_top_0s_0_1s(verilog) instance CORETSEi11i[14:0] @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSEIOi0[0] (in view: work.perfn_top_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSEIOi0[1] (in view: work.perfn_top_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:MF179 : | Found 17 by 17 bit equality operator ('==') un12_CORETSEoi1i (in view: work.perfn_top_0s_0_1s(verilog)) @N:MF179 : perfn_top.v(4371) | Found 16 by 16 bit equality operator ('==') un6_CORETSEOOii (in view: work.perfn_top_0s_0_1s(verilog)) Encoding state machine CORETSEi1i1[31:0] (in view: work.pemgt(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEii1o.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSElOoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEoOoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEiOoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEOIoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEIIoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSElIoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEoIoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEiIoo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEOloo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEIloo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSElloo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEoloo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEo0oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEi0oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEO1oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEI1oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEl1oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEo1oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEi1oo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEIooo.CORETSEo11o[11:0] @N:MO231 : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSElooo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEoooo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEiooo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEOioo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEIioo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSElioo.CORETSEo11o[11:0] @N:MO231 : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) instance CORETSEI00o.CORETSEoioo.CORETSEo11o[11:0] @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[30] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[29] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[28] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[27] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[26] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[25] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEo00o.CORETSEll1o[24] (in view view:work.pemstat(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2167) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[25] because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[24]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2167) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[8] because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO231 : pemstat_linc.v(96) | Found counter in view:work.pemstat_linc(verilog) instance CORETSEo11o[17:0] @N:MO231 : mmcxwol.v(964) | Found counter in view:work.mmcxwol(verilog) instance CORETSEi11l[4:0] @N:MO231 : mmcxwol.v(765) | Found counter in view:work.mmcxwol(verilog) instance CORETSEl11l[4:0] @N:MO231 : msgmii_cnvtxo.v(267) | Found counter in view:work.msgmii_cnvtxo(verilog) instance CORETSElool[6:0] Encoding state machine CORETSEi1O0_1[3:0] (in view: work.perex_pcs_0s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4633) | There are no possible illegal states for state machine CORETSEi1O0_1[3:0] (in view: work.perex_pcs_0s_1s(verilog)); safe FSM implementation is not required. @N:MO231 : msgmii_peanx_top.v(3392) | Found counter in view:work.msgmii_peanx_top(verilog) instance CORETSEl1l0[20:0] @N:MF179 : msgmii_peanx_top.v(2379) | Found 15 by 15 bit equality operator ('==') CORETSEI000 (in view: work.msgmii_peanx_top(verilog)) @N:MF179 : msgmii_peanx_top.v(2664) | Found 16 by 16 bit equality operator ('==') CORETSEIo00 (in view: work.msgmii_peanx_top(verilog)) @N:MF179 : msgmii_peanx_top.v(2988) | Found 15 by 15 bit equality operator ('==') un7_CORETSEIO10 (in view: work.msgmii_peanx_top(verilog)) @N:MO231 : msgmii_cnvrxi.v(453) | Found counter in view:work.msgmii_cnvrxi(verilog) instance CORETSElool[5:0] @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] (in view view:work.Igloo2_1000BaseT_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] (in view view:work.Igloo2_1000BaseT_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] (in view view:work.Igloo2_1000BaseT_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] (in view view:work.Igloo2_1000BaseT_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine state[28:0] (in view: work.CoreConfigMaster_Z6(verilog)) original code -> new code 000000 -> 00000000000000000000000000001 000001 -> 00000000000000000000000000010 000010 -> 00000000000000000000000000100 000011 -> 00000000000000000000000001000 000100 -> 00000000000000000000000010000 000101 -> 00000000000000000000000100000 000110 -> 00000000000000000000001000000 000111 -> 00000000000000000000010000000 001001 -> 00000000000000000000100000000 001010 -> 00000000000000000001000000000 001011 -> 00000000000000000010000000000 001100 -> 00000000000000000100000000000 001101 -> 00000000000000001000000000000 001110 -> 00000000000000010000000000000 001111 -> 00000000000000100000000000000 010000 -> 00000000000001000000000000000 010001 -> 00000000000010000000000000000 010010 -> 00000000000100000000000000000 010011 -> 00000000001000000000000000000 010100 -> 00000000010000000000000000000 010101 -> 00000000100000000000000000000 010110 -> 00000001000000000000000000000 100000 -> 00000010000000000000000000000 100001 -> 00000100000000000000000000000 100010 -> 00001000000000000000000000000 100011 -> 00010000000000000000000000000 100100 -> 00100000000000000000000000000 100101 -> 01000000000000000000000000000 100110 -> 10000000000000000000000000000 @N:MO231 : coreconfigmaster.v(723) | Found counter in view:work.CoreConfigMaster_Z6(verilog) instance pause_count[4:0] @W:MO160 : coreconfigmaster.v(723) | Register bit HSIZE[2] (in view view:work.CoreConfigMaster_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:MF179 : coreconfigmaster.v(573) | Found 32 by 32 bit equality operator ('==') d_state160 (in view: work.CoreConfigMaster_Z6(verilog)) @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine state[2:0] (in view: work.CoreConfigP_Z11(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] (in view view:work.CoreConfigP_Z11(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z12(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z12(verilog) instance count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) instance count[6:0] Encoding state machine tx_st[4:0] (in view: work.coretse_if(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine rx_st[3:0] (in view: work.coretse_if(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 100 -> 11 @N:MO225 : coretse_if.v(140) | There are no possible illegal states for state machine rx_st[3:0] (in view: work.coretse_if(verilog)); safe FSM implementation is not required. @N:MO231 : coretse_if.v(53) | Found counter in view:work.coretse_if(verilog) instance pkt_cnt[9:0] @N:MO231 : coretse_if.v(53) | Found counter in view:work.coretse_if(verilog) instance RADDR[9:0] @N:MO231 : coretse_if.v(140) | Found counter in view:work.coretse_if(verilog) instance pkt_cnt_rx[9:0] @N:MO231 : coretse_if.v(140) | Found counter in view:work.coretse_if(verilog) instance WADDR[9:0] @N:MF179 : coretse_if.v(118) | Found 10 by 10 bit equality operator ('==') REN15 (in view: work.coretse_if(verilog)) Starting factoring (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 237MB peak: 237MB) @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.sdif_core_reset_n (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.sdif_core_reset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.hot_reset_n (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 300MB peak: 300MB) Available hyper_sources - for debug and ip models None Found @W:BN132 : msgmii_clkrst.v(159) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEoOol because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : msgmii_clkrst.v(120) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEii1l because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : msgmii_clkrst.v(172) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEiOol because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : msgmii_clkrst.v(211) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSElOol because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[50] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[31] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[30] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(8714) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOO0II (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(8619) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiilII (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEI00o.CORETSElooo.CORETSEoiIo (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEI00o.CORETSEIooo.CORETSEoiIo (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:32s; Memory used current: 273MB peak: 322MB) @W:BN132 : petfn_top.v(10298) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[49] because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[48]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2167) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[40] because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[28]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] (in view: work.top(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:35s; CPU Time elapsed 0h:00m:35s; Memory used current: 277MB peak: 322MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:46s; CPU Time elapsed 0h:00m:45s; Memory used current: 283MB peak: 322MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:46s; Memory used current: 284MB peak: 322MB) @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEIiO1I_0[4:0] (in view: work.top(verilog)) with 46 words by 5 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEIiO1I_0[4:0] (in view: work.top(verilog)) with 46 words by 5 bits. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEO0I1I (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEI0I1I (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEoiO1I[1:0] (in view: work.top(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEiiO1I (in view: work.top(verilog)) with 46 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEO0I1I (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEI0I1I (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEoiO1I[1:0] (in view: work.top(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEiiO1I (in view: work.top(verilog)) with 46 words by 1 bit. @N:MO106 : instructions.v(85) | Found ROM UROM\.UROM.doins[57:1] (in view: work.top_COREABC_0_COREABC_Z1(verilog)) with 63 words by 57 bits. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[14] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[8] because it is equivalent to instance COREABC_0.UROM.INSTR_ADDR[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[5] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[18] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[17] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[16]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[20] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[27] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_DATA[31] because it is equivalent to instance COREABC_0.UROM.INSTR_DATA[28]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_SLOT[3] because it is equivalent to instance COREABC_0.UROM.INSTR_SLOT[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_SLOT[2] because it is equivalent to instance COREABC_0.UROM.INSTR_SLOT[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[12] because it is equivalent to instance COREABC_0.UROM.INSTR_SLOT[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[11] because it is equivalent to instance COREABC_0.UROM.INSTR_SLOT[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[10] because it is equivalent to instance COREABC_0.UROM.INSTR_SLOT[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_SLOT[1] because it is equivalent to instance COREABC_0.UROM.INSTR_ADDR[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[15] because it is equivalent to instance COREABC_0.UROM.INSTR_ADDR[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[14] because it is equivalent to instance COREABC_0.UROM.INSTR_ADDR[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance COREABC_0.UROM.INSTR_ADDR[13] because it is equivalent to instance COREABC_0.UROM.INSTR_ADDR[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[6] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.pwrite_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.psel_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.pwrite_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.psel_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreconfigmaster.v(723) | Removing sequential instance Igloo2_1000BaseT_sb_0.ConfigMaster_0.state[8] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(3326) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElI0II (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(5935) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIl0II (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9508) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEil0II (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9650) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIOii (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[23] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[22] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[21] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreabc.v(494) | Removing sequential instance UROM\.INSTR_ADDR[9] (in view: work.top_COREABC_0_COREABC_Z1(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:52s; CPU Time elapsed 0h:00m:51s; Memory used current: 285MB peak: 322MB) Finished technology mapping (Real Time elapsed 0h:00m:58s; CPU Time elapsed 0h:00m:58s; Memory used current: 369MB peak: 369MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:59s -3.55ns 10144 / 5145 2 0h:00m:59s -3.42ns 9589 / 5145 3 0h:01m:00s -3.42ns 9589 / 5145 4 0h:01m:00s -3.42ns 9587 / 5145 @N:FX271 : msgmii_cnvtxo.v(292) | Replicating instance CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15 (in view: work.top(verilog)) with 98 loads 3 times to improve timing. @N:FX271 : pehst.v(1609) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110[1] (in view: work.top(verilog)) with 69 loads 3 times to improve timing. @N:FX271 : pehst.v(1609) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110[0] (in view: work.top(verilog)) with 47 loads 3 times to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[12] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[13] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[11] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[14] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[15] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[7] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[3] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[0] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[2] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[1] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[10] (in view: work.top(verilog)) with 8 loads 1 time to improve timing. @N:FX271 : amcxfif_hst.v(1999) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEolII.CORETSEoiOI[13] (in view: work.top(verilog)) with 16 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[6] (in view: work.top(verilog)) with 7 loads 1 time to improve timing. Timing driven replication report Added 20 Registers via timing driven replication Added 3 LUTs via timing driven replication 5 0h:01m:04s -2.15ns 9605 / 5165 6 0h:01m:05s -2.04ns 9608 / 5165 7 0h:01m:05s -1.91ns 9613 / 5165 8 0h:01m:05s -1.87ns 9614 / 5165 9 0h:01m:06s -1.88ns 9615 / 5165 10 0h:01m:06s -1.87ns 9616 / 5165 @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[4] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[5] (in view: work.top(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : pehst.v(1713) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[5] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : pehst.v(1713) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[6] (in view: work.top(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : permc_top.v(651) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[9] (in view: work.top(verilog)) with 8 loads 1 time to improve timing. @N:FX271 : pehst.v(1713) | Replicating instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[4] (in view: work.top(verilog)) with 9 loads 1 time to improve timing. Timing driven replication report Added 6 Registers via timing driven replication Added 0 LUTs via timing driven replication 11 0h:01m:07s -1.78ns 9619 / 5171 12 0h:01m:08s -1.78ns 9622 / 5171 13 0h:01m:08s -1.78ns 9623 / 5171 @N:FP130 : | Promoting Net genblk2\.RSTSYNC2_data on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_704 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.MSS_HPMS_READY_int_arst on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1900 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEolo0.CORETSEllol_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1901 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEIoi0_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1902 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEolo0.CORETSEilI0_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1903 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEio01_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1904 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEilII.CORETSEOIII_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1905 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEilII.CORETSEiOII_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1906 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEilII.CORETSEIIII_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1907 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEilII.CORETSEoOII_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1908 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEli1l_arst on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1909 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEOl11_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1910 @N:FP130 : | Promoting Net PHY_MDC_c on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1911 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1912 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0_INIT_APB_S_PCLK on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1913 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEO0I1_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1914 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEilII.CORETSElIII_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1915 @N:FP130 : | Promoting Net genblk2\.RSTSYNC2_arst on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_705 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEII11_i on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1916 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1917 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1918 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_0_1919 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:01m:12s; CPU Time elapsed 0h:01m:11s; Memory used current: 327MB peak: 371MB) Finished restoring hierarchy (Real Time elapsed 0h:01m:13s; CPU Time elapsed 0h:01m:12s; Memory used current: 329MB peak: 371MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 1863 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 3346 clock pin(s) of sequential element(s) 0 instances converted, 3346 sequential instances remain driven by gated/generated clocks ============================================================================== Non-Gated/Non-Generated Clocks =============================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0005 SERDES_IF_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF_0.SERDESIF_INST ClockId0006 SERDES_IF_0.SERDESIF_INST clock definition on SERDESIF_0 1723 CORETSE_0.CORETSEO.CORETSEOi[0] ClockId0007 Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST clock definition on MSS_010 109 SERDES_IF_0.SERDESIF_INST ClockId0008 Igloo2_1000BaseT_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 30 Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core ============================================================================================================================================================================================= ========================================================================================================================= Gated/Generated Clocks ========================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Igloo2_1000BaseT_sb_0.CCC_0.CCC_INST CCC 2802 Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_010 ClockId0002 FCCC_0.CCC_INST CCC 408 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEo1ol[8] No gated clock conversion method for cell cell:ACG4.SLE ClockId0003 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1 SLE 124 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[7] No gated clock conversion method for cell cell:ACG4.SLE ClockId0004 FCCC_0.CCC_INST CCC 12 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEolo0.CORETSEiolOI No gated clock conversion method for cell cell:ACG4.SLE =========================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:01m:14s; CPU Time elapsed 0h:01m:13s; Memory used current: 248MB peak: 371MB) Writing Analyst data base C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:01m:15s; CPU Time elapsed 0h:01m:15s; Memory used current: 303MB peak: 371MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Writing FDC file C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\synthesis\top_synplify.fdc Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:01m:19s; CPU Time elapsed 0h:01m:18s; Memory used current: 307MB peak: 371MB) Finished Writing Netlists (Real Time elapsed 0h:01m:19s; CPU Time elapsed 0h:01m:18s; Memory used current: 307MB peak: 371MB) Start final timing analysis (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:01m:19s; Memory used current: 289MB peak: 371MB) @W:MT246 : igloo2_1000baset_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock CLK0_PAD with period 20.00ns @N:MT615 : | Found clock Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 16.00ns @N:MT615 : | Found clock FCCC_0/GL1 with period 16.00ns @N:MT615 : | Found clock Igloo2_1000BaseT_sb_0/CCC_0/GL0 with period 20.00ns @N:MT615 : | Found clock Igloo2_1000BaseT_sb_0/CCC_0/GL3 with period 8.00ns @W:MT420 : | Found inferred clock pemgt|CORETSEOo1_inferred_clock with period 10.00ns. Please declare a user-defined clock on net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1. @W:MT420 : | Found inferred clock top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF_0.REFCLK1_OUT. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Jun 4 09:52:11 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0633_CORETSE_v2021.1\Libero\Hardware\CoreTSE_1000BaseT_Demo\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.840 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup FCCC_0/GL0 62.5 MHz 58.7 MHz 16.000 17.049 2.631 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz 69.8 MHz 16.000 14.326 7.486 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL0 50.0 MHz 41.3 MHz 20.000 24.199 -0.707 generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL3 125.0 MHz NA 8.000 NA NA generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 531.4 MHz 20.000 1.882 18.118 declared default_clkgroup Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 25.0 MHz 139.0 MHz 40.000 7.194 16.403 declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 103.3 MHz 8.000 9.680 -0.840 declared default_clkgroup pemgt|CORETSEOo1_inferred_clock 100.0 MHz 169.3 MHz 10.000 5.908 4.092 inferred Inferred_clkgroup_0 top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ======================================================================================================================================================================================================================= Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 18.118 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB | 40.000 33.386 | No paths - | 20.000 18.152 | 20.000 16.403 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 8.000 1.589 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] FCCC_0/GL0 | 8.000 5.440 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] FCCC_0/GL1 | 8.000 5.440 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 4.000 -0.840 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] pemgt|CORETSEOo1_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_0/GL0 SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 8.000 2.631 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_0/GL0 | 16.000 7.025 | No paths - | No paths - | No paths - FCCC_0/GL1 FCCC_0/GL0 | 8.000 7.486 | No paths - | No paths - | No paths - FCCC_0/GL1 FCCC_0/GL1 | 16.000 15.486 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 4.000 -0.707 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 FCCC_0/GL0 | 4.000 -0.262 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 FCCC_0/GL1 | 4.000 0.419 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 9.040 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 pemgt|CORETSEOo1_inferred_clock | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock FCCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock FCCC_0/GL1 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock Igloo2_1000BaseT_sb_0/CCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock pemgt|CORETSEOo1_inferred_clock | 10.000 4.092 | No paths - | No paths - | No paths - =========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FCCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[13] FCCC_0/GL0 SLE Q CORETSEIOI0[13] 0.094 2.631 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[12] FCCC_0/GL0 SLE Q CORETSEIOI0[12] 0.094 2.698 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[8] FCCC_0/GL0 SLE Q CORETSEIOI0[8] 0.094 2.740 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[7] FCCC_0/GL0 SLE Q CORETSEIOI0[7] 0.094 2.780 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[0] FCCC_0/GL0 SLE Q CORETSEIOI0[0] 0.094 2.807 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[9] FCCC_0/GL0 SLE Q CORETSEIOI0[9] 0.094 2.808 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[6] FCCC_0/GL0 SLE Q CORETSEIOI0[6] 0.094 2.847 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[10] FCCC_0/GL0 SLE Q CORETSEIOI0[10] 0.094 2.848 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[1] FCCC_0/GL0 SLE Q CORETSEIOI0[1] 0.094 2.875 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[2] FCCC_0/GL0 SLE Q CORETSEIOI0[2] 0.094 2.915 =========================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEoOl0 FCCC_0/GL0 SLE D CORETSEioI0 7.778 2.631 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEol10 FCCC_0/GL0 SLE D CORETSEll10 7.848 2.754 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEiOl0 FCCC_0/GL0 SLE D CORETSEOiI0 7.778 3.045 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEiiI0 FCCC_0/GL0 SLE D CORETSEOoI0 7.778 3.193 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEIl10 FCCC_0/GL0 SLE D CORETSEiI10 7.778 3.244 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[0] FCCC_0/GL0 SLE D CORETSEIO00[0] 7.778 3.275 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[2] FCCC_0/GL0 SLE D CORETSEIO00[2] 7.778 3.275 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[3] FCCC_0/GL0 SLE D CORETSEIO00[3] 7.778 3.275 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[4] FCCC_0/GL0 SLE D CORETSEIO00[4] 7.778 3.275 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[5] FCCC_0/GL0 SLE D CORETSEIO00[5] 7.778 3.275 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 5.147 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.631 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[13] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEoOl0 / D The start point is clocked by FCCC_0/GL0 [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[13] SLE Q Out 0.094 0.094 f - CORETSEIOI0[13] Net - - 0.849 - 8 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEiil0 CFG2 B In - 0.944 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEiil0 CFG2 Y Out 0.143 1.086 f - CORETSEiil0 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un2_CORETSEooI0_12 CFG4 D In - 1.518 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un2_CORETSEooI0_12 CFG4 Y Out 0.250 1.769 f - un2_CORETSEooI0_12 Net - - 0.744 - 5 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un2_CORETSEooI0 CFG2 A In - 2.512 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un2_CORETSEooI0 CFG2 Y Out 0.076 2.588 f - un2_CORETSEooI0 Net - - 0.849 - 8 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un1_CORETSEOiI0 CFG4 D In - 3.437 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.un1_CORETSEOiI0 CFG4 Y Out 0.250 3.688 f - un1_CORETSEOiI0 Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEOiI0 CFG4 D In - 3.904 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEOiI0 CFG4 Y Out 0.250 4.154 f - CORETSEOiI0 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEioI0_0 CFG3 B In - 4.802 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEioI0_0 CFG3 Y Out 0.129 4.931 r - CORETSEioI0 Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEoOl0 SLE D In - 5.147 r - =================================================================================================================================================== Total path delay (propagation time + setup) of 5.369 is 1.414(26.3%) logic and 3.955(73.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_0/GL1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] FCCC_0/GL1 SLE Q CORETSEo1li[0] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[1] FCCC_0/GL1 SLE Q CORETSEo1li[1] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[2] FCCC_0/GL1 SLE Q CORETSEo1li[2] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[3] FCCC_0/GL1 SLE Q CORETSEo1li[3] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[4] FCCC_0/GL1 SLE Q CORETSEo1li[4] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[5] FCCC_0/GL1 SLE Q CORETSEo1li[5] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[6] FCCC_0/GL1 SLE Q CORETSEo1li[6] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[7] FCCC_0/GL1 SLE Q CORETSEo1li[7] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[8] FCCC_0/GL1 SLE Q CORETSEo1li[8] 0.076 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9] FCCC_0/GL1 SLE Q CORETSEo1li[9] 0.076 7.486 ========================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] FCCC_0/GL1 SLE D CORETSEo1li[0] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[1] FCCC_0/GL1 SLE D CORETSEo1li[1] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[2] FCCC_0/GL1 SLE D CORETSEo1li[2] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[3] FCCC_0/GL1 SLE D CORETSEo1li[3] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[4] FCCC_0/GL1 SLE D CORETSEo1li[4] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[5] FCCC_0/GL1 SLE D CORETSEo1li[5] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[6] FCCC_0/GL1 SLE D CORETSEo1li[6] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[7] FCCC_0/GL1 SLE D CORETSEo1li[7] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[8] FCCC_0/GL1 SLE D CORETSEo1li[8] 7.778 7.486 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[9] FCCC_0/GL1 SLE D CORETSEo1li[9] 7.778 7.486 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 0.292 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.486 Number of logic level(s): 0 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] / D The start point is clocked by FCCC_0/GL1 [rising] (rise=8.000 fall=16.000 period=16.000) on pin CLK The end point is clocked by FCCC_0/GL0 [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] SLE Q Out 0.076 0.076 r - CORETSEo1li[0] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] SLE D In - 0.292 r - =============================================================================================================================================== Total path delay (propagation time + setup) of 0.514 is 0.298(58.0%) logic and 0.216(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEio1_fast[1] 0.094 -0.707 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1[3] 0.094 -0.672 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[0] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEio1_fast[0] 0.094 -0.595 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[5] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[5] 0.094 -0.551 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[6] 0.094 -0.377 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEolII.CORETSEoiOI_fast[13] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEoiOI_fast[13] 0.076 -0.348 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[7] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1[7] 0.094 -0.296 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_1_rep1 Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEio1_1_rep1 0.094 -0.149 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEOI1l_1[39] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEOI1l[39] 0.094 -0.072 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEOI1l_1[21] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEOI1l[21] 0.094 -0.066 ================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[3] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEOlIII[3] 3.778 -0.707 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIii Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEoIii 3.778 -0.672 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEOlIII[1] 3.778 -0.620 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1 Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEI0oi 3.778 -0.613 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[2] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEOlIII[2] 3.778 -0.567 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[0] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEOlIII[0] 3.778 -0.511 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOIIII[0] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEiOIII[0] 3.778 -0.387 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEoiOII[10] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEliOII[10] 3.778 -0.368 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEoiOII[11] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEliOII[11] 3.778 -0.368 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOIIII[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEiOIII[1] 3.778 -0.353 ===================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.485 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.707 Number of logic level(s): 4 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[3] / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] SLE Q Out 0.094 0.094 f - CORETSEio1_fast[1] Net - - 0.814 - 7 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 A In - 0.908 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 Y Out 0.076 0.984 f - CORETSEIlO1_fast[1] Net - - 1.105 - 30 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 C In - 2.089 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 Y Out 0.196 2.285 r - N_527 Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 D In - 2.993 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 Y Out 0.284 3.277 f - CORETSEiIIII Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[3] CFG4 D In - 3.985 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[3] CFG4 Y Out 0.284 4.269 r - CORETSEOlIII[3] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[3] SLE D In - 4.485 r - ======================================================================================================================================================== Total path delay (propagation time + setup) of 4.707 is 1.156(24.6%) logic and 3.551(75.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.450 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.672 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIii / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3] SLE Q Out 0.094 0.094 f - CORETSEIoO1[3] Net - - 0.973 - 13 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un17_CORETSEoO1i\.un17_CORETSEoO1i_c4_a0_0_RNI8LL01 CFG4 D In - 1.067 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un17_CORETSEoO1i\.un17_CORETSEoO1i_c4_a0_0_RNI8LL01 CFG4 Y Out 0.276 1.343 r - un23_CORETSEoO1i_5 Net - - 0.744 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_axb_7_i CFG2 A In - 2.086 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_axb_7_i CFG2 Y Out 0.087 2.174 r - un23_CORETSEoO1i_axb_7_i Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_7 CFG3 C In - 2.606 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_7 CFG3 Y Out 0.196 2.802 r - un23_CORETSEoO1i_cry_7 Net - - 0.744 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIii_1 CFG3 C In - 3.546 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIii_1 CFG3 Y Out 0.196 3.742 f - CORETSEoIii_1 Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIii CFG4 D In - 3.958 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIii CFG4 Y Out 0.276 4.234 r - CORETSEoIii Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIii SLE D In - 4.450 r - ===================================================================================================================================================================================== Total path delay (propagation time + setup) of 4.672 is 1.348(28.8%) logic and 3.324(71.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.398 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.620 Number of logic level(s): 4 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[1] / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] SLE Q Out 0.094 0.094 f - CORETSEio1_fast[1] Net - - 0.814 - 7 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 A In - 0.908 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 Y Out 0.076 0.984 f - CORETSEIlO1_fast[1] Net - - 1.105 - 30 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 C In - 2.089 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 Y Out 0.196 2.285 r - N_527 Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 D In - 2.993 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 Y Out 0.284 3.277 f - CORETSEiIIII Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[1] CFG4 C In - 3.985 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[1] CFG4 Y Out 0.196 4.182 r - CORETSEOlIII[1] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[1] SLE D In - 4.398 r - ======================================================================================================================================================== Total path delay (propagation time + setup) of 4.620 is 1.068(23.1%) logic and 3.551(76.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.391 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.613 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3] SLE Q Out 0.094 0.094 f - CORETSEIoO1[3] Net - - 0.973 - 13 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un17_CORETSEoO1i\.un17_CORETSEoO1i_c4_a0_0_RNI8LL01 CFG4 D In - 1.067 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un17_CORETSEoO1i\.un17_CORETSEoO1i_c4_a0_0_RNI8LL01 CFG4 Y Out 0.276 1.343 r - un23_CORETSEoO1i_5 Net - - 0.744 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_axb_7_i CFG2 A In - 2.086 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_axb_7_i CFG2 Y Out 0.087 2.174 r - un23_CORETSEoO1i_axb_7_i Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_7 CFG3 C In - 2.606 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un23_CORETSEoO1i_cry_7 CFG3 Y Out 0.196 2.802 r - un23_CORETSEoO1i_cry_7 Net - - 0.744 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEl0oi_d_0 CFG4 D In - 3.546 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEl0oi_d_0 CFG4 Y Out 0.236 3.782 r - CORETSEl0oi_d Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1_RNO CFG4 C In - 3.998 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1_RNO CFG4 Y Out 0.177 4.174 r - CORETSEI0oi Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1 SLE D In - 4.391 r - ===================================================================================================================================================================================== Total path delay (propagation time + setup) of 4.613 is 1.288(27.9%) logic and 3.324(72.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.373 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.595 Number of logic level(s): 4 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[0] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[3] / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[0] SLE Q Out 0.094 0.094 f - CORETSEio1_fast[0] Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 B In - 0.742 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEo0O0.CORETSElool15_fast CFG2 Y Out 0.129 0.871 r - CORETSEIlO1_fast[1] Net - - 1.105 - 30 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 C In - 1.976 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.un26_CORETSEoOiOI_i_o2 CFG4 Y Out 0.196 2.172 r - N_527 Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 D In - 2.881 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiIIII CFG4 Y Out 0.284 3.164 f - CORETSEiIIII Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[3] CFG4 D In - 3.873 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOlIII[3] CFG4 Y Out 0.284 4.157 r - CORETSEOlIII[3] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIlIII[3] SLE D In - 4.373 r - ======================================================================================================================================================== Total path delay (propagation time + setup) of 4.595 is 1.209(26.3%) logic and 3.385(73.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.076 18.118 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[4] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.076 18.227 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[7] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[7] 0.076 18.314 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[2] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 18.380 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[9] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[9] 0.076 18.386 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[12] 0.094 18.417 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[1] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.076 18.422 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[5] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.094 18.462 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[3] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.076 18.494 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[8] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 18.526 ========================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN release_sdif0_core6 19.706 18.118 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 18.425 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[11] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 18.440 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[10] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 18.454 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[9] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 18.468 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[8] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 18.482 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[7] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 18.497 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[6] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 18.511 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[5] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 18.525 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[4] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.778 18.539 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 1.588 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 18.118 Number of logic level(s): 2 Starting point: Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.076 0.076 r - count_sdif0[0] Net - - 0.648 - 3 Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core6_7 CFG4 D In - 0.724 r - Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core6_7 CFG4 Y Out 0.284 1.008 f - release_sdif0_core6_7 Net - - 0.216 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 B In - 1.224 f - Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 Y Out 0.143 1.367 f - release_sdif0_core6 Net - - 0.221 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 1.588 f - ======================================================================================================================= Total path delay (propagation time + setup) of 1.882 is 0.796(42.3%) logic and 1.085(57.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q psel 0.094 16.403 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.state[1] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 18.152 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.SDIF0_PENABLE Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PENABLE 0.094 18.358 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.state[0] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.695 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[15] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[15] 0.076 18.770 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[14] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[14] 0.094 18.842 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[4] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[4] 0.094 33.386 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[7] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[7] 5.613 33.590 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[0] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[0] 5.118 33.692 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[1] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[1] 5.053 33.866 ================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PSEL Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PSELx 18.557 16.403 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[2] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[3] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[4] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[5] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[6] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[7] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[8] 19.778 16.526 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[9] 19.778 16.526 ================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 1.443 + Clock delay at ending point: 0.000 (ideal) = Required time: 18.557 - Propagation time: 2.154 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 16.403 Number of logic level(s): 1 Starting point: Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=20.000 period=40.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=20.000 period=40.000) on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 f - psel Net - - 0.779 - 6 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_0_a2 CFG3 B In - 0.873 f - Igloo2_1000BaseT_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_0_a2 CFG3 Y Out 0.143 1.016 f - Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.138 - 35 SERDES_IF_0.SERDESIF_INST SERDESIF_0 APB_PSEL In - 2.154 f - ============================================================================================================================== Total path delay (propagation time + setup) of 3.597 is 1.680(46.7%) logic and 1.917(53.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o_fast[10] 0.094 -0.840 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[10] 0.094 -0.832 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[13] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[13] 0.094 -0.718 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[8] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[8] 0.094 -0.684 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[14] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o_fast[14] 0.094 -0.666 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[11] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[11] 0.094 -0.666 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[14] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[14] 0.094 -0.658 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[5] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[5] 0.094 -0.657 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[12] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[12] 0.094 -0.636 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[6] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[6] 0.094 -0.627 ================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[10] 3.778 -0.840 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[11] 3.778 -0.840 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[12] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[12] 3.778 -0.840 COREABC_0.STD_ACCUM_ZERO SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D to_logic_2\.tmp_4[0] 3.778 -0.537 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[38] 3.778 -0.039 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[41] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[41] 3.778 -0.039 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[9] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[9] 3.778 0.081 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[15] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[15] 3.778 0.081 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[6] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[6] 3.778 0.135 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[5] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[5] 3.778 0.141 ================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.618 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.840 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] SLE Q Out 0.094 0.094 f - CORETSEo0o_fast[10] Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 D In - 0.742 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 Y Out 0.250 0.993 f - CORETSEOO1o[10] Net - - 0.958 - 11 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 D In - 1.951 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 Y Out 0.250 2.201 f - un77_CORETSEii0o_4 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 D In - 2.633 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.276 2.909 r - CORETSEii0o[1] Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 D In - 3.341 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 Y Out 0.236 3.577 r - un164_CORETSEii0o_4 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[10] CFG4 C In - 4.225 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[10] CFG4 Y Out 0.177 4.402 r - CORETSEii0o[10] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] SLE D In - 4.618 r - =========================================================================================================================================================== Total path delay (propagation time + setup) of 4.840 is 1.505(31.1%) logic and 3.335(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.618 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.840 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] SLE Q Out 0.094 0.094 f - CORETSEo0o_fast[10] Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 D In - 0.742 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 Y Out 0.250 0.993 f - CORETSEOO1o[10] Net - - 0.958 - 11 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 D In - 1.951 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 Y Out 0.250 2.201 f - un77_CORETSEii0o_4 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 D In - 2.633 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.276 2.909 r - CORETSEii0o[1] Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 D In - 3.341 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 Y Out 0.236 3.577 r - un164_CORETSEii0o_4 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[11] CFG4 C In - 4.225 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[11] CFG4 Y Out 0.177 4.402 r - CORETSEii0o[11] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] SLE D In - 4.618 r - =========================================================================================================================================================== Total path delay (propagation time + setup) of 4.840 is 1.505(31.1%) logic and 3.335(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.618 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.840 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[12] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o_fast[10] SLE Q Out 0.094 0.094 f - CORETSEo0o_fast[10] Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 D In - 0.742 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 Y Out 0.250 0.993 f - CORETSEOO1o[10] Net - - 0.958 - 11 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 D In - 1.951 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 Y Out 0.250 2.201 f - un77_CORETSEii0o_4 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 D In - 2.633 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.276 2.909 r - CORETSEii0o[1] Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 D In - 3.341 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 Y Out 0.236 3.577 r - un164_CORETSEii0o_4 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[12] CFG4 C In - 4.225 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[12] CFG4 Y Out 0.177 4.402 r - CORETSEii0o[12] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[12] SLE D In - 4.618 r - =========================================================================================================================================================== Total path delay (propagation time + setup) of 4.840 is 1.505(31.1%) logic and 3.335(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.610 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.832 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] SLE Q Out 0.094 0.094 f - CORETSElio0[10] Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 C In - 0.802 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 Y Out 0.182 0.985 f - CORETSEOO1o[10] Net - - 0.958 - 11 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 D In - 1.943 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 Y Out 0.250 2.193 f - un77_CORETSEii0o_4 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 D In - 2.625 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.276 2.901 r - CORETSEii0o[1] Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 D In - 3.333 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 Y Out 0.236 3.569 r - un164_CORETSEii0o_4 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[10] CFG4 C In - 4.217 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[10] CFG4 Y Out 0.177 4.394 r - CORETSEii0o[10] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] SLE D In - 4.610 r - =========================================================================================================================================================== Total path delay (propagation time + setup) of 4.832 is 1.437(29.7%) logic and 3.395(70.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.610 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.832 Number of logic level(s): 5 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] (rise=0.000 fall=4.000 period=8.000) on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] SLE Q Out 0.094 0.094 f - CORETSElio0[10] Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 C In - 0.802 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[10] CFG4 Y Out 0.182 0.985 f - CORETSEOO1o[10] Net - - 0.958 - 11 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 D In - 1.943 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un77_CORETSEii0olto15_4 CFG4 Y Out 0.250 2.193 f - un77_CORETSEii0o_4 Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 D In - 2.625 f - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.276 2.901 r - CORETSEii0o[1] Net - - 0.432 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 D In - 3.333 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un164_CORETSEii0o_4 CFG4 Y Out 0.236 3.569 r - un164_CORETSEii0o_4 Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[11] CFG4 C In - 4.217 r - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[11] CFG4 Y Out 0.177 4.394 r - CORETSEii0o[11] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] SLE D In - 4.610 r - =========================================================================================================================================================== Total path delay (propagation time + setup) of 4.832 is 1.437(29.7%) logic and 3.395(70.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: pemgt|CORETSEOo1_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[2] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[2] 0.094 4.092 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[1] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[1] 0.076 4.261 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[4] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[4] 0.076 4.277 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[4] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[4] 0.094 4.330 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[3] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[3] 0.094 4.344 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[2] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[2] 0.076 4.410 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[0] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[0] 0.094 4.451 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEl1IOI[2] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEl1IOI[2] 0.094 4.507 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEl1IOI[1] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEl1IOI[1] 0.094 4.514 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[3] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[3] 0.094 4.699 ================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[9] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[9] 9.778 4.092 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[14] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[14] 9.778 4.125 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[8] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[8] 9.778 4.212 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[13] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[13] 9.778 4.218 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[6] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[6] 9.778 4.261 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[12] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[12] 9.778 4.330 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[0] pemgt|CORETSEOo1_inferred_clock SLE D un1_CORETSEiiIOI[0] 9.778 4.418 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[2] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[2] 9.778 4.418 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[5] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[5] 9.778 4.466 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[15] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[15] 9.778 4.511 ====================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 5.686 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 4.092 Number of logic level(s): 8 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[2] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[9] / D The start point is clocked by pemgt|CORETSEOo1_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by pemgt|CORETSEOo1_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[2] SLE Q Out 0.094 0.094 f - CORETSEi0IOI[2] Net - - 0.648 - 3 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.un5_CORETSEi11_NE_0 CFG2 A In - 0.742 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.un5_CORETSEi11_NE_0 CFG2 Y Out 0.076 0.818 f - un5_CORETSEi11_NE_0 Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.un5_CORETSEi11_NE CFG4 B In - 1.034 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.un5_CORETSEi11_NE CFG4 Y Out 0.143 1.177 f - un5_CORETSEi11_NE Net - - 0.920 - 10 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEI0lOI_1 CFG2 A In - 2.097 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEI0lOI_1 CFG2 Y Out 0.087 2.184 r - CORETSEI0lOI_1 Net - - 0.708 - 4 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEollOI CFG4 D In - 2.892 r - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEollOI CFG4 Y Out 0.236 3.128 r - CORETSEollOI Net - - 0.995 - 16 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI_2_1[9] CFG4 D In - 4.123 r - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI_2_1[9] CFG4 Y Out 0.284 4.407 f - CORETSEoiIOI_2_1[9] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI_2[9] CFG4 B In - 4.623 f - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI_2[9] CFG4 Y Out 0.129 4.752 r - CORETSEoiIOI_2[9] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI[9] CFG4 B In - 4.968 r - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoiIOI[9] CFG4 Y Out 0.143 5.111 r - CORETSEoiIOI[9] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI[9] CFG4 B In - 5.327 r - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI[9] CFG4 Y Out 0.143 5.470 r - CORETSEiiIOI[9] Net - - 0.216 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[9] SLE D In - 5.686 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.908 is 1.557(26.3%) logic and 4.352(73.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(16) | Timing constraint (through [get_pins { COREABC_0.NSYSRESET* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(19) | Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(21) | Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(22) | Timing constraint (to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(24) | Timing constraint (through [get_pins { Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(25) | Timing constraint (through [get_pins { Igloo2_1000BaseT_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:01m:19s; Memory used current: 293MB peak: 371MB) Finished timing report (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:01m:19s; Memory used current: 293MB peak: 371MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2gl010tvf400-1 Cell usage: AND2 1 use CCC 2 uses CLKINT 26 uses MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_0 1 use SYSRESET 1 use CFG1 27 uses CFG2 1095 uses CFG3 1915 uses CFG4 4987 uses Carry cells: ARI1 1438 uses - used for arithmetic functions ARI1 42 uses - used for Wide-Mux implementation Total ARI1 1480 uses Sequential Cells: SLE 5172 uses DSP Blocks: 0 of 22 (0%) I/O ports: 23 I/O primitives: 5 BIBUF 1 use INBUF 1 use INBUF_DIFF 1 use OUTBUF 2 uses Global Clock Buffers: 26 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 18 of 21 (85%) Total LUTs: 9504 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 648; LUTs = 648; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 5172 + 0 + 648 + 0 = 5820; Total number of LUTs after P&R: 9504 + 0 + 648 + 0 = 10152; Mapper successful! At Mapper Exit (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:01m:20s; Memory used current: 105MB peak: 371MB) Process took 0h:01m:21s realtime, 0h:01m:20s cputime # Fri Jun 4 09:52:12 2021 ###########################################################]