Project Settings Project Name top_syn Device Name synthesis: Microchip IGLOO2 : M2GL010T Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 266 305 0 - 00m:48s - 04-06-2021 09:50:41 (premap) Complete 90 47 0 0m:06s 0m:06s 247MB 04-06-2021 09:50:51 (fpga_mapper) Complete 239 96 0 01m:20s 01m:21s 371MB 04-06-2021 09:52:12 Multi-srs Generator Complete 00m:01s 04-06-2021 09:50:43 Area Summary Carry Cells 1480 Sequential Cells 5172 DSP Blocks (dsp_used) 0 I/O Cells 5 Global Clock Buffers 26 RAM1K18 (v_ram) 18 LUTs (total_luts) 9504 Timing Summary Clock Name Req Freq Est Freq Slack CLK0_PAD 50.0 MHz NA NA FCCC_0/GL0 62.5 MHz 58.7 MHz 2.631 FCCC_0/GL1 62.5 MHz 69.8 MHz 7.486 Igloo2_1000BaseT_sb_0/CCC_0/GL0 50.0 MHz 41.3 MHz -0.707 Igloo2_1000BaseT_sb_0/CCC_0/GL3 125.0 MHz NA NA Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 531.4 MHz 18.118 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 25.0 MHz 139.0 MHz 16.403 SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA NA SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 103.3 MHz -0.840 pemgt|CORETSEOo1_inferred_clock 100.0 MHz 169.3 MHz 4.092 top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 4 / 4