#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764D-ATHULDEEP #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\acmtable.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\debugblk.v" @I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\debugblk.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\support.v" @N:CG334 : debugblk.v(68) | Read directive translate_off @N:CG333 : debugblk.v(745) | Read directive translate_on @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\instructions.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\instructnvm_bb.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\iram512x9_rtl.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\instructram.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\ram256x16_rtl.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\ram256x8_rtl.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\ramblocks.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\COREABC_0\rtl\vlog\core\coreabc.v" @N:CG334 : coreabc.v(982) | Read directive translate_off @N:CG333 : coreabc.v(984) | Read directive translate_on @N:CG334 : coreabc.v(1379) | Read directive translate_off @N:CG333 : coreabc.v(1423) | Read directive translate_on @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxi.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvrxo.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxi.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_cnvtxo.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\peanx_sync.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_peanx_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\r10b8b.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pcs.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perex_pma.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petbm.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petcr.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\t8b10b.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petex_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_tbi.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\msgmii_core.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\rx4096x36.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_clkrst.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif_hst.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_fab.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxrfif_sys.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_fab.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_sys.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxtfif_wtm.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\amcxfif.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v" @I:"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\decoder.v":"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\include.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsm_sysreg.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mahbe_dual.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\mmcxwol.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecrc.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\perfn_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\permc_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petfn_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\petmc_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac_core.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pecar.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pehst.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemgt.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pe_mcxmac.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_ladd.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_linc.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sadd.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinc.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sinchd.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_sincnf.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat_store.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\pemstat.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_mem2p.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_2flp.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_fifo_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_hstinf.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rfp.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_rtc.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_tfp.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\ptp_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\si_sal.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\sib_sync_pulse.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\tx2048x40.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CORETSE\2.0.307\rtl\vlog\core_obfuscated\CoreTSE_top.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\CORETSE_0\rtl\vlog\core_obfuscated\CoreTSE.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\FCCC_0\Igloo2_1000BaseT_FCCC_0_FCCC.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\SERDES_IF_0\Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF_syn.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\SERDES_IF_0\Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\CCC_0\Igloo2_1000BaseT_sb_CCC_0_FCCC.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\FABOSC_0\Igloo2_1000BaseT_sb_FABOSC_0_OSC.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb_HPMS\Igloo2_1000BaseT_sb_HPMS_syn.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb_HPMS\Igloo2_1000BaseT_sb_HPMS.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT_sb\Igloo2_1000BaseT_sb.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\LSRAM_MTX_MRX\TPSRAM_0\LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\hdl\coretse_if.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\LSRAM_MTX_MRX\LSRAM_MTX_MRX.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" @I::"D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\component\work\Igloo2_1000BaseT\Igloo2_1000BaseT.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module Igloo2_1000BaseT @N:CG364 : igloo2.v(126) | Synthesizing module AND2 @N:CG364 : igloo2.v(286) | Synthesizing module BIBUF @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT @N:CG364 : coreabc.v(46) | Synthesizing module Igloo2_1000BaseT_COREABC_0_COREABC FAMILY=32'b00000000000000000000000000011000 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000010000 ICWIDTH=32'b00000000000000000000000000001011 ZRWIDTH=32'b00000000000000000000000000010000 IFWIDTH=32'b00000000000000000000000000000001 IIWIDTH=32'b00000000000000000000000000000001 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000001000 EN_RAM=32'b00000000000000000000000000000001 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000001 EN_INDIRECT=32'b00000000000000000000000000000001 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000011010 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000000100000000000 APB_SWIDTH=32'b00000000000000000000000000000100 RAMWIDTH=32'b00000000000000000000000000111010 SYNC_RESET=32'b00000000000000000000000000000000 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = Igloo2_1000BaseT_COREABC_0_COREABC_Z1 @N:CG364 : ramblocks.v(25) | Synthesizing module Igloo2_1000BaseT_COREABC_0_RAMBLOCKS DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011000 Generated name = Igloo2_1000BaseT_COREABC_0_RAMBLOCKS_32s_24s @N:CG364 : ram256x16_rtl.v(20) | Synthesizing module Igloo2_1000BaseT_COREABC_0_RAM256X16 @N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16 @W:CG360 : ramblocks.v(38) | No assignment to wire RDW @W:CG360 : ramblocks.v(44) | No assignment to wire RDYY @N:CG364 : instructions.v(26) | Synthesizing module Igloo2_1000BaseT_COREABC_0_INSTRUCTIONS AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000100 ICWIDTH=32'b00000000000000000000000000001011 IIWIDTH=32'b00000000000000000000000000000001 IFWIDTH=32'b00000000000000000000000000000001 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000100 IW=32'b00000000000000000000000000001011 FW=32'b00000000000000000000000000000101 iJUMP=32'b00000000000000000010001000000001 iCALL=32'b00000000000000000010001100000001 iRETURN=32'b00000000000000000010010000000001 iRETISR=32'b00000000000000000010010100000001 iWAIT=32'b00000000000000000010011000000001 iHALT=32'b00000000000000000010011000000001 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Sym_MDIO_STAT_REG=32'b00000000000000000000000000110100 Sym_TSE_MACFG1_REG=32'b00000000000000000000000000000000 Sym_TSE_MACFG2_REG=32'b00000000000000000000000000000100 Label_read_phy_status=32'b00000000000000000000000000101100 Label_delay_loop=32'b00000000000000000000000000110000 Label_Delay_loop_phy14=32'b00000000000000000000000000110001 Label_MDIO_wait_status=32'b00000000000000000000000000111011 Label_Status_reg_p0=32'b00000000000000000000000000111011 Generated name = Igloo2_1000BaseT_COREABC_0_INSTRUCTIONS_Z2 @W:CG133 : coreabc.v(686) | No assignment to MULT @W:CG133 : coreabc.v(687) | No assignment to A @W:CG133 : coreabc.v(688) | No assignment to B @W:CG360 : coreabc.v(227) | No assignment to wire DEBUG1 @W:CG360 : coreabc.v(228) | No assignment to wire DEBUG2 @W:CG360 : coreabc.v(229) | No assignment to wire DEBUGBLK_RESETN @W:CG133 : coreabc.v(255) | No assignment to iii @W:CG133 : coreabc.v(256) | No assignment to RAMDOUTXX @W:CG134 : coreabc.v(260) | No assignment to bit 11 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr @W:CL169 : coreabc.v(1031) | Pruning register GETINST @W:CL169 : coreabc.v(501) | Pruning register UROM.upper_addr[7:0] @W:CL208 : coreabc.v(1031) | All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization. @W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @W:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0, optimizing ... @W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0] @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000010001 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b011100 UPR_NIBBLE_POSN=4'b1000 FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b1000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z3 @N:CG364 : coreapb3_iaddr_reg.v(21) | Synthesizing module coreapb3_iaddr_reg SYNC_RESET=32'b00000000000000000000000000000000 APB_DWIDTH=6'b100000 MADDR_BITS=6'b011100 Generated name = coreapb3_iaddr_reg_0s_32_28 @N:CG364 : decoder.v(6) | Synthesizing module decoder @N:CG364 : tsm_sysreg.v(4) | Synthesizing module tsm_sysreg CORETSEoII=32'b00000000000000000000000000000001 CORETSEii=32'b00000000000000000000000000000000 Generated name = tsm_sysreg_1s_0s @N:CG364 : mahbe_dual.v(6) | Synthesizing module mahbe_dual CORETSEii=32'b00000000000000000000000000000000 CORETSEoII=32'b00000000000000000000000000000001 Generated name = mahbe_dual_0s_1s @W:CL169 : mahbe_dual.v(282) | Pruning register CORETSEI00l @N:CG364 : amcxtfif_fab.v(6) | Synthesizing module amcxtfif_fab TABITS=32'b00000000000000000000000000001011 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSElOoI=11'b00000000000 CORETSElO0I=12'b000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxtfif_fab_11s_32s_2s_0_0_1s @N:CG364 : amcxtfif_sys.v(6) | Synthesizing module amcxtfif_sys TABITS=32'b00000000000000000000000000001011 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEii=32'b00000000000000000000000000000000 CORETSElO0I=12'b000000000000 CORETSEoooI=14'b00000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxtfif_sys_11s_32s_2s_0s_0_0_1s @W:CL271 : amcxtfif_sys.v(1656) | Pruning bits 1 to 0 of CORETSEIIiI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1475) | Pruning bits 13 to 2 of CORETSElIiI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1447) | Pruning bits 1 to 0 of CORETSEOIiI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1380) | Pruning bits 1 to 0 of CORETSEiOiI[13:0] -- not in use ... @W:CL265 : amcxtfif_sys.v(1609) | Pruning bit 38 of CORETSEOliI[39:0] -- not in use ... @N:CG364 : amcxrfif_fab.v(6) | Synthesizing module amcxrfif_fab RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSElO0I=13'b0000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxrfif_fab_12s_32s_2s_0_1s @N:CG179 : amcxrfif_fab.v(971) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(977) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(983) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(989) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(995) | Removing redundant assignment @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[36] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[37] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[38] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSEOIOI[39] to a constant 0 @W:CL279 : amcxrfif_fab.v(1581) | Pruning register bits 39 to 36 of CORETSEOIOI[39:0] @W:CL169 : amcxrfif_fab.v(1022) | Pruning register CORETSEiI0I @N:CG364 : amcxrfif_sys.v(6) | Synthesizing module amcxrfif_sys CORETSEii=32'b00000000000000000000000000000000 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEIo0I=14'b00000000000000 CORETSElo0I=13'b0000000000000 CORETSElO0I=15'b000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s @N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module amcxtfif_wtm RABITS=32'b00000000000000000000000000001100 CORETSEO0II=32'b00000000000000000000000000000001 CORETSElOoI=12'b000000000000 CORETSElO0I=13'b0000000000000 Generated name = amcxtfif_wtm_12s_1s_0_0 @N:CG364 : amcxfif_hst.v(6) | Synthesizing module amcxfif_hst TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEIoII=13'b0000000000000 CORETSEloII=4'b0000 CORETSEooII=19'b0000000000000000000 CORETSEioII=12'b111111111111 CORETSEOiII=12'b111111111111 CORETSEIiII=14'b00000000000000 CORETSEliII=4'b0000 CORETSEoiII=3'b000 CORETSEiiII=18'b000000000000000000 CORETSEOOlI=13'b1111111111111 CORETSEIOlI=13'b1111111111111 CORETSElOlI=12'b111111111111 Generated name = amcxfif_hst_Z4 @W:CG360 : amcxfif_hst.v(904) | No assignment to wire CORETSEO0lI @N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module amcxfif_clkrst @N:CG364 : amcxfif.v(6) | Synthesizing module amcxfif TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEii1=32'b00000000000000000000000000100000 CORETSEOOo=32'b00000000000000000000000000000010 CORETSEii=32'b00000000000000000000000000000000 Generated name = amcxfif_11s_12s_32s_2s_0s @N:CG364 : petmc_top.v(6) | Synthesizing module petmc_top @N:CG364 : pecrc.v(6) | Synthesizing module pecrc @N:CG364 : petfn_top.v(6) | Synthesizing module petfn_top CORETSEOOI=32'b00000000000000000000000000000000 CORETSEIOI=1'b0 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petfn_top_0s_0_1s @N:CG179 : petfn_top.v(9933) | Removing redundant assignment @N:CG179 : petfn_top.v(9993) | Removing redundant assignment @W:CG133 : petfn_top.v(418) | No assignment to CORETSEO1oOI @W:CG360 : petfn_top.v(421) | No assignment to wire CORETSEI1oOI @W:CG360 : petfn_top.v(445) | No assignment to wire CORETSEOo0OI @W:CG133 : petfn_top.v(586) | No assignment to CORETSEOiiOI @W:CG360 : petfn_top.v(956) | No assignment to wire CORETSEliIII @W:CL169 : petfn_top.v(4062) | Pruning register CORETSEIoiOI[15:0] @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[5] to a constant 0 @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSEOoOII[6] to a constant 0 @W:CL279 : petfn_top.v(3748) | Pruning register bits 6 to 5 of CORETSEOoOII[6:0] @N:CG364 : perfn_top.v(6) | Synthesizing module perfn_top CORETSEii=32'b00000000000000000000000000000000 CORETSEIOI=1'b0 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = perfn_top_0s_0_1s @W:CG360 : perfn_top.v(343) | No assignment to wire CORETSEol0i @W:CG360 : perfn_top.v(650) | No assignment to wire CORETSEIioi @W:CG133 : perfn_top.v(653) | No assignment to CORETSElioi @N:CG364 : permc_top.v(6) | Synthesizing module permc_top @N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module pe_mcxmac_core CORETSEIOI=1'b0 CORETSEii=32'b00000000000000000000000000000000 CORETSEOOI=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_core_0_0s_0s @N:CG364 : pemgt.v(6) | Synthesizing module pemgt @N:CG364 : pehst.v(6) | Synthesizing module pehst @W:CG133 : pehst.v(613) | No assignment to CORETSEooI1 @W:CG133 : pehst.v(709) | No assignment to CORETSEioI1 @W:CG133 : pehst.v(714) | No assignment to CORETSEOiI1 @W:CG133 : pehst.v(716) | No assignment to CORETSEIiI1 @W:CL169 : pehst.v(1969) | Pruning register CORETSEo0i1 @W:CL169 : pehst.v(1939) | Pruning register CORETSEl0i1 @W:CL169 : pehst.v(1909) | Pruning register CORETSEI0i1 @N:CG364 : pecar.v(6) | Synthesizing module pecar @N:CG364 : pe_mcxmac.v(6) | Synthesizing module pe_mcxmac CORETSEIOI=1'b0 CORETSEOOI=32'b00000000000000000000000000000000 CORETSEii=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_0_0s_0s @W:CG360 : pe_mcxmac.v(676) | No assignment to wire CORETSEOii0 @W:CG360 : pe_mcxmac.v(679) | No assignment to wire CORETSEI0I0 @W:CG360 : pe_mcxmac.v(682) | No assignment to wire CORETSEl0I0 @N:CG364 : tsmac_top.v(4) | Synthesizing module tsmac_top TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MDIO_PHYID=32'b00000000000000000000000000010010 CORETSEIi=32'b00000000000000000000000000000001 CORETSEli=32'b00000000000000000000000000000001 CORETSEoi=32'b00000000000000000000000000000001 CORETSEii=32'b00000000000000000000000000000000 CORETSEOOI=32'b00000000000000000000000000000000 CORETSEIOI=32'b00000000000000000000000000000000 CORETSElOI=32'b00000000000000000000000000000001 CORETSEoOI=32'b00000000000000000000000000000010 CORETSEiOI=32'b00000000000000000000000000000001 CORETSEOII=32'b00000000000000000000000000000010 CORETSEIII=32'b00000000000000000000000000010010 CORETSElII=32'b00000000000000000000000000010010 CORETSEiII=32'b00000000000000000000000000000101 CORETSEOlI=32'b00000000000000000000000000000101 CORETSEoII=32'b00000000000000000000000000000001 Generated name = tsmac_top_Z5 @N:CG364 : sib_sync_pulse.v(5) | Synthesizing module sib_sync_pulse @N:CG364 : sib_sync_2flp.v(5) | Synthesizing module sib_sync_2flp CORETSEoO01I=32'b00000000000000000000000000000001 CORETSEiO01I=32'b00000000000000000000000000000000 Generated name = sib_sync_2flp_1s_0s @W:CG133 : sib_sync_2flp.v(62) | No assignment to CORETSEii1I @N:CG364 : pemstat_cntrl.v(6) | Synthesizing module pemstat_cntrl @W:CG360 : pemstat_cntrl.v(108) | No assignment to wire CORETSEi00o @W:CG360 : pemstat_cntrl.v(110) | No assignment to wire CORETSEO10o @W:CG133 : pemstat_cntrl.v(113) | No assignment to CORETSEI10o @W:CG133 : pemstat_cntrl.v(115) | No assignment to CORETSEl10o @W:CG133 : pemstat_cntrl.v(124) | No assignment to CORETSEi11I @W:CG133 : pemstat_cntrl.v(126) | No assignment to CORETSEIo0o @N:CG364 : pemstat_linc.v(6) | Synthesizing module pemstat_linc @N:CG179 : pemstat_linc.v(183) | Removing redundant assignment @N:CG179 : pemstat_linc.v(255) | Removing redundant assignment @N:CG364 : pemstat_ladd.v(6) | Synthesizing module pemstat_ladd @N:CG179 : pemstat_ladd.v(338) | Removing redundant assignment @N:CG364 : pemstat_sinc.v(6) | Synthesizing module pemstat_sinc @N:CG179 : pemstat_sinc.v(183) | Removing redundant assignment @N:CG179 : pemstat_sinc.v(255) | Removing redundant assignment @N:CG364 : pemstat_sinchd.v(6) | Synthesizing module pemstat_sinchd @N:CG179 : pemstat_sinchd.v(183) | Removing redundant assignment @N:CG179 : pemstat_sinchd.v(255) | Removing redundant assignment @N:CG364 : pemstat_sadd.v(6) | Synthesizing module pemstat_sadd @N:CG179 : pemstat_sadd.v(201) | Removing redundant assignment @N:CG179 : pemstat_sadd.v(278) | Removing redundant assignment @N:CG364 : pemstat_sincnf.v(6) | Synthesizing module pemstat_sincnf @N:CG179 : pemstat_sincnf.v(183) | Removing redundant assignment @N:CG179 : pemstat_sincnf.v(255) | Removing redundant assignment @N:CG364 : pemstat_store.v(6) | Synthesizing module pemstat_store @N:CG364 : pemstat_eim.v(6) | Synthesizing module pemstat_eim @N:CG364 : pemstat.v(6) | Synthesizing module pemstat @N:CG364 : mmcxwol.v(6) | Synthesizing module mmcxwol @N:CG364 : si_sal.v(4) | Synthesizing module si_sal @N:CG179 : si_sal.v(886) | Removing redundant assignment @W:CG360 : tsmac_top.v(149) | No assignment to wire CORETSElI0 @W:CG360 : tsmac_top.v(151) | No assignment to wire CORETSEoI0 @W:CG360 : tsmac_top.v(153) | No assignment to wire CORETSEiI0 @W:CG360 : tsmac_top.v(155) | No assignment to wire CORETSEOl0 @W:CG360 : tsmac_top.v(157) | No assignment to wire CORETSEIl0 @N:CG364 : tx2048x40.v(6) | Synthesizing module tx2048x40 TABITS=32'b00000000000000000000000000001011 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEI1I1I=32'b00000000000000000000000000000001 CORETSEl1I1I=32'b00000000000000000000000000000100 Generated name = tx2048x40_11s_1s_1s_4s @N:CL134 : tx2048x40.v(131) | Found RAM CORETSEi1I1I, depth=2048, width=40 @N:CG364 : rx4096x36.v(6) | Synthesizing module rx4096x36 RABITS=32'b00000000000000000000000000001100 CORETSEO0II=32'b00000000000000000000000000000001 CORETSEI1I1I=32'b00000000000000000000000000000001 CORETSEl1I1I=32'b00000000000000000000000000000100 Generated name = rx4096x36_12s_1s_1s_4s @N:CL134 : rx4096x36.v(131) | Found RAM CORETSEi1I1I, depth=4096, width=36 @N:CG364 : CoreTSE_top.v(2) | Synthesizing module CoreTSE_TOP GMII_TBI=32'b00000000000000000000000000000001 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 SAL=32'b00000000000000000000000000000001 WOL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s @N:CG364 : msgmii_clkrst.v(7) | Synthesizing module msgmii_clkrst @N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module msgmii_cnvtxi @W:CL169 : msgmii_cnvtxi.v(319) | Pruning register CORETSEloil[3:0] @N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module msgmii_cnvtxo @N:CG364 : t8b10b.v(6) | Synthesizing module t8b10b @N:CG364 : petex_top.v(6) | Synthesizing module petex_top CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petex_top_0s_1s @N:CG179 : petex_top.v(2036) | Removing redundant assignment @W:CL169 : petex_top.v(639) | Pruning register CORETSEII0OI @N:CG364 : perex_pma.v(6) | Synthesizing module perex_pma @W:CL169 : perex_pma.v(1536) | Pruning register CORETSEOili @W:CL169 : perex_pma.v(1506) | Pruning register CORETSEioli @W:CL169 : perex_pma.v(1476) | Pruning register CORETSEooli @N:CG364 : r10b8b.v(6) | Synthesizing module r10b8b @N:CG364 : perex_pcs.v(6) | Synthesizing module perex_pcs CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = perex_pcs_0s_1s @W:CL169 : perex_pcs.v(4065) | Pruning register CORETSEiOli @W:CL169 : perex_pcs.v(4010) | Pruning register CORETSElOli @W:CL169 : perex_pcs.v(3869) | Pruning register CORETSEliIi @W:CL265 : perex_pcs.v(1203) | Pruning bit 3 of CORETSEilio[3:0] -- not in use ... @W:CL265 : perex_pcs.v(1203) | Pruning bit 1 of CORETSEilio[3:0] -- not in use ... @N:CL177 : perex_pcs.v(3570) | Sharing sequential element CORETSEIoIi. @N:CG364 : peanx_sync.v(6) | Synthesizing module peanx_sync @N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module msgmii_peanx_top @W:CL169 : msgmii_peanx_top.v(3015) | Pruning register CORETSElO10 @W:CL265 : msgmii_peanx_top.v(2937) | Pruning bit 14 of CORETSEOO10[15:0] -- not in use ... @W:CL265 : msgmii_peanx_top.v(2345) | Pruning bit 14 of CORETSEO000[15:0] -- not in use ... @N:CL177 : msgmii_peanx_top.v(2271) | Sharing sequential element CORETSEiI00. @N:CG364 : petbm.v(6) | Synthesizing module petbm CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = petbm_0s_1s @W:CL169 : petbm.v(2461) | Pruning register CORETSEl1lOI @N:CG364 : petcr.v(7) | Synthesizing module petcr @N:CL177 : petcr.v(329) | Sharing sequential element CORETSEOO11. @N:CL177 : petcr.v(470) | Sharing sequential element CORETSEOO0OI. @N:CG364 : msgmii_tbi.v(6) | Synthesizing module msgmii_tbi CORETSEIOI=32'b00000000000000000000000000000000 CORETSEO0II=32'b00000000000000000000000000000001 Generated name = msgmii_tbi_0s_1s @W:CG360 : msgmii_tbi.v(387) | No assignment to wire CORETSEI010 @N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module msgmii_cnvrxi @W:CL169 : msgmii_cnvrxi.v(416) | Pruning register CORETSEOool[1:0] @N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module msgmii_cnvrxo @N:CG364 : msgmii_core.v(6) | Synthesizing module msgmii_core CORETSEIOI=32'b00000000000000000000000000000000 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = msgmii_core_0s_18s @W:CG781 : CoreTSE_top.v(861) | Undriven input CORETSElO0 on instance CORETSEIlI, tying to 0 @W:CG781 : CoreTSE_top.v(865) | Undriven input CORETSEoO0 on instance CORETSEIlI, tying to 0 @W:CG781 : CoreTSE_top.v(869) | Undriven input CORETSEiO0 on instance CORETSEIlI, tying to 0 @W:CG781 : CoreTSE_top.v(873) | Undriven input CORETSEOI0 on instance CORETSEIlI, tying to 0 @W:CG781 : CoreTSE_top.v(877) | Undriven input CORETSEII0 on instance CORETSEIlI, tying to 0 @W:CG781 : CoreTSE_top.v(901) | Undriven input CORETSEll0 on instance CORETSEIlI, tying to 0 @W:CG360 : CoreTSE_top.v(78) | No assignment to wire TXD @W:CG360 : CoreTSE_top.v(80) | No assignment to wire TXEN @W:CG360 : CoreTSE_top.v(82) | No assignment to wire TXER @N:CG364 : CoreTSE.v(2) | Synthesizing module Igloo2_1000BaseT_CORETSE_0_CORETSE FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 SAL=32'b00000000000000000000000000000001 WOL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 PACKET_SIZE=32'b00000000000000000000000000001011 Generated name = Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s @N:CG364 : igloo2.v(376) | Synthesizing module VCC @N:CG364 : igloo2.v(372) | Synthesizing module GND @N:CG364 : igloo2.v(727) | Synthesizing module CCC @N:CG364 : Igloo2_1000BaseT_FCCC_0_FCCC.v(5) | Synthesizing module Igloo2_1000BaseT_FCCC_0_FCCC @N:CG364 : igloo2.v(268) | Synthesizing module INBUF @N:CG364 : Igloo2_1000BaseT_sb_CCC_0_FCCC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_CCC_0_FCCC @N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster DATA_LOCATION=32'b00000000000000111110100000000000 ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000 ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 S7=32'b00000000000000000000000000000111 S8=32'b00000000000000000000000000001000 S9=32'b00000000000000000000000000001001 S10=32'b00000000000000000000000000001010 S11=32'b00000000000000000000000000001011 S12=32'b00000000000000000000000000001100 S13=32'b00000000000000000000000000001101 S14=32'b00000000000000000000000000001110 S15=32'b00000000000000000000000000001111 S16=32'b00000000000000000000000000010000 S17=32'b00000000000000000000000000010001 S18=32'b00000000000000000000000000010010 S19=32'b00000000000000000000000000010011 S20=32'b00000000000000000000000000010100 S21=32'b00000000000000000000000000010101 S22=32'b00000000000000000000000000010110 P0=32'b00000000000000000000000000100000 P1=32'b00000000000000000000000000100001 P2=32'b00000000000000000000000000100010 P3=32'b00000000000000000000000000100011 P4=32'b00000000000000000000000000100100 P5=32'b00000000000000000000000000100101 P6=32'b00000000000000000000000000100110 OP_COPY=7'b0000000 OP_POLL=7'b0000010 OP_LOAD=7'b0000011 OP_STORE=7'b0000100 OP_AND=7'b0000101 OP_OR=7'b0000110 Generated name = CoreConfigMaster_Z6 @W:CL190 : coreconfigmaster.v(723) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : coreconfigmaster.v(723) | Pruning register bit 0 of HTRANS[1:0] @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z7 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z8 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z9 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z10 @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z11 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z12 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(5) | Synthesizing module Igloo2_1000BaseT_sb_FABOSC_0_OSC @N:CG364 : Igloo2_1000BaseT_sb_HPMS_syn.v(5) | Synthesizing module MSS_010 @N:CG364 : Igloo2_1000BaseT_sb_HPMS.v(9) | Synthesizing module Igloo2_1000BaseT_sb_HPMS @N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET @N:CG364 : Igloo2_1000BaseT_sb.v(9) | Synthesizing module Igloo2_1000BaseT_sb @N:CG364 : coretse_if.v(18) | Synthesizing module coretse_if @A:CL282 : coretse_if.v(140) | Feedback mux created for signal bytes_valid_rx[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : coretse_if.v(140) | Feedback mux created for signal WDATA[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : coretse_if.v(53) | Feedback mux created for signal MTXDAT[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 @N:CG364 : LSRAM_MTX_MRX_TPSRAM_0_TPSRAM.v(5) | Synthesizing module LSRAM_MTX_MRX_TPSRAM_0_TPSRAM @N:CG364 : LSRAM_MTX_MRX.v(9) | Synthesizing module LSRAM_MTX_MRX @N:CG364 : igloo2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0 @N:CG364 : Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF @N:CG364 : Igloo2_1000BaseT.v(9) | Synthesizing module Igloo2_1000BaseT @W:CL156 : Igloo2_1000BaseT_SERDES_IF_0_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @N:CL201 : coretse_if.v(140) | Trying to extract state machine for register rx_st Extracted state machine for register rx_st State machine has 4 reachable states with original encodings of: 000 001 010 100 @N:CL201 : coretse_if.v(53) | Trying to extract state machine for register tx_st Extracted state machine for register tx_st State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @W:CL247 : Igloo2_1000BaseT_sb_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : Igloo2_1000BaseT_sb_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @N:CL201 : coreconfigmaster.v(723) | Trying to extract state machine for register state Extracted state machine for register state State machine has 29 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000110 000111 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 100000 100001 100010 100011 100100 100101 100110 @N:CL177 : petcr.v(343) | Sharing sequential element CORETSEIO11. @N:CL177 : petcr.v(484) | Sharing sequential element CORETSEIO0OI. @W:CL190 : petbm.v(669) | Optimizing register bit CORETSEllIOI[5] to a constant 0 @W:CL260 : petbm.v(669) | Pruning register bit 5 of CORETSEllIOI[5:0] @N:CL201 : msgmii_peanx_top.v(3347) | Trying to extract state machine for register CORETSElI10 @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSEIII0[15:0] is unused @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSEIII0[15:0] is unused @N:CL201 : perex_pcs.v(4633) | Trying to extract state machine for register CORETSEi1O0 Extracted state machine for register CORETSEi1O0 State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL157 : CoreTSE_top.v(78) | *Output TXD has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_top.v(80) | *Output TXEN has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_top.v(82) | *Output TXER has undriven bits -- simulation mismatch possible. @W:CL159 : CoreTSE_top.v(89) | Input RXD is unused @W:CL159 : CoreTSE_top.v(91) | Input RXDV is unused @W:CL159 : CoreTSE_top.v(93) | Input RXER is unused @W:CL159 : CoreTSE_top.v(95) | Input CRS is unused @W:CL159 : CoreTSE_top.v(97) | Input COL is unused @W:CL246 : pemstat_eim.v(151) | Input port bits 24 to 20 of CORETSEOiIo[31:0] are unused @W:CL247 : pemstat_store.v(176) | Input port bit 31 of CORETSEl00o[31:0] is unused @W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused @W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused @W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused @W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSEl00o[30:0] are unused @W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSEl00o[30:0] are unused @W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSEl00o[30:0] are unused @W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSEo0o[30:0] is unused @W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSEo0o[30:0] are unused @W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSElio0[51:0] are unused @W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSElio0[51:0] are unused @W:CL159 : sib_sync_2flp.v(24) | Input CORETSEoI01I is unused @W:CL159 : sib_sync_2flp.v(26) | Input CORETSEiI01I is unused @W:CL246 : tsmac_top.v(175) | Input port bits 31 to 10 of CORETSEiiI[31:0] are unused @W:CL246 : tsmac_top.v(175) | Input port bits 1 to 0 of CORETSEiiI[31:0] are unused @W:CL157 : tsmac_top.v(149) | *Output CORETSElI0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(151) | *Output CORETSEoI0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(153) | *Output CORETSEiI0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(155) | *Output CORETSEOl0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(157) | *Output CORETSEIl0 has undriven bits -- simulation mismatch possible. @W:CL159 : tsmac_top.v(139) | Input CORETSElO0 is unused @W:CL159 : tsmac_top.v(141) | Input CORETSEoO0 is unused @W:CL159 : tsmac_top.v(143) | Input CORETSEiO0 is unused @W:CL159 : tsmac_top.v(145) | Input CORETSEOI0 is unused @W:CL159 : tsmac_top.v(147) | Input CORETSEII0 is unused @W:CL159 : pecar.v(120) | Input CORETSEoIo is unused @W:CL159 : pecar.v(130) | Input CORETSEolo is unused @W:CL159 : pecar.v(143) | Input CORETSEoOo is unused @A:CL153 : pehst.v(613) | *Unassigned bits of CORETSEooI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(709) | *Unassigned bits of CORETSEioI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(714) | *Unassigned bits of CORETSEOiI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(716) | *Unassigned bits of CORETSEIiI1 are referenced and tied to 0 -- simulation mismatch possible. @W:CL159 : pehst.v(198) | Input CORETSEOoo0 is unused @N:CL201 : pemgt.v(547) | Trying to extract state machine for register CORETSEi1i1 Extracted state machine for register CORETSEi1i1 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 @W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSEl110[1:0] is unused @W:CL138 : perfn_top.v(3373) | Removing register 'CORETSEOOi0' because it is only assigned 0 or its original value. @N:CL201 : perfn_top.v(5127) | Trying to extract state machine for register CORETSEo0o @W:CL246 : perfn_top.v(142) | Input port bits 1 to 0 of CORETSEIoO1[7:0] are unused @N:CL135 : petfn_top.v(6206) | Found seqShift CORETSEOIlII, depth=3, width=8 @N:CL135 : petfn_top.v(7121) | Found seqShift CORETSEIllII, depth=4, width=1 @N:CL135 : petfn_top.v(6988) | Found seqShift CORETSEiIlII, depth=4, width=1 @N:CL135 : petfn_top.v(7239) | Found seqShift CORETSEollII, depth=4, width=1 @N:CL135 : petfn_top.v(2644) | Found seqShift CORETSEl1iOI, depth=3, width=1 @N:CL135 : petfn_top.v(2813) | Found seqShift CORETSEOOOII, depth=3, width=4 @N:CL135 : petfn_top.v(8329) | Found seqShift CORETSEl01, depth=3, width=1 @N:CL135 : petfn_top.v(7634) | Found seqShift CORETSEI01, depth=4, width=1 @N:CL201 : petfn_top.v(10298) | Trying to extract state machine for register CORETSElio0 @W:CL246 : petfn_top.v(214) | Input port bits 1 to 0 of CORETSEI0O1[6:0] are unused @W:CL246 : petfn_top.v(216) | Input port bits 1 to 0 of CORETSEl0O1[6:0] are unused @W:CL246 : petfn_top.v(218) | Input port bits 1 to 0 of CORETSEo0O1[6:0] are unused @W:CL246 : petfn_top.v(226) | Input port bits 9 to 6 of CORETSEi0O1[9:0] are unused @W:CL159 : petfn_top.v(326) | Input CORETSEO1i0 is unused @W:CL159 : petfn_top.v(329) | Input CORETSEI1i0 is unused @W:CL159 : petfn_top.v(337) | Input CORETSEl1i0 is unused @W:CL159 : petfn_top.v(340) | Input CORETSEo1i0 is unused @W:CL159 : petfn_top.v(351) | Input CORETSEi1i0 is unused @W:CL159 : petfn_top.v(343) | Input CORETSEOoi0 is unused @W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSEl110[1:0] is unused @W:CL159 : amcxfif_hst.v(232) | Input CORETSEiOOI is unused @N:CL201 : amcxtfif_wtm.v(268) | Trying to extract state machine for register CORETSEooiI Extracted state machine for register CORETSEooiI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL246 : amcxrfif_sys.v(234) | Input port bits 39 to 36 of CORETSEOOII[39:0] are unused @N:CL135 : amcxrfif_fab.v(1079) | Found seqShift CORETSEioi, depth=3, width=1 @N:CL201 : amcxrfif_fab.v(588) | Trying to extract state machine for register CORETSEO10I Extracted state machine for register CORETSEO10I State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 @W:CL247 : amcxrfif_fab.v(123) | Input port bit 12 of CORETSEIOII[13:0] is unused @N:CL201 : amcxtfif_sys.v(804) | Trying to extract state machine for register CORETSEiooI Extracted state machine for register CORETSEiooI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL246 : coreapb3_iaddr_reg.v(39) | Input port bits 31 to 24 of PADDR[31:0] are unused @W:CL159 : coreapb3.v(72) | Input IADDR is unused @W:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(122) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(123) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(124) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(125) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(126) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(127) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(128) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(129) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(130) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(131) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(132) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(133) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(134) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(135) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(136) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused @W:CL159 : ram256x16_rtl.v(23) | Input RESET is unused @N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : coreabc.v(134) | Input PSLVERR_M is unused @W:CL159 : coreabc.v(138) | Input INTREQ is unused @W:CL159 : coreabc.v(141) | Input INITDATVAL is unused @W:CL159 : coreabc.v(142) | Input INITDONE is unused @W:CL159 : coreabc.v(143) | Input INITADDR is unused @W:CL159 : coreabc.v(144) | Input INITDATA is unused @W:CL159 : coreabc.v(148) | Input PSEL_S is unused @W:CL159 : coreabc.v(149) | Input PENABLE_S is unused @W:CL159 : coreabc.v(150) | Input PWRITE_S is unused @W:CL159 : coreabc.v(151) | Input PADDR_S is unused @W:CL159 : coreabc.v(152) | Input PWDATA_S is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 27 15:53:23 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 27 15:53:23 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 4MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 27 15:53:23 2016 ###########################################################] @A: : | multi_srs_gen output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Multi-srs Generator Report Linked File: Igloo2_1000BaseT_multi_srs_gen.srr Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\designer\Igloo2_1000BaseT\synthesis.fdc @L: D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\synthesis\Igloo2_1000BaseT_scck.rpt Printing clock summary report in "D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\synthesis\Igloo2_1000BaseT_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 161MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 161MB) @W:BN231 : | Constraints on tristate nets currently not supported Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 161MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 161MB) @W:BN132 : petmc_top.v(2012) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEoio0, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEOil1.CORETSEiIl1 @W:BN132 : petfn_top.v(4500) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElIIII, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEllo @W:BN132 : petfn_top.v(6138) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOl0OI, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIll1 @W:BN132 : perfn_top.v(3332) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiio0, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEOioi @W:BN132 : permc_top.v(1848) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEIoOOI, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSElol1 @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : pemgt.v(2195) | Removing sequential instance CORETSEIoI1 of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(1031) | Removing sequential instance IO_OUT[0] of view:PrimLib.dffre(prim) in hierarchy view:work.Igloo2_1000BaseT_COREABC_0_COREABC_Z1(verilog) because there are no references to its outputs @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_1(verilog) because there are no references to its outputs @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSEOO11I\.CORETSEli01I of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : pecar.v(630) | Removing sequential instance CORETSEli01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(683) | Removing sequential instance CORETSEIO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEoi11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEIOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : msgmii_core.v(251) | Removing sequential instance CORETSEIi1[9:0] of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_core_0s_18s(verilog) because there are no references to its outputs @N:BN362 : pemgt.v(2657) | Removing sequential instance CORETSEl0Io of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : pecar.v(616) | Removing sequential instance CORETSEIi01 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(669) | Removing sequential instance CORETSEOO11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEli11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEOOo1 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(420) | Removing sequential instance CORETSEI001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(471) | Removing sequential instance CORETSEO101 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1055) | Removing sequential instance CORETSEo111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(250) | Removing sequential instance CORETSEIIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(289) | Removing sequential instance CORETSEoIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : pecar.v(406) | Removing sequential instance CORETSEO001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(457) | Removing sequential instance CORETSEi001 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1041) | Removing sequential instance CORETSEl111 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEIo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEio11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(237) | Removing sequential instance CORETSEOIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(276) | Removing sequential instance CORETSElIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : amcxtfif_fab.v(991) | Removing sequential instance CORETSEl0l of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog) because there are no references to its outputs @N:BN362 : mahbe_dual.v(282) | Removing sequential instance CORETSEl0Ol of view:PrimLib.dffse(prim) in hierarchy view:work.mahbe_dual_0s_1s(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEOo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEoo11 of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEO00l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s(verilog) because there are no references to its outputs @N:BN362 : tsm_sysreg.v(994) | Removing sequential instance genblk4\.CORETSEil0l[31:0] of view:PrimLib.dffse(prim) in hierarchy view:work.tsm_sysreg_1s_0s(verilog) because there are no references to its outputs @N:BN362 : tsm_sysreg.v(1037) | Removing sequential instance CORETSEIo11I[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.tsm_sysreg_1s_0s(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog) because there are no references to its outputs @N:BN362 : amcxtfif_fab.v(1025) | Removing sequential instance CORETSEl0oI[10:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog) because there are no references to its outputs @N:BN362 : amcxtfif_fab.v(1073) | Removing sequential instance CORETSEo0oI[11:0] of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog) because there are no references to its outputs @N:BN362 : amcxtfif_fab.v(939) | Removing sequential instance CORETSEO0oI of view:PrimLib.dffr(prim) in hierarchy view:work.amcxtfif_fab_11s_32s_2s_0_0_1s(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_0(verilog) because there are no references to its outputs @W:MT462 : igloo2_1000baset_serdes_if_0_serdes_if.v(98) | Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=21 set on top level netlist Igloo2_1000BaseT Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 189MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz 20.000 declared default_clkgroup FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL0 50.0 MHz 20.000 generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL3 125.0 MHz 8.000 generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup System 100.0 MHz 10.000 system system_clkgroup pemgt|CORETSEOo1_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ================================================================================================================================================================================ @W:MT532 : msgmii_clkrst.v(354) | Found signal identified as System clock which controls 3 sequential elements including CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEI0O0.CORETSEiO1. Using this clock, which has no specified timing constraint, can adversely impact design performance. @W:MT530 : pemgt.v(1863) | Found inferred clock pemgt|CORETSEOo1_inferred_clock which controls 290 sequential elements including CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEIOIo[7:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\synthesis\Igloo2_1000BaseT.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 108MB peak: 189MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Sun Nov 27 15:53:26 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 163MB peak: 164MB) @W:BN231 : | Constraints on tristate nets currently not supported @W:MO171 : coreabc.v(484) | Sequential instance COREABC_0.UROM\.INSTR_MUXC reduced to a combinational gate by constant propagation @W:MO111 : tsmac_top.v(157) | Tristate driver CORETSEIl0 on net CORETSEIl0 has its enable tied to GND (module tsmac_top_Z5) @W:MO111 : tsmac_top.v(155) | Tristate driver CORETSEOl0 on net CORETSEOl0 has its enable tied to GND (module tsmac_top_Z5) @W:MO111 : tsmac_top.v(153) | Tristate driver CORETSEiI0 on net CORETSEiI0 has its enable tied to GND (module tsmac_top_Z5) @W:MO111 : tsmac_top.v(151) | Tristate driver CORETSEoI0 on net CORETSEoI0 has its enable tied to GND (module tsmac_top_Z5) @W:MO111 : tsmac_top.v(149) | Tristate driver CORETSElI0 on net CORETSElI0 has its enable tied to GND (module tsmac_top_Z5) @W:MO111 : coretse_top.v(82) | Tristate driver TXER on net TXER has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(80) | Tristate driver TXEN on net TXEN has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_2 on net TXD_2 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_3 on net TXD_3 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_4 on net TXD_4 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_5 on net TXD_5 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_6 on net TXD_6 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_7 on net TXD_7 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(78) | Tristate driver TXD_8 on net TXD_8 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[0] on net TXD[0] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[1] on net TXD[1] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[2] on net TXD[2] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[3] on net TXD[3] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[4] on net TXD[4] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[5] on net TXD[5] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[6] on net TXD[6] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXD_t[7] on net TXD[7] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXEN_t on net TXEN has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : | Tristate driver TXER_t on net TXER has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) @W:MO111 : igloo2_1000baset_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) @W:MO111 : igloo2_1000baset_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) @W:MO111 : igloo2_1000baset_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) @W:MO111 : igloo2_1000baset_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) @W:MO111 : igloo2_1000baset_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) @N:BN362 : pecar.v(951) | Removing sequential instance CORETSEliI1.CORETSEi011 of view:PrimLib.sdffr(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : pecar.v(907) | Removing sequential instance CORETSEliI1.CORETSEo011 of view:PrimLib.sdffr(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : pecar.v(886) | Removing sequential instance CORETSEliI1.CORETSEI011 of view:PrimLib.dff(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : pecar.v(872) | Removing sequential instance CORETSEliI1.CORETSEO011 of view:PrimLib.dff(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(216) | Removing sequential instance CORETSEolo0.CORETSElolOI of view:PrimLib.sdffr(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(195) | Removing sequential instance CORETSEolo0.CORETSEOolOI of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(181) | Removing sequential instance CORETSEolo0.CORETSEi1lOI of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(354) | Removing sequential instance CORETSEI0O0.CORETSEiO1 of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_core_0s_18s(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(328) | Removing sequential instance CORETSEI0O0.CORETSEOlol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_core_0s_18s(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(315) | Removing sequential instance CORETSEI0O0.CORETSEiIol of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_core_0s_18s(verilog) because there are no references to its outputs @W:MO171 : coreresetp.v(769) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : pemstat_cntrl.v(406) | Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEli0o reduced to a combinational gate by constant propagation @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @W:BN132 : coreresetp.v(963) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q1, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q1 @W:BN132 : coreresetp.v(963) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q2, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q2 Available hyper_sources - for debug and ip models None Found @W:MT462 : igloo2_1000baset_serdes_if_0_serdes_if.v(98) | Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. @N:FA239 : t8b10b.v(148) | ROM CORETSEII11I[5:0] mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSEoI11I[1:0] mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSElI11I mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSEiiO1I mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSEII11I[5:0] mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSEII11I[5:0]', 32 words by 6 bits @N:FA239 : t8b10b.v(148) | ROM CORETSEoI11I[1:0] mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSEoI11I[1:0]', 32 words by 2 bits @N:FA239 : t8b10b.v(148) | ROM CORETSElI11I mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSElI11I', 32 words by 1 bits @N:FA239 : t8b10b.v(148) | ROM CORETSEiiO1I mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSEiiO1I', 32 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] mapped in logic. @N:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSEo0I1I', 16 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSEl0I1I', 16 words by 1 bits @N:FA239 : r10b8b.v(1950) | ROM CORETSEoII1I[2:0] mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSEoII1I[2:0]', 12 words by 3 bits @N:FA239 : r10b8b.v(1950) | ROM CORETSEOlI1I mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSEOlI1I', 12 words by 1 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEOII1I[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEIOI1I[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEiOI1I[1:0]', 14 words by 2 bits @N:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] mapped in logic. @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSEOOI1I[1:0]', 46 words by 2 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] mapped in logic. @N:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] mapped in logic. @N:FA239 : r10b8b.v(1950) | ROM CORETSEoII1I[3:0] mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSEoII1I[3:0]', 12 words by 4 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSEo0I1I mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSEo0I1I', 16 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSEl0I1I mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSEl0I1I', 16 words by 1 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEOII1I[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEOII1I[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEIOI1I[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEIOI1I[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSEiOI1I[1:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSEiOI1I[1:0]', 14 words by 2 bits @N:FA239 : r10b8b.v(268) | ROM CORETSEOOI1I[1:0] mapped in logic. @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSEOOI1I[1:0]', 46 words by 2 bits @N:BN362 : pemgt.v(2142) | Removing sequential instance CORETSEOoI1[4:0] of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : msgmii_cnvtxo.v(414) | Removing sequential instance CORETSEll1 of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_cnvtxo(verilog) because there are no references to its outputs Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 172MB) Encoding state machine ICYCLE[3:0] (view:work.Igloo2_1000BaseT_COREABC_0_COREABC_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1031) | No possible illegal states for state machine ICYCLE[3:0],safe FSM implementation is disabled @N:FX404 : coreabc.v(1100) | Found addmux in view:work.Igloo2_1000BaseT_COREABC_0_COREABC_Z1(verilog) inst ZREGISTER_26[15:0] from un33_ZREGISTER[15:0] @W:MO129 : coreabc.v(484) | Sequential instance COREABC_0.UROM.INSTR_SLOT[0] reduced to a combinational gate by constant propagation @W:FX107 : ram256x16_rtl.v(32) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : ram256x16_rtl.v(32) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for UG3\.UR32\.UR0.RAM[15:0] (view:work.Igloo2_1000BaseT_COREABC_0_RAMBLOCKS_32s_24s(verilog)). @W:FX107 : ram256x16_rtl.v(32) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : ram256x16_rtl.v(32) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for UG3\.UR_xhdl12.RAM[15:0] (view:work.Igloo2_1000BaseT_COREABC_0_RAMBLOCKS_32s_24s(verilog)). @N:FX403 : rx4096x36.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSEoo0.CORETSEi1I1I[35:0] with specified coding style. Inferring block RAM. @W:FX107 : rx4096x36.v(131) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : rx4096x36.v(131) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for CORETSEoo0.CORETSEi1I1I[35:0] (view:work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)). @N:FX403 : tx2048x40.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSEO10.CORETSEi1I1I[39:0] with specified coding style. Inferring block RAM. @W:FX107 : tx2048x40.v(131) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : tx2048x40.v(131) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for CORETSEO10.CORETSEi1I1I[39:0] (view:work.CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s(verilog)). @N:MF179 : amcxtfif_fab.v(762) | Found 11 bit by 11 bit '==' comparator, 'un3_CORETSEiO1I' Encoding state machine CORETSEiooI[5:0] (view:work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:FX404 : amcxtfif_sys.v(1276) | Found addmux in view:work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog) inst un1_CORETSEoOiI_3_0_m[13:0] from un1_CORETSEoOiI_3_1[13:0] @N:MF179 : amcxtfif_sys.v(2069) | Found 12 bit by 12 bit '==' comparator, 'un1_CORETSEoOiI' Encoding state machine CORETSEO10I[4:0] (view:work.amcxrfif_fab_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : amcxrfif_fab.v(497) | Found 13 bit by 13 bit '==' comparator, 'un4_CORETSEoO0I' @N: : amcxrfif_sys.v(1963) | Found counter in view:work.amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s(verilog) inst CORETSEO11I[13:0] @N:MF179 : amcxrfif_sys.v(1281) | Found 12 bit by 12 bit '==' comparator, 'un3_CORETSEiO1I' Encoding state machine CORETSEooiI[5:0] (view:work.amcxtfif_wtm_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N: : amcxtfif_wtm.v(524) | Found counter in view:work.amcxtfif_wtm_12s_1s_0_0(verilog) inst CORETSEioiI[15:0] @N:MF179 : | Found 17 bit by 17 bit '==' comparator, 'un12_CORETSEO00II' @N:MF179 : petfn_top.v(9617) | Found 16 bit by 16 bit '==' comparator, 'un18_CORETSEO00II' @N:MF179 : petfn_top.v(4272) | Found 16 bit by 16 bit '==' comparator, 'un3_CORETSEIOIII' @N:MF179 : petfn_top.v(5110) | Found 10 bit by 10 bit '==' comparator, 'CORETSEi0III' @N: : perfn_top.v(2477) | Found counter in view:work.perfn_top_0s_0_1s(verilog) inst CORETSEi11i[14:0] @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSEIOi0[0] of view:PrimLib.dffr(prim) in hierarchy view:work.perfn_top_0s_0_1s(verilog) because there are no references to its outputs @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSEIOi0[1] of view:PrimLib.dffr(prim) in hierarchy view:work.perfn_top_0s_0_1s(verilog) because there are no references to its outputs @N:MF179 : | Found 17 bit by 17 bit '==' comparator, 'un21_CORETSEoi1i' @N:MF179 : perfn_top.v(4371) | Found 16 bit by 16 bit '==' comparator, 'un6_CORETSEOOii' Encoding state machine CORETSEi1i1[31:0] (view:work.pemgt(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEii1o.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSElOoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEoOoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEiOoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEOIoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEIIoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSElIoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEoIoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEiIoo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEOloo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEIloo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSElloo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEoloo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEo0oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEi0oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEO1oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEI1oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEl1oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEo1oo.CORETSEo11o[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEi1oo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEIooo.CORETSEo11o[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSElooo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEoooo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEiooo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEOioo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEIioo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSElioo.CORETSEo11o[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSEI00o.CORETSEoioo.CORETSEo11o[11:0] @W:MO129 : pemstat_cntrl.v(2167) | Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[36] reduced to a combinational gate by constant propagation @W:MO129 : pemstat_cntrl.v(2167) | Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[37] reduced to a combinational gate by constant propagation @W:BN132 : pemstat_cntrl.v(2167) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[25], because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[24] @W:BN132 : pemstat_cntrl.v(2167) | Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[8], because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[7] @N: : pemstat_linc.v(96) | Found counter in view:work.pemstat_linc(verilog) inst CORETSEo11o[17:0] @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[30] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[29] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[28] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[27] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[26] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[25] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSEll1o[24] is always 0, optimizing ... @N: : mmcxwol.v(964) | Found counter in view:work.mmcxwol(verilog) inst CORETSEi11l[4:0] @N: : mmcxwol.v(765) | Found counter in view:work.mmcxwol(verilog) inst CORETSEl11l[4:0] @N: : msgmii_cnvtxo.v(267) | Found counter in view:work.msgmii_cnvtxo(verilog) inst CORETSElool[6:0] Encoding state machine CORETSEi1O0_1[3:0] (view:work.perex_pcs_0s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4633) | No possible illegal states for state machine CORETSEi1O0_1[3:0],safe FSM implementation is disabled @N: : msgmii_peanx_top.v(3392) | Found counter in view:work.msgmii_peanx_top(verilog) inst CORETSEl1l0[20:0] @N:MF179 : msgmii_peanx_top.v(2379) | Found 15 bit by 15 bit '==' comparator, 'CORETSEI000' @N:MF179 : msgmii_peanx_top.v(2664) | Found 16 bit by 16 bit '==' comparator, 'CORETSEIo00' @N:MF179 : msgmii_peanx_top.v(2988) | Found 15 bit by 15 bit '==' comparator, 'un7_CORETSEIO10' @N: : msgmii_cnvrxi.v(453) | Found counter in view:work.msgmii_cnvrxi(verilog) inst CORETSElool[5:0] @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.Igloo2_1000BaseT_sb(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ... @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.Igloo2_1000BaseT_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.Igloo2_1000BaseT_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.Igloo2_1000BaseT_sb(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(163) | Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31], because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] Encoding state machine state[28:0] (view:work.CoreConfigMaster_Z6(verilog)) original code -> new code 000000 -> 00000000000000000000000000001 000001 -> 00000000000000000000000000010 000010 -> 00000000000000000000000000100 000011 -> 00000000000000000000000001000 000100 -> 00000000000000000000000010000 000101 -> 00000000000000000000000100000 000110 -> 00000000000000000000001000000 000111 -> 00000000000000000000010000000 001001 -> 00000000000000000000100000000 001010 -> 00000000000000000001000000000 001011 -> 00000000000000000010000000000 001100 -> 00000000000000000100000000000 001101 -> 00000000000000001000000000000 001110 -> 00000000000000010000000000000 001111 -> 00000000000000100000000000000 010000 -> 00000000000001000000000000000 010001 -> 00000000000010000000000000000 010010 -> 00000000000100000000000000000 010011 -> 00000000001000000000000000000 010100 -> 00000000010000000000000000000 010101 -> 00000000100000000000000000000 010110 -> 00000001000000000000000000000 100000 -> 00000010000000000000000000000 100001 -> 00000100000000000000000000000 100010 -> 00001000000000000000000000000 100011 -> 00010000000000000000000000000 100100 -> 00100000000000000000000000000 100101 -> 01000000000000000000000000000 100110 -> 10000000000000000000000000000 @N: : coreconfigmaster.v(723) | Found counter in view:work.CoreConfigMaster_Z6(verilog) inst pause_count[4:0] @W:MO160 : coreconfigmaster.v(723) | Register bit HSIZE[2] is always 0, optimizing ... @N:MF179 : coreconfigmaster.v(573) | Found 32 bit by 32 bit '==' comparator, 'd_state152' Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z9_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine state[2:0] (view:work.CoreConfigP_Z11(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z12(verilog) inst count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF_READY_int, because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_state[6] Encoding state machine state[3:0] (view:work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | No possible illegal states for state machine state[3:0],safe FSM implementation is disabled @N: : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) inst count[6:0] Encoding state machine tx_st[4:0] (view:work.coretse_if(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine rx_st[3:0] (view:work.coretse_if(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 100 -> 11 @N:MO225 : coretse_if.v(140) | No possible illegal states for state machine rx_st[3:0],safe FSM implementation is disabled @N: : coretse_if.v(53) | Found counter in view:work.coretse_if(verilog) inst pkt_cnt[9:0] @N: : coretse_if.v(53) | Found counter in view:work.coretse_if(verilog) inst RADDR[9:0] @N: : coretse_if.v(140) | Found counter in view:work.coretse_if(verilog) inst pkt_cnt_rx[9:0] @N: : coretse_if.v(140) | Found counter in view:work.coretse_if(verilog) inst WADDR[9:0] @N:MF179 : coretse_if.v(118) | Found 10 bit by 10 bit '==' comparator, 'REN13' @N:BN362 : pemgt.v(547) | Removing sequential instance CORETSEo1I1.CORETSEi1i1[31] in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.Igloo2_1000BaseT_sb(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_SLOT[1] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_SLOT[2] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_SLOT[3] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[11] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[12] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[13] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[14] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[15] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 266MB peak: 267MB) @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.sdif_core_reset_n in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.sdif_core_reset_n_q1 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.hot_reset_n in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @W:BN132 : msgmii_clkrst.v(159) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEoOol, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol @W:BN132 : msgmii_clkrst.v(120) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEii1l, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol @W:BN132 : msgmii_clkrst.v(172) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEiOol, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol @W:BN132 : msgmii_clkrst.v(211) | Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSElOol, because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[31] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[30] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(8714) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEOO0II in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(8619) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEiilII in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 256MB peak: 270MB) @N:BN362 : coreresetp.v(1170) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.psel_q2 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_q1 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset_q in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled_q in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_q in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.pwrite_q1 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.psel_q1 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset_entry_p in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled_entry_p in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_entry_p in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.pwrite_q2 in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[1] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[0] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.state[1] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[4] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[3] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[2] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[1] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q1[0] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[4] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[3] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[2] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.genblk2\.sdif0_phr.count[6:0] of view:PrimLib.counter(prim) in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : coreconfigmaster.v(723) | Removing sequential instance Igloo2_1000BaseT_sb_0.ConfigMaster_0.state[8] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(9650) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIOii in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(9508) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEil0II in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(5935) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSEIl0II in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(3326) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElI0II in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[23] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[22] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[21] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10298) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[50] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEI00o.CORETSElooo.CORETSEoiIo in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEI00o.CORETSEIooo.CORETSEoiIo in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 228MB peak: 281MB) @N:FX404 : perfn_top.v(2143) | Found addmux in view:work.Igloo2_1000BaseT(verilog) inst CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEII1i_i_m2[15:0] from CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un6_CORETSEII1i_1[15:0] @N:FX404 : coreabc.v(792) | Found addmux in view:work.Igloo2_1000BaseT(verilog) inst COREABC_0.ACCUM_NEXT_m6[31:0] from COREABC_0.un1_ACCUMULATOR[31:0] @N:FX404 : coreconfigmaster.v(164) | Found addmux in view:work.Igloo2_1000BaseT(verilog) inst Igloo2_1000BaseT_sb_0.ConfigMaster_0.d_bytecount_0[15:0] from Igloo2_1000BaseT_sb_0.ConfigMaster_0.un1_bytecount_16[15:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 232MB peak: 281MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:34s; Memory used current: 248MB peak: 281MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:35s; CPU Time elapsed 0h:00m:34s; Memory used current: 244MB peak: 281MB) @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEO0I1I[0:0]', 64 words by 1 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEI0I1I[0:0]', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEIiO1I[4:0]', 46 words by 5 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEIiO1I[4:0]', 46 words by 5 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEO0I1I', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEoiO1I[1:0]', 46 words by 2 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEl1li.CORETSEiiO1I', 46 words by 1 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEI0I1I', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEoiO1I[1:0]', 46 words by 2 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEO1li.CORETSEiiO1I', 46 words by 1 bits @N:MO106 : instructions.v(85) | Found ROM, 'COREABC_0.UROM\.UROM.doins[57:1]', 63 words by 57 bits @N:BN362 : coreabc.v(484) | Removing sequential instance COREABC_0.UROM\.INSTR_ADDR[10] in hierarchy view:work.Igloo2_1000BaseT(verilog) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:40s; CPU Time elapsed 0h:00m:40s; Memory used current: 247MB peak: 281MB) Finished technology mapping (Real Time elapsed 0h:00m:48s; CPU Time elapsed 0h:00m:47s; Memory used current: 293MB peak: 328MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:48s -3.73ns 9815 / 5133 2 0h:00m:49s -3.73ns 9514 / 5133 3 0h:00m:49s -3.08ns 9515 / 5133 4 0h:00m:49s -2.52ns 9515 / 5133 5 0h:00m:50s -2.52ns 9517 / 5133 @N:FX271 : pehst.v(1713) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[3]" with 13 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[5]" with 8 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[4]" with 10 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[6]" with 7 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[2]" with 8 loads replicated 1 times to improve timing @N:FX271 : amcxfif_hst.v(1999) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEolII.CORETSEoiOI[13]" with 23 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[11]" with 4 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1609) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110[1]" with 60 loads replicated 3 times to improve timing @N:FX271 : pehst.v(1609) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110[0]" with 39 loads replicated 3 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_529_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_291_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_532_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_344_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_523_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_520_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_97_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_81_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.N_524_i" with 2 loads replicated 1 times to improve timing Timing driven replication report Added 13 Registers via timing driven replication Added 9 LUTs via timing driven replication 6 0h:00m:55s -2.46ns 9525 / 5146 7 0h:00m:56s -2.46ns 9525 / 5146 @N:FP130 : | Promoting Net COREABC_0_PRESETN on CLKINT I_2179 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0_HPMS_READY on CLKINT I_2180 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEllol_i on CLKINT I_2181 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEIoi0_i on CLKINT I_2182 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEilI0_i on CLKINT I_2183 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEloi0_i on CLKINT I_2184 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEOIII_i on CLKINT I_2185 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiOII_i on CLKINT I_2186 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIIII_i on CLKINT I_2187 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEoOII_i on CLKINT I_2188 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEI0O0.un1_CORETSEIi1l_i on CLKINT I_2189 @N:FP130 : | Promoting Net PHY_MDC_c on CLKINT I_2190 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEOl11_i on CLKINT I_2191 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0_INIT_APB_S_PRESET_N on CLKINT I_2192 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0_INIT_APB_S_PCLK on CLKINT I_2193 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEil11_i on CLKINT I_2194 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSElIII_i on CLKINT I_2195 @N:FP130 : | Promoting Net CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEliI1.CORETSEII11_i on CLKINT I_2196 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_2197 @N:FP130 : | Promoting Net Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_2198 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:59s; CPU Time elapsed 0h:00m:58s; Memory used current: 302MB peak: 328MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:59s; CPU Time elapsed 0h:00m:59s; Memory used current: 309MB peak: 328MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 7 non-gated/non-generated clock tree(s) driving 5081 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 124 clock pin(s) of sequential element(s) 0 instances converted, 124 sequential instances remain driven by gated/generated clocks ======================================================================================= Non-Gated/Non-Generated Clocks ======================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 Igloo2_1000BaseT_sb_0.CCC_0.GL0_INST CLKINT 2815 Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST ClockId0003 CLKINT_0 CLKINT 1705 CORETSE_0.CORETSEO.CORETSEOi[8] ClockId0004 FCCC_0.GL0_INST CLKINT 408 CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEOiO0.CORETSElool[5] ClockId0005 Igloo2_1000BaseT_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 30 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] ClockId0006 FCCC_0.GL1_INST CLKINT 12 CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEi0O0.CORETSEolo0.CORETSEoolOI ClockId0007 SERDES_IF_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF_0.SERDESIF_INST ClockId0008 Igloo2_1000BaseT_sb_0.Igloo2_1000BaseT_sb_HPMS_0.MSS_ADLIB_INST clock definition on MSS_010 110 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.SDIF_RELEASED_q2 ============================================================================================================================================================================================================== ===================================================================================================================== Gated/Generated Clocks ===================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1 SLE 124 CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEoOI0 No gated clock conversion method for cell cell:ACG4.SLE ================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:01m:00s; CPU Time elapsed 0h:01m:00s; Memory used current: 230MB peak: 328MB) Writing Analyst data base D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\synthesis\synwork\Igloo2_1000BaseT_m.srm @W:MT462 : igloo2_1000baset_serdes_if_0_serdes_if.v(98) | Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. Finished Writing Netlist Databases (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:02s; Memory used current: 284MB peak: 328MB) Writing EDIF Netlist and constraint files @W:MT462 : igloo2_1000baset_serdes_if_0_serdes_if.v(98) | Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:01m:05s; CPU Time elapsed 0h:01m:04s; Memory used current: 287MB peak: 328MB) Start final timing analysis (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:05s; Memory used current: 274MB peak: 328MB) @W:MT246 : igloo2_1000baset_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock CLK0_PAD with period 20.00ns Found clock SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns Found clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns Found clock Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB with period 40.00ns Found clock Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns Found clock Igloo2_1000BaseT_sb_0/CCC_0/GL0 with period 20.00ns Found clock Igloo2_1000BaseT_sb_0/CCC_0/GL3 with period 8.00ns Found clock FCCC_0/GL0 with period 16.00ns Found clock FCCC_0/GL1 with period 16.00ns @W:MT420 : | Found inferred clock pemgt|CORETSEOo1_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Sun Nov 27 15:54:33 2016 # Top view: Igloo2_1000BaseT Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\DATA\CORETSE _MSSMAC\DG0633_Eth_loop_back _igloo2\DG0633_11.7_SP2 _Eth_loop_back_IGLOO2\Hardware\CoreTSE_1000BaseT_Demo\designer\Igloo2_1000BaseT\synthesis.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.311 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup FCCC_0/GL0 62.5 MHz 59.3 MHz 16.000 16.873 2.744 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz 78.6 MHz 16.000 12.721 7.106 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL0 50.0 MHz 37.7 MHz 20.000 26.554 -1.282 generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/CCC_0/GL3 125.0 MHz NA 8.000 NA NA generated (from CLK0_PAD) default_clkgroup Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 431.2 MHz 20.000 2.319 17.681 declared default_clkgroup Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 25.0 MHz 138.5 MHz 40.000 7.219 16.544 declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 94.1 MHz 8.000 10.622 -1.311 declared default_clkgroup pemgt|CORETSEOo1_inferred_clock 100.0 MHz 158.9 MHz 10.000 6.295 3.705 inferred Inferred_clkgroup_0 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ======================================================================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.681 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB | 40.000 32.781 | No paths - | 20.000 17.990 | 20.000 16.544 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 8.000 0.259 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] FCCC_0/GL0 | 8.000 5.476 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] FCCC_0/GL1 | 8.000 5.476 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 4.000 -1.311 | No paths - | No paths - | No paths - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] pemgt|CORETSEOo1_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_0/GL0 SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 8.000 2.744 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_0/GL0 | 16.000 7.003 | No paths - | No paths - | No paths - FCCC_0/GL1 FCCC_0/GL0 | 8.000 7.106 | No paths - | No paths - | No paths - FCCC_0/GL1 FCCC_0/GL1 | 16.000 15.106 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB | 20.000 False | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 4.000 -1.282 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 FCCC_0/GL0 | 4.000 -0.218 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 FCCC_0/GL1 | 4.000 0.820 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 Igloo2_1000BaseT_sb_0/CCC_0/GL0 | 20.000 7.576 | No paths - | No paths - | No paths - Igloo2_1000BaseT_sb_0/CCC_0/GL0 pemgt|CORETSEOo1_inferred_clock | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock FCCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock FCCC_0/GL1 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock Igloo2_1000BaseT_sb_0/CCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSEOo1_inferred_clock pemgt|CORETSEOo1_inferred_clock | 10.000 3.705 | No paths - | No paths - | No paths - =========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FCCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIOil[8] FCCC_0/GL0 SLE Q CORETSEIOil[8] 0.094 2.744 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEiIil[8] FCCC_0/GL0 SLE Q CORETSEiIil[8] 0.094 2.784 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEiOil[8] FCCC_0/GL0 SLE Q CORETSEiOil[8] 0.094 2.812 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSElIil[8] FCCC_0/GL0 SLE Q CORETSElIil[8] 0.094 2.851 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEoOil[8] FCCC_0/GL0 SLE Q CORETSEoOil[8] 0.094 2.851 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEiiol[8] FCCC_0/GL0 SLE Q CORETSEiiol[8] 0.094 2.879 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEooIi FCCC_0/GL0 SLE Q CORETSEiiO0 0.094 3.027 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEOiol[8] FCCC_0/GL0 SLE Q CORETSEOiol[8] 0.094 3.235 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEliol[8] FCCC_0/GL0 SLE Q CORETSEliol[8] 0.094 3.303 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEoIo0.CORETSEIOI0[2] FCCC_0/GL0 SLE Q CORETSEIOI0[2] 0.076 3.332 ========================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol[0] FCCC_0/GL0 SLE D N_136_i_0 7.778 2.744 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEoOl0 FCCC_0/GL0 SLE D CORETSEioI0 7.778 3.027 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol[1] FCCC_0/GL0 SLE D CORETSEl0ol_5[1] 7.778 3.280 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[0] FCCC_0/GL0 SLE D CORETSEIO00[0] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[1] FCCC_0/GL0 SLE D CORETSEIO00[1] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[2] FCCC_0/GL0 SLE D CORETSEIO00[2] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[3] FCCC_0/GL0 SLE D CORETSEIO00[3] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[4] FCCC_0/GL0 SLE D CORETSEIO00[4] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[5] FCCC_0/GL0 SLE D CORETSEIO00[5] 7.778 3.332 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEiIo0.CORETSEo1I0[6] FCCC_0/GL0 SLE D CORETSEIO00[6] 7.778 3.332 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 5.034 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.744 Number of logic level(s): 7 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIOil[8] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol[0] / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIOil[8] SLE Q Out 0.094 0.094 - CORETSEIOil[8] Net - - 0.509 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.un36_CORETSEIlil[8] CFG2 B In - 0.603 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.un36_CORETSEIlil[8] CFG2 Y Out 0.143 0.746 - un36_CORETSEIlil[8] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil_8[8] CFG4 D In - 1.229 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil_8[8] CFG4 Y Out 0.250 1.479 - CORETSEIlil_8[8] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil_12[8] CFG2 A In - 1.962 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil_12[8] CFG2 Y Out 0.076 2.038 - CORETSEIlil_12[8] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil[8] CFG4 C In - 2.521 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEOiO0.CORETSEIlil[8] CFG4 Y Out 0.182 2.703 - CORETSEi0ol Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEI0il5_0_a3 CFG3 B In - 3.325 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEI0il5_0_a3 CFG3 Y Out 0.129 3.454 - CORETSEI0il5 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol_5_i_0[0] CFG4 B In - 4.076 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol_5_i_0[0] CFG4 Y Out 0.143 4.219 - CORETSEl0ol_5_i_0[0] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol_RNO[0] CFG4 C In - 4.702 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol_RNO[0] CFG4 Y Out 0.194 4.896 - N_136_i_0 Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEIiO0.CORETSEl0ol[0] SLE D In - 5.034 - ========================================================================================================================================= Total path delay (propagation time + setup) of 5.256 is 1.433(27.3%) logic and 3.823(72.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_0/GL1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] FCCC_0/GL1 SLE Q CORETSEo1li[0] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[1] FCCC_0/GL1 SLE Q CORETSEo1li[1] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[2] FCCC_0/GL1 SLE Q CORETSEo1li[2] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[3] FCCC_0/GL1 SLE Q CORETSEo1li[3] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[4] FCCC_0/GL1 SLE Q CORETSEo1li[4] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[5] FCCC_0/GL1 SLE Q CORETSEo1li[5] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[6] FCCC_0/GL1 SLE Q CORETSEo1li[6] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[7] FCCC_0/GL1 SLE Q CORETSEo1li[7] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[8] FCCC_0/GL1 SLE Q CORETSEo1li[8] 0.076 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[9] FCCC_0/GL1 SLE Q CORETSEo1li[9] 0.076 7.106 ========================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] FCCC_0/GL1 SLE D CORETSEo1li[0] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[1] FCCC_0/GL1 SLE D CORETSEo1li[1] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[2] FCCC_0/GL1 SLE D CORETSEo1li[2] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[3] FCCC_0/GL1 SLE D CORETSEo1li[3] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[4] FCCC_0/GL1 SLE D CORETSEo1li[4] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[5] FCCC_0/GL1 SLE D CORETSEo1li[5] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[6] FCCC_0/GL1 SLE D CORETSEo1li[6] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[7] FCCC_0/GL1 SLE D CORETSEo1li[7] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[8] FCCC_0/GL1 SLE D CORETSEo1li[8] 7.778 7.106 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[9] FCCC_0/GL1 SLE D CORETSEo1li[9] 7.778 7.106 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 0.672 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.106 Number of logic level(s): 0 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] / D The start point is clocked by FCCC_0/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEo1li[0] SLE Q Out 0.076 0.076 - CORETSEo1li[0] Net - - 0.596 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSElIo0.CORETSEi1li[0] SLE D In - 0.672 - =============================================================================================================================================== Total path delay (propagation time + setup) of 0.894 is 0.298(33.3%) logic and 0.596(66.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[3] 0.094 -1.282 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[6] 0.094 -1.254 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[2] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[2] 0.094 -1.148 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[4] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[4] 0.094 -1.083 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1[4] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1[4] 0.094 -0.841 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEolII.CORETSEoiOI_fast[13] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEoiOI_fast[13] 0.076 -0.819 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEolII.CORETSEilOI[12] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEilOI[12] 0.094 -0.816 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEl110_fast[1] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEI_fast[1] 0.076 -0.808 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEO1O1[3] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEO1O1[3] 0.094 -0.799 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[5] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE Q CORETSEIoO1_fast[5] 0.094 -0.773 ================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEl0oi 3.778 -1.282 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEIi0i Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEOo0i 3.778 -1.167 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEOlo1 Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_339_i_0 3.778 -1.150 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIo1 Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_334_i_0 3.778 -1.150 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEiIii Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEoIii 3.778 -1.071 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSElo0i Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D CORETSEI10i 3.778 -1.030 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.CORETSEio0I[2] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_523_i_0_rep1 3.778 -0.819 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.CORETSEio0I[5] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_344_i_0_rep1 3.778 -0.819 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.CORETSEio0I[6] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_291_i_0_rep1 3.778 -0.819 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEIlII.CORETSEio0I[7] Igloo2_1000BaseT_sb_0/CCC_0/GL0 SLE D N_529_i_0_rep1 3.778 -0.819 ============================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.060 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.282 Number of logic level(s): 8 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] SLE Q Out 0.094 0.094 - CORETSEIoO1_fast[3] Net - - 0.708 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 A In - 0.802 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 Y Out 0.087 0.889 - g0_3_1 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 C In - 1.511 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 Y Out 0.177 1.688 - un22_CORETSEoO1i_5 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_5_i CFG2 A In - 2.277 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_5_i CFG2 Y Out 0.087 2.365 - un22_CORETSEoO1i_axb_5_i_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_5 ARI1 C In - 2.848 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_5 ARI1 FCO Out 0.228 3.076 - un22_CORETSEoO1i_cry_5 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCI In - 3.076 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCO Out 0.014 3.090 - un22_CORETSEoO1i_cry_6 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCI In - 3.090 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCO Out 0.014 3.104 - un22_CORETSEoO1i_cry_7 Net - - 0.882 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 D In - 3.987 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 Y Out 0.276 4.263 - CORETSEI0oi_i_0_a2_ns_1 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 C In - 4.746 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 Y Out 0.177 4.923 - CORETSEl0oi Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 SLE D In - 5.060 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.282 is 1.376(26.0%) logic and 3.907(74.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.046 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.268 Number of logic level(s): 7 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] SLE Q Out 0.094 0.094 - CORETSEIoO1_fast[3] Net - - 0.708 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 A In - 0.802 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 Y Out 0.087 0.889 - g0_3_1 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 C In - 1.511 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 Y Out 0.177 1.688 - un22_CORETSEoO1i_5 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_6_i CFG2 A In - 2.277 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_6_i CFG2 Y Out 0.087 2.365 - un22_CORETSEoO1i_axb_6_i_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 C In - 2.848 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCO Out 0.228 3.076 - un22_CORETSEoO1i_cry_6 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCI In - 3.076 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCO Out 0.014 3.090 - un22_CORETSEoO1i_cry_7 Net - - 0.882 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 D In - 3.973 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 Y Out 0.276 4.248 - CORETSEI0oi_i_0_a2_ns_1 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 C In - 4.732 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 Y Out 0.177 4.908 - CORETSEl0oi Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 SLE D In - 5.046 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.268 is 1.362(25.8%) logic and 3.907(74.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.254 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[3] SLE Q Out 0.094 0.094 - CORETSEIoO1_fast[3] Net - - 0.708 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 A In - 0.802 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 Y Out 0.087 0.889 - g0_3_1 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 C In - 1.511 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 Y Out 0.177 1.688 - un22_CORETSEoO1i_5 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_7_i CFG2 A In - 2.277 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_7_i CFG2 Y Out 0.087 2.365 - un22_CORETSEoO1i_axb_7_i_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 C In - 2.848 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCO Out 0.228 3.076 - un22_CORETSEoO1i_cry_7 Net - - 0.882 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 D In - 3.958 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 Y Out 0.276 4.234 - CORETSEI0oi_i_0_a2_ns_1 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 C In - 4.718 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 Y Out 0.177 4.894 - CORETSEl0oi Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 SLE D In - 5.032 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.254 is 1.347(25.6%) logic and 3.907(74.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.254 Number of logic level(s): 8 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] SLE Q Out 0.094 0.094 - CORETSEIoO1_fast[6] Net - - 0.637 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 B In - 0.732 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 Y Out 0.129 0.861 - g0_3_1 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 C In - 1.482 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 Y Out 0.177 1.659 - un22_CORETSEoO1i_5 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_5_i CFG2 A In - 2.249 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_5_i CFG2 Y Out 0.087 2.336 - un22_CORETSEoO1i_axb_5_i_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_5 ARI1 C In - 2.820 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_5 ARI1 FCO Out 0.228 3.047 - un22_CORETSEoO1i_cry_5 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCI In - 3.047 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCO Out 0.014 3.062 - un22_CORETSEoO1i_cry_6 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCI In - 3.062 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCO Out 0.014 3.076 - un22_CORETSEoO1i_cry_7 Net - - 0.882 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 D In - 3.958 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 Y Out 0.276 4.234 - CORETSEI0oi_i_0_a2_ns_1 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 C In - 4.717 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 Y Out 0.177 4.894 - CORETSEl0oi Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 SLE D In - 5.032 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.254 is 1.418(27.0%) logic and 3.836(73.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.018 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.240 Number of logic level(s): 7 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 / D The start point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEloI1.CORETSEIoO1_fast[6] SLE Q Out 0.094 0.094 - CORETSEIoO1_fast[6] Net - - 0.637 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 B In - 0.732 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3_1 CFG2 Y Out 0.129 0.861 - g0_3_1 Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 C In - 1.482 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.g0_3 CFG4 Y Out 0.177 1.659 - un22_CORETSEoO1i_5 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_6_i CFG2 A In - 2.249 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_axb_6_i CFG2 Y Out 0.087 2.336 - un22_CORETSEoO1i_axb_6_i_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 C In - 2.820 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_6 ARI1 FCO Out 0.228 3.047 - un22_CORETSEoO1i_cry_6 Net - - 0.000 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCI In - 3.047 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.un22_CORETSEoO1i_cry_7 ARI1 FCO Out 0.014 3.062 - un22_CORETSEoO1i_cry_7 Net - - 0.882 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 D In - 3.944 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns_1_0 CFG4 Y Out 0.276 4.220 - CORETSEI0oi_i_0_a2_ns_1 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 C In - 4.703 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEI0oi_i_0_a2_ns CFG4 Y Out 0.177 4.880 - CORETSEl0oi Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEoil1.CORETSEoIo1 SLE D In - 5.018 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.240 is 1.404(26.8%) logic and 3.836(73.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.094 17.681 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[1] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.094 17.746 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[2] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 17.760 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[3] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.094 17.774 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[4] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.094 17.789 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[5] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.094 17.803 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[6] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.094 17.817 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[7] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[7] 0.094 17.831 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[8] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 17.845 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[9] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[9] 0.094 17.858 ======================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 17.681 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[11] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 17.695 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[10] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 17.709 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[9] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 17.724 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[8] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 17.738 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[7] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 17.752 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[6] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 17.766 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[5] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 17.780 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[4] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.778 17.794 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[3] Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[3] 19.778 17.809 ============================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 2.097 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.681 Number of logic level(s): 13 Starting point: Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] / D The start point is clocked by Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.094 0.094 - count_sdif0[0] Net - - 0.637 - 3 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_s_2071 ARI1 B In - 0.732 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_s_2071 ARI1 FCO Out 0.174 0.906 - count_sdif0_s_2071_FCO Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCI In - 0.906 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCO Out 0.014 0.920 - count_sdif0_cry[1] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCI In - 0.920 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCO Out 0.014 0.935 - count_sdif0_cry[2] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCI In - 0.935 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCO Out 0.014 0.949 - count_sdif0_cry[3] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCI In - 0.949 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCO Out 0.014 0.963 - count_sdif0_cry[4] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCI In - 0.963 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCO Out 0.014 0.977 - count_sdif0_cry[5] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCI In - 0.977 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCO Out 0.014 0.991 - count_sdif0_cry[6] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCI In - 0.991 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCO Out 0.014 1.006 - count_sdif0_cry[7] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCI In - 1.006 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCO Out 0.014 1.020 - count_sdif0_cry[8] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCI In - 1.020 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCO Out 0.014 1.034 - count_sdif0_cry[9] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCI In - 1.034 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCO Out 0.014 1.048 - count_sdif0_cry[10] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCI In - 1.048 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCO Out 0.014 1.062 - count_sdif0_cry[11] Net - - 0.000 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_s[12] ARI1 FCI In - 1.062 - Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0_s[12] ARI1 S Out 0.063 1.126 - count_sdif0_s[12] Net - - 0.971 - 1 Igloo2_1000BaseT_sb_0.CORERESETP_0.count_sdif0[12] SLE D In - 2.097 - ===================================================================================================================== Total path delay (propagation time + setup) of 2.319 is 0.710(30.6%) logic and 1.609(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q psel 0.094 16.544 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.state[1] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 17.990 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.SDIF0_PENABLE Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PENABLE 0.094 18.288 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.state[0] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.745 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[14] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[14] 0.094 18.765 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[15] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[15] 0.076 18.859 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[0] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[0] 5.118 32.781 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[1] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[1] 5.053 32.846 SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PRDATA[7] Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PRDATA[7] 5.613 32.989 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.paddr[4] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE Q Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PADDR[4] 0.094 33.316 ================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SERDESIF_0 APB_PSEL Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PSELx 18.487 16.544 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.853 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE D prdata[1] 19.778 16.853 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[0] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[1] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[2] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[3] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[4] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[5] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.soft_reset_reg[6] Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB SLE EN soft_reset_reg6 19.706 17.016 ================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 1.513 + Clock delay at ending point: 0.000 (ideal) = Required time: 18.487 - Propagation time: 1.943 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 16.544 Number of logic level(s): 1 Starting point: Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- Igloo2_1000BaseT_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.708 - 5 Igloo2_1000BaseT_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 B In - 0.802 - Igloo2_1000BaseT_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 Y Out 0.143 0.945 - Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PSELx Net - - 0.998 - 36 SERDES_IF_0.SERDESIF_INST SERDESIF_0 APB_PSEL In - 1.943 - ================================================================================================================================ Total path delay (propagation time + setup) of 3.456 is 1.750(50.6%) logic and 1.706(49.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSEIOOI[28] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEIOOI[28] 0.094 -1.311 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[11] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[11] 0.094 -1.204 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[8] 0.094 -1.193 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[4] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[4] 0.094 -1.193 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[10] 0.094 -1.181 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[13] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[13] 0.094 -1.127 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[10] 0.094 -1.126 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[7] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[7] 0.076 -1.113 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[15] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSElio0[15] 0.094 -1.067 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[6] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE Q CORETSEo0o[6] 0.076 -1.057 ========================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.STD_ACCUM_ZERO SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D tmp_4[0] 3.778 -1.311 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[11] 3.778 -1.204 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[38] 3.848 -1.193 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[41] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[41] 3.848 -1.193 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[12] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[12] 3.778 -1.159 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[10] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[10] 3.778 -1.139 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[6] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[6] 3.778 -1.000 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[42] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[42] 3.778 -0.426 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[43] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[43] 3.778 -0.350 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[5] SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] SLE D CORETSEii0o[5] 3.778 -0.311 ============================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.089 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.311 Number of logic level(s): 7 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSEIOOI[28] / Q Ending point: COREABC_0.STD_ACCUM_ZERO / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEooo1I.CORETSEiIII.CORETSEIOOI[28] SLE Q Out 0.094 0.094 - CORETSEIOOI[28] Net - - 0.509 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEiIi[28] CFG4 D In - 0.603 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEiIi[28] CFG4 Y Out 0.250 0.853 - CORETSEiIi[28] Net - - 0.548 - 2 COREABC_0.ACCUM_NEXT_bm[28] CFG4 B In - 1.401 - COREABC_0.ACCUM_NEXT_bm[28] CFG4 Y Out 0.143 1.544 - ACCUM_NEXT_bm[28] Net - - 0.483 - 1 COREABC_0.ACCUM_NEXT_ns[28] CFG3 C In - 2.027 - COREABC_0.ACCUM_NEXT_ns[28] CFG3 Y Out 0.182 2.209 - ACCUM_NEXT[28] Net - - 0.548 - 2 COREABC_0.to_logic_2\.tmp_4_13[0] CFG4 B In - 2.757 - COREABC_0.to_logic_2\.tmp_4_13[0] CFG4 Y Out 0.129 2.886 - tmp_4_13[0] Net - - 0.483 - 1 COREABC_0.to_logic_2\.tmp_4_26_1[0] CFG4 B In - 3.369 - COREABC_0.to_logic_2\.tmp_4_26_1[0] CFG4 Y Out 0.143 3.513 - tmp_4_26_1[0] Net - - 0.483 - 1 COREABC_0.to_logic_2\.tmp_4_26[0] CFG4 D In - 3.996 - COREABC_0.to_logic_2\.tmp_4_26[0] CFG4 Y Out 0.236 4.232 - tmp_4_26[0] Net - - 0.483 - 1 COREABC_0.to_logic_2\.tmp_4[0] CFG4 D In - 4.715 - COREABC_0.to_logic_2\.tmp_4[0] CFG4 Y Out 0.236 4.951 - tmp_4[0] Net - - 0.138 - 1 COREABC_0.STD_ACCUM_ZERO SLE D In - 5.089 - ===================================================================================================================================== Total path delay (propagation time + setup) of 5.311 is 1.636(30.8%) logic and 3.675(69.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 4.982 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.204 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[11] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEIil1.CORETSElio0[11] SLE Q Out 0.094 0.094 - CORETSElio0[11] Net - - 0.637 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_0_0[11] CFG4 D In - 0.732 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_0_0[11] CFG4 Y Out 0.250 0.982 - CORETSEOO1o[11] Net - - 0.622 - 4 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un44_CORETSEii0olto15_2 CFG4 C In - 1.604 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un44_CORETSEii0olto15_2 CFG4 Y Out 0.182 1.786 - un68_CORETSEii0o_1 Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un68_CORETSEii0olto15_4 CFG2 A In - 2.376 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un68_CORETSEii0olto15_4 CFG2 Y Out 0.076 2.451 - un68_CORETSEii0o_4 Net - - 0.648 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 B In - 3.099 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o[1] CFG4 Y Out 0.129 3.228 - CORETSEii0o[1] Net - - 0.590 - 3 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_m2_0_a2 CFG4 D In - 3.818 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_m2_0_a2 CFG4 Y Out 0.284 4.102 - CORETSEii0o_N_5_mux_0 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_0_a2[11] CFG4 C In - 4.650 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_0_a2[11] CFG4 Y Out 0.194 4.844 - CORETSEii0o[11] Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[11] SLE D In - 4.982 - =========================================================================================================================================================== Total path delay (propagation time + setup) of 5.204 is 1.431(27.5%) logic and 3.773(72.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.152 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.848 - Propagation time: 5.041 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.193 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] SLE Q Out 0.094 0.094 - CORETSEo0o[8] Net - - 0.735 - 6 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[8] CFG4 D In - 0.830 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[8] CFG4 Y Out 0.250 1.080 - CORETSEOO1o[8] Net - - 0.689 - 7 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_RNI633U1[5] CFG4 D In - 1.769 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_RNI633U1[5] CFG4 Y Out 0.250 2.019 - un91_CORETSEii0olto4_0_2 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 C In - 2.567 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 Y Out 0.182 2.749 - un484_CORETSEii0olt10 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 D In - 3.232 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 Y Out 0.250 3.482 - un484_CORETSEii0olt15 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 B In - 4.030 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 Y Out 0.143 4.173 - CORETSEii0o_0_a3_0_a2_1_d[38] Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[38] CFG4 C In - 4.721 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[38] CFG4 Y Out 0.182 4.903 - CORETSEii0o[38] Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] SLE D In - 5.041 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 5.193 is 1.504(29.0%) logic and 3.689(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.152 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.848 - Propagation time: 5.041 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.193 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[41] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[8] SLE Q Out 0.094 0.094 - CORETSEo0o[8] Net - - 0.735 - 6 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[8] CFG4 D In - 0.830 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[8] CFG4 Y Out 0.250 1.080 - CORETSEOO1o[8] Net - - 0.689 - 7 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_RNI633U1[5] CFG4 D In - 1.769 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o_RNI633U1[5] CFG4 Y Out 0.250 2.019 - un91_CORETSEii0olto4_0_2 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 C In - 2.567 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 Y Out 0.182 2.749 - un484_CORETSEii0olt10 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 D In - 3.232 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 Y Out 0.250 3.482 - un484_CORETSEii0olt15 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 B In - 4.030 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 Y Out 0.143 4.173 - CORETSEii0o_0_a3_0_a2_1_d[38] Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[41] CFG4 C In - 4.721 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[41] CFG4 Y Out 0.182 4.903 - CORETSEii0o[41] Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[41] SLE D In - 5.041 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 5.193 is 1.504(29.0%) logic and 3.689(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.152 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.848 - Propagation time: 5.041 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.193 Number of logic level(s): 6 Starting point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[4] / Q Ending point: CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] / D The start point is clocked by SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] [rising] on pin CLK The end point is clocked by Igloo2_1000BaseT_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEl0I1.CORETSEiil1.CORETSEo0o[4] SLE Q Out 0.094 0.094 - CORETSEo0o[4] Net - - 0.708 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[4] CFG4 D In - 0.802 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEOO1o[4] CFG4 Y Out 0.250 1.053 - CORETSEOO1o[4] Net - - 0.648 - 5 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un91_CORETSEii0olto4_d CFG4 D In - 1.700 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un91_CORETSEii0olto4_d CFG4 Y Out 0.250 1.950 - un91_CORETSEii0olto4_d Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 D In - 2.498 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto9 CFG4 Y Out 0.250 2.748 - un484_CORETSEii0olt10 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 D In - 3.232 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.un484_CORETSEii0olto10 CFG4 Y Out 0.250 3.482 - un484_CORETSEii0olt15 Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 B In - 4.030 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2_1_d[38] CFG3 Y Out 0.143 4.173 - CORETSEii0o_0_a3_0_a2_1_d[38] Net - - 0.548 - 2 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[38] CFG4 C In - 4.721 - CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEii0o_0_a3_0_a2[38] CFG4 Y Out 0.182 4.903 - CORETSEii0o[38] Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I\.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[38] SLE D In - 5.041 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 5.193 is 1.572(30.3%) logic and 3.621(69.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: pemgt|CORETSEOo1_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[1] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[1] 0.094 3.705 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[3] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[3] 0.094 3.780 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEl1IOI[4] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEl1IOI[4] 0.094 3.864 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[1] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[1] 0.094 3.962 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[3] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[3] 0.094 4.154 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[4] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[4] 0.094 4.221 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[0] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[0] 0.094 4.393 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[2] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[2] 0.094 4.432 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[4] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEllIOI[4] 0.094 4.484 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi0IOI[2] pemgt|CORETSEOo1_inferred_clock SLE Q CORETSEi0IOI[2] 0.094 4.563 ================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[13] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[13] 9.778 3.705 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[14] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[14] 9.778 3.705 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[2] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[2] 9.778 3.798 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[4] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[4] 9.778 3.798 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[5] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[5] 9.778 3.798 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[9] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[9] 9.778 3.798 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[15] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[15] 9.778 3.798 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[3] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[3] 9.778 3.858 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[7] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[7] 9.778 4.065 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[6] pemgt|CORETSEOo1_inferred_clock SLE D CORETSEiiIOI[6] 9.778 4.098 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 6.073 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.705 Number of logic level(s): 7 Starting point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[1] / Q Ending point: CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[14] / D The start point is clocked by pemgt|CORETSEOo1_inferred_clock [rising] on pin CLK The end point is clocked by pemgt|CORETSEOo1_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEllIOI[1] SLE Q Out 0.094 0.094 - CORETSEllIOI[1] Net - - 0.876 - 14 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi11_0_a2_3_0_a2_0 CFG2 A In - 0.970 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi11_0_a2_3_0_a2_0 CFG2 Y Out 0.087 1.057 - CORETSEi11_0_a2_3_0_a2_0 Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi11_0_a2_3_0_a2 CFG4 D In - 1.540 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEi11_0_a2_3_0_a2 CFG4 Y Out 0.236 1.776 - N_527 Net - - 0.648 - 5 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEollOI_m1_e_2_RNIT8TC1 CFG4 D In - 2.424 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEollOI_m1_e_2_RNIT8TC1 CFG4 Y Out 0.236 2.660 - N_1140 Net - - 0.761 - 12 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_a2_0[7] CFG3 A In - 3.421 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_a2_0[7] CFG3 Y Out 0.067 3.488 - N_539 Net - - 0.772 - 13 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_2[14] CFG4 D In - 4.260 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_2[14] CFG4 Y Out 0.236 4.496 - CORETSEiiIOI_0_0_2[14] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_4[14] CFG4 D In - 4.979 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0_4[14] CFG4 Y Out 0.236 5.215 - CORETSEiiIOI_0_0_4[14] Net - - 0.483 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0[14] CFG4 D In - 5.699 - CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEiiIOI_0_0[14] CFG4 Y Out 0.236 5.935 - CORETSEiiIOI[14] Net - - 0.138 - 1 CORETSE_0.CORETSEO.CORETSEio0\.CORETSEOi0.CORETSEi0O0.CORETSEOlo0.CORETSEOOlOI[14] SLE D In - 6.073 - ============================================================================================================================================================= Total path delay (propagation time + setup) of 6.295 is 1.650(26.2%) logic and 4.644(73.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] @W:MT447 : synthesis.fdc(19) | Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(21) | Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(22) | Timing constraint (to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(24) | Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(25) | Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(26) | Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(27) | Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(28) | Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_RXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(29) | Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(30) | Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:05s; Memory used current: 275MB peak: 328MB) Finished timing report (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:05s; Memory used current: 275MB peak: 328MB) --------------------------------------- Resource Usage Report for Igloo2_1000BaseT Mapping to part: m2gl010tfbga484-1 Cell usage: AND2 1 use CCC 2 uses CLKINT 25 uses MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_0 1 use SYSRESET 1 use CFG1 23 uses CFG2 1223 uses CFG3 1752 uses CFG4 5193 uses Carry primitives used for arithmetic functions: ARI1 1438 uses Sequential Cells: SLE 5146 uses DSP Blocks: 0 I/O ports: 23 I/O primitives: 5 BIBUF 1 use INBUF 1 use INBUF_DIFF 1 use OUTBUF 2 uses Global Clock Buffers: 25 RAM/ROM usage summary Block Rams (RAM1K18) : 16 Block Rams (RAM64x18) : 8 Total LUTs: 9629 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 288; LUTs = 288; RAM1K18 Interface Logic : SLEs = 576; LUTs = 576; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 5146 + 288 + 576 + 0 = 6010; Total number of LUTs after P&R: 9629 + 288 + 576 + 0 = 10493; Mapper successful! At Mapper Exit (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:06s; Memory used current: 81MB peak: 328MB) Process took 0h:01m:06s realtime, 0h:01m:06s cputime # Sun Nov 27 15:54:33 2016 ###########################################################]