@W: BN231 |Constraints on tristate nets currently not supported
@W: MO171 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance COREABC_0.UROM\.INSTR_MUXC reduced to a combinational gate by constant propagation 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v":157:0:157:9|Tristate driver CORETSEIl0 on net CORETSEIl0 has its enable tied to GND (module tsmac_top_Z5) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v":155:0:155:9|Tristate driver CORETSEOl0 on net CORETSEOl0 has its enable tied to GND (module tsmac_top_Z5) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v":153:0:153:9|Tristate driver CORETSEiI0 on net CORETSEiI0 has its enable tied to GND (module tsmac_top_Z5) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v":151:0:151:9|Tristate driver CORETSEoI0 on net CORETSEoI0 has its enable tied to GND (module tsmac_top_Z5) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tsmac_top.v":149:0:149:9|Tristate driver CORETSElI0 on net CORETSElI0 has its enable tied to GND (module tsmac_top_Z5) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":82:0:82:3|Tristate driver TXER on net TXER has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":80:0:80:3|Tristate driver TXEN on net TXEN has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_2 on net TXD_2 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_3 on net TXD_3 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_4 on net TXD_4 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_5 on net TXD_5 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_6 on net TXD_6 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_7 on net TXD_7 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\coretse_top.v":78:0:78:2|Tristate driver TXD_8 on net TXD_8 has its enable tied to GND (module CoreTSE_TOP_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[0] on net TXD[0] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[1] on net TXD[1] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[2] on net TXD[2] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[3] on net TXD[3] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[4] on net TXD[4] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[5] on net TXD[5] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[6] on net TXD[6] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXD_t[7] on net TXD[7] has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXEN_t on net TXEN has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :|Tristate driver TXER_t on net TXER has its enable tied to GND (module Igloo2_1000BaseT_CORETSE_0_CORETSE_19s_1s_1s_1s_1s_18s_11s) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\fabosc_0\igloo2_1000baset_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\fabosc_0\igloo2_1000baset_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\fabosc_0\igloo2_1000baset_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\fabosc_0\igloo2_1000baset_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) 
@W: MO111 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\fabosc_0\igloo2_1000baset_sb_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module Igloo2_1000BaseT_sb_FABOSC_0_OSC) 
@W: MO171 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v":406:0:406:5|Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEli0o reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q1
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif3_spll_lock_q2,  because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif0_spll_lock_q2
@W: MT462 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\serdes_if_0\igloo2_1000baset_serdes_if_0_serdes_if.v":98:15:98:32|Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MO129 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\coreabc_0\rtl\vlog\core\coreabc.v":484:12:484:17|Sequential instance COREABC_0.UROM.INSTR_SLOT[0] reduced to a combinational gate by constant propagation
@W: FX107 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\coreabc_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\coreabc_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\rx4096x36.v":131:0:131:5|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\tx2048x40.v":131:0:131:5|No read/write conflict check. Possible simulation mismatch!
@W: MO129 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[36] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Sequential instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[37] reduced to a combinational gate by constant propagation
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[25],  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[24]
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Removing instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[8],  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEIlI.CORETSEOOi1I.CORETSEOIi1I.CORETSEO00o.CORETSEIOlo[7]
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[30] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[29] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[28] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[27] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[26] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[25] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSEll1o[24] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance Igloo2_1000BaseT_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Register bit HSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing instance Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF_READY_int,  because it is equivalent to instance Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_state[6]
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v":159:0:159:5|Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEoOol,  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v":120:0:120:5|Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEii1l,  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEIOol
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v":172:0:172:5|Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEiOol,  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol
@W: BN132 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\actel\directcore\coretse\2.0.307\rtl\vlog\core_obfuscated\msgmii_clkrst.v":211:0:211:5|Removing instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSElOol,  because it is equivalent to instance CORETSE_0.CORETSEO.CORETSEio0.CORETSEOi0.CORETSEI0O0.CORETSEOOol
@W: MT462 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\serdes_if_0\igloo2_1000baset_serdes_if_0_serdes_if.v":98:15:98:32|Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset\serdes_if_0\igloo2_1000baset_serdes_if_0_serdes_if.v":98:15:98:32|Net SERDES_IF_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT246 :"d:\data\coretse _mssmac\dg0633_eth_loop_back _igloo2\dg0633_11.7_sp2 _eth_loop_back_igloo2\hardware\coretse_1000baset_demo\component\work\igloo2_1000baset_sb\ccc_0\igloo2_1000baset_sb_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock pemgt|CORETSEOo1_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_0.CORETSEO.CORETSEIlI.CORETSEioo1I.CORETSEo1I1.CORETSEOo1"
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":19:0:19:0|Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":21:0:21:0|Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":22:0:22:0|Timing constraint (to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":24:0:24:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":25:0:25:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":26:0:26:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":27:0:27:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":28:0:28:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_RXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":29:0:29:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":30:0:30:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":19:0:19:0|Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc Igloo2_1000BaseT_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.MSS_HPMS_READY_int Igloo2_1000BaseT_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":21:0:21:0|Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":22:0:22:0|Timing constraint (to [get_cells { Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Igloo2_1000BaseT_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":24:0:24:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":25:0:25:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":26:0:26:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":27:0:27:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":28:0:28:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_RXCLK[1] }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":29:0:29:0|Timing constraint (from [get_clocks { Igloo2_1000BaseT_sb_0.CCC_0.GL0 }] to [get_clocks { FCCC_0.GL1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":30:0:30:0|Timing constraint (from [get_clocks { SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1] }] to [get_clocks { FCCC_0.GL0 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT445 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":31:0:31:0|Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PWRITE Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PADDR[*] Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PWDATA[*] Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }]) (min delay -24.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT445 :"d:/data/coretse _mssmac/dg0633_eth_loop_back _igloo2/dg0633_11.7_sp2 _eth_loop_back_igloo2/hardware/coretse_1000baset_demo/designer/igloo2_1000baset/synthesis.fdc":32:0:32:0|Timing constraint (through [get_nets { Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Igloo2_1000BaseT_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Igloo2_1000BaseT_sb_0.CORECONFIGP_0.state[0] }]) (min delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
