Timing Multi Corner Report Min Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Fri Jun 4 10:21:09 2021

Design top
Family IGLOO2
Die M2GL010T
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
CLK0_PAD 20.000 50.000
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q N/A N/A
FCCC_0/GL0 16.000 62.500 0.295 BEST
FCCC_0/GL1 16.000 62.500 0.307 BEST
Igloo2_1000BaseT_sb_0/CCC_0/GL0 20.000 50.000 0.289 BEST
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 0.301 BEST
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 40.000 25.000 0.150 BEST
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 8.000 125.000
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 8.000 125.000 0.295 BEST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain CLK0_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin Igloo2_1000BaseT_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD

SET Register to Register

No Path

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Removal

No Path

SET Asynchronous to Register

No Path

Clock Domain CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEliIOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoOI0:D 0.325 2.170 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEi1IOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEi1IOI:D 0.322 2.182 0.000 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:D 0.335 2.184 0.000 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[3]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[3]:D 0.335 2.184 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEi0Oo:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEi0Oo:D 0.335 2.188 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEliIOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoOI0:D
data arrival time 2.170
data required time - N/C
slack N/C
Data arrival time calculation
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q 0.000 0.000
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q Clock source + 0.000 0.000 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEOo1 + 1.021 1.021 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:YSn cell ADLIB:GB + 0.147 1.168 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_YNn_GSouth + 0.188 1.356 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.168 1.524 8 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEliIOI:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0_rgbl_net_1 + 0.321 1.845 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEliIOI:Q cell ADLIB:SLE + 0.058 1.903 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoOI0:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEliIOI + 0.267 2.170 r
data arrival time 2.170
Data required time calculation
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q N/C N/C
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q Clock source + 0.000 N/C r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEOo1 + 1.021 N/C f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:YSn cell ADLIB:GB + 0.147 N/C 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_YNn_GSouth + 0.188 N/C f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.168 N/C 8 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoOI0:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB0_rgbl_net_1 + 0.339 N/C r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoOI0:D Library hold time ADLIB:SLE + 0.000 N/C
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

No Path

Clock Domain FCCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl0li:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo0li:D 0.305 0.295 3.612 3.317 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo1O0[11]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEo1ol[11]:D 0.317 0.301 3.599 3.298 0.000 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[20]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[4]:D 0.322 0.305 3.610 3.305 0.000 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEIilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:D 0.316 0.306 3.586 3.280 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[15]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEoili[15]:D 0.316 0.306 3.595 3.289 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl0li:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo0li:D
data arrival time 3.612
data required time - 3.317
slack 0.295
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 2.791 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.168 2.959 70 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl0li:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 + 0.348 3.307 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl0li:Q cell ADLIB:SLE + 0.062 3.369 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo0li:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEl0li + 0.243 3.612 r
data arrival time 3.612
Data required time calculation
FCCC_0/GL0 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 2.791 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.168 2.959 70 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo0li:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 + 0.358 3.317 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo0li:D Library hold time ADLIB:SLE + 0.000 3.317
data required time 3.317
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOiol[0]:ALn 1.505 1.446 4.775 3.329 0.000 -0.059 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOOil[5]:ALn 1.505 1.446 4.775 3.329 0.000 -0.059 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOOil[0]:ALn 1.505 1.446 4.775 3.329 0.000 -0.059 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEIOil[5]:ALn 1.505 1.446 4.775 3.329 0.000 -0.059 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEIOil[3]:ALn 1.472 1.446 4.742 3.296 0.000 -0.026 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOiol[0]:ALn
data arrival time 4.775
data required time - 3.329
slack 1.446
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB3:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 2.791 f
FCCC_0/GL0_INST/U0_RGB1_RGB3:YL cell ADLIB:RGB + 0.168 2.959 57 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 + 0.311 3.270 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:Q cell ADLIB:SLE + 0.072 3.342 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoilOI:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSElilOI + 0.213 3.555 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoilOI:Y cell ADLIB:CFG2 + 0.067 3.622 9 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB1:An net CORETSE_0/CORETSEO/CORETSEoilOI + 0.623 4.245 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.168 4.413 70 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOiol[0]:ALn net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB1_rgbl_net_1 + 0.362 4.775 r
data arrival time 4.775
Data required time calculation
FCCC_0/GL0 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 2.791 f
FCCC_0/GL0_INST/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.168 2.959 70 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOiol[0]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 + 0.370 3.329 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEOiO0/CORETSEOiol[0]:ALn Library removal time ADLIB:SLE + 0.000 3.329
data required time 3.329
Operating Conditions BEST

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to FCCC_0/GL0

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[10]:D 4.541 1.256 4.541 3.285 0.000 BEST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[12]:D 4.816 1.531 4.816 3.285 0.000 BEST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[17]:D 4.904 1.628 4.904 3.276 0.000 BEST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[13]:D 4.992 1.701 4.992 3.291 0.000 BEST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[15]:D 5.079 1.790 5.079 3.289 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[10]:D
data arrival time 4.541
data required time - 3.285
slack 1.256
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[30] cell ADLIB:SERDESIF_IP + -0.153 -0.153 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[10]:B net SERDES_IF_0_EPCS_3_RX_DATA[0] + 0.516 0.363 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[10]:Y cell ADLIB:CFG3 + 0.135 0.498 2 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST5:A net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[10] + 0.788 1.286 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST5:Y cell ADLIB:CFG1D_TEST + 0.231 1.517 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST4:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net5 + 0.206 1.723 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST4:Y cell ADLIB:CFG1D_TEST + 0.231 1.954 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST3:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net4 + 0.131 2.085 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST3:Y cell ADLIB:CFG1D_TEST + 0.231 2.316 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST2:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net3 + 0.205 2.521 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.231 2.752 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST1:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net2 + 0.131 2.883 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.231 3.114 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST0:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net1 + 0.208 3.322 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.231 3.553 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net0 + 0.131 3.684 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.231 3.915 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[10]:D net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li[10]_CFG1D_TEST_net + 0.626 4.541 r
data arrival time 4.541
Data required time calculation
FCCC_0/GL0 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB6:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 2.791 f
FCCC_0/GL0_INST/U0_RGB1_RGB6:YL cell ADLIB:RGB + 0.168 2.959 28 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[10]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB6_rgbl_net_1 + 0.326 3.285 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[10]:D Library hold time ADLIB:SLE + 0.000 3.285
data required time 3.285
Operating Conditions BEST

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_0/GL0

No Path

SET FCCC_0/GL1 to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[3]:D 0.316 8.295 3.594 -4.701 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[9]:D 0.324 8.318 3.609 -4.709 0.000 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[7]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[7]:D 0.319 8.326 3.602 -4.724 0.000 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[8]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[8]:D 0.409 8.401 3.688 -4.713 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[1]:D 0.406 8.404 3.685 -4.719 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[3]:D
data arrival time 3.594
data required time - -4.701
slack 8.295
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.207 2.798 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.966 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:CLK net FCCC_0_GL1 + 0.312 3.278 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:Q cell ADLIB:SLE + 0.058 3.336 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[3]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEo1li[3] + 0.258 3.594 r
data arrival time 3.594
Data required time calculation
FCCC_0/GL0 Clock Constraint -8.000 -8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 -8.000 r
Clock generation + 2.330 -5.670
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 -5.531 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 -5.421 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB4:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.212 -5.209 f
FCCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.168 -5.041 18 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[3]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.340 -4.701 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[3]:D Library hold time ADLIB:SLE + 0.000 -4.701
data required time -4.701
Operating Conditions BEST

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to FCCC_0/GL0

No Path

Clock Domain FCCC_0/GL1

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D 0.323 0.307 3.601 3.294 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D
data arrival time 3.601
data required time - 3.294
slack 0.307
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.207 2.798 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.966 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK net FCCC_0_GL1 + 0.312 3.278 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:Q cell ADLIB:SLE + 0.058 3.336 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSEoolOI + 0.265 3.601 r
data arrival time 3.601
Data required time calculation
FCCC_0/GL1 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.207 2.798 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.966 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK net FCCC_0_GL1 + 0.328 3.294 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D Library hold time ADLIB:SLE + 0.000 3.294
data required time 3.294
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:ALn 0.707 0.696 3.991 3.295 0.000 -0.011 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:ALn 0.706 0.702 3.990 3.288 0.000 -0.004 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[8]:ALn 1.188 1.184 4.472 3.288 0.000 -0.004 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[5]:ALn 1.188 1.184 4.472 3.288 0.000 -0.004 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:ALn 1.188 1.184 4.472 3.288 0.000 -0.004 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:ALn
data arrival time 3.991
data required time - 3.295
slack 0.696
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.207 2.798 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.966 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK net FCCC_0_GL1 + 0.318 3.284 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:Q cell ADLIB:SLE + 0.072 3.356 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEOilOI:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSEiolOI + 0.213 3.569 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEOilOI:Y cell ADLIB:CFG2 + 0.067 3.636 10 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:ALn net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEIOo0_i + 0.355 3.991 r
data arrival time 3.991
Data required time calculation
FCCC_0/GL1 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.207 2.798 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.966 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:CLK net FCCC_0_GL1 + 0.329 3.295 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:ALn Library removal time ADLIB:SLE + 0.000 3.295
data required time 3.295
Operating Conditions BEST

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to FCCC_0/GL1

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL1

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:D 4.816 1.528 4.816 3.288 0.000 BEST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[5]:D 4.883 1.595 4.883 3.288 0.000 BEST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[0]:D 4.890 1.595 4.890 3.295 0.000 BEST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[3]:D 4.991 1.703 4.991 3.288 0.000 BEST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[7]:D 5.057 1.764 5.057 3.293 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:D
data arrival time 4.816
data required time - 3.288
slack 1.528
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[32] cell ADLIB:SERDESIF_IP + -0.160 -0.160 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST5:A net SERDES_IF_0_EPCS_3_RX_DATA[2] + 0.751 0.591 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST5:Y cell ADLIB:CFG1D_TEST + 0.231 0.822 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST4:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net5 + 0.206 1.028 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST4:Y cell ADLIB:CFG1D_TEST + 0.231 1.259 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST3:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net4 + 0.129 1.388 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST3:Y cell ADLIB:CFG1D_TEST + 0.231 1.619 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST2:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net3 + 0.207 1.826 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.231 2.057 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST1:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net2 + 0.130 2.187 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.231 2.418 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST0:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net1 + 0.345 2.763 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.231 2.994 1 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net0 + 0.129 3.123 r
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.231 3.354 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[12]:B net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12]_CFG1D_TEST_net + 0.728 4.082 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[12]:Y cell ADLIB:CFG3 + 0.135 4.217 2 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[12] + 0.599 4.816 r
data arrival time 4.816
Data required time calculation
FCCC_0/GL1 Clock Constraint 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 2.345 2.345
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.136 2.481 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.110 2.591 4 f
FCCC_0/GL1_INST/U0_RGB1_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.206 2.797 f
FCCC_0/GL1_INST/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.168 2.965 3 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:CLK net FCCC_0/GL1_INST/U0_RGB1_RGB1_rgbl_net_1 + 0.323 3.288 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:D Library hold time ADLIB:SLE + 0.000 3.288
data required time 3.288
Operating Conditions BEST

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_0/GL1

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to FCCC_0/GL1

No Path

Clock Domain Igloo2_1000BaseT_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEiIOo:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOlOo:D 0.307 0.289 3.458 3.169 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEOloI:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEIloI:D 0.316 0.300 3.446 3.146 0.000 BEST
Path 3 COREABC_0/genblk2.RSTSYNC1:CLK COREABC_0/genblk2.RSTSYNC2:D 0.316 0.300 3.450 3.150 0.000 BEST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_state[0]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_state[1]:D 0.311 0.301 3.475 3.174 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEOlII/CORETSEIl0I:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEOlII/CORETSEOl0I:D 0.311 0.301 3.453 3.152 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEiIOo:CLK
To: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOlOo:D
data arrival time 3.458
data required time - 3.169
slack 0.289
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.218 2.218
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.132 2.350 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.110 2.460 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.186 2.646 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11:YR cell ADLIB:RGB + 0.168 2.814 78 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEiIOo:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11_rgbr_net_1 + 0.337 3.151 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEiIOo:Q cell ADLIB:SLE + 0.062 3.213 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOlOo:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEiIOo + 0.245 3.458 r
data arrival time 3.458
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 Clock Constraint 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.218 2.218
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.132 2.350 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.110 2.460 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.186 2.646 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11:YR cell ADLIB:RGB + 0.168 2.814 78 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOlOo:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB11_rgbr_net_1 + 0.355 3.169 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOlOo:D Library hold time ADLIB:SLE + 0.000 3.169
data required time 3.169
Operating Conditions BEST

SET External Hold

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) External Hold (ns) Operating Conditions
Path 1 PHY_MDIO CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D 3.403 3.403 0.000 -0.172 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PHY_MDIO
To: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D
data arrival time 3.403
data required time - N/C
slack N/C
Data arrival time calculation
PHY_MDIO 0.000 0.000 r
BIBUF_0/U0/U_IOPAD:PAD net PHY_MDIO + 0.000 0.000 r
BIBUF_0/U0/U_IOPAD:Y cell ADLIB:IOPAD_BI + 0.799 0.799 1 r
BIBUF_0/U0/U_IOINFF:A net BIBUF_0/U0/YIN1 + -0.016 0.783 r
BIBUF_0/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.041 0.824 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un17_CORETSEi11:D net BIBUF_0_Y + 1.171 1.995 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un17_CORETSEi11:Y cell ADLIB:CFG4 + 0.226 2.221 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0]:A net CORETSE_0/CORETSEO/un17_CORETSEi11 + 0.951 3.172 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0]:Y cell ADLIB:CFG4 + 0.181 3.353 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0] + 0.050 3.403 r
data arrival time 3.403
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 N/C N/C
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.287 N/C
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.137 N/C r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.113 N/C 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.190 N/C f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:YR cell ADLIB:RGB + 0.173 N/C 73 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13_rgbr_net_1 + 0.331 N/C r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D Library hold time ADLIB:SLE + 0.000 N/C
Operating Conditions BEST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIo1:CLK PHY_MDIO 3.410 6.556 6.556 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:CLK PHY_MDC 3.848 7.010 7.010 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSElo1:CLK PHY_MDIO 4.003 7.143 7.143 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIo1:CLK
To: PHY_MDIO
data arrival time 6.556
data required time - N/C
slack N/C
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.218 2.218
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.132 2.350 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.460 17 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.187 2.647 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:YR cell ADLIB:RGB + 0.168 2.815 47 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIo1:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16_rgbr_net_1 + 0.331 3.146 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIo1:Q cell ADLIB:SLE + 0.058 3.204 8 r
BIBUF_0/U0/U_IOOUTFF:A net CORETSE_0_MDO + 1.575 4.779 r
BIBUF_0/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.124 4.903 1 r
BIBUF_0/U0/U_IOPAD:D net BIBUF_0/U0/DOUT + 0.054 4.957 r
BIBUF_0/U0/U_IOPAD:PAD cell ADLIB:IOPAD_BI + 1.599 6.556 1 r
PHY_MDIO net PHY_MDIO + 0.000 6.556 r
data arrival time 6.556
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 N/C N/C
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.218 N/C
PHY_MDIO N/C r
Operating Conditions BEST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_state[0]:ALn 0.540 0.525 3.678 3.153 0.000 -0.015 BEST
Path 2 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0_enable:ALn 0.540 0.525 3.678 3.153 0.000 -0.015 BEST
Path 3 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core_clk_base:ALn 0.557 0.528 3.701 3.173 0.000 -0.029 BEST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core_q1:ALn 0.557 0.529 3.701 3.172 0.000 -0.028 BEST
Path 5 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/ddr_settled_clk_base:ALn 0.557 0.529 3.701 3.172 0.000 -0.028 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:CLK
To: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_state[0]:ALn
data arrival time 3.678
data required time - 3.153
slack 0.525
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.218 2.218
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.132 2.350 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.460 17 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.195 2.655 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:YR cell ADLIB:RGB + 0.168 2.823 64 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24_rgbr_net_1 + 0.315 3.138 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:Q cell ADLIB:SLE + 0.058 3.196 4 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_state[0]:ALn net Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_clk_base + 0.482 3.678 r
data arrival time 3.678
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 Clock Constraint 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.218 2.218
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.132 2.350 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.460 17 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.194 2.654 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR cell ADLIB:RGB + 0.168 2.822 38 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_state[0]:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1 + 0.331 3.153 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_state[0]:ALn Library removal time ADLIB:SLE + 0.000 3.153
data required time 3.153
Operating Conditions BEST

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

Clock Domain Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:D 0.305 0.301 3.447 3.146 0.000 BEST
Path 2 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:D 0.319 0.302 3.457 3.155 0.000 BEST
Path 3 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0_enable_q1:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0_enable_rcosc:D 0.312 0.308 3.464 3.156 0.000 BEST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:D 0.397 0.387 3.549 3.162 0.000 BEST
Path 5 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_rcosc:D 0.396 0.393 3.549 3.156 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:CLK
To: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:D
data arrival time 3.447
data required time - 3.146
slack 0.301
Data arrival time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.160 1.160 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.102 1.262 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.042 2.304 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.147 2.451 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.206 2.657 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.168 2.825 2 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbr_net_1 + 0.317 3.142 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:Q cell ADLIB:SLE + 0.062 3.204 1 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:D net Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc_q1 + 0.243 3.447 r
data arrival time 3.447
Data required time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.160 1.160 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.102 1.262 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.042 2.304 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.147 2.451 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.206 2.657 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.168 2.825 2 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbr_net_1 + 0.321 3.146 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:D Library hold time ADLIB:SLE + 0.000 3.146
data required time 3.146
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:ALn 0.429 0.420 3.574 3.154 0.000 -0.009 BEST
Path 2 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[0]:ALn 0.429 0.420 3.574 3.154 0.000 -0.009 BEST
Path 3 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[12]:ALn 0.429 0.426 3.574 3.148 0.000 -0.003 BEST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[3]:ALn 0.556 0.523 3.701 3.178 0.000 -0.033 BEST
Path 5 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11]:ALn 0.556 0.523 3.701 3.178 0.000 -0.033 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
To: Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:ALn
data arrival time 3.574
data required time - 3.154
slack 0.420
Data arrival time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.160 1.160 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.102 1.262 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.042 2.304 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.147 2.451 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.206 2.657 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.168 2.825 18 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.320 3.145 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:Q cell ADLIB:SLE + 0.058 3.203 14 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:ALn net sdif0_areset_n_rcosc + 0.371 3.574 r
data arrival time 3.574
Data required time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.160 1.160 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.102 1.262 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.042 2.304 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.147 2.451 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.206 2.657 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.168 2.825 18 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.329 3.154 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:ALn Library removal time ADLIB:SLE + 0.000 3.154
data required time 3.154
Operating Conditions BEST

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

No Path

Clock Domain Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:D 1.948 0.150 1.948 1.798 0.000 BEST
Path 2 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[1]:D 0.373 0.354 2.161 1.807 0.000 BEST
Path 3 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[1]:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:D 0.367 0.366 2.164 1.798 0.000 BEST
Path 4 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/soft_reset_reg[15]:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:D 0.420 0.410 2.224 1.814 0.000 BEST
Path 5 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/INIT_DONE_q1:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/INIT_DONE_q2:D 0.412 0.417 2.209 1.792 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB
To: Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:D
data arrival time 1.948
data required time - 1.798
slack 0.150
Data arrival time calculation
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 0.000 0.000
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PSEL cell ADLIB:MSS_010_IP + 0.671 0.671 1 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/next_state5:B net Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_TMP_0_FIC_2_APB_MASTER_PSELx + 0.715 1.386 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/next_state5:Y cell ADLIB:CFG2 + 0.058 1.444 2 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state_ns_0_a3_0_a2[0]:B net Igloo2_1000BaseT_sb_0/CORECONFIGP_0/next_state5 + 0.314 1.758 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state_ns_0_a3_0_a2[0]:Y cell ADLIB:CFG2 + 0.139 1.897 1 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:D net Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state_ns[0] + 0.051 1.948 f
data arrival time 1.948
Data required time calculation
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Min Delay Constraint 0.000 0.000
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:An net CLK_CONFIG_APB + 0.933 0.933 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:YSn cell ADLIB:GB + 0.147 1.080 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_YNn_GSouth + 0.207 1.287 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.168 1.455 40 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0_rgbr_net_1 + 0.343 1.798 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/state[0]:D Library hold time ADLIB:SLE + 0.000 1.798
data required time 1.798
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Removal

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSEIOOl:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSElOOl:D 0.314 0.295 1.930 1.635 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEiO01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSElll0:D 0.307 0.297 1.920 1.623 0.000 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEOi[2]:CLK CORETSE_0/CORETSEO/CORETSEOi[3]:D 0.316 0.298 1.928 1.630 0.000 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEIil1/CORETSElOlII[4]:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEIil1/CORETSEiOlII[4]:D 0.316 0.298 1.923 1.625 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEIIi1I.CORETSElIi1I/CORETSEol1l:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEIIi1I.CORETSElIi1I/CORETSEil1l:D 0.316 0.299 1.916 1.617 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSEIOOl:CLK
To: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSElOOl:D
data arrival time 1.930
data required time - 1.635
slack 0.295
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 0.759 0.759 f
CLKINT_0:YNn cell ADLIB:GB + 0.147 0.906 15 f
CLKINT_0/U0_RGB1_RGB6:An net CLKINT_0/U0_YNn + 0.205 1.111 f
CLKINT_0/U0_RGB1_RGB6:YR cell ADLIB:RGB + 0.168 1.279 14 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSEIOOl:CLK net CLKINT_0/U0_RGB1_RGB6_rgbr_net_1 + 0.337 1.616 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSEIOOl:Q cell ADLIB:SLE + 0.062 1.678 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSElOOl:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSEIOOl + 0.252 1.930 r
data arrival time 1.930
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 0.759 0.759 f
CLKINT_0:YNn cell ADLIB:GB + 0.147 0.906 15 f
CLKINT_0/U0_RGB1_RGB6:An net CLKINT_0/U0_YNn + 0.205 1.111 f
CLKINT_0/U0_RGB1_RGB6:YR cell ADLIB:RGB + 0.168 1.279 14 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSElOOl:CLK net CLKINT_0/U0_RGB1_RGB6_rgbr_net_1 + 0.356 1.635 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEllII/CORETSElOOl:D Library hold time ADLIB:SLE + 0.000 1.635
data required time 1.635
Operating Conditions BEST

SET External Hold

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:ALn 0.734 0.707 2.340 1.633 0.000 -0.027 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEo1l0:ALn 0.734 0.707 2.340 1.633 0.000 -0.027 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEi1l0:ALn 0.734 0.707 2.340 1.633 0.000 -0.027 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEI100[1]:ALn 0.734 0.707 2.340 1.633 0.000 -0.027 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEI100[0]:ALn 0.734 0.713 2.340 1.627 0.000 -0.021 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:ALn
data arrival time 2.340
data required time - 1.633
slack 0.707
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 0.759 0.759 f
CLKINT_0:YSn cell ADLIB:GB + 0.147 0.906 17 f
CLKINT_0/U0_RGB1_RGB26:An net CLKINT_0/U0_YNn_GSouth + 0.212 1.118 f
CLKINT_0/U0_RGB1_RGB26:YL cell ADLIB:RGB + 0.168 1.286 34 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:CLK net CLKINT_0/U0_RGB1_RGB26_rgbl_net_1 + 0.320 1.606 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEli01:Q cell ADLIB:SLE + 0.072 1.678 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoi01:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSEli01 + 0.204 1.882 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoi01:Y cell ADLIB:CFG2 + 0.067 1.949 296 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:ALn net CORETSE_0/CORETSEO/CORETSEoi01 + 0.391 2.340 r
data arrival time 2.340
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 0.759 0.759 f
CLKINT_0:YSn cell ADLIB:GB + 0.147 0.906 17 f
CLKINT_0/U0_RGB1_RGB26:An net CLKINT_0/U0_YNn_GSouth + 0.212 1.118 f
CLKINT_0/U0_RGB1_RGB26:YL cell ADLIB:RGB + 0.168 1.286 34 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:CLK net CLKINT_0/U0_RGB1_RGB26_rgbl_net_1 + 0.347 1.633 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:ALn Library removal time ADLIB:SLE + 0.000 1.633
data required time 1.633
Operating Conditions BEST

SET External Removal

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

SET FCCC_0/GL0 to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEooIi:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEll01:D 0.325 1.954 3.592 1.638 0.000 BEST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[12]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo0I0[12]:D 0.381 2.041 3.655 1.614 0.000 BEST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[12]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEi0I0[12]:D 0.381 2.041 3.655 1.614 0.000 BEST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEOOI0:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEol01:D 0.413 2.062 3.689 1.627 0.000 BEST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[10]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEOo00[10]:D 0.402 2.082 3.688 1.606 0.000 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEooIi:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEll01:D
data arrival time 3.592
data required time - 1.638
slack 1.954
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.330 2.330
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.139 2.469 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.110 2.579 9 f
FCCC_0/GL0_INST/U0_RGB1:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.210 2.789 f
FCCC_0/GL0_INST/U0_RGB1:YL cell ADLIB:RGB + 0.168 2.957 48 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEooIi:CLK net FCCC_0_GL0 + 0.310 3.267 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEooIi:Q cell ADLIB:SLE + 0.058 3.325 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEll01:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiiO0 + 0.267 3.592 r
data arrival time 3.592
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 0.759 0.759 f
CLKINT_0:YSn cell ADLIB:GB + 0.147 0.906 17 f
CLKINT_0/U0_RGB1_RGB22:An net CLKINT_0/U0_YNn_GSouth + 0.210 1.116 f
CLKINT_0/U0_RGB1_RGB22:YL cell ADLIB:RGB + 0.168 1.284 40 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEll01:CLK net CLKINT_0/U0_RGB1_RGB22_rgbl_net_1 + 0.354 1.638 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEl010/CORETSEll01:D Library hold time ADLIB:SLE + 0.000 1.638
data required time 1.638
Operating Conditions BEST

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets