Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Fri Jun 4 10:21:06 2021

Design top
Family IGLOO2
Die M2GL010T
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
CLK0_PAD 20.000 50.000
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q N/A N/A
FCCC_0/GL0 16.000 62.500 3.628 WORST
FCCC_0/GL1 16.000 62.500 3.425 WORST
Igloo2_1000BaseT_sb_0/CCC_0/GL0 20.000 50.000 8.098 WORST
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 17.033 WORST
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 40.000 25.000 15.752 WORST
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 8.000 125.000
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 8.000 125.000 1.750 WORST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain CLK0_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin Igloo2_1000BaseT_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D 7.561 10.324 0.254 7.838 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[2]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D 7.310 10.065 0.254 7.579 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[1]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D 7.235 9.990 0.254 7.504 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[2]:D 7.181 9.944 0.254 7.441 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[3]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D 7.142 9.906 0.254 7.420 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D
data required time N/C
data arrival time - 10.324
slack N/C
Data arrival time calculation
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q 0.000 0.000
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q Clock source + 0.000 0.000 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEOo1 + 1.525 1.525 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:YSn cell ADLIB:GB + 0.221 1.746 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB2:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_YNn_GSouth + 0.285 2.031 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 2.282 12 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB2_rgbl_net_1 + 0.481 2.763 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEllIOI[4]:Q cell ADLIB:SLE + 0.110 2.873 9 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un6_CORETSEiiIOI_1:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEllIOI[4] + 1.068 3.941 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un6_CORETSEiiIOI_1:Y cell ADLIB:CFG2 + 0.147 4.088 2 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un6_CORETSEiiIOI:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/un6_CORETSEiiIOI_1 + 0.232 4.320 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un6_CORETSEiiIOI:Y cell ADLIB:CFG4 + 0.158 4.478 8 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEollOI:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/un6_CORETSEiiIOI + 1.347 5.825 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEollOI:Y cell ADLIB:CFG4 + 0.072 5.897 16 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0_3:A net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEollOI_net_4 + 1.563 7.460 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0_3:Y cell ADLIB:CFG4 + 0.234 7.694 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0_5:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEoiIOI_m2_e_0_3 + 0.941 8.635 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0_5:Y cell ADLIB:CFG4 + 0.164 8.799 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEoiIOI_m2_e_0_5 + 0.703 9.502 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEoiIOI_m2_e_0:Y cell ADLIB:CFG4 + 0.311 9.813 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEiiIOI[8]:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEoiIOI_N_5_mux_0 + 0.337 10.150 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEiiIOI[8]:Y cell ADLIB:CFG4 + 0.099 10.249 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEOlo0/CORETSEiiIOI[8] + 0.075 10.324 r
data arrival time 10.324
Data required time calculation
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q N/C N/C
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q Clock source + 0.000 N/C r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEOo1 + 1.525 N/C f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1911:YSn cell ADLIB:GB + 0.221 N/C 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB4:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_YNn_GSouth + 0.285 N/C f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.251 N/C 7 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1911/U0_RGB1_RGB4_rgbl_net_1 + 0.458 N/C r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/CORETSEOOlOI[8]:D Library setup time ADLIB:SLE - 0.254 N/C
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q

No Path

Clock Domain FCCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEIili:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:D 8.905 6.832 13.832 20.664 0.254 9.168 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:D 8.917 6.835 13.829 20.664 0.254 9.165 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo1O0[0]:D 8.784 6.937 13.713 20.650 0.254 9.063 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo1O0[3]:D 8.784 6.947 13.713 20.660 0.254 9.053 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEo1O0[1]:D 8.783 6.947 13.712 20.659 0.254 9.053 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEIili:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:D
data required time 20.664
data arrival time - 13.832
slack 6.832
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.478 3.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 3.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB5:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 4.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB5:YL cell ADLIB:RGB + 0.251 4.420 28 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEIili:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1 + 0.507 4.927 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEIili:Q cell ADLIB:SLE + 0.110 5.037 24 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEoi10[2]:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEIili + 0.669 5.706 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEoi10[2]:Y cell ADLIB:CFG3 + 0.099 5.805 48 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEI0I1I.m3:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoi10[2] + 0.984 6.789 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEI0I1I.m3:Y cell ADLIB:CFG3 + 0.225 7.014 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEO0I1I.m7:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEO1li/m3 + 0.226 7.240 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEO0I1I.m7:Y cell ADLIB:CFG4 + 0.164 7.404 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEO0I1I.i4_mux_i:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEO1li/i5_mux + 0.227 7.631 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEO1li/CORETSEO0I1I.i4_mux_i:Y cell ADLIB:CFG4 + 0.099 7.730 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEOIio_0_1[1]:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEO0I1I + 0.998 8.728 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEOIio_0_1[1]:Y cell ADLIB:CFG4 + 0.072 8.800 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEOIio_0[1]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEOIio_0_1[1] + 0.214 9.014 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEOIio_0[1]:Y cell ADLIB:CFG4 + 0.072 9.086 6 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/un1_CORETSElII1I:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEOIio[1] + 0.773 9.859 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/un1_CORETSElII1I:Y cell ADLIB:CFG4 + 0.074 9.933 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSElII1I_6:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEl1li/un1_CORETSElII1I + 0.338 10.271 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSElII1I_6:Y cell ADLIB:CFG4 + 0.072 10.343 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSElII1I:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEl1li/CORETSElII1I_6 + 0.879 11.222 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSElII1I:Y cell ADLIB:CFG3 + 0.072 11.294 11 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSEllI1I56:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEl1li/CORETSElII1I + 1.051 12.345 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSEllI1I56:Y cell ADLIB:CFG3 + 0.096 12.441 7 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSEllI1I56_RNIG1397:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEl1li/CORETSEllI1I56 + 0.987 13.428 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEl1li/CORETSEllI1I56_RNIG1397:Y cell ADLIB:CFG3 + 0.099 13.527 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEoIo0/CORETSEilI1I_0_0_iv_i[4] + 0.305 13.832 r
data arrival time 13.832
Data required time calculation
FCCC_0/GL0 Clock Constraint 16.000 16.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 16.000 r
Clock generation + 3.478 19.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 19.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 19.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB0:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.317 20.168 f
FCCC_0/GL0_INST/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.251 20.419 64 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 + 0.499 20.918 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEllio[28]:D Library setup time ADLIB:SLE - 0.254 20.664
data required time 20.664
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[18]:ALn 2.404 13.265 7.288 20.553 0.353 2.735 -0.022 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEOoli[7]:ALn 2.404 13.265 7.288 20.553 0.353 2.735 -0.022 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEOoli[19]:ALn 2.404 13.265 7.288 20.553 0.353 2.735 -0.022 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEOoli[18]:ALn 2.404 13.265 7.288 20.553 0.353 2.735 -0.022 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEOoli[16]:ALn 2.404 13.265 7.288 20.553 0.353 2.735 -0.022 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[18]:ALn
data required time 20.553
data arrival time - 7.288
slack 13.265
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.478 3.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 3.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB3:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 4.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB3:YL cell ADLIB:RGB + 0.251 4.420 57 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 + 0.464 4.884 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSElilOI:Q cell ADLIB:SLE + 0.108 4.992 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoilOI:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSElilOI + 0.320 5.312 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoilOI:Y cell ADLIB:CFG2 + 0.099 5.411 9 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB7:An net CORETSE_0/CORETSEO/CORETSEoilOI + 1.084 6.495 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB7:YL cell ADLIB:RGB + 0.251 6.746 28 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[18]:ALn net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1901/U0_RGB1_RGB7_rgbl_net_1 + 0.542 7.288 r
data arrival time 7.288
Data required time calculation
FCCC_0/GL0 Clock Constraint 16.000 16.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 16.000 r
Clock generation + 3.478 19.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 19.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 19.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB7:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 20.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB7:YL cell ADLIB:RGB + 0.251 20.420 28 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[18]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB7_rgbl_net_1 + 0.486 20.906 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSElO0i[18]:ALn Library recovery time ADLIB:SLE - 0.353 20.553
data required time 20.553
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to FCCC_0/GL0

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[16]:D 9.073 3.628 9.073 12.701 0.174 WORST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[14]:D 9.079 3.636 9.079 12.715 0.174 WORST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[19]:D 8.821 3.812 8.821 12.633 0.254 WORST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[18]:D 8.398 4.290 8.398 12.688 0.174 WORST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[11]:D 8.245 4.474 8.245 12.719 0.165 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[16]:D
data required time 12.701
data arrival time - 9.073
slack 3.628
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[36] cell ADLIB:SERDESIF_IP + 0.075 0.075 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST7:A net SERDES_IF_0_EPCS_3_RX_DATA[6] + 1.068 1.143 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST7:Y cell ADLIB:CFG1D_TEST + 0.372 1.515 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST6:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net7 + 0.303 1.818 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST6:Y cell ADLIB:CFG1D_TEST + 0.372 2.190 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST5:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net6 + 0.204 2.394 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST5:Y cell ADLIB:CFG1D_TEST + 0.372 2.766 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST4:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net5 + 1.221 3.987 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST4:Y cell ADLIB:CFG1D_TEST + 0.372 4.359 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST3:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net4 + 0.204 4.563 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST3:Y cell ADLIB:CFG1D_TEST + 0.372 4.935 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST2:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net3 + 0.302 5.237 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.372 5.609 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST1:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net2 + 0.303 5.912 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 6.284 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST0:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net1 + 0.204 6.488 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 6.860 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net0 + 0.226 7.086 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST:Y cell ADLIB:CFG1C_TEST + 0.209 7.295 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST_net + 0.203 7.498 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 7.870 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[16]:B net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net + 0.962 8.832 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[16]:Y cell ADLIB:CFG3 + 0.164 8.996 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[16]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16] + 0.077 9.073 f
data arrival time 9.073
Data required time calculation
FCCC_0/GL0 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 8.000 r
Clock generation + 3.478 11.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 11.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 11.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB7:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 12.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB7:YL cell ADLIB:RGB + 0.251 12.420 28 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[16]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB7_rgbl_net_1 + 0.455 12.875 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[16]:D Library setup time ADLIB:SLE - 0.174 12.701
data required time 12.701
Operating Conditions WORST

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_0/GL0

No Path

SET FCCC_0/GL1 to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[4]:D 1.033 6.713 5.930 12.643 0.254 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[6]:D 0.814 6.889 5.720 12.609 0.254 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[2]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[2]:D 0.793 6.930 5.692 12.622 0.254 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[0]:D 0.785 6.932 5.694 12.626 0.254 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[5]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[5]:D 0.780 6.958 5.679 12.637 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[4]:D
data required time 12.643
data arrival time - 5.930
slack 6.713
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 3.502 3.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 3.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 3.871 4 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.309 4.180 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 4.431 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:CLK net FCCC_0/GL1_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.466 4.897 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:Q cell ADLIB:SLE + 0.087 4.984 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[4]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEo1li[4] + 0.946 5.930 r
data arrival time 5.930
Data required time calculation
FCCC_0/GL0 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 8.000 r
Clock generation + 3.478 11.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 11.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 11.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB4:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 12.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.251 12.420 18 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[4]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.477 12.897 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li[4]:D Library setup time ADLIB:SLE - 0.254 12.643
data required time 12.643
Operating Conditions WORST

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to FCCC_0/GL0

No Path

Clock Domain FCCC_0/GL1

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D 0.482 15.259 5.382 20.641 0.254 0.741 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D
data required time 20.641
data arrival time - 5.382
slack 15.259
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 3.502 3.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 3.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 3.871 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.312 4.183 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.251 4.434 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:CLK net FCCC_0_GL1 + 0.466 4.900 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEoolOI:Q cell ADLIB:SLE + 0.087 4.987 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSEoolOI + 0.395 5.382 r
data arrival time 5.382
Data required time calculation
FCCC_0/GL1 Clock Constraint 16.000 16.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 16.000 r
Clock generation + 3.502 19.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 19.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 19.871 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.312 20.183 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.251 20.434 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK net FCCC_0_GL1 + 0.461 20.895 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:D Library setup time ADLIB:SLE - 0.254 20.641
data required time 20.641
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:ALn 2.211 13.412 7.120 20.532 0.353 2.588 0.024 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[0]:ALn 1.940 13.692 6.849 20.541 0.354 2.308 0.014 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:ALn 1.785 13.836 6.694 20.530 0.353 2.164 0.026 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[7]:ALn 1.785 13.844 6.694 20.538 0.353 2.156 0.018 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:ALn 1.785 13.845 6.694 20.539 0.353 2.155 0.017 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:ALn
data required time 20.532
data arrival time - 7.120
slack 13.412
Data arrival time calculation
FCCC_0/GL1 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 0.000 r
Clock generation + 3.502 3.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 3.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 3.871 4 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.312 4.183 f
FCCC_0/GL1_INST/U0_RGB1:YL cell ADLIB:RGB + 0.251 4.434 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:CLK net FCCC_0_GL1 + 0.475 4.909 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEiolOI:Q cell ADLIB:SLE + 0.108 5.017 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEOilOI:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEolo0_inst_1/CORETSEiolOI + 0.320 5.337 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEolo0/CORETSEOilOI:Y cell ADLIB:CFG2 + 0.099 5.436 10 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:ALn net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEIOo0_i + 1.684 7.120 r
data arrival time 7.120
Data required time calculation
FCCC_0/GL1 Clock Constraint 16.000 16.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 16.000 r
Clock generation + 3.502 19.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 19.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 19.871 4 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.309 20.180 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 20.431 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:CLK net FCCC_0/GL1_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.454 20.885 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:ALn Library recovery time ADLIB:SLE - 0.353 20.532
data required time 20.532
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to FCCC_0/GL1

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL1

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:D 9.293 3.425 9.293 12.718 0.174 WORST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[8]:D 9.063 3.648 9.063 12.711 0.174 WORST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[9]:D 8.821 3.821 8.821 12.642 0.254 WORST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[4]:D 8.230 4.479 8.230 12.709 0.174 WORST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[1]:D 8.088 4.543 8.088 12.631 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:D
data required time 12.718
data arrival time - 9.293
slack 3.425
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[36] cell ADLIB:SERDESIF_IP + 0.075 0.075 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST7:A net SERDES_IF_0_EPCS_3_RX_DATA[6] + 1.068 1.143 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST7:Y cell ADLIB:CFG1D_TEST + 0.372 1.515 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST6:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net7 + 0.303 1.818 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST6:Y cell ADLIB:CFG1D_TEST + 0.372 2.190 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST5:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net6 + 0.204 2.394 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST5:Y cell ADLIB:CFG1D_TEST + 0.372 2.766 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST4:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net5 + 1.221 3.987 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST4:Y cell ADLIB:CFG1D_TEST + 0.372 4.359 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST3:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net4 + 0.204 4.563 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST3:Y cell ADLIB:CFG1D_TEST + 0.372 4.935 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST2:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net3 + 0.302 5.237 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.372 5.609 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST1:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net2 + 0.303 5.912 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 6.284 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST0:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net1 + 0.204 6.488 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 6.860 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net0 + 0.226 7.086 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST:Y cell ADLIB:CFG1C_TEST + 0.209 7.295 1 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST:A net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1C_TEST_net + 0.203 7.498 f
mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 7.870 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[16]:B net mdr_CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16]_CFG1D_TEST_net + 0.962 8.832 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEi1li_5[16]:Y cell ADLIB:CFG3 + 0.164 8.996 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSElIo0/CORETSEi1li_5[16] + 0.297 9.293 f
data arrival time 9.293
Data required time calculation
FCCC_0/GL1 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 8.000 r
Clock generation + 3.502 11.502
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.203 11.705 r
FCCC_0/GL1_INST:YSn cell ADLIB:GB + 0.166 11.871 4 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:An net FCCC_0/GL1_INST/U0_YNn_GSouth + 0.309 12.180 f
FCCC_0/GL1_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 12.431 4 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:CLK net FCCC_0/GL1_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.461 12.892 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSElIo0/CORETSEo1li[6]:D Library setup time ADLIB:SLE - 0.174 12.718
data required time 12.718
Operating Conditions WORST

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_0/GL1

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to FCCC_0/GL1

No Path

Clock Domain Igloo2_1000BaseT_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[6]:CLK COREABC_0/STD_ACCUM_ZERO:D 11.732 8.098 16.463 24.561 0.174 11.902 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[5]:CLK COREABC_0/STD_ACCUM_ZERO:D 11.723 8.107 16.454 24.561 0.174 11.893 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[7]:CLK COREABC_0/STD_ACCUM_ZERO:D 11.443 8.375 16.186 24.561 0.174 11.625 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[3]:CLK COREABC_0/STD_ACCUM_ZERO:D 11.334 8.410 16.071 24.481 0.254 11.590 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEol0l:CLK COREABC_0/STD_ACCUM_ZERO:D 11.264 8.544 16.017 24.561 0.174 11.456 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[6]:CLK
To: COREABC_0/STD_ACCUM_ZERO:D
data required time 24.561
data arrival time - 16.463
slack 8.098
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.367 3.367
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.197 3.564 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 3.729 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.287 4.016 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 4.267 55 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[6]:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.464 4.731 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEoIOl[6]:Q cell ADLIB:SLE + 0.108 4.839 16 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEOo0l/un1_CORETSEIlOl_0_a2:C net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEIIo[6] + 1.149 5.988 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1I/CORETSEOo0l/un1_CORETSEIlOl_0_a2:Y cell ADLIB:CFG4 + 0.147 6.135 6 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/CORETSEloo1_1:A net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiOo_i_1 + 0.724 6.859 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/CORETSEloo1_1:Y cell ADLIB:CFG2 + 0.074 6.933 31 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/CORETSEl1i1:C net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEloo1_1 + 1.645 8.578 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/CORETSEl1i1:Y cell ADLIB:CFG3 + 0.074 8.652 16 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/un1_CORETSEiIi[17]:A net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEl1i1 + 0.939 9.591 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEloI1/un1_CORETSEiIi[17]:Y cell ADLIB:CFG2 + 0.074 9.665 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_9[17]:D net CORETSE_0/CORETSEO/CORETSEIlI/un1_CORETSEiIi[17] + 0.456 10.121 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_9[17]:Y cell ADLIB:CFG4 + 0.202 10.323 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_13[17]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_9[17] + 0.853 11.176 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_13[17]:Y cell ADLIB:CFG4 + 0.074 11.250 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_15[17]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_13[17] + 1.258 12.508 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_15[17]:Y cell ADLIB:CFG4 + 0.074 12.582 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_16[17]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_15[17] + 0.224 12.806 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_16[17]:Y cell ADLIB:CFG4 + 0.074 12.880 1 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi[17]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi_16[17] + 0.813 13.693 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi[17]:Y cell ADLIB:CFG4 + 0.158 13.851 2 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/CoreAPB3_0_APBmslave0_PRDATA_m[17]:C net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEiIi[17] + 0.670 14.521 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/CoreAPB3_0_APBmslave0_PRDATA_m[17]:Y cell ADLIB:CFG4 + 0.072 14.593 1 r
COREABC_0/ACCUM_NEXT_110:B net COREABC_0_APB3master_PRDATA[17] + 0.082 14.675 r
COREABC_0/ACCUM_NEXT_110:Y cell ADLIB:CFG3 + 0.072 14.747 1 r
COREABC_0/ACCUM_NEXT[17]:B net COREABC_0/ACCUM_NEXT_110 + 0.216 14.963 r
COREABC_0/ACCUM_NEXT[17]:Y cell ADLIB:CFG4 + 0.072 15.035 2 r
COREABC_0/to_logic_2.tmp_4_16[0]:A net COREABC_0/ACCUM_NEXT[17] + 0.641 15.676 r
COREABC_0/to_logic_2.tmp_4_16[0]:Y cell ADLIB:CFG4 + 0.225 15.901 1 f
COREABC_0/to_logic_2.tmp_4_28[0]:C net COREABC_0/to_logic_2.tmp_4_16[0] + 0.221 16.122 f
COREABC_0/to_logic_2.tmp_4_28[0]:Y cell ADLIB:CFG4 + 0.087 16.209 1 f
COREABC_0/to_logic_2.tmp_4[0]:C net COREABC_0/to_logic_2.tmp_4_28[0] + 0.093 16.302 f
COREABC_0/to_logic_2.tmp_4[0]:Y cell ADLIB:CFG4 + 0.087 16.389 1 f
COREABC_0/STD_ACCUM_ZERO:D net COREABC_0/to_logic_2.tmp_4[0] + 0.074 16.463 f
data arrival time 16.463
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 Clock Constraint 20.000 20.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 20.000 r
Clock generation + 3.367 23.367
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.197 23.564 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 23.729 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.286 24.015 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.251 24.266 63 r
COREABC_0/STD_ACCUM_ZERO:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.469 24.735 r
COREABC_0/STD_ACCUM_ZERO:D Library setup time ADLIB:SLE - 0.174 24.561
data required time 24.561
Operating Conditions WORST

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 PHY_MDIO CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D 5.272 5.272 0.174 0.851 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PHY_MDIO
To: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D
data required time N/C
data arrival time - 5.272
slack N/C
Data arrival time calculation
PHY_MDIO 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:PAD net PHY_MDIO + 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:Y cell ADLIB:IOPAD_BI + 1.403 1.403 1 f
BIBUF_0/U0/U_IOINFF:A net BIBUF_0/U0/YIN1 + -0.015 1.388 f
BIBUF_0/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.067 1.455 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un17_CORETSEi11:D net BIBUF_0_Y + 1.709 3.164 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEOlo0/un17_CORETSEi11:Y cell ADLIB:CFG4 + 0.363 3.527 1 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0]:A net CORETSE_0/CORETSEO/un17_CORETSEi11 + 1.382 4.909 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0]:Y cell ADLIB:CFG4 + 0.287 5.196 1 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOOIo[0] + 0.076 5.272 f
data arrival time 5.272
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 N/C N/C
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.266 N/C
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.191 N/C r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.160 N/C 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.269 N/C f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:YR cell ADLIB:RGB + 0.243 N/C 73 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13_rgbr_net_1 + 0.466 N/C r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIOIo[0]:D Library setup time ADLIB:SLE - 0.174 N/C
Operating Conditions WORST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSElo1:CLK PHY_MDIO 8.269 13.014 13.014 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:CLK PHY_MDC 6.200 10.978 10.978 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEIo1:CLK PHY_MDIO 5.466 10.221 10.221 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSElo1:CLK
To: PHY_MDIO
data required time N/C
data arrival time - 13.014
slack N/C
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.367 3.367
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.197 3.564 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.730 17 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.281 4.011 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:YR cell ADLIB:RGB + 0.250 4.261 47 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSElo1:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16_rgbr_net_1 + 0.484 4.745 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSElo1:Q cell ADLIB:SLE + 0.108 4.853 6 f
BIBUF_0/U0/U_IOENFF:A net CORETSE_0_MDOEN + 2.640 7.493 f
BIBUF_0/U0/U_IOENFF:Y cell ADLIB:IOENFF_BYPASS + 0.330 7.823 1 f
BIBUF_0/U0/U_IOPAD:E net BIBUF_0/U0/EOUT + 0.059 7.882 f
BIBUF_0/U0/U_IOPAD:PAD cell ADLIB:IOPAD_BI + 5.132 13.014 1 f
PHY_MDIO net PHY_MDIO + 0.000 13.014 f
data arrival time 13.014
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 N/C N/C
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.367 N/C
PHY_MDIO N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 COREABC_0/genblk2.RSTSYNC2:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEoIoI:ALn 5.139 14.478 9.886 24.364 0.353 5.522 0.030 WORST
Path 2 COREABC_0/genblk2.RSTSYNC2:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEOloI:ALn 5.139 14.478 9.886 24.364 0.353 5.522 0.030 WORST
Path 3 COREABC_0/genblk2.RSTSYNC2:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEOIoI:ALn 5.139 14.478 9.886 24.364 0.353 5.522 0.030 WORST
Path 4 COREABC_0/genblk2.RSTSYNC2:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEIloI:ALn 5.139 14.487 9.886 24.373 0.353 5.513 0.021 WORST
Path 5 COREABC_0/genblk2.RSTSYNC2:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEI0i:ALn 5.139 14.487 9.886 24.373 0.353 5.513 0.021 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: COREABC_0/genblk2.RSTSYNC2:CLK
To: CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEoIoI:ALn
data required time 24.364
data arrival time - 9.886
slack 14.478
Data arrival time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 0.000 0.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.367 3.367
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.197 3.564 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.730 17 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.289 4.019 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20:YR cell ADLIB:RGB + 0.250 4.269 17 r
COREABC_0/genblk2.RSTSYNC2:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20_rgbr_net_1 + 0.478 4.747 r
COREABC_0/genblk2.RSTSYNC2:Q cell ADLIB:SLE + 0.087 4.834 17 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEilII/CORETSEI0II_s:A net COREABC_0/genblk2.RSTSYNC2 + 1.631 6.465 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEilII/CORETSEI0II_s:Y cell ADLIB:CFG2 + 0.143 6.608 2 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEilII/un1_CORETSEoOII:A net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEilII_inst_2/CORETSEI0II_0 + 0.230 6.838 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEilII/un1_CORETSEoOII:Y cell ADLIB:CFG2 + 0.099 6.937 152 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEoIoI:ALn net CORETSE_0/CORETSEO/CORETSEIlI/un1_CORETSEoOII + 2.949 9.886 r
data arrival time 9.886
Data required time calculation
Igloo2_1000BaseT_sb_0/CCC_0/GL0 Clock Constraint 20.000 20.000
Igloo2_1000BaseT_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 20.000 r
Clock generation + 3.367 23.367
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_net + 0.197 23.564 r
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 23.729 16 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:An net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_YNn + 0.280 24.009 f
Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:YR cell ADLIB:RGB + 0.250 24.259 63 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEoIoI:CLK net Igloo2_1000BaseT_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12_rgbr_net_1 + 0.458 24.717 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEoIII/CORETSEoIoI:ALn Library recovery time ADLIB:SLE - 0.353 24.364
data required time 24.364
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] to Igloo2_1000BaseT_sb_0/CCC_0/GL0

No Path

Clock Domain Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN 2.610 17.033 7.338 24.371 0.308 2.967 WORST
Path 2 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[8]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN 2.487 17.169 7.202 24.371 0.308 2.831 WORST
Path 3 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[2]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN 2.355 17.301 7.070 24.371 0.308 2.699 WORST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[0]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN 2.294 17.384 6.987 24.371 0.308 2.616 WORST
Path 5 Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[10]:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN 2.216 17.440 6.931 24.371 0.308 2.560 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11]:CLK
To: Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN
data required time 24.371
data arrival time - 7.338
slack 17.033
Data arrival time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.730 1.730 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.882 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.554 3.436 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.221 3.657 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.310 3.967 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.250 4.217 18 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11]:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.511 4.728 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11]:Q cell ADLIB:SLE + 0.108 4.836 2 f
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6_1:A net Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0[11] + 0.673 5.509 f
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6_1:Y cell ADLIB:CFG4 + 0.315 5.824 1 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6:A net Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6_1 + 0.233 6.057 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6:Y cell ADLIB:CFG4 + 0.225 6.282 1 f
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN net Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core6 + 1.056 7.338 f
data arrival time 7.338
Data required time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.730 21.730 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.882 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.554 23.436 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.221 23.657 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.310 23.967 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.250 24.217 18 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.462 24.679 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif0_core:EN Library setup time ADLIB:SLE - 0.308 24.371
data required time 24.371
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif3_core:ALn 1.587 18.016 6.291 24.307 0.353 1.984 0.044 WORST
Path 2 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif1_core:ALn 1.376 18.230 6.071 24.301 0.353 1.770 0.041 WORST
Path 3 Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif2_core:ALn 1.389 18.278 6.069 24.347 0.353 1.722 -0.020 WORST
Path 4 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/ddr_settled:ALn 1.141 18.492 5.836 24.328 0.353 1.508 0.014 WORST
Path 5 Igloo2_1000BaseT_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK Igloo2_1000BaseT_sb_0/CORERESETP_0/count_sdif0_enable_rcosc:ALn 1.141 18.492 5.836 24.328 0.353 1.508 0.014 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK
To: Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif3_core:ALn
data required time 24.307
data arrival time - 6.291
slack 18.016
Data arrival time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.730 1.730 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.882 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.554 3.436 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.221 3.657 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.305 3.962 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.250 4.212 9 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.492 4.704 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 4.791 1 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif3_core:ALn net Igloo2_1000BaseT_sb_0/CORERESETP_0/sdif3_areset_n_rcosc + 1.500 6.291 r
data arrival time 6.291
Data required time calculation
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.730 21.730 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.882 1 r
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Igloo2_1000BaseT_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.554 23.436 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YSn cell ADLIB:GB + 0.221 23.657 4 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn_GSouth + 0.308 23.965 f
Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.250 24.215 1 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif3_core:CLK net Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.445 24.660 r
Igloo2_1000BaseT_sb_0/CORERESETP_0/release_sdif3_core:ALn Library recovery time ADLIB:SLE - 0.353 24.307
data required time 24.307
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to Igloo2_1000BaseT_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

No Path

Clock Domain Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[22]:D 3.909 15.752 6.672 22.424 0.254 8.496 WORST
Path 2 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL 2.776 16.029 5.539 21.568 1.424 7.942 WORST
Path 3 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:D 2.399 17.250 5.162 22.412 0.254 5.500 WORST
Path 4 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:D 2.399 17.250 5.162 22.412 0.254 5.500 WORST
Path 5 Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:D 2.398 17.262 5.161 22.423 0.254 5.476 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK
To: Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[22]:D
data required time 22.424
data arrival time - 6.672
slack 15.752
Data arrival time calculation
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB 0.000 0.000
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:An net CLK_CONFIG_APB + 1.543 1.543 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:YSn cell ADLIB:GB + 0.223 1.766 6 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_YNn_GSouth + 0.292 2.058 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.182 2.240 40 f
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB0_rgbr_net_1 + 0.523 2.763 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel:Q cell ADLIB:SLE + 0.087 2.850 6 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/R_SDIF0_PSEL_0_a2:B net Igloo2_1000BaseT_sb_0/CORECONFIGP_0/psel + 0.318 3.168 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/R_SDIF0_PSEL_0_a2:Y cell ADLIB:CFG3 + 0.202 3.370 35 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[22]:A net Igloo2_1000BaseT_sb_0_SDIF0_INIT_APB_PSELx + 1.514 4.884 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[22]:Y cell ADLIB:CFG2 + 0.158 5.042 1 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[22]:D net Igloo2_1000BaseT_sb_0/CORECONFIGP_0/prdata[22] + 1.630 6.672 r
data arrival time 6.672
Data required time calculation
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB Clock Constraint 20.000 20.000
Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 20.000 r
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:An net CLK_CONFIG_APB + 1.392 21.392 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1/un23_CORETSEoO1i_cry_0_1913:YSn cell ADLIB:GB + 0.221 21.613 6 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB2:An net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_YNn_GSouth + 0.309 21.922 f
CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 22.172 12 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[22]:CLK net CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEl0I1/CORETSEoil1_inst_1/un23_CORETSEoO1i_cry_0_1913/U0_RGB1_RGB2_rgbr_net_1 + 0.506 22.678 r
Igloo2_1000BaseT_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[22]:D Library setup time ADLIB:SLE - 0.254 22.424
data required time 22.424
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to Igloo2_1000BaseT_sb_0/Igloo2_1000BaseT_sb_HPMS_0/CLK_CONFIG_APB

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEo0O0/CORETSEiIO0[4]:CLK SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24] 1.918 1.750 4.338 6.088 1.912 6.250 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEiIII/CORETSEiooI[3]:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEiIII/CORETSElioI:D 5.931 1.786 8.334 10.120 0.254 6.214 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEiIII/CORETSEiooI[5]:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEiIII/CORETSElioI:D 5.823 1.885 8.235 10.120 0.254 6.115 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEo0O0/CORETSEiIO0[0]:CLK SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[20] 1.767 1.888 4.190 6.078 1.922 6.112 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEIlII/CORETSEio0I[3]:CLK CORETSE_0/CORETSEO/CORETSEIlI/CORETSEooo1I/CORETSEIlII/CORETSEoO1I[11]:EN 5.719 1.959 8.111 10.070 0.308 6.041 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEo0O0/CORETSEiIO0[4]:CLK
To: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24]
data required time 6.088
data arrival time - 4.338
slack 1.750
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 1.133 1.133 f
CLKINT_0:YSn cell ADLIB:GB + 0.221 1.354 17 f
CLKINT_0/U0_RGB1_RGB30:An net CLKINT_0/U0_YNn_GSouth + 0.316 1.670 f
CLKINT_0/U0_RGB1_RGB30:YR cell ADLIB:RGB + 0.250 1.920 45 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEo0O0/CORETSEiIO0[4]:CLK net CLKINT_0/U0_RGB1_RGB30_rgbr_net_1 + 0.500 2.420 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEo0O0/CORETSEiIO0[4]:Q cell ADLIB:SLE + 0.108 2.528 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoOo0/CORETSEil1[4]:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEiIO0[4] + 0.602 3.130 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoOo0/CORETSEil1[4]:Y cell ADLIB:CFG4 + 0.164 3.294 2 f
SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_203:B net CORETSE_0_TCG[4] + 0.575 3.869 f
SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_203:IPB cell ADLIB:IP_INTERFACE + 0.224 4.093 1 f
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24] net SERDES_IF_0/SERDESIF_INST/EPCS_TXDATA_net[24] + 0.245 4.338 f
data arrival time 4.338
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 8.000 8.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 8.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24] Library setup time ADLIB:SERDESIF_IP - 1.912 6.088
data required time 6.088
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[3]:ALn 3.135 4.521 5.513 10.034 0.353 3.479 -0.009 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[7]:ALn 2.761 4.896 5.139 10.035 0.353 3.104 -0.010 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[2]:ALn 2.761 4.896 5.139 10.035 0.353 3.104 -0.010 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEI11:ALn 2.761 4.896 5.139 10.035 0.353 3.104 -0.010 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[6]:ALn 2.761 4.905 5.139 10.044 0.353 3.095 -0.019 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[3]:ALn
data required time 10.034
data arrival time - 5.513
slack 4.521
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 0.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 1.133 1.133 f
CLKINT_0:YSn cell ADLIB:GB + 0.221 1.354 17 f
CLKINT_0/U0_RGB1_RGB19:An net CLKINT_0/U0_YNn_GSouth + 0.311 1.665 f
CLKINT_0/U0_RGB1_RGB19:YR cell ADLIB:RGB + 0.250 1.915 27 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:CLK net CLKINT_0/U0_RGB1_RGB19_rgbr_net_1 + 0.463 2.378 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol:Q cell ADLIB:SLE + 0.108 2.486 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/un1_CORETSEIi1l:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/CORETSEOOol + 0.684 3.170 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEI0O0/un1_CORETSEIi1l:Y cell ADLIB:CFG2 + 0.087 3.257 150 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[3]:ALn net CORETSE_0/CORETSEO/CORETSEIi1l + 2.256 5.513 r
data arrival time 5.513
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 8.000 8.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 8.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 1.133 9.133 f
CLKINT_0:YSn cell ADLIB:GB + 0.221 9.354 17 f
CLKINT_0/U0_RGB1_RGB26:An net CLKINT_0/U0_YNn_GSouth + 0.318 9.672 f
CLKINT_0/U0_RGB1_RGB26:YL cell ADLIB:RGB + 0.251 9.923 34 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[3]:CLK net CLKINT_0/U0_RGB1_RGB26_rgbl_net_1 + 0.464 10.387 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEIiO0/CORETSEi01[3]:ALn Library recovery time ADLIB:SLE - 0.353 10.034
data required time 10.034
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0/CORETSEO/CORETSEIlI/CORETSEioo1I/CORETSEo1I1/CORETSEOo1:Q to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

SET FCCC_0/GL0 to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[0]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEoi00:D 3.125 2.112 8.020 10.132 0.254 WORST
Path 2 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[5]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo100:D 3.048 2.210 7.946 10.156 0.254 WORST
Path 3 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[7]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo1I0[15]:D 2.983 2.232 7.890 10.122 0.254 WORST
Path 4 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[7]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo1I0[10]:D 2.984 2.232 7.891 10.123 0.254 WORST
Path 5 CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[7]:CLK CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEo1I0[8]:D 2.983 2.233 7.890 10.123 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[0]:CLK
To: CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEoi00:D
data required time 10.132
data arrival time - 8.020
slack 2.112
Data arrival time calculation
FCCC_0/GL0 0.000 0.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.478 3.478
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.207 3.685 r
FCCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.851 9 f
FCCC_0/GL0_INST/U0_RGB1_RGB2:An net FCCC_0/GL0_INST/U0_YNn_GSouth + 0.318 4.169 f
FCCC_0/GL0_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.251 4.420 64 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[0]:CLK net FCCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.475 4.895 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEoIo0/CORETSEIOI0[0]:Q cell ADLIB:SLE + 0.108 5.003 8 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEOo00_RNI4IBK[0]:B net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEIOI0[0] + 0.985 5.988 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEOo00_RNI4IBK[0]:P cell ADLIB:ARI1_CC + 0.200 6.188 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEOo00_RNI4IBK[0]_CC_0:P[0] net NET_CC_CONFIG2800 + 0.000 6.188 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEOo00_RNI4IBK[0]_CC_0:CC[8] cell ADLIB:CC_CONFIG + 0.712 6.900 1 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEOo00_RNIKGC56[15]_FCINST1:CC net NET_CC_CONFIG2826 + 0.000 6.900 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEOo00_RNIKGC56[15]_FCINST1:CO cell ADLIB:FCEND_BUFF_CC + 0.073 6.973 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSElo00:A net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEIo00_0_data_tmp[7] + 0.338 7.311 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSElo00:Y cell ADLIB:CFG4 + 0.087 7.398 2 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEOi00[0]:C net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSElo00_net_30 + 0.229 7.627 f
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEOi00[0]:Y cell ADLIB:CFG4 + 0.147 7.774 2 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEli00:A net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEOi00[0] + 0.097 7.871 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEli00:Y cell ADLIB:CFG2 + 0.074 7.945 1 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEoi00:D net CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0_inst_1/CORETSEiIo0/CORETSEli00 + 0.075 8.020 r
data arrival time 8.020
Data required time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] Clock Constraint 8.000 8.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 8.000 r
CLKINT_0:An net SERDES_IF_0_EPCS_3_TX_CLK + 1.133 9.133 f
CLKINT_0:YSn cell ADLIB:GB + 0.221 9.354 17 f
CLKINT_0/U0_RGB1_RGB22:An net CLKINT_0/U0_YNn_GSouth + 0.315 9.669 f
CLKINT_0/U0_RGB1_RGB22:YL cell ADLIB:RGB + 0.251 9.920 40 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEoi00:CLK net CLKINT_0/U0_RGB1_RGB22_rgbl_net_1 + 0.466 10.386 r
CORETSE_0/CORETSEO/CORETSEio0.CORETSEOi0/CORETSEi0O0/CORETSEiIo0/CORETSEoi00:D Library setup time ADLIB:SLE - 0.254 10.132
data required time 10.132
Operating Conditions WORST

SET Igloo2_1000BaseT_sb_0/CCC_0/GL0 to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets