| Project Settings |
|---|
| Project Name | PCIe_HPDMA_top_syn | Implementation Name | synthesis |
| Top Module | PCIe_HPDMA_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
90 |
556 |
0 |
- |
0m:05s |
- |
22-02-2016
PM 03:03:54 |
| (premap) | Complete |
102 |
12 |
0 |
0m:01s |
0m:01s |
167MB |
22-02-2016
PM 03:03:57 |
| (fpga_mapper) | Complete |
54 |
150 |
0 |
0m:12s |
0m:12s |
213MB |
22-02-2016
PM 03:04:10 |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 22-02-2016
PM 03:03:56 |
| Area Summary |
|---|
| |
| Carry Cells | 301 |
Sequential Cells | 1491 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 65 |
| Global Clock Buffers | 11 |
Block Rams (RAM1K18)
(v_ram) | 16 |
| LUTs
(total_luts) | 2195 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PCIe_HPDMA_0.CCC_0.GL0_net | 80.0 MHz | 105.7 MHz | 3.036 |
| PCIe_HPDMA_0.CCC_0.GL3_net | 125.0 MHz | 270.5 MHz | 4.303 |
| PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 100.0 MHz | 428.6 MHz | 7.667 |
| PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 128.9 MHz | 1.427 |
| System | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 3 / 1 |
| |
|