#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-DONTHUS1 #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\AHB_IF.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\Debounce.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\CCC_0\PCIe_HPDMA_CCC_0_FCCC.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_HPMS\PCIe_HPDMA_HPMS_syn.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_HPMS\PCIe_HPDMA_HPMS.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\PCIe_HPDMA.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_AHBLMasterIF.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREHPDMACTRL_0\rtl\vlog\core\CoreHPDMACtrl.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\SERDES_IF_0\PCIe_HPDMA_top_SERDES_IF_0_SERDES_IF_syn.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\SERDES_IF_0\PCIe_HPDMA_top_SERDES_IF_0_SERDES_IF.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v" @I::"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\PCIe_HPDMA_top.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module PCIe_HPDMA_top @N:CG364 : AHB_IF.v(21) | Synthesizing module AHB_IF Idle_1=3'b000 Write_FIC_0=3'b001 Write_FIC_1=3'b010 Write_FIC_2=3'b011 Read_FIC_0=3'b100 Read_FIC_1=3'b101 Read_FIC_2=3'b110 Data_size=5'b00000 Generated name = AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1 @W:CG360 : AHB_IF.v(60) | No assignment to wire HSIZE_int @A:CL282 : AHB_IF.v(81) | Feedback mux created for signal HWDATA_int[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : AHB_IF.v(81) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : AHB_IF.v(81) | Pruning register bit 0 of HTRANS[1:0] @N:CG364 : PCIe_Slave.v(22) | Synthesizing module COMMAND_DECODER @W:CL271 : PCIe_Slave.v(75) | Pruning bits 31 to 21 of dma_size[31:0] -- not in use ... @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal dma_size[20:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal pc_base_int[23:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal haddr_int[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal dma_dir[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal PC_BASE_ADDR[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL113 : PCIe_Slave.v(75) | Feedback mux created for signal HREADYOUT. @W:CL113 : PCIe_Slave.v(75) | Feedback mux created for signal HREADY. @N:CL177 : PCIe_Slave.v(75) | Sharing sequential element HREADY. @A:CL282 : PCIe_Slave.v(75) | Feedback mux created for signal HRDATA[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL251 : PCIe_Slave.v(75) | All reachable assignments to HREADYOUT assign 1, register removed by optimization @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_PAU_RES[1] to a constant 1 @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_PAU_RES[2] to a constant 1 @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_PAU_RES[3] to a constant 1 @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_VALID[1] to a constant 0 @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_VALID[2] to a constant 0 @W:CL190 : PCIe_Slave.v(180) | Optimizing register bit HPD_VALID[3] to a constant 0 @W:CL279 : PCIe_Slave.v(180) | Pruning register bits 3 to 1 of HPD_VALID[3:0] @W:CL279 : PCIe_Slave.v(180) | Pruning register bits 3 to 1 of HPD_PAU_RES[3:0] @W:CG775 : CoreAHBLSRAM.v(29) | Found Component PCIe_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB @N:CG364 : AHBLSramIf.v(29) | Synthesizing module PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf SYNC_RESET=32'b00000000000000000000000000000000 IDLE=2'b00 AHB_WR=2'b01 AHB_RD=2'b10 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 RESP_OKAY=2'b00 RESP_ERROR=2'b01 TRN_IDLE=2'b00 TRN_BUSY=2'b01 TRN_SEQ=2'b11 TRN_NONSEQ=2'b10 Generated name = PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2 @W:CL169 : AHBLSramIf.v(165) | Pruning register HWDATA_d[31:0] @W:CL169 : AHBLSramIf.v(165) | Pruning register HTRANS_d[1:0] @W:CL169 : AHBLSramIf.v(165) | Pruning register HSEL_d @W:CL169 : AHBLSramIf.v(165) | Pruning register HREADYIN_d @N:CG364 : SramCtrlIf.v(29) | Synthesizing module PCIe_HPDMA_top_COREAHBLSRAM_0_SramCtrlIf SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 LSRAM_NUM_LOCATIONS_4=32'b00000000000000000010000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 USRAM_NUM_LOCATIONS_4=32'b00000000000000000000000010000000 AHB_DWIDTH=32'b00000000000000000000000000100000 SYNC_RESET=32'b00000000000000000000000000000000 S_IDLE=2'b00 S_WR=2'b01 S_RD=2'b10 Generated name = PCIe_HPDMA_top_COREAHBLSRAM_0_SramCtrlIf_0s_32768s_8192s_512s_128s_32s_0s_0_1_2 @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 @N:CG364 : lsram_2048to139264x8.v(28) | Synthesizing module PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8 DEPTH=32'b00000000000000000010000000000000 SYNC_RESET=32'b00000000000000000000000000000000 AHB_DWIDTH=32'b00000000000000000000000000001000 Generated name = PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s @W:CG133 : lsram_2048to139264x8.v(118) | No assignment to writeData0 @W:CG133 : lsram_2048to139264x8.v(119) | No assignment to writeData1 @W:CG133 : lsram_2048to139264x8.v(120) | No assignment to writeData2 @W:CG133 : lsram_2048to139264x8.v(121) | No assignment to writeData3 @W:CG133 : lsram_2048to139264x8.v(122) | No assignment to writeData4 @W:CG133 : lsram_2048to139264x8.v(123) | No assignment to writeData5 @W:CG133 : lsram_2048to139264x8.v(124) | No assignment to writeData6 @W:CG133 : lsram_2048to139264x8.v(125) | No assignment to writeData7 @W:CG133 : lsram_2048to139264x8.v(126) | No assignment to writeData8 @W:CG133 : lsram_2048to139264x8.v(127) | No assignment to writeData9 @W:CG133 : lsram_2048to139264x8.v(128) | No assignment to writeData10 @W:CG133 : lsram_2048to139264x8.v(129) | No assignment to writeData11 @W:CG133 : lsram_2048to139264x8.v(130) | No assignment to writeData12 @W:CG133 : lsram_2048to139264x8.v(131) | No assignment to writeData13 @W:CG133 : lsram_2048to139264x8.v(132) | No assignment to writeData14 @W:CG133 : lsram_2048to139264x8.v(133) | No assignment to writeData15 @W:CG133 : lsram_2048to139264x8.v(134) | No assignment to writeData16 @W:CG133 : lsram_2048to139264x8.v(154) | No assignment to writeAddr0 @W:CG133 : lsram_2048to139264x8.v(155) | No assignment to writeAddr1 @W:CG133 : lsram_2048to139264x8.v(156) | No assignment to writeAddr2 @W:CG133 : lsram_2048to139264x8.v(157) | No assignment to writeAddr3 @W:CG133 : lsram_2048to139264x8.v(158) | No assignment to writeAddr4 @W:CG133 : lsram_2048to139264x8.v(159) | No assignment to writeAddr5 @W:CG133 : lsram_2048to139264x8.v(160) | No assignment to writeAddr6 @W:CG133 : lsram_2048to139264x8.v(161) | No assignment to writeAddr7 @W:CG133 : lsram_2048to139264x8.v(162) | No assignment to writeAddr8 @W:CG133 : lsram_2048to139264x8.v(163) | No assignment to writeAddr9 @W:CG133 : lsram_2048to139264x8.v(164) | No assignment to writeAddr10 @W:CG133 : lsram_2048to139264x8.v(165) | No assignment to writeAddr11 @W:CG133 : lsram_2048to139264x8.v(166) | No assignment to writeAddr12 @W:CG133 : lsram_2048to139264x8.v(167) | No assignment to writeAddr13 @W:CG133 : lsram_2048to139264x8.v(168) | No assignment to writeAddr14 @W:CG133 : lsram_2048to139264x8.v(169) | No assignment to writeAddr15 @W:CG133 : lsram_2048to139264x8.v(170) | No assignment to writeAddr16 @W:CG133 : lsram_2048to139264x8.v(172) | No assignment to readAddr0 @W:CG133 : lsram_2048to139264x8.v(173) | No assignment to readAddr1 @W:CG133 : lsram_2048to139264x8.v(174) | No assignment to readAddr2 @W:CG133 : lsram_2048to139264x8.v(175) | No assignment to readAddr3 @W:CG133 : lsram_2048to139264x8.v(176) | No assignment to readAddr4 @W:CG133 : lsram_2048to139264x8.v(177) | No assignment to readAddr5 @W:CG133 : lsram_2048to139264x8.v(178) | No assignment to readAddr6 @W:CG133 : lsram_2048to139264x8.v(179) | No assignment to readAddr7 @W:CG133 : lsram_2048to139264x8.v(180) | No assignment to readAddr8 @W:CG133 : lsram_2048to139264x8.v(181) | No assignment to readAddr9 @W:CG133 : lsram_2048to139264x8.v(182) | No assignment to readAddr10 @W:CG133 : lsram_2048to139264x8.v(183) | No assignment to readAddr11 @W:CG133 : lsram_2048to139264x8.v(184) | No assignment to readAddr12 @W:CG133 : lsram_2048to139264x8.v(185) | No assignment to readAddr13 @W:CG133 : lsram_2048to139264x8.v(186) | No assignment to readAddr14 @W:CG133 : lsram_2048to139264x8.v(187) | No assignment to readAddr15 @W:CG133 : lsram_2048to139264x8.v(188) | No assignment to readAddr16 @W:CL169 : lsram_2048to139264x8.v(218) | Pruning register ckRdAddr[15:9] @N:CG179 : SramCtrlIf.v(394) | Removing redundant assignment @W:CG133 : SramCtrlIf.v(98) | No assignment to ahbsram_wdata_upd_r @W:CG133 : SramCtrlIf.v(99) | No assignment to u_ahbsram_wdata_upd_r @W:CG360 : SramCtrlIf.v(106) | No assignment to wire u_BUSY_all_0 @W:CG360 : SramCtrlIf.v(107) | No assignment to wire u_BUSY_all_1 @W:CG360 : SramCtrlIf.v(108) | No assignment to wire u_BUSY_all_2 @W:CG360 : SramCtrlIf.v(109) | No assignment to wire u_BUSY_all_3 @N:CG364 : CoreAHBLSRAM.v(29) | Synthesizing module PCIe_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM FAMILY=32'b00000000000000000000000000011000 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = PCIe_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM_24s_32s_32s_32768s_512s_0s_0s @N:CG364 : HPDMA_UserIF.v(30) | Synthesizing module HPDMA_UserIF @N:CG179 : HPDMA_UserIF.v(316) | Removing redundant assignment @N:CG179 : HPDMA_UserIF.v(394) | Removing redundant assignment @W:CL169 : HPDMA_UserIF.v(614) | Pruning register done_intr0_d1 @W:CL169 : HPDMA_UserIF.v(614) | Pruning register done_intr1_d1 @W:CL169 : HPDMA_UserIF.v(614) | Pruning register done_intr2_d1 @W:CL169 : HPDMA_UserIF.v(614) | Pruning register done_intr3_d1 @W:CL169 : HPDMA_UserIF.v(526) | Pruning register error_intr0_d1 @W:CL169 : HPDMA_UserIF.v(526) | Pruning register error_intr1_d1 @W:CL169 : HPDMA_UserIF.v(526) | Pruning register error_intr2_d1 @W:CL169 : HPDMA_UserIF.v(526) | Pruning register error_intr3_d1 @W:CL169 : HPDMA_UserIF.v(347) | Pruning register new_serv_d1 @W:CL169 : HPDMA_UserIF.v(347) | Pruning register ucvalid_d1[3:0] @W:CL169 : HPDMA_UserIF.v(347) | Pruning register ustart_d1[3:0] @W:CL169 : HPDMA_UserIF.v(347) | Pruning register cudmacyc_end_d2 @W:CL169 : HPDMA_UserIF.v(261) | Pruning register udone_d1[3:0] @W:CL169 : HPDMA_UserIF.v(261) | Pruning register uerror_d1[3:0] @N:CG364 : HPDMA_CmdDec.v(30) | Synthesizing module HPDMA_CmdDec @W:CG133 : HPDMA_CmdDec.v(199) | No assignment to fcpop_d1 @W:CL169 : HPDMA_CmdDec.v(652) | Pruning register fctrans_done_d1 @W:CL169 : HPDMA_CmdDec.v(652) | Pruning register fctrans_done_d2 @W:CL169 : HPDMA_CmdDec.v(243) | Pruning register cfburst_len_rd_d1[31:0] @W:CL207 : HPDMA_CmdDec.v(730) | All reachable assignments to cfrd_req_o assign 0, register removed by optimization. @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[1] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[2] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[3] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[4] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[5] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[6] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[7] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[8] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[9] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[10] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[11] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[12] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[13] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[14] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[15] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[16] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[17] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[18] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[19] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[20] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[21] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[22] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[23] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[24] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[25] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[26] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[27] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[28] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[29] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[30] to a constant 0 @W:CL190 : HPDMA_CmdDec.v(243) | Optimizing register bit cfburst_len_wr_d1[31] to a constant 0 @W:CL279 : HPDMA_CmdDec.v(243) | Pruning register bits 31 to 1 of cfburst_len_wr_d1[31:0] @N:CG364 : HPDMA_FSMCtrl.v(30) | Synthesizing module HPDMA_fsm_ctrl @W:CL169 : HPDMA_FSMCtrl.v(881) | Pruning register busreq_prev @W:CL169 : HPDMA_FSMCtrl.v(863) | Pruning register pop_d1 @W:CL169 : HPDMA_FSMCtrl.v(800) | Pruning register fmhtrans_int2[1:0] @W:CL169 : HPDMA_FSMCtrl.v(666) | Pruning register haddr_prev[29:0] @W:CL169 : HPDMA_FSMCtrl.v(647) | Pruning register latch_addr_d2 @W:CL169 : HPDMA_FSMCtrl.v(647) | Pruning register latch_addr_d3 @W:CL169 : HPDMA_FSMCtrl.v(606) | Pruning register latch_addr_d1 @W:CL169 : HPDMA_FSMCtrl.v(594) | Pruning register state_prev_clk[3:0] @W:CL169 : HPDMA_FSMCtrl.v(274) | Pruning register clr_req @W:CL190 : HPDMA_FSMCtrl.v(262) | Optimizing register bit fmhburst_d1[1] to a constant 0 @W:CL190 : HPDMA_FSMCtrl.v(262) | Optimizing register bit fmhburst_d1[2] to a constant 0 @W:CL190 : HPDMA_FSMCtrl.v(785) | Optimizing register bit fmhtrans_int[0] to a constant 0 @W:CL279 : HPDMA_FSMCtrl.v(262) | Pruning register bits 2 to 1 of fmhburst_d1[2:0] @W:CL260 : HPDMA_FSMCtrl.v(785) | Pruning register bit 0 of fmhtrans_int[1:0] @N:CG364 : HPDMA_AHBLMasterIF.v(30) | Synthesizing module HPDMA_AHBLMasterIF @N:CG364 : CoreHPDMACtrl.v(30) | Synthesizing module PCIe_HPDMA_top_COREHPDMACTRL_0_COREHPDMACTRL FAMILY=32'b00000000000000000000000000011000 DESC_WIDTH=32'b00000000000000000000000000000100 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 Generated name = PCIe_HPDMA_top_COREHPDMACTRL_0_COREHPDMACTRL_24s_4s_32s_32s @N:CG364 : Debounce.v(20) | Synthesizing module DEBOUNCE @N:CG179 : Debounce.v(81) | Removing redundant assignment @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT @N:CG364 : igloo2.v(376) | Synthesizing module VCC @N:CG364 : igloo2.v(372) | Synthesizing module GND @N:CG364 : igloo2.v(727) | Synthesizing module CCC @N:CG364 : PCIe_HPDMA_CCC_0_FCCC.v(5) | Synthesizing module PCIe_HPDMA_CCC_0_FCCC @N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster DATA_LOCATION=32'b00000000000000111110100000000000 ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000 ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 S7=32'b00000000000000000000000000000111 S8=32'b00000000000000000000000000001000 S9=32'b00000000000000000000000000001001 S10=32'b00000000000000000000000000001010 S11=32'b00000000000000000000000000001011 S12=32'b00000000000000000000000000001100 S13=32'b00000000000000000000000000001101 S14=32'b00000000000000000000000000001110 S15=32'b00000000000000000000000000001111 S16=32'b00000000000000000000000000010000 S17=32'b00000000000000000000000000010001 S18=32'b00000000000000000000000000010010 S19=32'b00000000000000000000000000010011 S20=32'b00000000000000000000000000010100 S21=32'b00000000000000000000000000010101 S22=32'b00000000000000000000000000010110 P0=32'b00000000000000000000000000100000 P1=32'b00000000000000000000000000100001 P2=32'b00000000000000000000000000100010 P3=32'b00000000000000000000000000100011 P4=32'b00000000000000000000000000100100 P5=32'b00000000000000000000000000100101 P6=32'b00000000000000000000000000100110 OP_COPY=7'b0000000 OP_POLL=7'b0000010 OP_LOAD=7'b0000011 OP_STORE=7'b0000100 OP_AND=7'b0000101 OP_OR=7'b0000110 Generated name = CoreConfigMaster_Z3 @W:CL190 : coreconfigmaster.v(723) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : coreconfigmaster.v(723) | Pruning register bit 0 of HTRANS[1:0] @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000011 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z4 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000011 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_3_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z5 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z6 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000000011 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b011000 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b1 M0_AHBSLOT1ENABLE=1'b1 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000000011 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z7 @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z8 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z9 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b10000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_65536_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b1 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b1 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b10000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z10 @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z11 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z12 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : PCIe_HPDMA_FABOSC_0_OSC.v(5) | Synthesizing module PCIe_HPDMA_FABOSC_0_OSC @N:CG364 : igloo2.v(274) | Synthesizing module OUTBUF @N:CG364 : igloo2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : igloo2.v(286) | Synthesizing module BIBUF @N:CG364 : igloo2.v(268) | Synthesizing module INBUF @N:CG364 : PCIe_HPDMA_HPMS_syn.v(5) | Synthesizing module MSS_010 @N:CG364 : PCIe_HPDMA_HPMS.v(9) | Synthesizing module PCIe_HPDMA_HPMS @N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET @N:CG364 : PCIe_HPDMA.v(9) | Synthesizing module PCIe_HPDMA @N:CG364 : PCIe_Reg_Config.v(22) | Synthesizing module PCIe_Reg_Config @W:CL113 : PCIe_Reg_Config.v(47) | Feedback mux created for signal READ. @A:CL282 : PCIe_Reg_Config.v(47) | Feedback mux created for signal DATAOUT[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : PCIe_Reg_Config.v(47) | Feedback mux created for signal ADDR[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL250 : PCIe_Reg_Config.v(47) | All reachable assignments to READ assign 0, register removed by optimization @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[0] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[1] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[2] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[4] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[5] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[8] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[9] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[10] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[11] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[12] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[13] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[14] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[16] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[18] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[19] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[20] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[21] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[22] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[23] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[24] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[25] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[26] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[27] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[28] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[29] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit ADDR[31] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[0] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[1] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[2] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[3] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[4] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[5] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[6] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[7] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[8] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[9] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[10] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[11] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[12] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[13] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[14] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[15] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[16] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[17] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[18] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[19] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[20] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[21] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[22] is always 0, optimizing ... @W:CL189 : PCIe_Reg_Config.v(47) | Register bit DATAOUT[23] is always 0, optimizing ... @W:CL260 : PCIe_Reg_Config.v(47) | Pruning register bit 31 of ADDR[31:0] @W:CL279 : PCIe_Reg_Config.v(47) | Pruning register bits 29 to 18 of ADDR[31:0] @W:CL260 : PCIe_Reg_Config.v(47) | Pruning register bit 16 of ADDR[31:0] @W:CL279 : PCIe_Reg_Config.v(47) | Pruning register bits 14 to 8 of ADDR[31:0] @W:CL279 : PCIe_Reg_Config.v(47) | Pruning register bits 5 to 4 of ADDR[31:0] @W:CL279 : PCIe_Reg_Config.v(47) | Pruning register bits 2 to 0 of ADDR[31:0] @W:CL279 : PCIe_Reg_Config.v(47) | Pruning register bits 23 to 0 of DATAOUT[31:0] @N:CG364 : igloo2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : PCIe_HPDMA_top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0 @N:CG364 : PCIe_HPDMA_top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module PCIe_HPDMA_top_SERDES_IF_0_SERDES_IF @N:CG364 : PCIe_HPDMA_top.v(9) | Synthesizing module PCIe_HPDMA_top @N:CL201 : PCIe_Reg_Config.v(47) | Trying to extract state machine for register config_st Extracted state machine for register config_st State machine has 3 reachable states with original encodings of: 000 011 100 @W:CL260 : PCIe_Reg_Config.v(47) | Pruning register bit 7 of ADDR[7:6] @W:CL159 : PCIe_Reg_Config.v(27) | Input DATAIN is unused @W:CL159 : PCIe_Reg_Config.v(33) | Input VALID is unused @W:CL247 : PCIe_HPDMA_HPMS.v(89) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : PCIe_HPDMA_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : PCIe_HPDMA_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 2 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 2 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @N:CL201 : coreconfigmaster.v(723) | Trying to extract state machine for register state Extracted state machine for register state State machine has 29 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000110 000111 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 100000 100001 100010 100011 100100 100101 100110 @W:CL159 : HPDMA_AHBLMasterIF.v(72) | Input HCLK is unused @W:CL159 : HPDMA_AHBLMasterIF.v(73) | Input HRESETN is unused @W:CL190 : HPDMA_FSMCtrl.v(262) | Optimizing register bit fmhburst_d1[0] to a constant 0 @W:CL169 : HPDMA_FSMCtrl.v(262) | Pruning register fmhburst_d1[0] @N:CL201 : HPDMA_FSMCtrl.v(292) | Trying to extract state machine for register curr_state Extracted state machine for register curr_state State machine has 7 reachable states with original encodings of: 0000 0001 0010 0101 1000 1001 1011 @N:CL201 : HPDMA_CmdDec.v(281) | Trying to extract state machine for register hpd_curr_state Extracted state machine for register hpd_curr_state State machine has 23 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 @W:CL159 : HPDMA_CmdDec.v(137) | Input fcdataout_i is unused @N:CL177 : HPDMA_UserIF.v(366) | Sharing sequential element uvalid_r1. @W:CL246 : CoreAHBLSRAM.v(69) | Input port bits 31 to 20 of HADDR[31:0] are unused @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 15 to 14 of writeAddr[15:0] are unused @W:CL159 : lsram_2048to139264x8.v(61) | Input ren is unused @W:CL159 : lsram_2048to139264x8.v(63) | Input readAddr is unused @N:CL201 : SramCtrlIf.v(133) | Trying to extract state machine for register sramcurr_state Extracted state machine for register sramcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(75) | Input port bits 19 to 18 of ahbsram_addr[19:0] are unused @N:CL201 : AHBLSramIf.v(189) | Trying to extract state machine for register ahbcurr_state Extracted state machine for register ahbcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : AHBLSramIf.v(98) | Input BUSY is unused @N:CL201 : PCIe_Slave.v(260) | Trying to extract state machine for register hpd_st Extracted state machine for register hpd_st State machine has 2 reachable states with original encodings of: 00 01 @N:CL201 : PCIe_Slave.v(180) | Trying to extract state machine for register dma_loop_st Extracted state machine for register dma_loop_st State machine has 2 reachable states with original encodings of: 00 01 @W:CL247 : PCIe_Slave.v(27) | Input port bit 0 of HTRANS[1:0] is unused @W:CL159 : PCIe_Slave.v(34) | Input HSIZE is unused @W:CL159 : PCIe_Slave.v(49) | Input HPD_ERROR is unused @W:CL159 : PCIe_Slave.v(50) | Input HPD_START is unused @N:CL201 : AHB_IF.v(81) | Trying to extract state machine for register ahb_fsm_current_state Extracted state machine for register ahb_fsm_current_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 103MB peak: 120MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Mon Feb 22 15:03:53 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 15:03:54 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime # Mon Feb 22 15:03:54 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\bin64\syn_nfilter.exe changed - recompiling File D:\PCIE\IGL2_HPDMA\11.6\m2gl_dg0585_hpms_hpdma_liberov11p5_df\LiberoProject\PCIe_HPDMA_1\synthesis\synwork\PCIe_HPDMA_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 15:03:56 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\synthesis\PCIe_HPDMA_top_syn_1.fdc Linked File: PCIe_HPDMA_top_scck.rpt Printing clock summary report in "D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\synthesis\PCIe_HPDMA_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 140MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 140MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 140MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_16, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_15 @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z11(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(81) | Removing sequential instance DATAOUT[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(81) | Removing sequential instance VALID of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(3350) | Removing instance slavestage_10 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_4(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : hpdma_fsmctrl.v(770) | Removing sequential instance fmhsel_o of view:PrimLib.dffr(prim) in hierarchy view:work.HPDMA_fsm_ctrl(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(973) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(993) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1013) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1033) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1053) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1073) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1093) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1113) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1133) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1153) | Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1173) | Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1193) | Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1213) | Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(973) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(993) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1013) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1033) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1053) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1073) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1093) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1113) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1133) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1153) | Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1173) | Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1193) | Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1213) | Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(973) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(993) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1013) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1033) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1053) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1073) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1093) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1113) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1133) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1153) | Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1173) | Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1193) | Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1213) | Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(973) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(993) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1013) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1033) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1053) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1073) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1093) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1113) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1133) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1153) | Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1173) | Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1193) | Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(1213) | Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8_8192s_0s_8s_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_4(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z12(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_3(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=21 set on top level netlist PCIe_HPDMA_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 167MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CCC_0.GL0_net 80.0 MHz 12.500 declared default_clkgroup PCIe_HPDMA_0.CCC_0.GL3_net 125.0 MHz 8.000 declared default_clkgroup PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 =============================================================================================================================== @W:MT530 : coreconfigp.v(447) | Found inferred clock PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 111 sequential elements including PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1613) | Found inferred clock PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 46 sequential elements including PCIe_HPDMA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\synthesis\PCIe_HPDMA_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 167MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 15:03:57 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 149MB) @W:MO111 : pcie_hpdma_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance PCIe_HPDMA_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.v(912) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(884) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(912) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(856) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(1549) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core @W:BN132 : coreresetp.v(1581) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif3_core, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core @W:BN132 : coreresetp.v(1646) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif3_core_q1, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core_q1 @W:BN132 : coreresetp.v(1646) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core_q1, because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core_q1 Available hyper_sources - for debug and ip models None Found @N:MT480 : pcie_hpdma_top_syn_1.fdc(18) | Assigning clock "PCIe_HPDMA_0.CCC_0.GL0_net" to command: create_clock {n:PCIe_HPDMA_0.CCC_0.GL0_net} -period {12.5} -waveform {0 6.25} -add @N:MT480 : pcie_hpdma_top_syn_1.fdc(19) | Assigning clock "PCIe_HPDMA_0.CCC_0.GL3_net" to command: create_clock {n:PCIe_HPDMA_0.CCC_0.GL3_net} -period {8} -waveform {0 4} -add Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 151MB) @W:MO160 : hpdma_userif.v(283) | Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[3] is always 0, optimizing ... @W:MO160 : hpdma_userif.v(283) | Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[2] is always 0, optimizing ... @W:MO160 : hpdma_userif.v(283) | Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[1] is always 0, optimizing ... @W:MO160 : hpdma_userif.v(484) | Register bit COREHPDMACTRL_0.U_UserIF.error_intr1 is always 0, optimizing ... @W:MO160 : hpdma_userif.v(484) | Register bit COREHPDMACTRL_0.U_UserIF.error_intr2 is always 0, optimizing ... @W:MO160 : hpdma_userif.v(484) | Register bit COREHPDMACTRL_0.U_UserIF.error_intr3 is always 0, optimizing ... @W:MO160 : hpdma_userif.v(572) | Register bit COREHPDMACTRL_0.U_UserIF.done_intr1 is always 0, optimizing ... @W:MO160 : hpdma_userif.v(572) | Register bit COREHPDMACTRL_0.U_UserIF.done_intr2 is always 0, optimizing ... @W:MO160 : hpdma_userif.v(572) | Register bit COREHPDMACTRL_0.U_UserIF.done_intr3 is always 0, optimizing ... Encoding state machine ahb_fsm_current_state[6:0] (view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @W:MO129 : ahb_if.v(81) | Sequential instance AHB_IF_0.ahb_fsm_current_state[4] reduced to a combinational gate by constant propagation @W:MO160 : ahb_if.v(81) | Register bit ahb_fsm_current_state[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit ahb_fsm_current_state[6] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[18] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[17] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[16] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[15] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[12] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[10] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[7] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[6] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[4] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[3] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[2] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[1] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA_int[0] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[31] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[29] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[28] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[27] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[26] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[25] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[24] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[18] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[16] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[12] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[10] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[4] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[2] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[1] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HADDR[0] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[18] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[17] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[16] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[15] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[12] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[10] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[7] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[6] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[4] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[3] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[2] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[1] is always 0, optimizing ... @W:MO160 : ahb_if.v(81) | Register bit HWDATA[0] is always 0, optimizing ... Encoding state machine hpd_st[1:0] (view:work.COMMAND_DECODER(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : pcie_slave.v(260) | No possible illegal states for state machine hpd_st[1:0],safe FSM implementation is disabled Encoding state machine dma_loop_st[1:0] (view:work.COMMAND_DECODER(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : pcie_slave.v(180) | No possible illegal states for state machine dma_loop_st[1:0],safe FSM implementation is disabled @N: : pcie_slave.v(260) | Found counter in view:work.COMMAND_DECODER(verilog) inst clk_cnt[31:0] @N: : pcie_slave.v(301) | Found counter in view:work.COMMAND_DECODER(verilog) inst blink_cnt[23:0] Encoding state machine ahbcurr_state[2:0] (view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : ahblsramif.v(165) | Removing sequential instance HADDR_d[16] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(165) | Removing sequential instance HADDR_d[17] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(165) | Removing sequential instance HADDR_d[18] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(165) | Removing sequential instance HADDR_d[19] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs Encoding state machine sramcurr_state[2:0] (view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_SramCtrlIf_0s_32768s_8192s_512s_128s_32s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine hpd_curr_state[22:0] (view:work.HPDMA_CmdDec(verilog)) original code -> new code 00000 -> 00000000000000000000001 00001 -> 00000000000000000000010 00010 -> 00000000000000000000100 00011 -> 00000000000000000001000 00100 -> 00000000000000000010000 00101 -> 00000000000000000100000 00110 -> 00000000000000001000000 00111 -> 00000000000000010000000 01000 -> 00000000000000100000000 01001 -> 00000000000001000000000 01010 -> 00000000000010000000000 01011 -> 00000000000100000000000 01100 -> 00000000001000000000000 01101 -> 00000000010000000000000 01110 -> 00000000100000000000000 01111 -> 00000001000000000000000 10000 -> 00000010000000000000000 10001 -> 00000100000000000000000 10010 -> 00001000000000000000000 10011 -> 00010000000000000000000 10100 -> 00100000000000000000000 10101 -> 01000000000000000000000 10110 -> 10000000000000000000000 @W:MO160 : hpdma_cmddec.v(281) | Register bit hpd_curr_state[19] is always 0, optimizing ... Encoding state machine curr_state[6:0] (view:work.HPDMA_fsm_ctrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : hpdma_fsmctrl.v(579) | Removing sequential instance burstwrflag_last_n of view:PrimLib.dffse(prim) in hierarchy view:work.HPDMA_fsm_ctrl(verilog) because there are no references to its outputs @N: : hpdma_fsmctrl.v(693) | Found counter in view:work.HPDMA_fsm_ctrl(verilog) inst word_count[31:0] @W:MO160 : hpdma_fsmctrl.v(713) | Register bit fmhaddr_o[1] is always 0, optimizing ... @W:MO160 : hpdma_fsmctrl.v(713) | Register bit fmhaddr_o[0] is always 0, optimizing ... @W:MO160 : hpdma_fsmctrl.v(631) | Register bit cfrd_req_d1 is always 0, optimizing ... @N: : debounce.v(53) | Found counter in view:work.DEBOUNCE(verilog) inst q_reg[15:0] @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ... @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs Encoding state machine state[28:0] (view:work.CoreConfigMaster_Z3(verilog)) original code -> new code 000000 -> 00000000000000000000000000001 000001 -> 00000000000000000000000000010 000010 -> 00000000000000000000000000100 000011 -> 00000000000000000000000001000 000100 -> 00000000000000000000000010000 000101 -> 00000000000000000000000100000 000110 -> 00000000000000000000001000000 000111 -> 00000000000000000000010000000 001001 -> 00000000000000000000100000000 001010 -> 00000000000000000001000000000 001011 -> 00000000000000000010000000000 001100 -> 00000000000000000100000000000 001101 -> 00000000000000001000000000000 001110 -> 00000000000000010000000000000 001111 -> 00000000000000100000000000000 010000 -> 00000000000001000000000000000 010001 -> 00000000000010000000000000000 010010 -> 00000000000100000000000000000 010011 -> 00000000001000000000000000000 010100 -> 00000000010000000000000000000 010101 -> 00000000100000000000000000000 010110 -> 00000001000000000000000000000 100000 -> 00000010000000000000000000000 100001 -> 00000100000000000000000000000 100010 -> 00001000000000000000000000000 100011 -> 00010000000000000000000000000 100100 -> 00100000000000000000000000000 100101 -> 01000000000000000000000000000 100110 -> 10000000000000000000000000000 @N: : coreconfigmaster.v(723) | Found counter in view:work.CoreConfigMaster_Z3(verilog) inst pause_count[4:0] @W:MO160 : coreconfigmaster.v(723) | Register bit HSIZE[2] is always 0, optimizing ... @N:MF179 : coreconfigmaster.v(573) | Found 32 bit by 32 bit '==' comparator, 'd_state152' Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[15] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[11] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[7] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[14] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[10] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[6] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[2] removed due to constant propagation Encoding state machine state[2:0] (view:work.CoreConfigP_Z11(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ... Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z12(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z12(verilog) inst count_ddr[13:0] @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z12(verilog) inst count_sdif0[12:0] Encoding state machine state[3:0] (view:work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | No possible illegal states for state machine state[3:0],safe FSM implementation is disabled @N: : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) inst count[6:0] Encoding state machine config_st[2:0] (view:work.PCIe_Reg_Config(verilog)) original code -> new code 000 -> 00 011 -> 01 100 -> 10 @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[0] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[0] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(165) | Removing sequential instance COREAHBLSRAM_0.U_PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 178MB peak: 178MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(229) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[10] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_defaultslavesm.v(64) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.masterstage_2.default_slave_sm.defSlaveSMCurrentState in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 179MB) @N:BN362 : coreconfigmaster.v(723) | Removing sequential instance PCIe_HPDMA_0.ConfigMaster_0.state[8] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 163MB peak: 181MB) @N:FX404 : coreconfigmaster.v(164) | Found addmux in view:work.PCIe_HPDMA_top(verilog) inst PCIe_HPDMA_0.ConfigMaster_0.d_bytecount_0[15:0] from PCIe_HPDMA_0.ConfigMaster_0.un1_bytecount_16[15:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 164MB peak: 181MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 164MB peak: 181MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 163MB peak: 181MB) Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 164MB peak: 181MB) Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 210MB peak: 213MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:08s 0.87ns 2371 / 1491 2 0h:00m:08s 0.87ns 2228 / 1491 @N:FP130 : | Promoting Net un1_PCIe_HPDMA_0_1 on CLKINT I_968 @N:FP130 : | Promoting Net PCIe_HPDMA_0_INIT_DONE on CLKINT I_969 @N:FP130 : | Promoting Net PCIe_HPDMA_0_INIT_APB_S_PRESET_N on CLKINT I_970 @N:FP130 : | Promoting Net PCIe_HPDMA_0_INIT_APB_S_PCLK on CLKINT I_971 @N:FP130 : | Promoting Net PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm on CLKINT I_972 @N:FP130 : | Promoting Net PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_973 @N:FP130 : | Promoting Net PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_974 @N:FP130 : | Promoting Net PCIe_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_975 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 211MB peak: 213MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 213MB peak: 213MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 1416 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 111 clock pin(s) of sequential element(s) 0 instances converted, 111 sequential instances remain driven by gated/generated clocks =============================================================== Non-Gated/Non-Generated Clocks =============================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 PCIe_HPDMA_0.CCC_0.GL0_INST CLKINT 1343 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST ClockId0003 PCIe_HPDMA_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 38 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[12] ClockId0004 PCIe_HPDMA_0.CCC_0.GL3_INST CLKINT 35 PCIe_HPDMA_0.CORERESETP_0.genblk2.sdif0_phr.count[6] ============================================================================================================================================================== ============================================================================================= Gated/Generated Clocks ============================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST MSS_010 111 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_010 =================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 174MB peak: 213MB) Writing Analyst data base D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\synthesis\synwork\PCIe_HPDMA_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 206MB peak: 213MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 207MB peak: 213MB) Start final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 205MB peak: 213MB) @W:MT246 : pcie_hpdma_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT" Found clock PCIe_HPDMA_0.CCC_0.GL3_net with period 8.00ns Found clock PCIe_HPDMA_0.CCC_0.GL0_net with period 12.50ns @S |##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 22 15:04:10 2016 # Top view: PCIe_HPDMA_top Requested Frequency: 80.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\synthesis\PCIe_HPDMA_top_syn_1.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.427 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CCC_0.GL0_net 80.0 MHz 105.7 MHz 12.500 9.464 3.036 declared default_clkgroup PCIe_HPDMA_0.CCC_0.GL3_net 125.0 MHz 270.5 MHz 8.000 3.697 4.303 declared default_clkgroup PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 428.6 MHz 10.000 2.333 7.667 inferred Inferred_clkgroup_1 PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 128.9 MHz 10.000 7.758 1.427 inferred Inferred_clkgroup_0 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ===================================================================================================================================================================== @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CCC_0.GL0_net PCIe_HPDMA_0.CCC_0.GL0_net | 12.500 3.036 | No paths - | No paths - | No paths - PCIe_HPDMA_0.CCC_0.GL0_net PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_0.CCC_0.GL0_net PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_0.CCC_0.GL3_net PCIe_HPDMA_0.CCC_0.GL3_net | 8.000 4.303 | No paths - | No paths - | No paths - PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_0.CCC_0.GL0_net | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_0.CCC_0.GL3_net | Diff grp - | No paths - | No paths - | Diff grp - PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 2.242 | No paths - | 5.000 2.892 | 5.000 1.427 PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock PCIe_HPDMA_0.CCC_0.GL0_net | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 10.000 7.667 | No paths - | No paths - | No paths - ====================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PCIe_HPDMA_0.CCC_0.GL0_net ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_0.CCC_0.GL0_net MSS_010 F_HM0_ADDR[26] PCIe_HPDMA_HPMS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] 2.671 3.036 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_0.CCC_0.GL0_net MSS_010 F_HM0_ADDR[25] PCIe_HPDMA_HPMS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] 2.420 3.132 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_0.CCC_0.GL0_net MSS_010 F_HM0_TRANS1 PCIe_HPDMA_HPMS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] 2.577 3.490 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_0.CCC_0.GL0_net MSS_010 F_HM0_ADDR[24] PCIe_HPDMA_HPMS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] 2.569 3.767 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_0.CCC_0.GL0_net MSS_010 F_FM0_READYOUT CoreAHBLite_1_AHBmslave16_HREADY 2.481 3.783 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_0.CCC_0.GL0_net SERDESIF_0 M_AWADDR_HADDR[1] SERDES_IF_0_AHB_MASTER_HADDR[1] 3.749 3.931 PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] PCIe_HPDMA_0.CCC_0.GL0_net SLE Q arbRegSMCurrentState[9] 0.076 3.946 PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[13] PCIe_HPDMA_0.CCC_0.GL0_net SLE Q arbRegSMCurrentState[13] 0.076 3.971 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_0.CCC_0.GL0_net SERDESIF_0 M_AWADDR_HADDR[28] SERDES_IF_0_AHB_MASTER_HADDR[28] 3.538 3.975 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_0.CCC_0.GL0_net SERDESIF_0 M_AWADDR_HADDR[14] SERDES_IF_0_AHB_MASTER_HADDR[14] 3.738 3.986 ========================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_0.CCC_0.GL0_net SERDESIF_0 S_AWBURST_HTRANS[1] N_2100_i_0 11.769 3.036 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_0.CCC_0.GL0_net SERDESIF_0 S_AWID_HSEL[0] un1_masterAddrInProg_6_i_0 11.945 3.320 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[2] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[3] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[4] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[5] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[6] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[7] PCIe_HPDMA_0.CCC_0.GL0_net SLE EN N_195_i_0 12.207 3.344 =========================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.500 - Setup time: 0.731 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.769 - Propagation time: 8.733 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.036 Number of logic level(s): 5 Starting point: PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST / F_HM0_ADDR[26] Ending point: SERDES_IF_0.SERDESIF_INST / S_AWBURST_HTRANS[1] The start point is clocked by PCIe_HPDMA_0.CCC_0.GL0_net [rising] on pin CLK_BASE The end point is clocked by PCIe_HPDMA_0.CCC_0.GL0_net [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST MSS_010 F_HM0_ADDR[26] Out 2.671 2.671 - PCIe_HPDMA_HPMS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] Net - - 0.977 - 2 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR_i_m3[26] CFG3 B In - 3.648 - PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR_i_m3[26] CFG3 Y Out 0.143 3.791 - N_248 Net - - 0.706 - 8 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.address_decode.sdec_raw_0_a2_i_o2[0] CFG4 C In - 4.497 - PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.address_decode.sdec_raw_0_a2_i_o2[0] CFG4 Y Out 0.177 4.673 - N_245 Net - - 0.670 - 6 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL[0] CFG3 A In - 5.343 - PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL[0] CFG3 Y Out 0.087 5.430 - m0s0AddrSel Net - - 0.821 - 7 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_i[0] CFG3 C In - 6.251 - PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_i[0] CFG3 Y Out 0.182 6.433 - N_2088 Net - - 1.078 - 39 PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_i_RNI18JD6[0] CFG4 D In - 7.511 - PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_i_RNI18JD6[0] CFG4 Y Out 0.250 7.761 - N_2100_i_0 Net - - 0.971 - 1 SERDES_IF_0.SERDESIF_INST SERDESIF_0 S_AWBURST_HTRANS[1] In - 8.733 - =============================================================================================================================================================================================== Total path delay (propagation time + setup) of 9.464 is 4.241(44.8%) logic and 5.222(55.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_0.CCC_0.GL3_net ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count 0.094 4.303 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[0] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[0] 0.094 4.459 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[1] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[1] 0.094 4.527 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[4] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[4] 0.076 4.535 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[2] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[2] 0.076 4.603 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[3] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[3] 0.076 4.640 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[5] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[5] 0.094 5.232 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[6] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q count[6] 0.094 5.299 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[1] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q counte 0.094 5.432 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[1] PCIe_HPDMA_0.CCC_0.GL3_net SLE Q ltssm_q2[1] 0.094 5.456 ============================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] PCIe_HPDMA_0.CCC_0.GL3_net SLE D state_RNO[0] 7.778 4.303 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.hot_reset_n PCIe_HPDMA_0.CCC_0.GL3_net SLE EN N_1924_i_0 7.707 4.567 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[1] PCIe_HPDMA_0.CCC_0.GL3_net SLE D N_8 7.778 5.023 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet PCIe_HPDMA_0.CCC_0.GL3_net SLE D LTSSM_DetectQuiet_3 7.778 5.456 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled PCIe_HPDMA_0.CCC_0.GL3_net SLE D LTSSM_Disabled_3 7.778 5.456 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset PCIe_HPDMA_0.CCC_0.GL3_net SLE D LTSSM_HotReset_3 7.778 5.456 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[6] PCIe_HPDMA_0.CCC_0.GL3_net SLE D count_s[6] 7.778 5.541 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[5] PCIe_HPDMA_0.CCC_0.GL3_net SLE D count_s[5] 7.778 5.555 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[4] PCIe_HPDMA_0.CCC_0.GL3_net SLE D count_s[4] 7.778 5.569 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count[3] PCIe_HPDMA_0.CCC_0.GL3_net SLE D count_s[3] 7.778 5.583 ============================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 3.475 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 4.303 Number of logic level(s): 4 Starting point: PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] / Q Ending point: PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] / D The start point is clocked by PCIe_HPDMA_0.CCC_0.GL3_net [rising] on pin CLK The end point is clocked by PCIe_HPDMA_0.CCC_0.GL3_net [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] SLE Q Out 0.094 0.094 - count Net - - 0.848 - 12 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNIUFFE[4] CFG2 A In - 0.943 - PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNIUFFE[4] CFG2 Y Out 0.076 1.018 - m6_3 Net - - 0.483 - 1 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNIL6U72[5] CFG4 D In - 1.502 - PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNIL6U72[5] CFG4 Y Out 0.250 1.752 - N_16_mux Net - - 0.590 - 3 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO_0[0] CFG4 D In - 2.342 - PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO_0[0] CFG4 Y Out 0.276 2.618 - N_10 Net - - 0.483 - 1 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO[0] CFG4 D In - 3.101 - PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO[0] CFG4 Y Out 0.236 3.337 - state_RNO[0] Net - - 0.138 - 1 PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] SLE D In - 3.475 - ============================================================================================================================= Total path delay (propagation time + setup) of 3.697 is 1.154(31.2%) logic and 2.543(68.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.count_ddr[0] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[0] 0.094 7.667 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[0] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[0] 0.094 7.681 PCIe_HPDMA_0.CORERESETP_0.count_ddr[1] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[1] 0.094 7.732 PCIe_HPDMA_0.CORERESETP_0.count_ddr[2] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[2] 0.094 7.746 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[1] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[1] 0.094 7.746 PCIe_HPDMA_0.CORERESETP_0.count_ddr[3] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[3] 0.094 7.760 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[2] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[2] 0.094 7.760 PCIe_HPDMA_0.CORERESETP_0.count_ddr[4] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[4] 0.094 7.774 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[3] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[3] 0.094 7.774 PCIe_HPDMA_0.CORERESETP_0.count_ddr[5] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[5] 0.094 7.789 ===================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.count_ddr[13] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[13] 9.778 7.667 PCIe_HPDMA_0.CORERESETP_0.count_ddr[12] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[12] 9.778 7.681 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[12] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[12] 9.778 7.681 PCIe_HPDMA_0.CORERESETP_0.count_ddr[11] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[11] 9.778 7.695 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[11] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[11] 9.778 7.695 PCIe_HPDMA_0.CORERESETP_0.count_ddr[10] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[10] 9.778 7.709 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[10] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[10] 9.778 7.709 PCIe_HPDMA_0.CORERESETP_0.count_ddr[9] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[9] 9.778 7.723 PCIe_HPDMA_0.CORERESETP_0.count_sdif0[9] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[9] 9.778 7.723 PCIe_HPDMA_0.CORERESETP_0.count_ddr[8] PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[8] 9.778 7.738 ========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.111 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.667 Number of logic level(s): 14 Starting point: PCIe_HPDMA_0.CORERESETP_0.count_ddr[0] / Q Ending point: PCIe_HPDMA_0.CORERESETP_0.count_ddr[13] / D The start point is clocked by PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK The end point is clocked by PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.094 0.094 - count_ddr[0] Net - - 0.637 - 3 PCIe_HPDMA_0.CORERESETP_0.count_ddr_s_963 ARI1 B In - 0.732 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_s_963 ARI1 FCO Out 0.174 0.906 - count_ddr_s_963_FCO Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCI In - 0.906 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCO Out 0.014 0.920 - count_ddr_cry[1] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCI In - 0.920 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCO Out 0.014 0.935 - count_ddr_cry[2] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCI In - 0.935 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCO Out 0.014 0.949 - count_ddr_cry[3] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCI In - 0.949 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCO Out 0.014 0.963 - count_ddr_cry[4] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCI In - 0.963 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCO Out 0.014 0.977 - count_ddr_cry[5] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCI In - 0.977 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCO Out 0.014 0.991 - count_ddr_cry[6] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCI In - 0.991 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCO Out 0.014 1.006 - count_ddr_cry[7] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCI In - 1.006 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCO Out 0.014 1.020 - count_ddr_cry[8] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCI In - 1.020 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCO Out 0.014 1.034 - count_ddr_cry[9] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCI In - 1.034 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCO Out 0.014 1.048 - count_ddr_cry[10] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCI In - 1.048 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCO Out 0.014 1.062 - count_ddr_cry[11] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCI In - 1.062 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCO Out 0.014 1.077 - count_ddr_cry[12] Net - - 0.000 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr_s[13] ARI1 FCI In - 1.077 - PCIe_HPDMA_0.CORERESETP_0.count_ddr_s[13] ARI1 S Out 0.063 1.140 - count_ddr_s[13] Net - - 0.971 - 1 PCIe_HPDMA_0.CORERESETP_0.count_ddr[13] SLE D In - 2.111 - ========================================================================================================== Total path delay (propagation time + setup) of 2.333 is 0.724(31.1%) logic and 1.609(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORECONFIGP_0.psel PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 1.427 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock MSS_010 MDDR_FABRIC_PREADY CORECONFIGP_0_MDDR_APBmslave_PREADY 5.435 2.242 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[7] PCIe_HPDMA_0_SDIF0_INIT_APB_PRDATA[7] 5.613 2.362 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock MSS_010 MDDR_FABRIC_PRDATA[5] CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] 5.383 2.592 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock MSS_010 MDDR_FABRIC_PRDATA[2] CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] 5.382 2.593 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock MSS_010 MDDR_FABRIC_PRDATA[4] CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] 5.335 2.640 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[1] PCIe_HPDMA_0_SDIF0_INIT_APB_PRDATA[1] 5.053 2.742 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[6] PCIe_HPDMA_0_SDIF0_INIT_APB_PRDATA[6] 5.083 2.749 PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.MSS_ADLIB_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock MSS_010 MDDR_FABRIC_PRDATA[7] CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] 5.255 2.796 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[0] PCIe_HPDMA_0_SDIF0_INIT_APB_PRDATA[0] 5.118 2.824 =========================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PSEL PCIe_HPDMA_0_SDIF0_INIT_APB_PSELx 3.487 1.427 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata_N_3_mux_i_0 4.778 1.637 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[8] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[9] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[10] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[10] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[11] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[11] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[12] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[12] 4.778 1.702 PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[14] PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[14] 4.778 1.702 ============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.513 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.487 - Propagation time: 2.060 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.427 Number of logic level(s): 1 Starting point: PCIe_HPDMA_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.759 - 7 PCIe_HPDMA_0.CORECONFIGP_0.prdata_0_iv_0_a2_1_0[5] CFG3 B In - 0.853 - PCIe_HPDMA_0.CORECONFIGP_0.prdata_0_iv_0_a2_1_0[5] CFG3 Y Out 0.143 0.996 - PCIe_HPDMA_0_SDIF0_INIT_APB_PSELx Net - - 1.064 - 36 SERDES_IF_0.SERDESIF_INST SERDESIF_0 APB_PSEL In - 2.060 - =========================================================================================================================== Total path delay (propagation time + setup) of 3.573 is 1.750(49.0%) logic and 1.823(51.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 205MB peak: 213MB) Finished timing report (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 205MB peak: 213MB) --------------------------------------- Resource Usage Report for PCIe_HPDMA_top Mapping to part: m2gl010tfbga484-1 Cell usage: CCC 1 use CLKINT 11 uses MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_0 1 use SYSRESET 1 use CFG1 13 uses CFG2 497 uses CFG3 352 uses CFG4 1032 uses Carry primitives used for arithmetic functions: ARI1 301 uses Sequential Cells: SLE 1491 uses DSP Blocks: 0 I/O ports: 84 I/O primitives: 65 BIBUF 20 uses INBUF 8 uses INBUF_DIFF 1 use OUTBUF 35 uses OUTBUF_DIFF 1 use Global Clock Buffers: 11 RAM/ROM usage summary Block Rams (RAM1K18) : 16 Total LUTs: 2195 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 576; LUTs = 576; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 1491 + 0 + 576 + 0 = 2067; Total number of LUTs after P&R: 2195 + 0 + 576 + 0 = 2771; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 59MB peak: 213MB) Process took 0h:00m:12s realtime, 0h:00m:12s cputime # Mon Feb 22 15:04:10 2016 ###########################################################]