@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3626:2:3626:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_16,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_15
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3166:2:3166:13|Removing user instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT530 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 111 sequential elements including PCIe_HPDMA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 46 sequential elements including PCIe_HPDMA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
