@W: MO111 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_FABOSC_0_OSC) 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance PCIe_HPDMA_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif3_core,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif3_core_q1,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core_q1
@W: BN132 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.release_sdif2_core_q1,  because it is equivalent to instance PCIe_HPDMA_0.CORERESETP_0.release_sdif1_core_q1
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":283:3:283:8|Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":283:3:283:8|Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":283:3:283:8|Register bit COREHPDMACTRL_0.U_UserIF.ustart_o_1[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":484:3:484:8|Register bit COREHPDMACTRL_0.U_UserIF.error_intr1 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":484:3:484:8|Register bit COREHPDMACTRL_0.U_UserIF.error_intr2 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":484:3:484:8|Register bit COREHPDMACTRL_0.U_UserIF.error_intr3 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":572:3:572:8|Register bit COREHPDMACTRL_0.U_UserIF.done_intr1 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":572:3:572:8|Register bit COREHPDMACTRL_0.U_UserIF.done_intr2 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_userif.v":572:3:572:8|Register bit COREHPDMACTRL_0.U_UserIF.done_intr3 is always 0, optimizing ...
@W: MO129 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Sequential instance AHB_IF_0.ahb_fsm_current_state[4] reduced to a combinational gate by constant propagation
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit ahb_fsm_current_state[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit ahb_fsm_current_state[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA_int[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[31] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[29] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[28] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[27] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[26] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[25] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[24] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[23] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[22] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[21] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[20] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[18] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[17] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[14] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[13] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[10] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[9] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[5] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[3] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\ahb_if.v":81:0:81:5|Register bit HWDATA[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_cmddec.v":281:3:281:8|Register bit hpd_curr_state[19] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_fsmctrl.v":713:3:713:8|Register bit fmhaddr_o[1] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_fsmctrl.v":713:3:713:8|Register bit fmhaddr_o[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_fsmctrl.v":631:2:631:7|Register bit cfrd_req_d1 is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Register bit HSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[11] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[7] is always 0, optimizing ...
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] is always 0, optimizing ...
@W: MO197 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[14] removed due to constant propagation
@W: MO197 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[10] removed due to constant propagation
@W: MO197 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[6] removed due to constant propagation
@W: MO197 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[2] removed due to constant propagation
@W: MO160 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit paddr[16] is always 0, optimizing ...
@W: MT246 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma\ccc_0\pcie_hpdma_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock PCIe_HPDMA_HPMS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_0.PCIe_HPDMA_HPMS_0.FIC_2_APB_M_PCLK"
@W: MT420 |Found inferred clock PCIe_HPDMA_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT"
