@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT480 :"d:/pcie/igl2_hpdma/11.7/m2gl_dg0585_hpms_hpdma_liberov11p6_df/liberoproject/pcie_hpdma/synthesis/pcie_hpdma_top_syn_1.fdc":18:0:18:0|Assigning clock "PCIe_HPDMA_0.CCC_0.GL0_net" to command: create_clock {n:PCIe_HPDMA_0.CCC_0.GL0_net} -period {12.5} -waveform {0 6.25} -add 
@N: MT480 :"d:/pcie/igl2_hpdma/11.7/m2gl_dg0585_hpms_hpdma_liberov11p6_df/liberoproject/pcie_hpdma/synthesis/pcie_hpdma_top_syn_1.fdc":19:0:19:0|Assigning clock "PCIe_HPDMA_0.CCC_0.GL3_net" to command: create_clock {n:PCIe_HPDMA_0.CCC_0.GL3_net} -period {8} -waveform {0 4} -add 
@N: MO225 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\pcie_slave.v":260:0:260:5|No possible illegal states for state machine hpd_st[1:0],safe FSM implementation is disabled
@N: MO225 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\hdl\pcie_slave.v":180:0:180:5|No possible illegal states for state machine dma_loop_st[1:0],safe FSM implementation is disabled
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[16] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[17] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[18] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[19] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\corehpdmactrl\2.1.103\rtl\vlog\core\ hpdma_fsmctrl.v":579:2:579:7|Removing sequential instance burstwrflag_last_n of view:PrimLib.dffse(prim) in hierarchy view:work.HPDMA_fsm_ctrl(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: MF179 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":573:21:573:46|Found 32 bit by 32 bit '==' comparator, 'd_state152'
@N: MO225 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|No possible illegal states for state machine state[3:0],safe FSM implementation is disabled
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[0] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[0] in hierarchy view:work.PCIe_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance COREAHBLSRAM_0.U_PCIe_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance PCIe_HPDMA_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[10] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":64:4:64:9|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_1.matrix4x16.masterstage_2.default_slave_sm.defSlaveSMCurrentState in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Removing sequential instance PCIe_HPDMA_0.ConfigMaster_0.state[8] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance PCIe_HPDMA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.PCIe_HPDMA_top(verilog) because there are no references to its outputs 
@N: FX404 :"d:\pcie\igl2_hpdma\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\liberoproject\pcie_hpdma\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":164:8:164:11|Found addmux in view:work.PCIe_HPDMA_top(verilog) inst PCIe_HPDMA_0.ConfigMaster_0.d_bytecount_0[15:0] from PCIe_HPDMA_0.ConfigMaster_0.un1_bytecount_16[15:0] 
@N: FP130 |Promoting Net un1_PCIe_HPDMA_0_1 on CLKINT  I_968 
@N: FP130 |Promoting Net PCIe_HPDMA_0_INIT_DONE on CLKINT  I_969 
@N: FP130 |Promoting Net PCIe_HPDMA_0_INIT_APB_S_PRESET_N on CLKINT  I_970 
@N: FP130 |Promoting Net PCIe_HPDMA_0_INIT_APB_S_PCLK on CLKINT  I_971 
@N: FP130 |Promoting Net PCIe_HPDMA_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm on CLKINT  I_972 
@N: FP130 |Promoting Net PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_973 
@N: FP130 |Promoting Net PCIe_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_974 
@N: FP130 |Promoting Net PCIe_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT  I_975 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
