@W: CG360 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\AHB_IF.v":60:13:60:21|No assignment to wire HSIZE_int
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\AHB_IF.v":81:0:81:5|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\AHB_IF.v":81:0:81:5|Pruning register bit 0 of HTRANS[1:0] 
@W: CL271 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":75:0:75:5|Pruning bits 31 to 21 of dma_size[31:0] -- not in use ...
@W: CL113 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":75:0:75:5|Feedback mux created for signal HREADYOUT.
@W: CL113 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":75:0:75:5|Feedback mux created for signal HREADY.
@W: CL251 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":75:0:75:5|All reachable assignments to HREADYOUT assign 1, register removed by optimization
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_PAU_RES[1] to a constant 1
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_PAU_RES[2] to a constant 1
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_PAU_RES[3] to a constant 1
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_VALID[1] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_VALID[2] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Optimizing register bit HPD_VALID[3] to a constant 0
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Pruning register bits 3 to 1 of HPD_VALID[3:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":180:0:180:5|Pruning register bits 3 to 1 of HPD_PAU_RES[3:0] 
@W: CG775 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:48|Found Component PCIe_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":165:3:165:8|Pruning register HWDATA_d[31:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":165:3:165:8|Pruning register HTRANS_d[1:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":165:3:165:8|Pruning register HSEL_d 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":165:3:165:8|Pruning register HREADYIN_d 
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":118:36:118:45|No assignment to writeData0
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":119:36:119:45|No assignment to writeData1
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":120:36:120:45|No assignment to writeData2
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":121:36:121:45|No assignment to writeData3
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":122:36:122:45|No assignment to writeData4
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":123:36:123:45|No assignment to writeData5
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":124:36:124:45|No assignment to writeData6
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":125:36:125:45|No assignment to writeData7
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":126:36:126:45|No assignment to writeData8
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":127:36:127:45|No assignment to writeData9
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":128:36:128:46|No assignment to writeData10
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":129:36:129:46|No assignment to writeData11
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":130:36:130:46|No assignment to writeData12
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":131:36:131:46|No assignment to writeData13
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":132:36:132:46|No assignment to writeData14
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":133:36:133:46|No assignment to writeData15
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":134:36:134:46|No assignment to writeData16
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":154:35:154:44|No assignment to writeAddr0
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":155:35:155:44|No assignment to writeAddr1
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":156:35:156:44|No assignment to writeAddr2
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":157:35:157:44|No assignment to writeAddr3
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":158:35:158:44|No assignment to writeAddr4
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":159:35:159:44|No assignment to writeAddr5
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":160:35:160:44|No assignment to writeAddr6
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":161:35:161:44|No assignment to writeAddr7
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":162:35:162:44|No assignment to writeAddr8
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":163:35:163:44|No assignment to writeAddr9
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":164:35:164:45|No assignment to writeAddr10
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":165:35:165:45|No assignment to writeAddr11
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":166:35:166:45|No assignment to writeAddr12
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":167:35:167:45|No assignment to writeAddr13
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":168:35:168:45|No assignment to writeAddr14
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":169:35:169:45|No assignment to writeAddr15
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":170:35:170:45|No assignment to writeAddr16
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":172:35:172:43|No assignment to readAddr0
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":173:35:173:43|No assignment to readAddr1
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":174:35:174:43|No assignment to readAddr2
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":175:35:175:43|No assignment to readAddr3
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":176:35:176:43|No assignment to readAddr4
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":177:35:177:43|No assignment to readAddr5
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":178:35:178:43|No assignment to readAddr6
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":179:35:179:43|No assignment to readAddr7
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":180:35:180:43|No assignment to readAddr8
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":181:35:181:43|No assignment to readAddr9
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":182:35:182:44|No assignment to readAddr10
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":183:35:183:44|No assignment to readAddr11
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":184:35:184:44|No assignment to readAddr12
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":185:35:185:44|No assignment to readAddr13
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":186:35:186:44|No assignment to readAddr14
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":187:35:187:44|No assignment to readAddr15
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":188:35:188:44|No assignment to readAddr16
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":218:4:218:9|Pruning register ckRdAddr[15:9] 
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":98:31:98:49|No assignment to ahbsram_wdata_upd_r
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":99:31:99:51|No assignment to u_ahbsram_wdata_upd_r
@W: CG360 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":106:31:106:42|No assignment to wire u_BUSY_all_0
@W: CG360 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":107:31:107:42|No assignment to wire u_BUSY_all_1
@W: CG360 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":108:31:108:42|No assignment to wire u_BUSY_all_2
@W: CG360 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":109:31:109:42|No assignment to wire u_BUSY_all_3
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":614:3:614:8|Pruning register done_intr0_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":614:3:614:8|Pruning register done_intr1_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":614:3:614:8|Pruning register done_intr2_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":614:3:614:8|Pruning register done_intr3_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":526:3:526:8|Pruning register error_intr0_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":526:3:526:8|Pruning register error_intr1_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":526:3:526:8|Pruning register error_intr2_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":526:3:526:8|Pruning register error_intr3_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":347:3:347:8|Pruning register new_serv_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":347:3:347:8|Pruning register ucvalid_d1[3:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":347:3:347:8|Pruning register ustart_d1[3:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":347:3:347:8|Pruning register cudmacyc_end_d2 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":261:3:261:8|Pruning register udone_d1[3:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_UserIF.v":261:3:261:8|Pruning register uerror_d1[3:0] 
@W: CG133 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":199:29:199:36|No assignment to fcpop_d1
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":652:3:652:8|Pruning register fctrans_done_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":652:3:652:8|Pruning register fctrans_done_d2 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Pruning register cfburst_len_rd_d1[31:0] 
@W: CL207 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":730:3:730:8|All reachable assignments to cfrd_req_o assign 0, register removed by optimization.
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[1] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[2] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[3] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[4] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[5] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[6] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[7] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[8] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[9] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[10] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[11] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[12] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[13] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[14] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[15] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[16] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[17] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[18] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[19] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[20] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[21] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[22] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[23] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[24] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[25] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[26] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[27] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[28] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[29] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[30] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Optimizing register bit cfburst_len_wr_d1[31] to a constant 0
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":243:3:243:8|Pruning register bits 31 to 1 of cfburst_len_wr_d1[31:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":881:3:881:8|Pruning register busreq_prev 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":863:6:863:11|Pruning register pop_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":800:5:800:10|Pruning register fmhtrans_int2[1:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":666:3:666:8|Pruning register haddr_prev[29:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":647:2:647:7|Pruning register latch_addr_d2 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":647:2:647:7|Pruning register latch_addr_d3 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":606:2:606:7|Pruning register latch_addr_d1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":594:2:594:7|Pruning register state_prev_clk[3:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":274:3:274:8|Pruning register clr_req 
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":262:3:262:8|Optimizing register bit fmhburst_d1[1] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":262:3:262:8|Optimizing register bit fmhburst_d1[2] to a constant 0
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":785:5:785:10|Optimizing register bit fmhtrans_int[0] to a constant 0
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":262:3:262:8|Pruning register bits 2 to 1 of fmhburst_d1[2:0] 
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":785:5:785:10|Pruning register bit 0 of fmhtrans_int[1:0] 
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Pruning register bit 0 of HTRANS[1:0] 
@W: CG775 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CL113 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Feedback mux created for signal READ.
@W: CL250 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|All reachable assignments to READ assign 0, register removed by optimization
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[0] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[1] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[2] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[4] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[5] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[8] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[9] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[10] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[11] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[12] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[13] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[14] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[16] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[18] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[19] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[20] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[21] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[22] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[23] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[24] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[25] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[26] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[27] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[28] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[29] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit ADDR[31] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[0] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[1] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[2] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[3] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[4] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[5] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[6] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[7] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[8] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[9] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[10] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[11] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[12] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[13] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[14] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[15] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[16] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[17] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[18] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[19] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[20] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[21] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[22] is always 0, optimizing ...
@W: CL189 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Register bit DATAOUT[23] is always 0, optimizing ...
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bit 31 of ADDR[31:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bits 29 to 18 of ADDR[31:0] 
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bit 16 of ADDR[31:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bits 14 to 8 of ADDR[31:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bits 5 to 4 of ADDR[31:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bits 2 to 0 of ADDR[31:0] 
@W: CL279 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bits 23 to 0 of DATAOUT[31:0] 
@W: CL260 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":47:0:47:5|Pruning register bit 7 of ADDR[7:6] 
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":27:21:27:26|Input DATAIN is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Reg_Config.v":33:11:33:15|Input VALID is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_HPMS\PCIe_HPDMA_HPMS.v":89:14:89:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL157 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA\FABOSC_0\PCIe_HPDMA_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bit 31 of prdata[31:0] is unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bits 25 to 0 of prdata[31:0] are unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":123:15:123:23|Input HBURST_M0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":124:15:124:22|Input HPROT_M0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":134:15:134:23|Input HBURST_M1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":135:15:135:22|Input HPROT_M1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":145:15:145:23|Input HBURST_M2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":146:15:146:22|Input HPROT_M2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":156:15:156:23|Input HBURST_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":157:15:157:22|Input HPROT_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":69:18:69:26|Input HWDATA_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":73:18:73:26|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":74:13:74:24|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":75:13:75:20|Input HRESP_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":84:18:84:26|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":85:13:85:24|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":86:13:86:20|Input HRESP_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":95:18:95:26|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":96:13:96:24|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":97:13:97:20|Input HRESP_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":106:18:106:26|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":107:13:107:24|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":108:13:108:20|Input HRESP_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":117:18:117:26|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":118:13:118:24|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":119:13:119:20|Input HRESP_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":128:18:128:26|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":129:13:129:24|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":130:13:130:20|Input HRESP_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":139:18:139:26|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":140:13:140:24|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":141:13:141:20|Input HRESP_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":150:18:150:26|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":151:13:151:24|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":152:13:152:20|Input HRESP_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":161:18:161:26|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":162:13:162:24|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":163:13:163:20|Input HRESP_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":172:18:172:26|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":173:13:173:24|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":174:13:174:20|Input HRESP_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":183:18:183:27|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":184:13:184:25|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":185:13:185:21|Input HRESP_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":194:18:194:27|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":195:13:195:25|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":196:13:196:21|Input HRESP_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":205:18:205:27|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":206:13:206:25|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":207:13:207:21|Input HRESP_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":216:18:216:27|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":217:13:217:25|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":218:13:218:21|Input HRESP_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":227:18:227:27|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":228:13:228:25|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":229:13:229:21|Input HRESP_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":238:18:238:27|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":239:13:239:25|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":240:13:240:21|Input HRESP_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input SDATAREADY is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input SHRESP is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S16 is unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":123:15:123:23|Input HBURST_M0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":124:15:124:22|Input HPROT_M0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":134:15:134:23|Input HBURST_M1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":135:15:135:22|Input HPROT_M1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":145:15:145:23|Input HBURST_M2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":146:15:146:22|Input HPROT_M2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":156:15:156:23|Input HBURST_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":157:15:157:22|Input HPROT_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":51:18:51:26|Input HWDATA_M1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":60:18:60:26|Input HWDATA_M2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":69:18:69:26|Input HWDATA_M3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":95:18:95:26|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":96:13:96:24|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":97:13:97:20|Input HRESP_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":106:18:106:26|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":107:13:107:24|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":108:13:108:20|Input HRESP_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":117:18:117:26|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":118:13:118:24|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":119:13:119:20|Input HRESP_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":128:18:128:26|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":129:13:129:24|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":130:13:130:20|Input HRESP_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":139:18:139:26|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":140:13:140:24|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":141:13:141:20|Input HRESP_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":150:18:150:26|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":151:13:151:24|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":152:13:152:20|Input HRESP_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":161:18:161:26|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":162:13:162:24|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":163:13:163:20|Input HRESP_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":172:18:172:26|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":173:13:173:24|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":174:13:174:20|Input HRESP_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":183:18:183:27|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":184:13:184:25|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":185:13:185:21|Input HRESP_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":194:18:194:27|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":195:13:195:25|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":196:13:196:21|Input HRESP_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":205:18:205:27|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":206:13:206:25|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":207:13:207:21|Input HRESP_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":216:18:216:27|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":217:13:217:25|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":218:13:218:21|Input HRESP_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":227:18:227:27|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":228:13:228:25|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":229:13:229:21|Input HRESP_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":238:18:238:27|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":239:13:239:25|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":240:13:240:21|Input HRESP_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":249:18:249:27|Input HRDATA_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":250:13:250:25|Input HREADYOUT_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":251:13:251:21|Input HRESP_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input SDATAREADY is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input SHRESP is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S16 is unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 2 of SDATAREADY[16:0] are unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 2 of SHRESP[16:0] are unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S16 is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_AHBLMasterIF.v":72:28:72:31|Input HCLK is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_AHBLMasterIF.v":73:28:73:34|Input HRESETN is unused
@W: CL190 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":262:3:262:8|Optimizing register bit fmhburst_d1[0] to a constant 0
@W: CL169 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_FSMCtrl.v":262:3:262:8|Pruning register fmhburst_d1[0] 
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\Actel\DirectCore\COREHPDMACTRL\2.1.103\rtl\vlog\core\ HPDMA_CmdDec.v":137:29:137:39|Input fcdataout_i is unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":69:28:69:32|Input port bits 31 to 20 of HADDR[31:0] are unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":62:26:62:34|Input port bits 15 to 14 of writeAddr[15:0] are unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":61:26:61:28|Input ren is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":63:26:63:33|Input readAddr is unused
@W: CL246 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":75:29:75:40|Input port bits 19 to 18 of ahbsram_addr[19:0] are unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\component\work\PCIe_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":98:28:98:31|Input BUSY is unused
@W: CL247 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":27:20:27:25|Input port bit 0 of HTRANS[1:0] is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":34:20:34:24|Input HSIZE is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":49:18:49:26|Input HPD_ERROR is unused
@W: CL159 :"D:\PCIE\IGL2_HPDMA\11.7\m2gl_dg0585_hpms_hpdma_liberov11p6_df\LiberoProject\PCIe_HPDMA\hdl\PCIe_Slave.v":50:18:50:26|Input HPD_START is unused

