@W: BN137 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\standby_control.vhd":119:0:119:5|Found combinational loop during mapping at net Standby_Control_0.PLL_PowerDown
@W: MT530 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\cnt_up.vhd":40:6:40:7|Found inferred clock IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock which controls 6003 sequential elements including Fabric_Logic_0.U1.F\.0\.F0\.U1.CNTVAL[17:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\we_cnt.vhd":64:6:64:7|Found inferred clock WE_CNT|TC_inferred_clock which controls 1 sequential elements including Fabric_Logic_0.U2.U2.U3.WE_REG. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\wa_cnt.vhd":38:6:38:7|Found inferred clock WE_CNT|WE_inferred_clock which controls 218 sequential elements including Fabric_Logic_0.U2.U2.U1.CNTVAL[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
