@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\work\IGL2_Standby\IGL2_Standby.vhd":17:7:17:18|Top entity is set to IGL2_Standby.
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\work\IGL2_Standby\IGL2_Standby.vhd":17:7:17:18|Synthesizing work.igl2_standby.rtl 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\Standby_Control.vhd":23:7:23:21|Synthesizing work.standby_control.bh 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":215:10:215:13|Synthesizing smartfusion2.nor2.syn_black_box 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":191:10:191:13|Synthesizing smartfusion2.and2.syn_black_box 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":342:10:342:12|Synthesizing smartfusion2.inv.syn_black_box 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\work\IGL2_Standby\OSC_0\IGL2_Standby_OSC_0_OSC.vhd":8:7:8:28|Synthesizing work.igl2_standby_osc_0_osc.def_arch 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":39:7:39:12|Synthesizing work.xtlosc.def_arch 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":95:7:95:16|Synthesizing work.xtlosc_fab.def_arch 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\component\work\IGL2_Standby\FCCC_0\IGL2_Standby_FCCC_0_FCCC.vhd":8:7:8:30|Synthesizing work.igl2_standby_fccc_0_fccc.def_arch 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":794:10:794:12|Synthesizing smartfusion2.ccc.syn_black_box 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\Fabric_Logic.vhd":22:7:22:18|Synthesizing work.fabric_logic.struct 
@N: CD364 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\Fabric_Logic.vhd":82:4:82:9|Removed redundant assignment
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\shift_register.vhd":23:7:23:20|Synthesizing work.shift_register.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\DFN1C0_18.vhd":23:7:23:15|Synthesizing work.dfn1c0_18.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\DFN1C0_18.vhd":36:10:36:15|Synthesizing work.dfn1c0.syn_black_box 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\MULT11_LSRAM11.vhd":21:7:21:20|Synthesizing work.mult11_lsram11.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\MUXBUS.vhd":21:7:21:12|Synthesizing work.muxbus.rtl 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\LSRAM1Kx18.vhd":22:7:22:16|Synthesizing work.lsram1kx18.behav 
@N: CL134 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\LSRAM1Kx18.vhd":36:7:36:12|Found RAM ramtmp, depth=1024, width=18
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\SIGN8x8_MULT.vhd":22:7:22:20|Synthesizing work.sign18x18_mult.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\WE_AD_GEN.vhd":21:7:21:15|Synthesizing work.we_ad_gen.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\WE_CNT.vhd":21:7:21:12|Synthesizing work.we_cnt.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\RA_CNT.vhd":21:7:21:12|Synthesizing work.ra_cnt.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\WA_CNT.vhd":21:7:21:12|Synthesizing work.wa_cnt.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\CNT_UP269.vhd":23:7:23:15|Synthesizing work.cnt_up269.struct 
@N: CD630 :"F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\hdl\CNT_UP.vhd":21:7:21:12|Synthesizing work.cnt_up.struct 
@N|Running in 64-bit mode

