@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\sign8x8_mult.vhd":43:6:43:7|Removing sequential instance Fabric_Logic_0.U2.F.5.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.5.U3.DIN1_REG[17:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\sign8x8_mult.vhd":43:6:43:7|Removing sequential instance Fabric_Logic_0.U2.F.0.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U3.DIN1_REG[17:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\sign8x8_mult.vhd":43:6:43:7|Removing sequential instance Fabric_Logic_0.U2.F.2.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.2.U3.DIN1_REG[17:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\sign8x8_mult.vhd":43:6:43:7|Removing sequential instance Fabric_Logic_0.U2.F.1.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.1.U3.DIN1_REG[17:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.9.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.10.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.2.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.5.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.8.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN132 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":43:4:43:5|Removing sequential instance Fabric_Logic_0.U2.F.7.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
@W: BN137 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\standby_control.vhd":119:0:119:5|Found combinational loop during mapping at net Standby_Control_0_PLL_PowerDown
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\lsram1kx18.vhd":36:7:36:12|No read/write conflict check. Possible simulation mismatch!
@W: BN137 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\hdl\standby_control.vhd":119:0:119:5|Found combinational loop during mapping at net Standby_Control_0.Standby_Control_0_PLL_PowerDown
@W: MT246 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\component\work\igl2_standby\osc_0\igl2_standby_osc_0_osc.vhd":53:4:53:11|Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"f:\microsemi_prj\igl2_standby_tutorial\libero_project\igl2_standby\component\work\igl2_standby\fccc_0\igl2_standby_fccc_0_fccc.vhd":108:4:108:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"
@W: MT420 |Found inferred clock WE_CNT|WE_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Fabric_Logic_0.U2.U2.U3.WE"
@W: MT420 |Found inferred clock WE_CNT|TC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Fabric_Logic_0.U2.U2.U3.TC"
