Project Settings
Project Name | IGL2_Standby_syn | Implementation Name | synthesis
Top Module | work.IGL2_Standby | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 34 | 5 | 0 | - | 0m:01s | - | 2/18/2016 3:59:28 PM
(premap) | Complete | 3 | 4 | 0 | 0m:00s | 0m:01s | 157MB | 2/18/2016 3:59:31 PM
(fpga_mapper) | Complete | 220 | 28 | 0 | 0m:12s | 0m:12s | 180MB | 2/18/2016 3:59:44 PM
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 2/18/2016 3:59:30 PM
Area Summary
Carry Cells | 5185 | Sequential Cells | 4952
DSP Blocks (MACC) (dsp_used) | 11 | I/O Cells | 43
Global Clock Buffers | 5 | Block Rams (RAM1K18) (v_ram) | 11
LUTs (total_luts) | 5361 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 324.8 MHz | 6.921
WE_CNT|TC_inferred_clock | 100.0 MHz | 659.0 MHz | 8.482
WE_CNT|WE_inferred_clock | 100.0 MHz | 380.3 MHz | 7.371
System | 100.0 MHz | 149.5 MHz | 3.309
Optimizations Summary
Combined Clock Conversion | 1 / 2 |  |