`

    #Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
    #install: F:\Microsemi\Libero_SoC_v11.7\Synplify
    #OS: Windows 7 6.1
    #Hostname: W764-HARISAKOL

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : IGL2_Standby.vhd(17) | Top entity is set to IGL2_Standby.
    VHDL syntax check successful!
    @N:CD630 : IGL2_Standby.vhd(17) | Synthesizing work.igl2_standby.rtl
    @N:CD630 : Standby_Control.vhd(23) | Synthesizing work.standby_control.bh
    @N:CD630 : smartfusion2.vhd(215) | Synthesizing smartfusion2.nor2.syn_black_box
    Post processing for smartfusion2.nor2.syn_black_box
    @N:CD630 : smartfusion2.vhd(191) | Synthesizing smartfusion2.and2.syn_black_box
    Post processing for smartfusion2.and2.syn_black_box
    @N:CD630 : smartfusion2.vhd(342) | Synthesizing smartfusion2.inv.syn_black_box
    Post processing for smartfusion2.inv.syn_black_box
    Post processing for work.standby_control.bh
    @N:CD630 : IGL2_Standby_OSC_0_OSC.vhd(8) | Synthesizing work.igl2_standby_osc_0_osc.def_arch
    @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box
    Post processing for smartfusion2.clkint.syn_black_box
    @N:CD630 : osc_comps.vhd(39) | Synthesizing work.xtlosc.def_arch
    Post processing for work.xtlosc.def_arch
    @N:CD630 : osc_comps.vhd(95) | Synthesizing work.xtlosc_fab.def_arch
    Post processing for work.xtlosc_fab.def_arch
    Post processing for work.igl2_standby_osc_0_osc.def_arch
    @W:CL240 : IGL2_Standby_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : IGL2_Standby_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : IGL2_Standby_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : IGL2_Standby_OSC_0_OSC.vhd(11) | RCOSC_25_50MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @N:CD630 : IGL2_Standby_FCCC_0_FCCC.vhd(8) | Synthesizing work.igl2_standby_fccc_0_fccc.def_arch
    @N:CD630 : smartfusion2.vhd(794) | Synthesizing smartfusion2.ccc.syn_black_box
    Post processing for smartfusion2.ccc.syn_black_box
    @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    Post processing for work.igl2_standby_fccc_0_fccc.def_arch
    @N:CD630 : Fabric_Logic.vhd(22) | Synthesizing work.fabric_logic.struct
    @N:CD364 : Fabric_Logic.vhd(82) | Removed redundant assignment
    @N:CD630 : shift_register.vhd(23) | Synthesizing work.shift_register.struct
    @N:CD630 : DFN1C0_18.vhd(23) | Synthesizing work.dfn1c0_18.struct
    @W:CD280 : DFN1C0_18.vhd(36) | Unbound component DFN1C0 mapped to black box
    @N:CD630 : DFN1C0_18.vhd(36) | Synthesizing work.dfn1c0.syn_black_box
    Post processing for work.dfn1c0.syn_black_box
    Post processing for work.dfn1c0_18.struct
    Post processing for work.shift_register.struct
    @N:CD630 : MULT11_LSRAM11.vhd(21) | Synthesizing work.mult11_lsram11.struct
    @N:CD630 : MUXBUS.vhd(21) | Synthesizing work.muxbus.rtl
    Post processing for work.muxbus.rtl
    @N:CD630 : LSRAM1Kx18.vhd(22) | Synthesizing work.lsram1kx18.behav
    Post processing for work.lsram1kx18.behav
    @N:CL134 : LSRAM1Kx18.vhd(36) | Found RAM ramtmp, depth=1024, width=18
    @N:CD630 : SIGN8x8_MULT.vhd(22) | Synthesizing work.sign18x18_mult.struct
    Post processing for work.sign18x18_mult.struct
    @N:CD630 : WE_AD_GEN.vhd(21) | Synthesizing work.we_ad_gen.struct
    @N:CD630 : WE_CNT.vhd(21) | Synthesizing work.we_cnt.struct
    Post processing for work.we_cnt.struct
    @N:CD630 : RA_CNT.vhd(21) | Synthesizing work.ra_cnt.struct
    Post processing for work.ra_cnt.struct
    @N:CD630 : WA_CNT.vhd(21) | Synthesizing work.wa_cnt.struct
    Post processing for work.wa_cnt.struct
    Post processing for work.we_ad_gen.struct
    Post processing for work.mult11_lsram11.struct
    @N:CD630 : CNT_UP269.vhd(23) | Synthesizing work.cnt_up269.struct
    @N:CD630 : CNT_UP.vhd(21) | Synthesizing work.cnt_up.struct
    Post processing for work.cnt_up.struct
    Post processing for work.cnt_up269.struct
    Post processing for work.fabric_logic.struct
    Post processing for work.igl2_standby.rtl

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Feb 18 15:59:28 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Feb 18 15:59:28 2016

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Feb 18 15:59:28 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Feb 18 15:59:30 2016

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: IGL2_Standby_scck.rpt
    Printing clock  summary report in "F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\synthesis\IGL2_Standby_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 107MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)

    Warning: Found 1 combinational loops!
    @W:BN137 : standby_control.vhd(119) | Found combinational loop during mapping at net Standby_Control_0.PLL_PowerDown
    1) instance NOR2_0 (view:work.Standby_Control(bh)), output net "PLL_PowerDown" in work.Standby_Control(bh)
        net        Standby_Control_0.PLL_PowerDown
        input  pin Standby_Control_0.NOR2_1/B
        instance   Standby_Control_0.NOR2_1 (cell NOR2)
        output pin Standby_Control_0.NOR2_1/Y
        net        Standby_Control_0.NOR2_1_Y
        input  pin Standby_Control_0.NOR2_0/B
        instance   Standby_Control_0.NOR2_0 (cell NOR2)
        output pin Standby_Control_0.NOR2_0/Y
        net        Standby_Control_0.PLL_PowerDown
    End of loops
    syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist IGL2_Standby

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 153MB peak: 157MB)

    @S |Clock Summary
    *****************

    Start                                               Requested     Requested     Clock        Clock
    Clock                                               Frequency     Period        Type         Group
    ----------------------------------------------------------------------------------------------------------------
    IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    System                                              100.0 MHz     10.000        system       system_clkgroup
    WE_CNT|TC_inferred_clock                            100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    WE_CNT|WE_inferred_clock                            100.0 MHz     10.000        inferred     Inferred_clkgroup_2
    ================================================================================================================

    @W:MT530 : cnt_up.vhd(40) | Found inferred clock IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock which controls 6003 sequential elements including Fabric_Logic_0.U1.F\.0\.F0\.U1.CNTVAL[17:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : we_cnt.vhd(64) | Found inferred clock WE_CNT|TC_inferred_clock which controls 1 sequential elements including Fabric_Logic_0.U2.U2.U3.WE_REG. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : wa_cnt.vhd(38) | Found inferred clock WE_CNT|WE_inferred_clock which controls 218 sequential elements including Fabric_Logic_0.U2.U2.U1.CNTVAL[9:0]. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\synthesis\IGL2_Standby.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 157MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Feb 18 15:59:31 2016

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 136MB)

    @W:BN132 : sign8x8_mult.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.5.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.5.U3.DIN1_REG[17:0]
    @W:BN132 : sign8x8_mult.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.0.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U3.DIN1_REG[17:0]
    @W:BN132 : sign8x8_mult.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.2.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.2.U3.DIN1_REG[17:0]
    @W:BN132 : sign8x8_mult.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.1.U3.DIN2_REG[17:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.1.U3.DIN1_REG[17:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.9.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.10.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.2.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.5.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.8.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]
    @W:BN132 : lsram1kx18.vhd(43) | Removing sequential instance Fabric_Logic_0.U2.F.7.U4.RAddr_Reg[9:0],  because it is equivalent to instance Fabric_Logic_0.U2.F.0.U4.RAddr_Reg[9:0]

    Available hyper_sources - for debug and ip models
    	None Found

    Warning: Found 1 combinational loops!
    @W:BN137 : standby_control.vhd(119) | Found combinational loop during mapping at net Standby_Control_0_PLL_PowerDown
    1) instance Standby_Control_0.NOR2_0 (view:work.IGL2_Standby(rtl)), output net "Standby_Control_0_PLL_PowerDown" in work.IGL2_Standby(rtl)
        net        Standby_Control_0_PLL_PowerDown
        input  pin Standby_Control_0.NOR2_1/B
        instance   Standby_Control_0.NOR2_1 (cell NOR2)
        output pin Standby_Control_0.NOR2_1/Y
        net        Standby_Control_0.NOR2_1_Y
        input  pin Standby_Control_0.NOR2_0/B
        instance   Standby_Control_0.NOR2_0 (cell NOR2)
        output pin Standby_Control_0.NOR2_0/Y
        net        Standby_Control_0_PLL_PowerDown
    End of loops

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)

    @N: : fabric_logic.vhd(76) | Found counter in view:work.Fabric_Logic(struct) inst CNTVAL[25:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.199\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.72\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.12\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.73\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.13\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.74\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.14\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.75\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.15\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.76\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.16\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.77\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.17\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.262\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.139\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.200\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.140\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.201\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.141\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.202\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.63\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.21\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.82\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.23\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.84\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.4\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.22\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.240\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.180\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.241\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.181\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.242\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.27\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.88\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.28\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.89\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.29\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.90\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.30\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.91\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.31\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.92\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.32\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.93\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.33\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.94\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.34\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.95\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.35\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.96\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.36\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.97\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.37\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.98\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.38\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.99\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.39\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.100\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.40\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.101\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.41\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.102\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.42\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.103\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.43\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.104\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.44\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.105\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.45\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.106\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.46\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.107\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.47\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.108\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.48\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.109\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.49\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.110\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.50\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.111\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.51\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.112\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.52\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.113\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.53\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.114\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.54\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.115\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.55\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.116\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.56\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.117\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.57\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.118\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.58\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.206\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.146\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.207\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.147\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.208\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.184\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.1\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.62\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.2\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.3\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.64\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.123\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.246\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.253\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.247\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.254\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.248\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.255\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.78\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.68\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.8\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.69\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.9\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.70\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.10\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.71\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.132\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.193\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.133\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.194\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.134\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.195\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.135\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.196\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.136\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.197\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.137\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.198\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.138\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.249\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.119\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.59\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.120\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.60\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.121\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.61\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.83\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.142\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.203\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.144\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.205\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.145\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.125\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.186\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.126\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.187\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.127\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.188\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.148\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.209\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.149\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.210\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.150\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.211\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.151\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.212\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.152\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.213\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.153\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.214\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.154\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.215\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.155\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.216\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.156\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.217\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.157\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.218\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.158\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.219\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.159\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.220\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.160\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.221\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.161\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.222\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.162\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.223\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.163\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.224\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.164\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.225\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.165\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.226\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.166\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.227\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.167\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.228\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.168\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.229\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.169\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.230\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.170\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.231\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.171\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.232\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.172\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.233\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.173\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.234\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.174\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.235\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.175\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.236\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.176\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.237\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.177\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.238\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.178\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.239\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.179\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.18\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.79\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.19\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.80\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.20\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.81\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.182\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.122\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.183\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.124\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.185\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.244\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.24\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.85\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.25\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.86\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.26\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.87\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.11\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.189\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.129\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.190\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.130\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.191\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.131\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.192\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.266\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.260\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.267\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.261\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.268\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.7\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.256\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.263\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.257\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.264\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.258\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.265\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.259\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.128\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.65\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.5\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.66\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.6\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.67\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.251\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.204\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.243\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.250\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.245\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.252\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.143\.F1\.U2.CNTVAL[17:0]
    @N: : cnt_up.vhd(40) | Found counter in view:work.CNT_UP269(struct) inst F\.0\.F0\.U1.CNTVAL[17:0]
    @N: : mult11_lsram11.vhd(112) | Found counter in view:work.Mult11_LSRAM11(struct) inst CNTVAL2[16:0]
    @N: : mult11_lsram11.vhd(103) | Found counter in view:work.Mult11_LSRAM11(struct) inst CNTVAL1[10:0]
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.9\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.0\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.10\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.2\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.5\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.8\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.7\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.6\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.4\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.3\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @W:FX107 : lsram1kx18.vhd(36) | No read/write conflict check. Possible simulation mismatch!
    @N:MF707 : lsram1kx18.vhd(36) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for F\.1\.U4.ramtmp[17:0] (view:work.Mult11_LSRAM11(struct)).
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[1] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[3] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[4] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[5] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[6] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[7] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[8] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @A:BN291 : lsram1kx18.vhd(43) | Boundary register F\.0\.U4.RAddr_Reg[9] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.3\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.6\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_0(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.9\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_1(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.2\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_2(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.5\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_3(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.4\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_4(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.7\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_5(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.10\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_6(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.1\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_7(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.0\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_8(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[18] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[19] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[20] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[21] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[22] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[23] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[24] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[25] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs
    @N:BN362 : sign8x8_mult.vhd(43) | Removing sequential instance F\.8\.U3.DOUT_REG[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac_9(preserved) because there are no references to its outputs

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 144MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 144MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 144MB)

    Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 164MB peak: 165MB)

    Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 165MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:04s		     1.15ns		5307 /      4952
    @N:FP130 :  | Promoting Net LD_c on CLKINT  I_346
    @N:FP130 :  | Promoting Net FCCC_0_LOCK on CLKINT  I_347
    @N:FP130 :  | Promoting Net Fabric_Logic_0.U2.WE on CLKINT  I_348

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 165MB peak: 180MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 175MB peak: 180MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 5209 clock pin(s) of sequential element(s)
    2 gated/generated clock tree(s) driving 21 clock pin(s) of sequential element(s)
    0 instances converted, 21 sequential instances remain driven by gated/generated clocks

    ================================ Non-Gated/Non-Generated Clocks =================================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    -------------------------------------------------------------------------------------------------
    ClockId0003        FCCC_0.GL0_INST     CLKINT                 5209       Fabric_Logic_0.CNTVAL[25]
    =================================================================================================
    ============================================================================== Gated/Generated Clocks ==============================================================================
    Clock Tree ID     Driving Element                    Drive Element Type     Fanout     Sample Instance                       Explanation
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        Fabric_Logic_0.U2.U2.U3.WE_REG     SLE                    20         Fabric_Logic_0.U2.U2.U1.CNTVAL[5]     No gated clock conversion method for cell cell:ACG4.SLE
    ClockId0002        Fabric_Logic_0.U2.U2.U3.TC         SLE                    1          Fabric_Logic_0.U2.U2.U3.WE_REG        No gated clock conversion method for cell cell:ACG4.SLE
    ====================================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 117MB peak: 180MB)

    Writing Analyst data base F:\Microsemi_prj\IGL2_Standby_tutorial\Libero_project\IGL2_Standby\synthesis\synwork\IGL2_Standby_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 168MB peak: 180MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    J-2015.03M-SP1-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 169MB peak: 180MB)

    Start final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 168MB peak: 180MB)

    Warning: Found 1 combinational loops!
    @W:BN137 : standby_control.vhd(119) | Found combinational loop during mapping at net Standby_Control_0.Standby_Control_0_PLL_PowerDown
    1) instance NOR2_0 (view:work.Standby_Control(netlist)), output net "Standby_Control_0_PLL_PowerDown" in work.Standby_Control(netlist)
        net        Standby_Control_0.Standby_Control_0_PLL_PowerDown
        input  pin Standby_Control_0.NOR2_1/B
        instance   Standby_Control_0.NOR2_1 (cell NOR2)
        output pin Standby_Control_0.NOR2_1/Y
        net        Standby_Control_0.NOR2_1_Y
        input  pin Standby_Control_0.NOR2_0/B
        instance   Standby_Control_0.NOR2_0 (cell NOR2)
        output pin Standby_Control_0.NOR2_0/Y
        net        Standby_Control_0.Standby_Control_0_PLL_PowerDown
    End of loops
    @W:MT246 : igl2_standby_osc_0_osc.vhd(53) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : igl2_standby_fccc_0_fccc.vhd(108) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"

    @W:MT420 :  | Found inferred clock WE_CNT|WE_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Fabric_Logic_0.U2.U2.U3.WE"

    @W:MT420 :  | Found inferred clock WE_CNT|TC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Fabric_Logic_0.U2.U2.U3.TC"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Thu Feb 18 15:59:44 2016
    #

    Top view:               IGL2_Standby
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 3.309

                                                        Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                      Frequency     Frequency     Period        Period        Slack     Type         Group
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     324.8 MHz     10.000        3.079         6.921     inferred     Inferred_clkgroup_0
    WE_CNT|TC_inferred_clock                            100.0 MHz     659.0 MHz     10.000        1.518         8.482     inferred     Inferred_clkgroup_1
    WE_CNT|WE_inferred_clock                            100.0 MHz     380.3 MHz     10.000        2.629         7.371     inferred     Inferred_clkgroup_2
    System                                              100.0 MHz     149.5 MHz     10.000        6.691         3.309     system       system_clkgroup
    ======================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                         Ending                                           |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                           System                                           |  10.000      3.309  |  No paths    -      |  No paths    -      |  No paths    -
    IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock  IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock  |  10.000      6.921  |  No paths    -      |  No paths    -      |  No paths    -
    WE_CNT|TC_inferred_clock                         IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    WE_CNT|TC_inferred_clock                         WE_CNT|TC_inferred_clock                         |  10.000      8.482  |  No paths    -      |  No paths    -      |  No paths    -
    WE_CNT|WE_inferred_clock                         IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  Diff grp    -
    WE_CNT|WE_inferred_clock                         WE_CNT|WE_inferred_clock                         |  10.000      7.371  |  10.000      7.371  |  No paths    -      |  No paths    -
    ========================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                               Starting                                                                             Arrival
    Instance                                   Reference                                           Type     Pin     Net             Time        Slack
                                               Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[0]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[0]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[1]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[1]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[2]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[2]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[3]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[3]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[4]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[4]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[5]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[5]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[6]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[6]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[7]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[7]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[8]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[8]     0.076       6.921
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[9]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       DIN2_REG[9]     0.076       6.921
    =================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                  Starting                                                                              Required
    Instance                                                      Reference                                           Type     Pin      Net             Time         Slack
                                                                  Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.F\.9\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.1\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.8\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.4\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.10\.U3.U\.DOUT_REG_2_mulonly_0[35:0]     IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.2\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.0\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.5\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.6\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    Fabric_Logic_0.U2.F\.7\.U3.U\.DOUT_REG_2_mulonly_0[35:0]      IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     DIN2_REG[0]     7.991        6.921
    ======================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            2.009
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.991

        - Propagation time:                      1.070
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 6.921

        Number of logic level(s):                0
        Starting point:                          Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[0] / Q
        Ending point:                            Fabric_Logic_0.U2.F\.0\.U3.U\.DOUT_REG_2_mulonly_0[35:0] / A[0]
        The start point is clocked by            IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
        The end   point is clocked by            IGL2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

    Instance / Net                                                        Pin      Pin               Arrival     No. of
    Name                                                         Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.F\.0\.U3.DIN1_REG[0]                       SLE      Q        Out     0.076     0.076       -
    DIN2_REG[0]                                                  Net      -        -       0.994     -           22
    Fabric_Logic_0.U2.F\.0\.U3.U\.DOUT_REG_2_mulonly_0[35:0]     MACC     A[0]     In      -         1.070       -
    =======================================================================================================================
    Total path delay (propagation time + setup) of 3.079 is 2.085(67.7%) logic and 0.994(32.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: WE_CNT|TC_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                       Starting                                               Arrival
    Instance                           Reference                    Type     Pin     Net      Time        Slack
                                       Clock
    -----------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U3.WE_REG     WE_CNT|TC_inferred_clock     SLE      Q       WE_i     0.094       8.482
    ===========================================================================================================

    Ending Points with Worst Slack
    ******************************

                                       Starting                                                   Required
    Instance                           Reference                    Type     Pin     Net          Time         Slack
                                       Clock
    ----------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U3.WE_REG     WE_CNT|TC_inferred_clock     SLE      D       WE_i_i_0     9.778        8.482
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      1.296
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 8.482

        Number of logic level(s):                1
        Starting point:                          Fabric_Logic_0.U2.U2.U3.WE_REG / Q
        Ending point:                            Fabric_Logic_0.U2.U2.U3.WE_REG / D
        The start point is clocked by            WE_CNT|TC_inferred_clock [rising] on pin CLK
        The end   point is clocked by            WE_CNT|TC_inferred_clock [rising] on pin CLK

    Instance / Net                                  Pin      Pin               Arrival     No. of
    Name                                   Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U3.WE_REG         SLE      Q        Out     0.094     0.094       -
    WE_i                                   Net      -        -       0.977     -           2
    Fabric_Logic_0.U2.U2.U3.WE_REG_RNO     CFG1     A        In      -         1.071       -
    Fabric_Logic_0.U2.U2.U3.WE_REG_RNO     CFG1     Y        Out     0.087     1.158       -
    WE_i_i_0                               Net      -        -       0.138     -           1
    Fabric_Logic_0.U2.U2.U3.WE_REG         SLE      D        In      -         1.296       -
    =================================================================================================
    Total path delay (propagation time + setup) of 1.517 is 0.403(26.6%) logic and 1.114(73.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: WE_CNT|WE_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                Arrival
    Instance                              Reference                    Type     Pin     Net       Time        Slack
                                          Clock
    ---------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U2.CNTVAL[0]     WE_CNT|WE_inferred_clock     SLE      Q       RA[0]     0.094       7.371
    Fabric_Logic_0.U2.U2.U1.CNTVAL[0]     WE_CNT|WE_inferred_clock     SLE      Q       WA[0]     0.094       7.371
    Fabric_Logic_0.U2.U2.U2.CNTVAL[1]     WE_CNT|WE_inferred_clock     SLE      Q       RA[1]     0.094       7.385
    Fabric_Logic_0.U2.U2.U1.CNTVAL[1]     WE_CNT|WE_inferred_clock     SLE      Q       WA[1]     0.094       7.385
    Fabric_Logic_0.U2.U2.U1.CNTVAL[2]     WE_CNT|WE_inferred_clock     SLE      Q       WA[2]     0.094       7.400
    Fabric_Logic_0.U2.U2.U2.CNTVAL[2]     WE_CNT|WE_inferred_clock     SLE      Q       RA[2]     0.094       7.400
    Fabric_Logic_0.U2.U2.U1.CNTVAL[3]     WE_CNT|WE_inferred_clock     SLE      Q       WA[3]     0.094       7.414
    Fabric_Logic_0.U2.U2.U2.CNTVAL[3]     WE_CNT|WE_inferred_clock     SLE      Q       RA[3]     0.094       7.414
    Fabric_Logic_0.U2.U2.U2.CNTVAL[4]     WE_CNT|WE_inferred_clock     SLE      Q       RA[4]     0.094       7.428
    Fabric_Logic_0.U2.U2.U1.CNTVAL[4]     WE_CNT|WE_inferred_clock     SLE      Q       WA[4]     0.094       7.428
    ===============================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                               Required
    Instance                              Reference                    Type     Pin     Net                      Time         Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U2.CNTVAL[9]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_s_9_S         9.778        7.371
    Fabric_Logic_0.U2.U2.U1.CNTVAL[9]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_s_9_S_0       9.778        7.371
    Fabric_Logic_0.U2.U2.U2.CNTVAL[8]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_8_S       9.778        7.385
    Fabric_Logic_0.U2.U2.U1.CNTVAL[8]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_8_S_0     9.778        7.385
    Fabric_Logic_0.U2.U2.U2.CNTVAL[7]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_7_S       9.778        7.399
    Fabric_Logic_0.U2.U2.U1.CNTVAL[7]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_7_S_0     9.778        7.399
    Fabric_Logic_0.U2.U2.U2.CNTVAL[6]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_6_S       9.778        7.413
    Fabric_Logic_0.U2.U2.U1.CNTVAL[6]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_6_S_0     9.778        7.413
    Fabric_Logic_0.U2.U2.U2.CNTVAL[5]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_5_S       9.778        7.427
    Fabric_Logic_0.U2.U2.U1.CNTVAL[5]     WE_CNT|WE_inferred_clock     SLE      D       un3_cntval_cry_5_S_0     9.778        7.427
    ===============================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      2.407
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 7.371

        Number of logic level(s):                10
        Starting point:                          Fabric_Logic_0.U2.U2.U2.CNTVAL[0] / Q
        Ending point:                            Fabric_Logic_0.U2.U2.U2.CNTVAL[9] / D
        The start point is clocked by            WE_CNT|WE_inferred_clock [falling] on pin CLK
        The end   point is clocked by            WE_CNT|WE_inferred_clock [falling] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    Fabric_Logic_0.U2.U2.U2.CNTVAL[0]              SLE      Q        Out     0.094     0.094       -
    RA[0]                                          Net      -        -       0.990     -           13
    Fabric_Logic_0.U2.U2.U2.un3_cntval_s_1_343     ARI1     B        In      -         1.085       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_s_1_343     ARI1     FCO      Out     0.174     1.259       -
    un3_cntval_s_1_343_FCO                         Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_1       ARI1     FCI      In      -         1.259       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_1       ARI1     FCO      Out     0.014     1.273       -
    un3_cntval_cry_1                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_2       ARI1     FCI      In      -         1.273       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_2       ARI1     FCO      Out     0.014     1.287       -
    un3_cntval_cry_2                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_3       ARI1     FCI      In      -         1.287       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_3       ARI1     FCO      Out     0.014     1.302       -
    un3_cntval_cry_3                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_4       ARI1     FCI      In      -         1.302       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_4       ARI1     FCO      Out     0.014     1.316       -
    un3_cntval_cry_4                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_5       ARI1     FCI      In      -         1.316       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_5       ARI1     FCO      Out     0.014     1.330       -
    un3_cntval_cry_5                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_6       ARI1     FCI      In      -         1.330       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_6       ARI1     FCO      Out     0.014     1.344       -
    un3_cntval_cry_6                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_7       ARI1     FCI      In      -         1.344       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_7       ARI1     FCO      Out     0.014     1.358       -
    un3_cntval_cry_7                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_8       ARI1     FCI      In      -         1.358       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_cry_8       ARI1     FCO      Out     0.014     1.373       -
    un3_cntval_cry_8                               Net      -        -       0.000     -           1
    Fabric_Logic_0.U2.U2.U2.un3_cntval_s_9         ARI1     FCI      In      -         1.373       -
    Fabric_Logic_0.U2.U2.U2.un3_cntval_s_9         ARI1     S        Out     0.063     1.436       -
    un3_cntval_s_9_S                               Net      -        -       0.971     -           1
    Fabric_Logic_0.U2.U2.U2.CNTVAL[9]              SLE      D        In      -         2.407       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 2.629 is 0.668(25.4%) logic and 1.962(74.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                       Starting                                                                Arrival
    Instance           Reference     Type       Pin        Net                                 Time        Slack
                       Clock
    ------------------------------------------------------------------------------------------------------------
    OSC_0.I_XTLOSC     System        XTLOSC     CLKOUT     OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC     0.000       3.309
    ============================================================================================================

    Ending Points with Worst Slack
    ******************************

                        Starting                                                                       Required
    Instance            Reference     Type     Pin                 Net                                 Time         Slack
                        Clock
    ---------------------------------------------------------------------------------------------------------------------
    FCCC_0.CCC_INST     System        CCC      PLL_ARST_N          Standby_Control_0_PLL_PowerDown     10.000       3.309
    FCCC_0.CCC_INST     System        CCC      PLL_POWERDOWN_N     Standby_Control_0_PLL_PowerDown     10.000       3.309
    FCCC_0.CCC_INST     System        CCC      XTLOSC              OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC     10.000       9.024
    =====================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         10.000

        - Propagation time:                      6.691
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     3.309

        Number of logic level(s):                5
        Starting point:                          OSC_0.I_XTLOSC / CLKOUT
        Ending point:                            FCCC_0.CCC_INST / PLL_ARST_N
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                     Pin            Pin               Arrival     No. of
    Name                                Type           Name           Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------
    OSC_0.I_XTLOSC                      XTLOSC         CLKOUT         Out     0.000     0.000       -
    OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC     Net            -              -       0.977     -           2
    OSC_0.I_XTLOSC_FAB                  XTLOSC_FAB     A              In      -         0.977       -
    OSC_0.I_XTLOSC_FAB                  XTLOSC_FAB     CLKOUT         Out     0.157     1.133       -
    N_XTLOSC_CLKINT                     Net            -              -       0.971     -           1
    OSC_0.I_XTLOSC_FAB_CLKINT           CLKINT         A              In      -         2.104       -
    OSC_0.I_XTLOSC_FAB_CLKINT           CLKINT         Y              Out     0.337     2.441       -
    OSC_0_XTLOSC_O2F                    Net            -              -       0.977     -           2
    Standby_Control_0.AND2_1            AND2           B              In      -         3.418       -
    Standby_Control_0.AND2_1            AND2           Y              Out     0.139     3.556       -
    AND2_1_Y                            Net            -              -       0.971     -           1
    Standby_Control_0.NOR2_1            NOR2           A              In      -         4.528       -
    Standby_Control_0.NOR2_1            NOR2           Y              Out     0.087     4.615       -
    NOR2_1_Y                            Net            -              -       0.971     -           1
    Standby_Control_0.NOR2_0            NOR2           B              In      -         5.586       -
    Standby_Control_0.NOR2_0            NOR2           Y              Out     0.133     5.719       -
    Standby_Control_0_PLL_PowerDown     Net            -              -       0.971     -           3
    FCCC_0.CCC_INST                     CCC            PLL_ARST_N     In      -         6.691       -
    ==========================================================================================================
    Total path delay (propagation time + setup) of 6.691 is 0.852(12.7%) logic and 5.839(87.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 169MB peak: 180MB)

    Finished timing report (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 169MB peak: 180MB)

    ---------------------------------------
    Resource Usage Report for IGL2_Standby

    Mapping to part: m2gl010tfbga484-1
    Cell usage:
    AND2            2 uses
    CCC             1 use
    CLKINT          5 uses
    DFN1C0          234 uses
    INV             2 uses
    NOR2            2 uses
    XTLOSC          1 use
    XTLOSC_FAB      1 use
    CFG1           9 uses
    CFG2           21 uses
    CFG3           1 use
    CFG4           145 uses

    Carry primitives used for arithmetic functions:
    ARI1           5185 uses

    Sequential Cells:
    SLE            4952 uses

    DSP Blocks:   11
     MACC:        11 Mults

    I/O ports: 44
    I/O primitives: 43
    INBUF          21 uses
    OUTBUF         22 uses

    Global Clock Buffers: 5

    RAM/ROM usage summary
    Block Rams (RAM1K18) : 11

    Total LUTs:    5361

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 396; LUTs = 396;
    MACC     Interface Logic : SLEs = 396; LUTs = 396;

    Total number of SLEs after P&R:  4952 + 0 + 396 + 396 = 5744;
    Total number of LUTs after P&R:  5361 + 0 + 396 + 396 = 6153;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 60MB peak: 180MB)

    Process took 0h:00m:12s realtime, 0h:00m:12s cputime
    # Thu Feb 18 15:59:44 2016

    ###########################################################]

`