#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020
#install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
#OS: Windows 8 6.2
#Hostname: HYD-LT-I63442

# Thu Apr  8 17:23:05 2021

#Implementation: synthesis


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v" (library work)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\CCC_0\MDDR_Demo_CCC_0_FCCC.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\FABOSC_0\MDDR_Demo_FABOSC_0_OSC.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS_syn.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v" (library work)
@W:CG1337 : axi_interconnect_ntom.v(5291) | Net RREADY_M0IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5292) | Net RREADY_M0IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5293) | Net RREADY_M0IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5294) | Net RREADY_M0IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5295) | Net RREADY_M0IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5296) | Net RREADY_M0IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5297) | Net RREADY_M0IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5298) | Net RREADY_M0IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5299) | Net RREADY_M0IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5300) | Net RREADY_M0IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5301) | Net RREADY_M0IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5302) | Net RREADY_M0IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5303) | Net RREADY_M0IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5304) | Net RREADY_M0IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5305) | Net RREADY_M0IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5306) | Net RREADY_M0IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5307) | Net RREADY_M0IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5309) | Net RREADY_M1IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5310) | Net RREADY_M1IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5311) | Net RREADY_M1IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5312) | Net RREADY_M1IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5313) | Net RREADY_M1IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5314) | Net RREADY_M1IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5315) | Net RREADY_M1IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5316) | Net RREADY_M1IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5317) | Net RREADY_M1IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5318) | Net RREADY_M1IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5319) | Net RREADY_M1IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5320) | Net RREADY_M1IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5321) | Net RREADY_M1IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5322) | Net RREADY_M1IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5323) | Net RREADY_M1IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5324) | Net RREADY_M1IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5325) | Net RREADY_M1IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5327) | Net RREADY_M2IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5328) | Net RREADY_M2IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5329) | Net RREADY_M2IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5330) | Net RREADY_M2IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5331) | Net RREADY_M2IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5332) | Net RREADY_M2IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5333) | Net RREADY_M2IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5334) | Net RREADY_M2IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5335) | Net RREADY_M2IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5336) | Net RREADY_M2IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5337) | Net RREADY_M2IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5338) | Net RREADY_M2IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5339) | Net RREADY_M2IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5340) | Net RREADY_M2IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5341) | Net RREADY_M2IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5342) | Net RREADY_M2IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5343) | Net RREADY_M2IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5345) | Net RREADY_M3IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5346) | Net RREADY_M3IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5347) | Net RREADY_M3IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5348) | Net RREADY_M3IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5349) | Net RREADY_M3IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5350) | Net RREADY_M3IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5351) | Net RREADY_M3IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5352) | Net RREADY_M3IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5353) | Net RREADY_M3IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5354) | Net RREADY_M3IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5355) | Net RREADY_M3IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5356) | Net RREADY_M3IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5357) | Net RREADY_M3IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5358) | Net RREADY_M3IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5359) | Net RREADY_M3IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5360) | Net RREADY_M3IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5361) | Net RREADY_M3IS16_gated is not declared.
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\MDDR_Demo.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_top\MDDR_Demo_top.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\UART_IF.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\top\top.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module top
@N:CG364 : AXI_IF.v(21) | Synthesizing module AXI_IF in library work.

	Idle_0=3'b000
	Idle_1=3'b001
	Write_0=3'b010
	Write_1=3'b011
	Read_0=3'b000
	Read_1=3'b001
	Read_2=3'b010
	Bresp_0=3'b100
	Write_2=3'b101
   Generated name = AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1
Running optimization stage 1 on AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1 .......
@A:CL282 : AXI_IF.v(220) | Feedback mux created for signal ARLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : AXI_IF.v(93) | Feedback mux created for signal AWLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : AXI_IF.v(93) | Feedback mux created for signal AWADDR[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : AXI_IF.v(93) | Optimizing register bit AWBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : AXI_IF.v(93) | Optimizing register bit AWSIZE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : AXI_IF.v(220) | Optimizing register bit ARBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : AXI_IF.v(93) | Pruning register bit 1 of AWBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : AXI_IF.v(93) | Pruning register bit 2 of AWSIZE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : AXI_IF.v(220) | Pruning register bit 1 of ARBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG775 : coreahblite.v(23) | Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB
@N:CG364 : igloo2.v(376) | Synthesizing module VCC in library work.
Running optimization stage 1 on VCC .......
@N:CG364 : igloo2.v(372) | Synthesizing module GND in library work.
Running optimization stage 1 on GND .......
@N:CG364 : igloo2.v(362) | Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
@N:CG364 : igloo2.v(729) | Synthesizing module CCC in library work.
Running optimization stage 1 on CCC .......
@N:CG364 : MDDR_Demo_CCC_0_FCCC.v(5) | Synthesizing module MDDR_Demo_CCC_0_FCCC in library work.
Running optimization stage 1 on MDDR_Demo_CCC_0_FCCC .......
@N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster in library work.

	DATA_LOCATION=32'b00000000000000111110100000000000
	ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000
	ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
	S7=32'b00000000000000000000000000000111
	S8=32'b00000000000000000000000000001000
	S9=32'b00000000000000000000000000001001
	S10=32'b00000000000000000000000000001010
	S11=32'b00000000000000000000000000001011
	S12=32'b00000000000000000000000000001100
	S13=32'b00000000000000000000000000001101
	S14=32'b00000000000000000000000000001110
	S15=32'b00000000000000000000000000001111
	S16=32'b00000000000000000000000000010000
	S17=32'b00000000000000000000000000010001
	S18=32'b00000000000000000000000000010010
	S19=32'b00000000000000000000000000010011
	S20=32'b00000000000000000000000000010100
	S21=32'b00000000000000000000000000010101
	S22=32'b00000000000000000000000000010110
	P0=32'b00000000000000000000000000100000
	P1=32'b00000000000000000000000000100001
	P2=32'b00000000000000000000000000100010
	P3=32'b00000000000000000000000000100011
	P4=32'b00000000000000000000000000100100
	P5=32'b00000000000000000000000000100101
	P6=32'b00000000000000000000000000100110
	OP_COPY=7'b0000000
	OP_POLL=7'b0000010
	OP_LOAD=7'b0000011
	OP_STORE=7'b0000100
	OP_AND=7'b0000101
	OP_OR=7'b0000110
   Generated name = CoreConfigMaster_Z2
Running optimization stage 1 on CoreConfigMaster_Z2 .......
@W:CL190 : coreconfigmaster.v(723) | Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : coreconfigmaster.v(723) | Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CG1283 : coreahblite.v(541) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite.v(541) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite.v(541) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite.v(541) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite_matrix4x16.v(2639) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3
Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z3 .......
@N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB.

	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	HRESPEXTEND=1'b1
   Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1
Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 .......
@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0
Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 .......
@W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W:CG1283 : coreahblite_matrix4x16.v(2703) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z4
Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z4 .......
@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0
Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 .......
@W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W:CG1283 : coreahblite_matrix4x16.v(2767) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG1283 : coreahblite_matrix4x16.v(2831) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB.

	SYNC_RESET=32'b00000000000000000000000000000000
	M0EXTEND=4'b0000
	M0DONE=4'b0001
	M0LOCK=4'b0010
	M0LOCKEXTEND=4'b0011
	M1EXTEND=4'b0100
	M1DONE=4'b0101
	M1LOCK=4'b0110
	M1LOCKEXTEND=4'b0111
	M2EXTEND=4'b1000
	M2DONE=4'b1001
	M2LOCK=4'b1010
	M2LOCKEXTEND=4'b1011
	M3EXTEND=4'b1100
	M3DONE=4'b1101
	M3LOCK=4'b1110
	M3LOCKEXTEND=4'b1111
	MASTER_0=4'b0001
	MASTER_1=4'b0010
	MASTER_2=4'b0100
	MASTER_3=4'b1000
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVEARBITER_Z5
Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z5 .......
@N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB.

	SYNC_RESET=32'b00000000000000000000000000000000
	TRN_IDLE=1'b0
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0
Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 .......
@N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB.

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s
Running optimization stage 1 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s .......
@N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB.

	FAMILY=6'b011000
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	SYNC_RESET=32'b00000000000000000000000000000000
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z6
Running optimization stage 1 on CoreAHBLite_Z6 .......
@W:CG1283 : MDDR_Demo.v(1393) | Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@N:CG364 : coreaxi.v(29) | Synthesizing module MDDR_Demo_COREAXI_0_COREAXI in library work.

	FAMILY=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	AWIDTH1=32'b00000000000000000000000000011000
	AWIDTH2=32'b00000000000000000000000000100000
	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SINGLE_MASTER=32'b00000000000000000000000000000001
	SINGLE_SLAVE=32'b00000000000000000000000000000000
	SINGLE_MASTER_SINGLE_SLAVE=32'b00000000000000000000000000000000
	COMB_REG=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	SLAVE_0=17'b00000000000000001
	SLAVE_1=17'b00000000000000010
	SLAVE_2=17'b00000000000000100
	SLAVE_3=17'b00000000000001000
	SLAVE_4=17'b00000000000010000
	SLAVE_5=17'b00000000000100000
	SLAVE_6=17'b00000000001000000
	SLAVE_7=17'b00000000010000000
	SLAVE_8=17'b00000000100000000
	SLAVE_9=17'b00000001000000000
	SLAVE_A=17'b00000010000000000
	SLAVE_B=17'b00000100000000000
	SLAVE_C=17'b00001000000000000
	SLAVE_D=17'b00010000000000000
	SLAVE_E=17'b00100000000000000
	SLAVE_F=17'b01000000000000000
	SLAVE_N=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = MDDR_Demo_COREAXI_0_COREAXI_Z7
@N:CG364 : axi_feedthrough.v(30) | Synthesizing module axi_feedthrough in library work.

	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SYNC_RESET=32'b00000000000000000000000000000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
   Generated name = axi_feedthrough_Z8
Running optimization stage 1 on axi_feedthrough_Z8 .......
@W:CG360 : coreaxi.v(1307) | Removing wire AWID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1308) | Removing wire AWADDR_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1309) | Removing wire AWLEN_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1310) | Removing wire AWSIZE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1311) | Removing wire AWBURST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1312) | Removing wire AWLOCK_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1313) | Removing wire AWCACHE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1314) | Removing wire AWPROT_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1315) | Removing wire AWVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1318) | Removing wire WID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1319) | Removing wire WDATA_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1320) | Removing wire WSTRB_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1321) | Removing wire WLAST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1322) | Removing wire WVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1328) | Removing wire BREADY_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1330) | Removing wire ARID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1331) | Removing wire ARADDR_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1332) | Removing wire ARLEN_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1333) | Removing wire ARSIZE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1334) | Removing wire ARBURST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1335) | Removing wire ARLOCK_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1336) | Removing wire ARCACHE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1337) | Removing wire ARPROT_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1338) | Removing wire ARVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1346) | Removing wire RREADY_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1350) | Removing wire AWID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1351) | Removing wire AWADDR_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1352) | Removing wire AWLEN_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1353) | Removing wire AWSIZE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1354) | Removing wire AWBURST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1355) | Removing wire AWLOCK_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1356) | Removing wire AWCACHE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1357) | Removing wire AWPROT_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1358) | Removing wire AWVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1361) | Removing wire WID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1362) | Removing wire WDATA_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1363) | Removing wire WSTRB_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1364) | Removing wire WLAST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1365) | Removing wire WVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1371) | Removing wire BREADY_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1373) | Removing wire ARID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1374) | Removing wire ARADDR_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1375) | Removing wire ARLEN_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1376) | Removing wire ARSIZE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1377) | Removing wire ARBURST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1378) | Removing wire ARLOCK_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1379) | Removing wire ARCACHE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1380) | Removing wire ARPROT_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1381) | Removing wire ARVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1389) | Removing wire RREADY_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1393) | Removing wire AWID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1394) | Removing wire AWADDR_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1395) | Removing wire AWLEN_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1396) | Removing wire AWSIZE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1397) | Removing wire AWBURST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1398) | Removing wire AWLOCK_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1399) | Removing wire AWCACHE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1400) | Removing wire AWPROT_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1401) | Removing wire AWVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1404) | Removing wire WID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1405) | Removing wire WDATA_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1406) | Removing wire WSTRB_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1407) | Removing wire WLAST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1408) | Removing wire WVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1414) | Removing wire BREADY_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1416) | Removing wire ARID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1417) | Removing wire ARADDR_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1418) | Removing wire ARLEN_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1419) | Removing wire ARSIZE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1420) | Removing wire ARBURST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1421) | Removing wire ARLOCK_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1422) | Removing wire ARCACHE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1423) | Removing wire ARPROT_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1424) | Removing wire ARVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1432) | Removing wire RREADY_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1436) | Removing wire AWID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1437) | Removing wire AWADDR_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1438) | Removing wire AWLEN_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1439) | Removing wire AWSIZE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1440) | Removing wire AWBURST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1441) | Removing wire AWLOCK_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1442) | Removing wire AWCACHE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1443) | Removing wire AWPROT_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1444) | Removing wire AWVALID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1447) | Removing wire WID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1448) | Removing wire WDATA_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1449) | Removing wire WSTRB_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1450) | Removing wire WLAST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1451) | Removing wire WVALID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1457) | Removing wire BREADY_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1459) | Removing wire ARID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1460) | Removing wire ARADDR_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1461) | Removing wire ARLEN_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1462) | Removing wire ARSIZE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1463) | Removing wire ARBURST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1464) | Removing wire ARLOCK_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1465) | Removing wire ARCACHE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1466) | Removing wire ARPROT_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1467) | Removing wire ARVALID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1475) | Removing wire RREADY_S4, as there is no assignment to it.

Only the first 100 messages of id 'CG360' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CG360' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG360} -count unlimited' in the Tcl shell.
Running optimization stage 1 on MDDR_Demo_COREAXI_0_COREAXI_Z7 .......
@W:CL318 : coreaxi.v(1144) | *Output AWREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1151) | *Output WREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1153) | *Output BID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1154) | *Output BRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1155) | *Output BVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1167) | *Output ARREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1169) | *Output RID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1170) | *Output RDATA_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1171) | *Output RRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1172) | *Output RLAST_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1173) | *Output RVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1187) | *Output AWREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1194) | *Output WREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1196) | *Output BID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1197) | *Output BRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1198) | *Output BVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1210) | *Output ARREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1212) | *Output RID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1213) | *Output RDATA_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1214) | *Output RRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1215) | *Output RLAST_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1216) | *Output RVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1230) | *Output AWREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1237) | *Output WREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1239) | *Output BID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1240) | *Output BRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1241) | *Output BVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1253) | *Output ARREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1255) | *Output RID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1256) | *Output RDATA_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1257) | *Output RRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1258) | *Output RLAST_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1259) | *Output RVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1307) | *Output AWID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1308) | *Output AWADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1309) | *Output AWLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1310) | *Output AWSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1311) | *Output AWBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1312) | *Output AWLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1313) | *Output AWCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1314) | *Output AWPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1315) | *Output AWVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1318) | *Output WID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1319) | *Output WDATA_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1320) | *Output WSTRB_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1321) | *Output WLAST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1322) | *Output WVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1328) | *Output BREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1330) | *Output ARID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1331) | *Output ARADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1332) | *Output ARLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1333) | *Output ARSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1334) | *Output ARBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1335) | *Output ARLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1336) | *Output ARCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1337) | *Output ARPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1338) | *Output ARVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1346) | *Output RREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1350) | *Output AWID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1351) | *Output AWADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1352) | *Output AWLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1353) | *Output AWSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1354) | *Output AWBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1355) | *Output AWLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1356) | *Output AWCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1357) | *Output AWPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1358) | *Output AWVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1361) | *Output WID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1362) | *Output WDATA_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1363) | *Output WSTRB_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1364) | *Output WLAST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1365) | *Output WVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1371) | *Output BREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1373) | *Output ARID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1374) | *Output ARADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1375) | *Output ARLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1376) | *Output ARSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1377) | *Output ARBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1378) | *Output ARLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1379) | *Output ARCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1380) | *Output ARPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1381) | *Output ARVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1389) | *Output RREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1393) | *Output AWID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1394) | *Output AWADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1395) | *Output AWLEN_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1396) | *Output AWSIZE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1397) | *Output AWBURST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1398) | *Output AWLOCK_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1399) | *Output AWCACHE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1400) | *Output AWPROT_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1401) | *Output AWVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1404) | *Output WID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1405) | *Output WDATA_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1406) | *Output WSTRB_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1407) | *Output WLAST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1408) | *Output WVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1414) | *Output BREADY_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1416) | *Output ARID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1417) | *Output ARADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.

Only the first 100 messages of id 'CL318' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CL318' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL318} -count unlimited' in the Tcl shell.
@N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work.

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z9
Running optimization stage 1 on CoreConfigP_Z9 .......
@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work.

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z10
Running optimization stage 1 on CoreResetP_Z10 .......
@W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work.
Running optimization stage 1 on RCOSC_25_50MHZ_FAB .......
@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work.
Running optimization stage 1 on RCOSC_25_50MHZ .......
@N:CG364 : MDDR_Demo_FABOSC_0_OSC.v(5) | Synthesizing module MDDR_Demo_FABOSC_0_OSC in library work.
Running optimization stage 1 on MDDR_Demo_FABOSC_0_OSC .......
@N:CG364 : igloo2.v(274) | Synthesizing module OUTBUF in library work.
Running optimization stage 1 on OUTBUF .......
@N:CG364 : igloo2.v(326) | Synthesizing module OUTBUF_DIFF in library work.
Running optimization stage 1 on OUTBUF_DIFF .......
@N:CG364 : igloo2.v(286) | Synthesizing module BIBUF in library work.
Running optimization stage 1 on BIBUF .......
@N:CG364 : igloo2.v(268) | Synthesizing module INBUF in library work.
Running optimization stage 1 on INBUF .......
@N:CG364 : MDDR_Demo_HPMS_syn.v(5) | Synthesizing module MSS_010 in library work.
Running optimization stage 1 on MSS_010 .......
@N:CG364 : MDDR_Demo_HPMS.v(9) | Synthesizing module MDDR_Demo_HPMS in library work.
Running optimization stage 1 on MDDR_Demo_HPMS .......
@N:CG364 : igloo2.v(720) | Synthesizing module SYSRESET in library work.
Running optimization stage 1 on SYSRESET .......
@N:CG364 : MDDR_Demo.v(9) | Synthesizing module MDDR_Demo in library work.
Running optimization stage 1 on MDDR_Demo .......
@N:CG364 : MDDR_Demo_top.v(9) | Synthesizing module MDDR_Demo_top in library work.
Running optimization stage 1 on MDDR_Demo_top .......
@N:CG364 : Clock_gen.v(30) | Synthesizing module UART_IF_COREUART_0_Clock_gen in library work.

	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000001
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = UART_IF_COREUART_0_Clock_gen_1s_0s
@N:CG179 : Clock_gen.v(346) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(427) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(532) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(611) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(716) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(808) | Removing redundant assignment.
@N:CG179 : Clock_gen.v(915) | Removing redundant assignment.
Running optimization stage 1 on UART_IF_COREUART_0_Clock_gen_1s_0s .......
@N:CG364 : Tx_async.v(14) | Synthesizing module UART_IF_COREUART_0_Tx_async in library work.

	SYNC_RESET=32'b00000000000000000000000000000000
	TX_FIFO=32'b00000000000000000000000000000000
	CUARTI1ll=32'b00000000000000000000000000000000
	CUARTl1ll=32'b00000000000000000000000000000001
	CUARTOO0l=32'b00000000000000000000000000000010
	CUARTIO0l=32'b00000000000000000000000000000011
	CUARTlO0l=32'b00000000000000000000000000000100
	CUARTOI0l=32'b00000000000000000000000000000101
	CUARTII0l=32'b00000000000000000000000000000110
   Generated name = UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s
@W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@N:CG179 : Tx_async.v(870) | Removing redundant assignment.
Running optimization stage 1 on UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s .......
@W:CL190 : Tx_async.v(301) | Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : Tx_async.v(301) | Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers.
@N:CG364 : Rx_async.v(14) | Synthesizing module UART_IF_COREUART_0_Rx_async in library work.

	SYNC_RESET=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	CUARTOIIl=32'b00000000000000000000000000000000
	CUARTIIIl=32'b00000000000000000000000000000001
	CUARTlIIl=32'b00000000000000000000000000000010
	CUARTOlIl=32'b00000000000000000000000000000011
   Generated name = UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s
@N:CG179 : Rx_async.v(750) | Removing redundant assignment.
@N:CG179 : Rx_async.v(857) | Removing redundant assignment.
Running optimization stage 1 on UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s .......
@W:CL177 : Rx_async.v(1613) | Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
@N:CG364 : CoreUART.v(14) | Synthesizing module UART_IF_COREUART_0_COREUART in library work.

	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000011000
	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000001
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = UART_IF_COREUART_0_COREUART_0s_0s_0s_24s_1s_0s
@N:CG179 : CoreUART.v(1338) | Removing redundant assignment.
@W:CG133 : CoreUART.v(333) | Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on UART_IF_COREUART_0_COREUART_0s_0s_0s_24s_1s_0s .......
@W:CL169 : CoreUART.v(1268) | Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1106) | Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(984) | Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(936) | Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(936) | Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(888) | Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(888) | Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(405) | Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers.
@N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 in library work.
Running optimization stage 1 on RAM1K18 .......
@N:CG364 : UART_IF_TPSRAM_0_TPSRAM.v(5) | Synthesizing module UART_IF_TPSRAM_0_TPSRAM in library work.
Running optimization stage 1 on UART_IF_TPSRAM_0_TPSRAM .......
@N:CG364 : UART_IF_FSM.v(20) | Synthesizing module UART_IF_FSM in library work.
@N:CG179 : UART_IF_FSM.v(430) | Removing redundant assignment.
@N:CG179 : UART_IF_FSM.v(437) | Removing redundant assignment.
Running optimization stage 1 on UART_IF_FSM .......
@A:CL282 : UART_IF_FSM.v(128) | Feedback mux created for signal WRITE_ADDRESS[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : UART_IF_FSM.v(128) | Feedback mux created for signal READ_ADDRESS[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : UART_IF_FSM.v(128) | Optimizing register bit option[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : UART_IF_FSM.v(128) | Optimizing register bit option[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : UART_IF_FSM.v(128) | Optimizing register bit option[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : UART_IF_FSM.v(128) | Pruning register bits 7 to 6 of option[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : UART_IF_FSM.v(128) | Pruning register bit 3 of option[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : UART_IF.v(9) | Synthesizing module UART_IF in library work.
Running optimization stage 1 on UART_IF .......
@N:CG364 : top.v(9) | Synthesizing module top in library work.
Running optimization stage 1 on top .......
Running optimization stage 2 on top .......
Running optimization stage 2 on UART_IF .......
Running optimization stage 2 on UART_IF_FSM .......
@N:CL201 : UART_IF_FSM.v(128) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 24 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001011
   001101
   001110
   001111
   010100
   010101
   010111
   011011
   011100
   011101
   011110
   011111
   100000
   100001
   100010
   100011
@W:CL279 : UART_IF_FSM.v(128) | Pruning register bits 3 to 1 of RLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : UART_IF_FSM.v(128) | Pruning register bits 3 to 1 of WLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : UART_IF_FSM.v(128) | Pruning register bit 5 of option[5:4]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on UART_IF_TPSRAM_0_TPSRAM .......
Running optimization stage 2 on RAM1K18 .......
Running optimization stage 2 on UART_IF_COREUART_0_COREUART_0s_0s_0s_24s_1s_0s .......
Running optimization stage 2 on UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s .......
@N:CL201 : Rx_async.v(871) | Trying to extract state machine for register CUARTll0.
Extracted state machine for register CUARTll0
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Running optimization stage 2 on UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s .......
@N:CL201 : Tx_async.v(301) | Trying to extract state machine for register CUARTlI0l.
Extracted state machine for register CUARTlI0l
State machine has 6 reachable states with original encodings of:
   00000000000000000000000000000000
   00000000000000000000000000000001
   00000000000000000000000000000010
   00000000000000000000000000000011
   00000000000000000000000000000100
   00000000000000000000000000000101
@N:CL159 : Tx_async.v(81) | Input CUARTI1I is unused.
@N:CL159 : Tx_async.v(84) | Input CUARTlO1 is unused.
@N:CL159 : Tx_async.v(87) | Input CUARTOI1 is unused.
Running optimization stage 2 on UART_IF_COREUART_0_Clock_gen_1s_0s .......
Running optimization stage 2 on MDDR_Demo_top .......
Running optimization stage 2 on MDDR_Demo .......
Running optimization stage 2 on SYSRESET .......
Running optimization stage 2 on MDDR_Demo_HPMS .......
@W:CL247 : MDDR_Demo_HPMS.v(112) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

Running optimization stage 2 on MSS_010 .......
Running optimization stage 2 on INBUF .......
Running optimization stage 2 on BIBUF .......
Running optimization stage 2 on OUTBUF_DIFF .......
Running optimization stage 2 on OUTBUF .......
Running optimization stage 2 on MDDR_Demo_FABOSC_0_OSC .......
@N:CL159 : MDDR_Demo_FABOSC_0_OSC.v(14) | Input XTL is unused.
Running optimization stage 2 on RCOSC_25_50MHZ .......
Running optimization stage 2 on RCOSC_25_50MHZ_FAB .......
Running optimization stage 2 on CoreResetP_Z10 .......
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state.
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state.
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state.
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state.
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state.
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused.
@N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused.
@N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused.
@N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused.
@N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused.
@N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused.
@N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused.
@N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused.
@N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused.
@N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused.
@N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused.
@N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused.
@N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused.
@N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused.
Running optimization stage 2 on CoreConfigP_Z9 .......
@N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Running optimization stage 2 on axi_feedthrough_Z8 .......
@W:CL246 : axi_feedthrough.v(310) | Input port bits 5 to 4 of BID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : axi_feedthrough.v(326) | Input port bits 5 to 4 of RID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : axi_feedthrough.v(243) | Input ACLK is unused.
@N:CL159 : axi_feedthrough.v(244) | Input ARESETN is unused.
Running optimization stage 2 on MDDR_Demo_COREAXI_0_COREAXI_Z7 .......
@N:CL159 : coreaxi.v(1135) | Input AWID_M1 is unused.
@N:CL159 : coreaxi.v(1136) | Input AWADDR_M1 is unused.
@N:CL159 : coreaxi.v(1137) | Input AWLEN_M1 is unused.
@N:CL159 : coreaxi.v(1138) | Input AWSIZE_M1 is unused.
@N:CL159 : coreaxi.v(1139) | Input AWBURST_M1 is unused.
@N:CL159 : coreaxi.v(1140) | Input AWLOCK_M1 is unused.
@N:CL159 : coreaxi.v(1141) | Input AWCACHE_M1 is unused.
@N:CL159 : coreaxi.v(1142) | Input AWPROT_M1 is unused.
@N:CL159 : coreaxi.v(1143) | Input AWVALID_M1 is unused.
@N:CL159 : coreaxi.v(1146) | Input WID_M1 is unused.
@N:CL159 : coreaxi.v(1147) | Input WDATA_M1 is unused.
@N:CL159 : coreaxi.v(1148) | Input WSTRB_M1 is unused.
@N:CL159 : coreaxi.v(1149) | Input WLAST_M1 is unused.
@N:CL159 : coreaxi.v(1150) | Input WVALID_M1 is unused.
@N:CL159 : coreaxi.v(1156) | Input BREADY_M1 is unused.
@N:CL159 : coreaxi.v(1158) | Input ARID_M1 is unused.
@N:CL159 : coreaxi.v(1159) | Input ARADDR_M1 is unused.
@N:CL159 : coreaxi.v(1160) | Input ARLEN_M1 is unused.
@N:CL159 : coreaxi.v(1161) | Input ARSIZE_M1 is unused.
@N:CL159 : coreaxi.v(1162) | Input ARBURST_M1 is unused.
@N:CL159 : coreaxi.v(1163) | Input ARLOCK_M1 is unused.
@N:CL159 : coreaxi.v(1164) | Input ARCACHE_M1 is unused.
@N:CL159 : coreaxi.v(1165) | Input ARPROT_M1 is unused.
@N:CL159 : coreaxi.v(1166) | Input ARVALID_M1 is unused.
@N:CL159 : coreaxi.v(1174) | Input RREADY_M1 is unused.
@N:CL159 : coreaxi.v(1178) | Input AWID_M2 is unused.
@N:CL159 : coreaxi.v(1179) | Input AWADDR_M2 is unused.
@N:CL159 : coreaxi.v(1180) | Input AWLEN_M2 is unused.
@N:CL159 : coreaxi.v(1181) | Input AWSIZE_M2 is unused.
@N:CL159 : coreaxi.v(1182) | Input AWBURST_M2 is unused.
@N:CL159 : coreaxi.v(1183) | Input AWLOCK_M2 is unused.
@N:CL159 : coreaxi.v(1184) | Input AWCACHE_M2 is unused.
@N:CL159 : coreaxi.v(1185) | Input AWPROT_M2 is unused.
@N:CL159 : coreaxi.v(1186) | Input AWVALID_M2 is unused.
@N:CL159 : coreaxi.v(1189) | Input WID_M2 is unused.
@N:CL159 : coreaxi.v(1190) | Input WDATA_M2 is unused.
@N:CL159 : coreaxi.v(1191) | Input WSTRB_M2 is unused.
@N:CL159 : coreaxi.v(1192) | Input WLAST_M2 is unused.
@N:CL159 : coreaxi.v(1193) | Input WVALID_M2 is unused.
@N:CL159 : coreaxi.v(1199) | Input BREADY_M2 is unused.
@N:CL159 : coreaxi.v(1201) | Input ARID_M2 is unused.
@N:CL159 : coreaxi.v(1202) | Input ARADDR_M2 is unused.
@N:CL159 : coreaxi.v(1203) | Input ARLEN_M2 is unused.
@N:CL159 : coreaxi.v(1204) | Input ARSIZE_M2 is unused.
@N:CL159 : coreaxi.v(1205) | Input ARBURST_M2 is unused.
@N:CL159 : coreaxi.v(1206) | Input ARLOCK_M2 is unused.
@N:CL159 : coreaxi.v(1207) | Input ARCACHE_M2 is unused.
@N:CL159 : coreaxi.v(1208) | Input ARPROT_M2 is unused.
@N:CL159 : coreaxi.v(1209) | Input ARVALID_M2 is unused.
@N:CL159 : coreaxi.v(1217) | Input RREADY_M2 is unused.
@N:CL159 : coreaxi.v(1221) | Input AWID_M3 is unused.
@N:CL159 : coreaxi.v(1222) | Input AWADDR_M3 is unused.
@N:CL159 : coreaxi.v(1223) | Input AWLEN_M3 is unused.
@N:CL159 : coreaxi.v(1224) | Input AWSIZE_M3 is unused.
@N:CL159 : coreaxi.v(1225) | Input AWBURST_M3 is unused.
@N:CL159 : coreaxi.v(1226) | Input AWLOCK_M3 is unused.
@N:CL159 : coreaxi.v(1227) | Input AWCACHE_M3 is unused.
@N:CL159 : coreaxi.v(1228) | Input AWPROT_M3 is unused.
@N:CL159 : coreaxi.v(1229) | Input AWVALID_M3 is unused.
@N:CL159 : coreaxi.v(1232) | Input WID_M3 is unused.
@N:CL159 : coreaxi.v(1233) | Input WDATA_M3 is unused.
@N:CL159 : coreaxi.v(1234) | Input WSTRB_M3 is unused.
@N:CL159 : coreaxi.v(1235) | Input WLAST_M3 is unused.
@N:CL159 : coreaxi.v(1236) | Input WVALID_M3 is unused.
@N:CL159 : coreaxi.v(1242) | Input BREADY_M3 is unused.
@N:CL159 : coreaxi.v(1244) | Input ARID_M3 is unused.
@N:CL159 : coreaxi.v(1245) | Input ARADDR_M3 is unused.
@N:CL159 : coreaxi.v(1246) | Input ARLEN_M3 is unused.
@N:CL159 : coreaxi.v(1247) | Input ARSIZE_M3 is unused.
@N:CL159 : coreaxi.v(1248) | Input ARBURST_M3 is unused.
@N:CL159 : coreaxi.v(1249) | Input ARLOCK_M3 is unused.
@N:CL159 : coreaxi.v(1250) | Input ARCACHE_M3 is unused.
@N:CL159 : coreaxi.v(1251) | Input ARPROT_M3 is unused.
@N:CL159 : coreaxi.v(1252) | Input ARVALID_M3 is unused.
@N:CL159 : coreaxi.v(1260) | Input RREADY_M3 is unused.
@N:CL159 : coreaxi.v(1316) | Input AWREADY_S1 is unused.

Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell.
Running optimization stage 2 on CoreAHBLite_Z6 .......
@W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused

@W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused

@W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused

@W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused

@W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused

@W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused

@W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused

@W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused

@W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused

@W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused

@W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused

@W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused

@W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused

@W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused

@W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused

@W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused

@W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused

@W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused

@W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused

@W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused

@W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused

Running optimization stage 2 on COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s .......
Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 .......
Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z5 .......
@N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState.
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 .......
Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z4 .......
Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 .......
@W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 .......
Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z3 .......
Running optimization stage 2 on CoreConfigMaster_Z2 .......
@N:CL201 : coreconfigmaster.v(723) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 29 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   100000
   100001
   100010
   100011
   100100
   100101
   100110
Running optimization stage 2 on MDDR_Demo_CCC_0_FCCC .......
Running optimization stage 2 on CCC .......
Running optimization stage 2 on CLKINT .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1 .......
@N:CL201 : AXI_IF.v(220) | Trying to extract state machine for register axi_fsm_read_state.
Extracted state machine for register axi_fsm_read_state
State machine has 3 reachable states with original encodings of:
   000
   001
   010
@N:CL201 : AXI_IF.v(93) | Trying to extract state machine for register axi_fsm_current_state.
Extracted state machine for register axi_fsm_current_state
State machine has 5 reachable states with original encodings of:
   001
   010
   011
   100
   101
@W:CL260 : AXI_IF.v(220) | Pruning register bit 1 of ARSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : AXI_IF.v(93) | Pruning register bits 7 to 1 of WSTRB[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : AXI_IF.v(93) | Pruning register bit 1 of AWSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:12s; Memory used current: 142MB peak: 158MB)

Process took 0h:00m:15s realtime, 0h:00m:12s cputime

Process completed successfully.
# Thu Apr  8 17:23:21 2021

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
File C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr  8 17:23:22 2021

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synwork\top_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:13s; Memory used current: 23MB peak: 32MB)

Process took 0h:00m:16s realtime, 0h:00m:13s cputime

Process completed successfully.
# Thu Apr  8 17:23:22 2021

###########################################################]

###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
File C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr  8 17:23:24 2021

###########################################################]

Premap Report

# Thu Apr  8 17:23:25 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

Reading constraint file: C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\designer\top\synthesis.fdc
@L: C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\top_scck.rpt 
See clock summary report "C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\top_scck.rpt"
@W:BN544 : synthesis.fdc(9) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@W:BN544 : synthesis.fdc(10) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 161MB peak: 161MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 161MB peak: 162MB)


Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 162MB peak: 162MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 162MB peak: 164MB)

@W:BN132 : axi_if.v(220) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.ARBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(93) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.AWBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3074) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3028) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(3350) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_10 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_matrix4x16.v(2936) | Removing user instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_1 because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_1 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_1 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_2 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_2 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_3 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_3 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_4 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_4 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_5 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_5 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_6 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_6 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_7 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_7 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_8 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_8 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_9 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_9 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_10 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) on net ARADDR_S1_10 (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) has its enable tied to GND.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(1388) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances.
@N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z4_0(verilog) because it does not drive other instances.
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances.
@N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z4_1(verilog) because it does not drive other instances.
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances.
@N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z4_2(verilog) because it does not drive other instances.
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because it does not drive other instances.
@N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because it does not drive other instances.
@N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because it does not drive other instances.
@N:BN115 : coreaxi.v(3681) | Removing instance genblk1\.u_axi_feedthrough (in view: work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog)) of type view:work.axi_feedthrough_Z8(verilog) because it does not drive other instances.
@N:BN115 : mddr_demo.v(1393) | Removing instance COREAXI_0 (in view: work.MDDR_Demo(verilog)) of type view:work.MDDR_Demo_COREAXI_0_COREAXI_Z7(verilog) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z9(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z9(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z9(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z9(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z9(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(1613) | Removing sequential instance CUARTI0I (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(1613) | Removing sequential instance CUARTIO0 (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because it does not drive other instances.
@N:BN362 : clock_gen.v(160) | Removing sequential instance genblk1\.CUARTOOI (in view: work.UART_IF_COREUART_0_Clock_gen_1s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(575) | Removing sequential instance CUARTO11 (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(1430) | Removing sequential instance CUARTI11 (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(653) | Removing sequential instance CUARTI01 (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(871) | Removing sequential instance CUARTl1Il (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : rx_async.v(871) | Removing sequential instance CUARTOOll (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:FX1184 :  | Applying syn_allowed_resources blockrams=21 on top level netlist top  

Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 202MB peak: 202MB)

@W:MT688 : synthesis.fdc(9) | No path from master pin (-source) to source of clock MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 due to black box MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST 
@W:MT688 : synthesis.fdc(10) | No path from master pin (-source) to source of clock MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 due to black box MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST 


Clock Summary
******************

          Start                                                            Requested     Requested     Clock                                                                             Clock                Clock
Level     Clock                                                            Frequency     Period        Type                                                                              Group                Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     50.0 MHz      20.000        declared                                                                          default_clkgroup     31   
1 .         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                          80.0 MHz      12.500        generated (from MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup     687  
1 .         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                          20.0 MHz      50.000        generated (from MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup     497  
                                                                                                                                                                                                                   
0 -       MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB      20.0 MHz      50.000        declared                                                                          default_clkgroup     109  
===================================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                 Clock     Source                                                                                  Clock Pin                                                                    Non-clock Pin     Non-clock Pin                                                                  
Clock                                                            Load      Pin                                                                                     Seq Example                                                                  Seq Example       Comb Example                                                                   
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     31        MDDR_Demo_top_0.MDDR_Demo_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ)            MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr_enable_q1.C               -                 MDDR_Demo_top_0.MDDR_Demo_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB)
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                            687       MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST.GL2(CCC)                                     UART_IF_0.UART_IF_FSM_0.RAM_WD[63:0].C                                       -                 MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.GL2_INST.I(BUFG)                             
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                            497       MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST.GL0(CCC)                                     MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST.CLK_BASE         -                 MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.GL0_INST.I(BUFG)                             
                                                                                                                                                                                                                                                                                                                                                 
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB      109       MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_010)     MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST.CLK_MDDR_APB     -                 MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv)       
=================================================================================================================================================================================================================================================================================================================================================

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\top.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 202MB)

Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00001
   010 -> 00010
   011 -> 00100
   100 -> 01000
   101 -> 10000
Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
Encoding state machine state[28:0] (in view: work.CoreConfigMaster_Z2(verilog))
original code -> new code
   000000 -> 00000000000000000000000000001
   000001 -> 00000000000000000000000000010
   000010 -> 00000000000000000000000000100
   000011 -> 00000000000000000000000001000
   000100 -> 00000000000000000000000010000
   000101 -> 00000000000000000000000100000
   000110 -> 00000000000000000000001000000
   000111 -> 00000000000000000000010000000
   001001 -> 00000000000000000000100000000
   001010 -> 00000000000000000001000000000
   001011 -> 00000000000000000010000000000
   001100 -> 00000000000000000100000000000
   001101 -> 00000000000000001000000000000
   001110 -> 00000000000000010000000000000
   001111 -> 00000000000000100000000000000
   010000 -> 00000000000001000000000000000
   010001 -> 00000000000010000000000000000
   010010 -> 00000000000100000000000000000
   010011 -> 00000000001000000000000000000
   010100 -> 00000000010000000000000000000
   010101 -> 00000000100000000000000000000
   010110 -> 00000001000000000000000000000
   100000 -> 00000010000000000000000000000
   100001 -> 00000100000000000000000000000
   100010 -> 00001000000000000000000000000
   100011 -> 00010000000000000000000000000
   100100 -> 00100000000000000000000000000
   100101 -> 01000000000000000000000000000
   100110 -> 10000000000000000000000000000
Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_1(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
Encoding state machine state[2:0] (in view: work.CoreConfigP_Z9(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z10(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine CUARTlI0l[5:0] (in view: work.UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
original code -> new code
   00000000000000000000000000000000 -> 000001
   00000000000000000000000000000001 -> 000010
   00000000000000000000000000000010 -> 000100
   00000000000000000000000000000011 -> 001000
   00000000000000000000000000000100 -> 010000
   00000000000000000000000000000101 -> 100000
Encoding state machine CUARTll0[3:0] (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine fsm[23:0] (in view: work.UART_IF_FSM(verilog))
original code -> new code
   000000 -> 000000000000000000000001
   000001 -> 000000000000000000000010
   000010 -> 000000000000000000000100
   000011 -> 000000000000000000001000
   000100 -> 000000000000000000010000
   000101 -> 000000000000000000100000
   000110 -> 000000000000000001000000
   000111 -> 000000000000000010000000
   001011 -> 000000000000000100000000
   001101 -> 000000000000001000000000
   001110 -> 000000000000010000000000
   001111 -> 000000000000100000000000
   010100 -> 000000000001000000000000
   010101 -> 000000000010000000000000
   010111 -> 000000000100000000000000
   011011 -> 000000001000000000000000
   011100 -> 000000010000000000000000
   011101 -> 000000100000000000000000
   011110 -> 000001000000000000000000
   011111 -> 000010000000000000000000
   100000 -> 000100000000000000000000
   100001 -> 001000000000000000000000
   100010 -> 010000000000000000000000
   100011 -> 100000000000000000000000

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 221MB)

@W:MF511 :  | Found issues with constraints. Please check constraint checker report "C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\top_cck.rpt" . 

Finished constraint checker (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 206MB peak: 221MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 99MB peak: 221MB)

Process took 0h:00m:05s realtime, 0h:00m:04s cputime
# Thu Apr  8 17:23:30 2021

###########################################################]

Map & Optimize Report

# Thu Apr  8 17:23:30 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 130MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB)

@N:MO111 : mddr_demo_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.MDDR_Demo_FABOSC_0_OSC(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N:BN362 : rx_async.v(1339) | Removing sequential instance CUARTI0Il (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)

Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00001
   010 -> 00010
   011 -> 00100
   100 -> 01000
   101 -> 10000
Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
@N:MO231 : axi_if.v(93) | Found counter in view:work.AXI_IF_0s_1s_2s_3s_0s_1s_2s_4294967292s_4294967293s_Z1(verilog) instance WDATA_int[63:0] 
Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.MDDR_Demo(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[16] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[17] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[18] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[19] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[20] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[21] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[22] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[23] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[24] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[25] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[26] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[27] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[28] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[29] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[30] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[31] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[11] (in view: work.MDDR_Demo(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[31] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[30] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[29] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[28] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[27] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[26] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[25] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[24] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[23] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[22] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[21] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.MDDR_Demo(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[14] (in view: work.MDDR_Demo(verilog)) because it does not drive other instances.
@W:BN132 : coreconfigp.v(546) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine state[28:0] (in view: work.CoreConfigMaster_Z2(verilog))
original code -> new code
   000000 -> 00000000000000000000000000001
   000001 -> 00000000000000000000000000010
   000010 -> 00000000000000000000000000100
   000011 -> 00000000000000000000000001000
   000100 -> 00000000000000000000000010000
   000101 -> 00000000000000000000000100000
   000110 -> 00000000000000000000001000000
   000111 -> 00000000000000000000010000000
   001001 -> 00000000000000000000100000000
   001010 -> 00000000000000000001000000000
   001011 -> 00000000000000000010000000000
   001100 -> 00000000000000000100000000000
   001101 -> 00000000000000001000000000000
   001110 -> 00000000000000010000000000000
   001111 -> 00000000000000100000000000000
   010000 -> 00000000000001000000000000000
   010001 -> 00000000000010000000000000000
   010010 -> 00000000000100000000000000000
   010011 -> 00000000001000000000000000000
   010100 -> 00000000010000000000000000000
   010101 -> 00000000100000000000000000000
   010110 -> 00000001000000000000000000000
   100000 -> 00000010000000000000000000000
   100001 -> 00000100000000000000000000000
   100010 -> 00001000000000000000000000000
   100011 -> 00010000000000000000000000000
   100100 -> 00100000000000000000000000000
   100101 -> 01000000000000000000000000000
   100110 -> 10000000000000000000000000000
@N:MO231 : coreconfigmaster.v(723) | Found counter in view:work.CoreConfigMaster_Z2(verilog) instance pause_count[4:0] 
@W:MO160 : coreconfigmaster.v(723) | Register bit HSIZE[2] (in view view:work.CoreConfigMaster_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:MF179 : coreconfigmaster.v(573) | Found 32 by 32 bit equality operator ('==') d_state152 (in view: work.CoreConfigMaster_Z2(verilog))
@N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_1(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z10(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z10(verilog) instance count_ddr[13:0] 
@N:MO231 : clock_gen.v(219) | Found counter in view:work.UART_IF_COREUART_0_Clock_gen_1s_0s(verilog) instance genblk1\.CUARTO0[12:0] 
Encoding state machine CUARTlI0l[5:0] (in view: work.UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
original code -> new code
   00000000000000000000000000000000 -> 000001
   00000000000000000000000000000001 -> 000010
   00000000000000000000000000000010 -> 000100
   00000000000000000000000000000011 -> 001000
   00000000000000000000000000000100 -> 010000
   00000000000000000000000000000101 -> 100000
@W:MO160 : tx_async.v(301) | Register bit CUARTlI0l[4] (in view view:work.UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:BN362 : tx_async.v(808) | Removing sequential instance CUARTO00l (in view: work.UART_IF_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) because it does not drive other instances.
Encoding state machine CUARTll0[3:0] (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@W:MO161 : rx_async.v(754) | Register bit CUARTIOll[3] (in view view:work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : rx_async.v(754) | Register bit CUARTIOll[2] (in view view:work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : rx_async.v(754) | Register bit CUARTIOll[1] (in view view:work.UART_IF_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine fsm[23:0] (in view: work.UART_IF_FSM(verilog))
original code -> new code
   000000 -> 000000000000000000000001
   000001 -> 000000000000000000000010
   000010 -> 000000000000000000000100
   000011 -> 000000000000000000001000
   000100 -> 000000000000000000010000
   000101 -> 000000000000000000100000
   000110 -> 000000000000000001000000
   000111 -> 000000000000000010000000
   001011 -> 000000000000000100000000
   001101 -> 000000000000001000000000
   001110 -> 000000000000010000000000
   001111 -> 000000000000100000000000
   010100 -> 000000000001000000000000
   010101 -> 000000000010000000000000
   010111 -> 000000000100000000000000
   011011 -> 000000001000000000000000
   011100 -> 000000010000000000000000
   011101 -> 000000100000000000000000
   011110 -> 000001000000000000000000
   011111 -> 000010000000000000000000
   100000 -> 000100000000000000000000
   100001 -> 001000000000000000000000
   100010 -> 010000000000000000000000
   100011 -> 100000000000000000000000
@N:MO231 : uart_if_fsm.v(128) | Found counter in view:work.UART_IF_FSM(verilog) instance cnt_1k[9:0] 
@N:MO231 : uart_if_fsm.v(128) | Found counter in view:work.UART_IF_FSM(verilog) instance RAM_WADDR[7:0] 
@N:MO231 : uart_if_fsm.v(128) | Found counter in view:work.UART_IF_FSM(verilog) instance RAM_RADDR[10:0] 

Starting factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 192MB peak: 204MB)

@W:BN132 : axi_if.v(93) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[3] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(93) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[2] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(93) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[1] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(220) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[3] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(220) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[2] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(220) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[1] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_0.CORERESETP_0.DDR_READY_int (in view: work.MDDR_Demo_top(verilog)) because it does not drive other instances.
@N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance MDDR_Demo_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view: work.MDDR_Demo_top(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:06s; Memory used current: 205MB peak: 205MB)

@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] (in view: work.top(verilog)) because it does not drive other instances.
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] (in view: work.top(verilog)) because it does not drive other instances.
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] (in view: work.top(verilog)) because it does not drive other instances.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:06s; Memory used current: 196MB peak: 208MB)

@N:BN362 : rx_async.v(1154) | Removing sequential instance UART_IF_0.COREUART_0.CUARTO01.CUARTO0Il[8] (in view: work.top(verilog)) because it does not drive other instances.
@W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] (in view: work.top(verilog)) because it does not drive other instances.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:07s; Memory used current: 197MB peak: 208MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:07s; Memory used current: 197MB peak: 208MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 197MB peak: 208MB)

@N:BN362 : coreconfigmaster.v(723) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.ConfigMaster_0.state[8] (in view: work.top(verilog)) because it does not drive other instances.

Finished preparing to map (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 198MB peak: 208MB)


Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:09s; Memory used current: 225MB peak: 225MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:09s		     3.38ns		1611 /      1240
@N:FP130 :  | Promoting Net INIT_DONE_int_arst on CLKINT  I_276  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MSS_HPMS_READY_int_arst on CLKINT  I_277  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.FIC_2_APB_M_PRESET_N_arst on CLKINT  I_278  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_279  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_280  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_281  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm0_areset_n_arst on CLKINT  I_282  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:10s; Memory used current: 226MB peak: 226MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:10s; Memory used current: 227MB peak: 227MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
2 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 1146 clock pin(s) of sequential element(s)
0 instances converted, 1146 sequential instances remain driven by gated/generated clocks

=============================================================================== Non-Gated/Non-Generated Clocks ================================================================================
Clock Tree ID     Driving Element                                                 Drive Element Type                     Fanout     Sample Instance                                            
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0003        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     clock definition on MSS_010            75         MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST
ClockId0004        MDDR_Demo_top_0.MDDR_Demo_0.FABOSC_0.I_RCOSC_25_50MHZ           clock definition on RCOSC_25_50MHZ     31         MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[13]     
===============================================================================================================================================================================================
=================================================================================================== Gated/Generated Clocks ===================================================================================================
Clock Tree ID     Driving Element                                Drive Element Type     Fanout     Sample Instance                                                 Explanation                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST     CCC                    671        MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63]                          No gated clock conversion method for cell cell:ACG4.SLE    
ClockId0002        MDDR_Demo_top_0.MDDR_Demo_0.CCC_0.CCC_INST     CCC                    475        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_010
==============================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:10s; Memory used current: 189MB peak: 227MB)

Writing Analyst data base C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\synthesis\synwork\top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:11s; Memory used current: 221MB peak: 227MB)

Writing Verilog Simulation files
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:13s; Memory used current: 222MB peak: 227MB)


Start final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:13s; Memory used current: 219MB peak: 227MB)

@W:MT246 : mddr_demo_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB with period 50.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 with period 50.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 with period 12.50ns  


##### START OF TIMING REPORT #####[
# Timing report written on Thu Apr  8 17:23:48 2021
#


Top view:               top
Requested Frequency:    20.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\designer\top\synthesis.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: 4.949

                                                                 Requested     Estimated     Requested     Estimated                Clock                                                                             Clock           
Starting Clock                                                   Frequency     Frequency     Period        Period        Slack      Type                                                                              Group           
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                            20.0 MHz      33.1 MHz      50.000        30.202        4.949      generated (from MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                            80.0 MHz      132.4 MHz     12.500        7.551         7.492      generated (from MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     50.0 MHz      502.7 MHz     20.000        1.989         18.011     declared                                                                          default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB      20.0 MHz      145.3 MHz     50.000        6.884         21.793     declared                                                                          default_clkgroup
======================================================================================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise  
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                      Ending                                                        |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT  MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT  |  20.000      18.011  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT  MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         |  10.000      False   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB   MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB   |  50.000      43.116  |  No paths    -      |  25.000      23.233  |  25.000      21.793
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB   MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         |  50.000      False   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT  |  10.000      False   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB   |  50.000      False   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         |  50.000      40.037  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                         |  12.500      4.950   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0                         |  12.500      10.115  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2                         |  12.500      7.492   |  No paths    -      |  No paths    -       |  No paths    -     
=====================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0
====================================



Starting Points with Worst Slack
********************************

                                                                Starting                                                                                                                      Arrival          
Instance                                                        Reference                                 Type        Pin                      Net                                            Time        Slack
                                                                Clock                                                                                                                                          
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_AWREADY_HREADYOUT0     AXI_IF_0_BIF_1_AWREADY                         2.946       4.949
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_WREADY                 AXI_IF_0_BIF_1_WREADY                          2.859       5.139
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RVALID                 MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0        2.762       5.970
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RLAST                  MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0         2.603       6.308
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_BVALID                 AXI_IF_0_BIF_1_BVALID                          2.788       8.346
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RDATA_HRDATA01[41]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[41]     3.062       8.391
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RDATA_HRDATA01[16]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[16]     2.600       8.413
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RDATA_HRDATA01[13]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[13]     2.572       8.441
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RDATA_HRDATA01[47]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[47]     2.554       8.459
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     MSS_010     F_RDATA_HRDATA01[36]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[36]     2.956       8.497
===============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                                  Required          
Instance                                  Reference                                 Type     Pin     Net            Time         Slack
                                          Clock                                                                                       
--------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[0]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[1]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[2]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[3]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[4]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[5]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[6]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[7]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[8]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[9]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0     SLE      EN      WDATA_inte     12.207       4.949
======================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      12.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.207

    - Propagation time:                      7.257
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     4.950

    Number of logic level(s):                2
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA_int[0] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 [rising] (rise=0.000 fall=25.000 period=50.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK

Instance / Net                                                              Pin                      Pin               Arrival     No. of    
Name                                                            Type        Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MSS_010     F_AWREADY_HREADYOUT0     Out     2.946     2.946 f     -         
AXI_IF_0_BIF_1_AWREADY                                          Net         -                        -       0.849     -           8         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNIBBE31[2]      CFG4        B                        In      -         3.795 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNIBBE31[2]      CFG4        Y                        Out     0.143     3.938 f     -         
N_145_i_0                                                       Net         -                        -       1.588     -           65        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI1V8H1[0]      CFG3        B                        In      -         5.526 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI1V8H1[0]      CFG3        Y                        Out     0.143     5.669 f     -         
WDATA_inte                                                      Net         -                        -       1.588     -           64        
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[0]                           SLE         EN                       In      -         7.257 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 7.550 is 3.525(46.7%) logic and 4.025(53.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2
====================================



Starting Points with Worst Slack
********************************

                                                      Starting                                                                                Arrival          
Instance                                              Reference                                 Type     Pin     Net                          Time        Slack
                                                      Clock                                                                                                    
---------------------------------------------------------------------------------------------------------------------------------------------------------------
UART_IF_0.COREUART_0.genblk1\.RXRDY                   MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       COREUART_0_RXRDY             0.076       7.492
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[1]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       axi_fsm_current_state[1]     0.094       7.578
UART_IF_0.UART_IF_FSM_0.rx_en                         MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       rx_en                        0.076       7.586
UART_IF_0.UART_IF_FSM_0.fsm[9]                        MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       fsm[9]                       0.094       7.690
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[2]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       axi_fsm_current_state[2]     0.094       7.762
UART_IF_0.UART_IF_FSM_0.fsm[4]                        MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       fsm[4]                       0.076       8.204
UART_IF_0.COREUART_0.CUARTO01.CUARTll0[1]             MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       CUARTll0[1]                  0.076       8.386
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[0]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       axi_fsm_current_state[0]     0.094       8.408
UART_IF_0.COREUART_0.CUARTO01.CUARTll0[0]             MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       CUARTll0[0]                  0.076       8.423
MDDR_Demo_top_0.AXI_IF_0.RREADY                       MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      Q       MDDR_Demo_top_0_RREADY       0.094       8.485
===============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                                     Required          
Instance                                  Reference                                 Type     Pin     Net               Time         Slack
                                          Clock                                                                                          
-----------------------------------------------------------------------------------------------------------------------------------------
UART_IF_0.UART_IF_FSM_0.cnt_data[1]       MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      D       cnt_data_8[1]     12.278       7.492
UART_IF_0.UART_IF_FSM_0.cnt_data[2]       MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      D       cnt_data_8[2]     12.278       7.512
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[0]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[1]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[2]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[3]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[4]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[5]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[6]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
MDDR_Demo_top_0.AXI_IF_0.WDATA_int[7]     MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2     SLE      EN      WDATA_inte        12.207       7.578
=========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      12.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.278

    - Propagation time:                      4.786
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 7.492

    Number of logic level(s):                5
    Starting point:                          UART_IF_0.COREUART_0.genblk1\.RXRDY / Q
    Ending point:                            UART_IF_0.UART_IF_FSM_0.cnt_data[1] / D
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                                    Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
UART_IF_0.COREUART_0.genblk1\.RXRDY                     SLE      Q        Out     0.076     0.076 r     -         
COREUART_0_RXRDY                                        Net      -        -       0.779     -           6         
UART_IF_0.UART_IF_FSM_0.fsm_ns_i_0_o2[4]                CFG2     A        In      -         0.855 r     -         
UART_IF_0.UART_IF_FSM_0.fsm_ns_i_0_o2[4]                CFG2     Y        Out     0.087     0.942 f     -         
N_393                                                   Net      -        -       0.708     -           4         
UART_IF_0.UART_IF_FSM_0.cnt_data_0_sqmuxa_i_o4_i_a3     CFG2     A        In      -         1.651 f     -         
UART_IF_0.UART_IF_FSM_0.cnt_data_0_sqmuxa_i_o4_i_a3     CFG2     Y        Out     0.076     1.726 f     -         
N_948                                                   Net      -        -       1.415     -           63        
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0_o3[0]              CFG4     C        In      -         3.141 f     -         
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0_o3[0]              CFG4     Y        Out     0.194     3.335 r     -         
N_403                                                   Net      -        -       0.648     -           3         
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0_1[1]               CFG4     D        In      -         3.983 r     -         
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0_1[1]               CFG4     Y        Out     0.284     4.267 f     -         
cnt_data_8_0_1[1]                                       Net      -        -       0.216     -           1         
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0[1]                 CFG4     A        In      -         4.483 f     -         
UART_IF_0.UART_IF_FSM_0.cnt_data_8_0[1]                 CFG4     Y        Out     0.087     4.570 r     -         
cnt_data_8[1]                                           Net      -        -       0.216     -           1         
UART_IF_0.UART_IF_FSM_0.cnt_data[1]                     SLE      D        In      -         4.786 r     -         
==================================================================================================================
Total path delay (propagation time + setup) of 5.008 is 1.026(20.5%) logic and 3.982(79.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT
====================================



Starting Points with Worst Slack
********************************

                                                          Starting                                                                                           Arrival           
Instance                                                  Reference                                                        Type     Pin     Net              Time        Slack 
                                                          Clock                                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[0]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[0]     0.076       18.011
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[1]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[1]     0.076       18.295
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[3]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[3]     0.076       18.314
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[4]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[4]     0.094       18.350
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[2]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[2]     0.076       18.382
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[5]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[5]     0.076       18.386
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[8]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[8]     0.094       18.418
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[6]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[6]     0.076       18.423
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[7]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[7]     0.076       18.454
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[9]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[9]     0.094       18.457
===============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                           Starting                                                                                              Required           
Instance                                                   Reference                                                        Type     Pin     Net                 Time         Slack 
                                                           Clock                                                                                                                    
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled       MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      EN      ddr_settled4        19.706       18.011
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[13]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[13]     19.778       18.411
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[12]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[12]     19.778       18.425
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[11]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[11]     19.778       18.440
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[10]     MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[10]     19.778       18.454
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[9]      MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[9]      19.778       18.468
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[8]      MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[8]      19.778       18.482
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[7]      MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[7]      19.778       18.497
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[6]      MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[6]      19.778       18.511
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[5]      MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[5]      19.778       18.525
====================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.294
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.706

    - Propagation time:                      1.696
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 18.011

    Number of logic level(s):                2
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[0] / Q
    Ending point:                            MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.count_ddr[0]       SLE      Q        Out     0.076     0.076 r     -         
count_ddr[0]                                                Net      -        -       0.648     -           3         
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled4_9     CFG4     D        In      -         0.724 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled4_9     CFG4     Y        Out     0.284     1.008 f     -         
ddr_settled4_9                                              Net      -        -       0.216     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled4       CFG4     D        In      -         1.224 f     -         
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled4       CFG4     Y        Out     0.250     1.474 f     -         
ddr_settled4                                                Net      -        -       0.221     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.ddr_settled        SLE      EN       In      -         1.696 f     -         
======================================================================================================================
Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB
====================================



Starting Points with Worst Slack
********************************

                                                                Starting                                                                                                                                           Arrival           
Instance                                                        Reference                                                       Type        Pin                        Net                                         Time        Slack 
                                                                Clock                                                                                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.psel                  MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          psel                                        0.076       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.state[1]              MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          state[1]                                    0.076       23.233
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.paddr[13]             MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          paddr[13]                                   0.094       23.626
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.state[0]              MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          state[0]                                    0.076       23.634
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.paddr[15]             MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          paddr[15]                                   0.094       23.691
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.MDDR_PENABLE          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          CORECONFIGP_0_MDDR_APBmslave_PENABLE        0.094       23.934
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.paddr[12]             MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE         Q                          paddr[12]                                   0.094       23.949
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     MSS_010     MDDR_FABRIC_PREADY         CORECONFIGP_0_MDDR_APBmslave_PREADY         5.435       43.116
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     MSS_010     MDDR_FABRIC_PRDATA[12]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[12]     5.461       43.818
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     MSS_010     MDDR_FABRIC_PRDATA[10]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[10]     5.432       43.847
=====================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                    Starting                                                                                       Required           
Instance                                                            Reference                                                       Type     Pin     Net           Time         Slack 
                                                                    Clock                                                                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[0]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[1]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[2]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[3]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[4]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[5]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[6]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[7]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[8]     24.778       21.793
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB     SLE      D       prdata[9]     24.778       21.793
======================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.778

    - Propagation time:                      2.985
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 21.793

    Number of logic level(s):                3
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.psel / Q
    Ending point:                            MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] / D
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=25.000 period=50.000) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=25.000 period=50.000) on pin CLK

Instance / Net                                                                    Pin      Pin               Arrival     No. of    
Name                                                                     Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.psel                           SLE      Q        Out     0.076     0.076 r     -         
psel                                                                     Net      -        -       0.648     -           3         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.int_sel_0_sqmuxa               CFG3     B        In      -         0.724 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.int_sel_0_sqmuxa               CFG3     Y        Out     0.143     0.867 r     -         
int_sel_0_sqmuxa                                                         Net      -        -       0.648     -           3         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa           CFG2     A        In      -         1.515 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa           CFG2     Y        Out     0.067     1.583 r     -         
un1_int_sel_0_sqmuxa                                                     Net      -        -       1.010     -           18        
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[16]     CFG4     C        In      -         2.592 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[16]     CFG4     Y        Out     0.177     2.769 r     -         
prdata[16]                                                               Net      -        -       0.216     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16]         SLE      D        In      -         2.985 r     -         
===================================================================================================================================
Total path delay (propagation time + setup) of 3.207 is 0.685(21.4%) logic and 2.522(78.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
@W:MT447 : synthesis.fdc(13) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm0_areset_n_rcosc MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(14) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(16) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_HPMS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(17) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
None

Finished final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:13s; Memory used current: 220MB peak: 227MB)


Finished timing report (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:14s; Memory used current: 220MB peak: 227MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: m2gl010tsvf400-1
Cell usage:
CCC             1 use
CLKINT          10 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
RCOSC_25_50MHZ_FAB  1 use
SYSRESET        1 use
CFG1           7 uses
CFG2           230 uses
CFG3           312 uses
CFG4           578 uses

Carry cells:
ARI1            305 uses - used for arithmetic functions
ARI1            5 uses - used for Wide-Mux implementation
Total ARI1      310 uses


Sequential Cells: 
SLE            1242 uses

DSP Blocks:    0 of 22 (0%)

I/O ports: 53
I/O primitives: 51
BIBUF          20 uses
INBUF          2 uses
OUTBUF         28 uses
OUTBUF_DIFF    1 use


Global Clock Buffers: 10

RAM/ROM usage summary
Total Block RAMs (RAM1K18) : 4 of 21 (19%)

Total LUTs:    1437

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 144; LUTs = 144;
MACC     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  1242 + 0 + 144 + 0 = 1386;
Total number of LUTs after P&R:  1437 + 0 + 144 + 0 = 1581;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:14s; Memory used current: 75MB peak: 227MB)

Process took 0h:00m:18s realtime, 0h:00m:14s cputime
# Thu Apr  8 17:23:49 2021

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