@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5291:10:5291:27|Net RREADY_M0IS0_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5292:10:5292:27|Net RREADY_M0IS1_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5293:10:5293:27|Net RREADY_M0IS2_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5294:10:5294:27|Net RREADY_M0IS3_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5295:10:5295:27|Net RREADY_M0IS4_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5296:10:5296:27|Net RREADY_M0IS5_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5297:10:5297:27|Net RREADY_M0IS6_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5298:10:5298:27|Net RREADY_M0IS7_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5299:10:5299:27|Net RREADY_M0IS8_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5300:10:5300:27|Net RREADY_M0IS9_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5301:10:5301:28|Net RREADY_M0IS10_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5302:10:5302:28|Net RREADY_M0IS11_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5303:10:5303:28|Net RREADY_M0IS12_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5304:10:5304:28|Net RREADY_M0IS13_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5305:10:5305:28|Net RREADY_M0IS14_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5306:10:5306:28|Net RREADY_M0IS15_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5307:10:5307:28|Net RREADY_M0IS16_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5309:10:5309:27|Net RREADY_M1IS0_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5310:10:5310:27|Net RREADY_M1IS1_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5311:10:5311:27|Net RREADY_M1IS2_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5312:10:5312:27|Net RREADY_M1IS3_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5313:10:5313:27|Net RREADY_M1IS4_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5314:10:5314:27|Net RREADY_M1IS5_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5315:10:5315:27|Net RREADY_M1IS6_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5316:10:5316:27|Net RREADY_M1IS7_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5317:10:5317:27|Net RREADY_M1IS8_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5318:10:5318:27|Net RREADY_M1IS9_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5319:10:5319:28|Net RREADY_M1IS10_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5320:10:5320:28|Net RREADY_M1IS11_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5321:10:5321:28|Net RREADY_M1IS12_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5322:10:5322:28|Net RREADY_M1IS13_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5323:10:5323:28|Net RREADY_M1IS14_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5324:10:5324:28|Net RREADY_M1IS15_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5325:10:5325:28|Net RREADY_M1IS16_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5327:10:5327:27|Net RREADY_M2IS0_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5328:10:5328:27|Net RREADY_M2IS1_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5329:10:5329:27|Net RREADY_M2IS2_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5330:10:5330:27|Net RREADY_M2IS3_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5331:10:5331:27|Net RREADY_M2IS4_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5332:10:5332:27|Net RREADY_M2IS5_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5333:10:5333:27|Net RREADY_M2IS6_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5334:10:5334:27|Net RREADY_M2IS7_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5335:10:5335:27|Net RREADY_M2IS8_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5336:10:5336:27|Net RREADY_M2IS9_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5337:10:5337:28|Net RREADY_M2IS10_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5338:10:5338:28|Net RREADY_M2IS11_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5339:10:5339:28|Net RREADY_M2IS12_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5340:10:5340:28|Net RREADY_M2IS13_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5341:10:5341:28|Net RREADY_M2IS14_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5342:10:5342:28|Net RREADY_M2IS15_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5343:10:5343:28|Net RREADY_M2IS16_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5345:10:5345:27|Net RREADY_M3IS0_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5346:10:5346:27|Net RREADY_M3IS1_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5347:10:5347:27|Net RREADY_M3IS2_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5348:10:5348:27|Net RREADY_M3IS3_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5349:10:5349:27|Net RREADY_M3IS4_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5350:10:5350:27|Net RREADY_M3IS5_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5351:10:5351:27|Net RREADY_M3IS6_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5352:10:5352:27|Net RREADY_M3IS7_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5353:10:5353:27|Net RREADY_M3IS8_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5354:10:5354:27|Net RREADY_M3IS9_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5355:10:5355:28|Net RREADY_M3IS10_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5356:10:5356:28|Net RREADY_M3IS11_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5357:10:5357:28|Net RREADY_M3IS12_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5358:10:5358:28|Net RREADY_M3IS13_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5359:10:5359:28|Net RREADY_M3IS14_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5360:10:5360:28|Net RREADY_M3IS15_gated is not declared.
@W: CG1337 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v":5361:10:5361:28|Net RREADY_M3IS16_gated is not declared.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Optimizing register bit AWBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Optimizing register bit AWSIZE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":220:0:220:5|Optimizing register bit ARBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Pruning register bit 1 of AWBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Pruning register bit 2 of AWSIZE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":220:0:220:5|Pruning register bit 1 of ARBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2639:2:2639:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":209:2:209:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2703:2:2703:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":209:2:209:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2767:2:2767:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2831:2:2831:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\MDDR_Demo.v":1393:0:1393:8|Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|Removing wire AWID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|Removing wire AWADDR_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|Removing wire AWLEN_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|Removing wire AWSIZE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|Removing wire AWBURST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|Removing wire AWLOCK_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|Removing wire AWCACHE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|Removing wire AWPROT_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|Removing wire AWVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|Removing wire WID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|Removing wire WDATA_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|Removing wire WSTRB_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|Removing wire WLAST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Removing wire WVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|Removing wire BREADY_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|Removing wire ARID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|Removing wire ARADDR_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|Removing wire ARLEN_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Removing wire ARSIZE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|Removing wire ARBURST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|Removing wire ARLOCK_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|Removing wire ARCACHE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|Removing wire ARPROT_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|Removing wire ARVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|Removing wire RREADY_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|Removing wire AWID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|Removing wire AWADDR_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|Removing wire AWLEN_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|Removing wire AWSIZE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|Removing wire AWBURST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|Removing wire AWLOCK_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|Removing wire AWCACHE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|Removing wire AWPROT_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|Removing wire AWVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|Removing wire WID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|Removing wire WDATA_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|Removing wire WSTRB_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|Removing wire WLAST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Removing wire WVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|Removing wire BREADY_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|Removing wire ARID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|Removing wire ARADDR_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|Removing wire ARLEN_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Removing wire ARSIZE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|Removing wire ARBURST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|Removing wire ARLOCK_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|Removing wire ARCACHE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|Removing wire ARPROT_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|Removing wire ARVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|Removing wire RREADY_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|Removing wire AWID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|Removing wire AWADDR_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|Removing wire AWLEN_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|Removing wire AWSIZE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|Removing wire AWBURST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|Removing wire AWLOCK_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|Removing wire AWCACHE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|Removing wire AWPROT_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|Removing wire AWVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|Removing wire WID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|Removing wire WDATA_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|Removing wire WSTRB_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|Removing wire WLAST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Removing wire WVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|Removing wire BREADY_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|Removing wire ARID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|Removing wire ARADDR_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|Removing wire ARLEN_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Removing wire ARSIZE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|Removing wire ARBURST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|Removing wire ARLOCK_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|Removing wire ARCACHE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|Removing wire ARPROT_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|Removing wire ARVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|Removing wire RREADY_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|Removing wire AWID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|Removing wire AWADDR_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|Removing wire AWLEN_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|Removing wire AWSIZE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|Removing wire AWBURST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|Removing wire AWLOCK_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|Removing wire AWCACHE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|Removing wire AWPROT_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|Removing wire AWVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|Removing wire WID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|Removing wire WDATA_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|Removing wire WSTRB_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|Removing wire WLAST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Removing wire WVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|Removing wire BREADY_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|Removing wire ARID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|Removing wire ARADDR_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|Removing wire ARLEN_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Removing wire ARSIZE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|Removing wire ARBURST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|Removing wire ARLOCK_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|Removing wire ARCACHE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|Removing wire ARPROT_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|Removing wire ARVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|Removing wire RREADY_S4, as there is no assignment to it.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1144:33:1144:42|*Output AWREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|*Output WREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1153:33:1153:38|*Output BID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1154:33:1154:40|*Output BRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|*Output BVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1167:33:1167:42|*Output ARREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1169:33:1169:38|*Output RID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1170:33:1170:40|*Output RDATA_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1171:33:1171:40|*Output RRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1172:33:1172:40|*Output RLAST_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1173:33:1173:41|*Output RVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1187:33:1187:42|*Output AWREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|*Output WREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1196:33:1196:38|*Output BID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1197:33:1197:40|*Output BRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|*Output BVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1210:33:1210:42|*Output ARREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1212:33:1212:38|*Output RID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1213:33:1213:40|*Output RDATA_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1214:33:1214:40|*Output RRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1215:33:1215:40|*Output RLAST_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1216:33:1216:41|*Output RVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1230:33:1230:42|*Output AWREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|*Output WREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1239:33:1239:38|*Output BID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1240:33:1240:40|*Output BRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|*Output BVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1253:33:1253:42|*Output ARREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1255:33:1255:38|*Output RID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1256:33:1256:40|*Output RDATA_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1257:33:1257:40|*Output RRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1258:33:1258:40|*Output RLAST_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1259:33:1259:41|*Output RVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|*Output AWID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|*Output AWADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|*Output AWLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|*Output AWSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|*Output AWBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|*Output AWLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|*Output AWCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|*Output AWPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|*Output AWVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|*Output WID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|*Output WDATA_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|*Output WSTRB_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|*Output WLAST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|*Output WVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|*Output BREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|*Output ARID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|*Output ARADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|*Output ARLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|*Output ARSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|*Output ARBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|*Output ARLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|*Output ARCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|*Output ARPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|*Output ARVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|*Output RREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|*Output AWID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|*Output AWADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|*Output AWLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|*Output AWSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|*Output AWBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|*Output AWLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|*Output AWCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|*Output AWPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|*Output AWVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|*Output WID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|*Output WDATA_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|*Output WSTRB_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|*Output WLAST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|*Output WVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|*Output BREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|*Output ARID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|*Output ARADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|*Output ARLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|*Output ARSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|*Output ARBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|*Output ARLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|*Output ARCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|*Output ARPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|*Output ARVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|*Output RREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|*Output AWID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|*Output AWADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|*Output AWLEN_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|*Output AWSIZE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|*Output AWBURST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|*Output AWLOCK_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|*Output AWCACHE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|*Output AWPROT_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|*Output AWVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|*Output WID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|*Output WDATA_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|*Output WSTRB_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|*Output WLAST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|*Output WVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|*Output BREADY_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|*Output ARID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|*Output ARADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CG1340 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":333:0:333:7|Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1268:0:1268:5|Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1106:0:1106:5|Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":984:0:984:5|Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":405:0:405:5|Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Optimizing register bit option[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Optimizing register bit option[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Optimizing register bit option[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Pruning register bits 7 to 6 of option[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Pruning register bit 3 of option[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Pruning register bits 3 to 1 of RLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Pruning register bits 3 to 1 of WLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Pruning register bit 5 of option[5:4]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS.v":112:14:112:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":310:57:310:62|Input port bits 5 to 4 of BID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":326:57:326:62|Input port bits 5 to 4 of RID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":220:0:220:5|Pruning register bit 1 of ARSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Pruning register bits 7 to 1 of WSTRB[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Pruning register bit 1 of AWSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.

