@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":21:7:21:12|Synthesizing module AXI_IF in library work.
@N: CG775 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":729:7:729:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\CCC_0\MDDR_Demo_CCC_0_FCCC.v":5:7:5:26|Synthesizing module MDDR_Demo_CCC_0_FCCC in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite in library COREAHBLITE_LIB.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:33|Synthesizing module MDDR_Demo_COREAXI_0_COREAXI in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|Synthesizing module axi_feedthrough in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\FABOSC_0\MDDR_Demo_FABOSC_0_OSC.v":5:7:5:28|Synthesizing module MDDR_Demo_FABOSC_0_OSC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010 in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS.v":9:7:9:20|Synthesizing module MDDR_Demo_HPMS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":720:7:720:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\MDDR_Demo.v":9:7:9:15|Synthesizing module MDDR_Demo in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_top\MDDR_Demo_top.v":9:7:9:19|Synthesizing module MDDR_Demo_top in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:27|Synthesizing module UART_IF_COREUART_0_Clock_gen in library work.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":346:0:346:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":427:0:427:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":532:0:532:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":611:0:611:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":716:0:716:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":808:0:808:6|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":915:0:915:6|Removing redundant assignment.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:26|Synthesizing module UART_IF_COREUART_0_Tx_async in library work.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":870:0:870:8|Removing redundant assignment.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:26|Synthesizing module UART_IF_COREUART_0_Rx_async in library work.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":750:0:750:7|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":857:0:857:8|Removing redundant assignment.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:26|Synthesizing module UART_IF_COREUART_0_COREUART in library work.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1338:0:1338:7|Removing redundant assignment.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":382:7:382:13|Synthesizing module RAM1K18 in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v":5:7:5:29|Synthesizing module UART_IF_TPSRAM_0_TPSRAM in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":20:7:20:17|Synthesizing module UART_IF_FSM in library work.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":430:35:430:45|Removing redundant assignment.
@N: CG179 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":437:15:437:20|Removing redundant assignment.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\UART_IF.v":9:7:9:13|Synthesizing module UART_IF in library work.
@N: CG364 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v":128:0:128:5|Trying to extract state machine for register fsm.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":871:0:871:5|Trying to extract state machine for register CUARTll0.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Trying to extract state machine for register CUARTlI0l.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":81:0:81:7|Input CUARTI1I is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":84:0:84:7|Input CUARTlO1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":87:0:87:7|Input CUARTOI1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\FABOSC_0\MDDR_Demo_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":243:32:243:35|Input ACLK is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":244:32:244:38|Input ARESETN is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1135:33:1135:39|Input AWID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1136:23:1136:31|Input AWADDR_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1137:33:1137:40|Input AWLEN_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1138:33:1138:41|Input AWSIZE_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1139:33:1139:42|Input AWBURST_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1140:33:1140:41|Input AWLOCK_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1141:33:1141:42|Input AWCACHE_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1142:33:1142:41|Input AWPROT_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1143:33:1143:42|Input AWVALID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1146:33:1146:38|Input WID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1147:33:1147:40|Input WDATA_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:33:1148:40|Input WSTRB_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1149:33:1149:40|Input WLAST_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1150:33:1150:41|Input WVALID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1156:33:1156:41|Input BREADY_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1158:33:1158:39|Input ARID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1159:23:1159:31|Input ARADDR_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Input ARLEN_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1161:33:1161:41|Input ARSIZE_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1162:33:1162:42|Input ARBURST_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1163:33:1163:41|Input ARLOCK_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1164:33:1164:42|Input ARCACHE_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1165:33:1165:41|Input ARPROT_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1166:33:1166:42|Input ARVALID_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Input RREADY_M1 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1178:33:1178:39|Input AWID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1179:23:1179:31|Input AWADDR_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1180:33:1180:40|Input AWLEN_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1181:33:1181:41|Input AWSIZE_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1182:33:1182:42|Input AWBURST_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1183:33:1183:41|Input AWLOCK_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1184:33:1184:42|Input AWCACHE_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1185:33:1185:41|Input AWPROT_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1186:33:1186:42|Input AWVALID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1189:33:1189:38|Input WID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1190:33:1190:40|Input WDATA_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:33:1191:40|Input WSTRB_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1192:33:1192:40|Input WLAST_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1193:33:1193:41|Input WVALID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1199:33:1199:41|Input BREADY_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1201:33:1201:39|Input ARID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1202:23:1202:31|Input ARADDR_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Input ARLEN_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1204:33:1204:41|Input ARSIZE_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1205:33:1205:42|Input ARBURST_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1206:33:1206:41|Input ARLOCK_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1207:33:1207:42|Input ARCACHE_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1208:33:1208:41|Input ARPROT_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1209:33:1209:42|Input ARVALID_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Input RREADY_M2 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1221:33:1221:39|Input AWID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1222:23:1222:31|Input AWADDR_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1223:33:1223:40|Input AWLEN_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1224:33:1224:41|Input AWSIZE_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1225:33:1225:42|Input AWBURST_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1226:33:1226:41|Input AWLOCK_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1227:33:1227:42|Input AWCACHE_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1228:33:1228:41|Input AWPROT_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1229:33:1229:42|Input AWVALID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1232:33:1232:38|Input WID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1233:33:1233:40|Input WDATA_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:33:1234:40|Input WSTRB_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1235:33:1235:40|Input WLAST_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1236:33:1236:41|Input WVALID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1242:33:1242:41|Input BREADY_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1244:33:1244:39|Input ARID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1245:23:1245:31|Input ARADDR_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Input ARLEN_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1247:33:1247:41|Input ARSIZE_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1248:33:1248:42|Input ARBURST_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1249:33:1249:41|Input ARLOCK_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1250:33:1250:42|Input ARCACHE_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1251:33:1251:41|Input ARPROT_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1252:33:1252:42|Input ARVALID_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Input RREADY_M3 is unused.
@N: CL159 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|Input AWREADY_S1 is unused.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Trying to extract state machine for register state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":220:0:220:5|Trying to extract state machine for register axi_fsm_read_state.
@N: CL201 :"C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v":93:0:93:5|Trying to extract state machine for register axi_fsm_current_state.
@N|Running in 64-bit mode

