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vMDDR_Demo_COREAXI_0_COREAXI
R0
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IIndBNAEOKiF:nYIehO?7H1
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vMDDR_Demo_FABOSC_0_OSC
R0
!s110 1617901424
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!s100 Mo6bO5;b5]k]ZhQ`lkdT>1
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S1
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8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/MDDR_Demo/FABOSC_0/MDDR_Demo_FABOSC_0_OSC.v
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vMDDR_Demo_HPMS
R0
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!s100 R_H@BhMIHLK57F`Q]Pd7n3
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IL6o4AVo@MfH:ScV`Jh^F?0
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w1617079386
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FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/MDDR_Demo_HPMS/MDDR_Demo_HPMS.v
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vMDDR_Demo_top
R0
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!s100 46]bTmlN5a1UH]Jn`<@5?3
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I[d?`_NOz`_d5;AU^=joli1
S1
R3
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n@m@d@d@r_@demo_top
vRESET_GEN
R0
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!s100 hgVkPLf9z2MF856UCU_Ei3
R2
IcH:nWGPgIOnM2g<?mlaA42
S1
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!s101 -O0
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n@r@e@s@e@t_@g@e@n
vtop
R0
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!s100 OC1<0APn4^`bR7UegKMkW0
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IC<M8[f^`BQ01KNGJ<bM:J1
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w1617079522
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!i122 117
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31
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!s101 -O0
!i113 1
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R9
vUART_IF
R0
R15
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!s100 :>Fo5^FZjaXbBPkK7ji[d3
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Il98QLIHo:az:^f9c>=lWG2
S1
R3
Z45 w1617882678
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FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/UART_IF.v
!i122 116
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R9
n@u@a@r@t_@i@f
vUART_IF_COREUART_0_Clock_gen
R0
Z46 !s110 1617901446
!i10b 1
!s100 cPg9hLa_lPdE82ZcORICS2
R2
INET<4DRUg1[a_;fP:oVGX2
S1
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Z47 w1617882672
8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v
FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v
!i122 112
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!s101 -O0
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n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_@clock_gen
vUART_IF_COREUART_0_COREUART
R0
R46
!i10b 1
!s100 IVh=9QSFbAfV:K?bUEk8U0
R2
IFfJkoC;EjzeH`]:nV3F3@0
S1
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R47
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FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v
!i122 113
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!s101 -O0
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R9
n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_@c@o@r@e@u@a@r@t
vUART_IF_COREUART_0_fifo_256x8
R0
R44
!i10b 1
!s100 SL0]mgFGg8li4bTT>[ccX1
R2
IE_zMcI_0FNPLgFSNn?Dem3
S1
R3
R47
Z49 8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v
Z50 FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v
!i122 111
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r1
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Z52 !s107 C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v|
Z53 !s90 -reportprogress|300|-sv|-work|presynth|C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v|
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R9
n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_fifo_256x8
vUART_IF_COREUART_0_fifo_ctrl_128
R0
R44
!i10b 1
!s100 OoB:]S5MU1Z?gJ<DTCbnX1
R2
Im7GXega]3MOl7lc>h^gR13
S1
R3
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L0 167 549
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r1
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31
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n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_fifo_ctrl_128
vUART_IF_COREUART_0_ram128x8_pa4
R0
R44
!i10b 1
!s100 >l2Oe@1mjd<n;ji]P=Edi0
R2
I:4=fTZDk]ZA]II;D1nB?>1
S1
R3
R47
R49
R50
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L0 716 371
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r1
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R8
R9
n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_ram128x8_pa4
vUART_IF_COREUART_0_Rx_async
R0
R44
!i10b 1
!s100 eJZ5n4R=^CYHjf9@1TM>@0
R2
I:Nl[h9z3e90TLUiz5nVnN2
S1
R3
R47
8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v
FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v
!i122 109
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!s101 -O0
!i113 1
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n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_@rx_async
vUART_IF_COREUART_0_Tx_async
R0
R44
!i10b 1
!s100 67_A9fo397>QizElZdc=Z0
R2
ImF:c2^mIiON=WJU8iA;CE3
S1
R3
R47
8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v
FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v
!i122 110
L0 14 883
R5
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r1
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31
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!s101 -O0
!i113 1
R8
R9
n@u@a@r@t_@i@f_@c@o@r@e@u@a@r@t_0_@tx_async
vUART_IF_FSM
R0
R46
!i10b 1
!s100 4lM9Wo[_g>f]`1DnTZc350
R2
I7`GQFFWdU<VHA?cNFhE[83
S1
R3
R11
8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/hdl/UART_IF_FSM.v
FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/hdl/UART_IF_FSM.v
!i122 114
L0 20 575
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31
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!s101 -O0
!i113 1
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R9
n@u@a@r@t_@i@f_@f@s@m
vUART_IF_TPSRAM_0_TPSRAM
R0
!s110 1617901447
!i10b 1
!s100 B7i`TBU9E^6gS^YfB9l753
R2
I5XPf0@cNO3RO24_ji]OjF1
S1
R3
R45
8C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM.v
FC:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM.v
!i122 115
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R5
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R48
!s107 C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM.v|
!s90 -reportprogress|300|-sv|-work|presynth|C:/Users/I63442/Desktop/v12.6 updates/Igloo2/DG0534_IGL2_MDDR_Demo_DF_1/Final/m2gl_dg0534_df/Libero_Project/component/work/UART_IF/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM.v|
!s101 -O0
!i113 1
R8
R9
n@u@a@r@t_@i@f_@t@p@s@r@a@m_0_@t@p@s@r@a@m
