Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Tue Mar 30 10:25:08 2021
Version: 3.0

Design: top
Family: IGLOO2
Die: M2GL010TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 211.287 100.0%
Static Power 91.307 43.2%
Dynamic Power 119.980 56.8%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 103.633 1.200 86.361
Rail VDDI 1.8 79.543 1.800 44.190
Rail VDDI 2.5 0.986 2.500 0.394
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.125 2.500 5.250
Rail CCC_NE1_PLL_VDDA 9.000 3.300 2.727

Breakdown by Clock

Power (mW) Percentage
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB (clocks) 0.283 0.3%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB (register outputs) 0.194 0.2%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB (combinational outputs) 2.377 2.6%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (clocks) 5.342 5.9%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (register outputs) 2.444 2.7%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (combinational outputs) 2.116 2.4%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 74.525 83.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.305 0.3%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 1.797 2.0%
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.308 0.3%
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.056 0.1%
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.027 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
Input to Output 0.040 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 4.434 2.1%
Type Gate 15.272 7.2%
Type I/O 85.655 40.5%
Type Memory 1.793 0.8%
Type Core Static 8.262 3.9%
Type Banks Static 0.447 0.2%
Type VPP Static 0.625 0.3%
Type Built-in Blocks 94.799 44.9%