Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Tue Mar 30 10:24:49 2021

Design top
Family IGLOO2
Die M2GL010TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 50.000 20.000 4.409 WORST
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 12.500 80.000 7.402 WORST
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 8.714 WORST
MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock 25.000 40.000 9.951 WORST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:EN 9.077 40.679 14.415 55.094 0.254 9.321 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:EN 9.077 40.679 14.415 55.094 0.254 9.321 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:EN 9.077 40.690 14.415 55.105 0.254 9.310 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:EN 9.077 40.691 14.415 55.106 0.254 9.309 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:EN 9.077 40.691 14.415 55.106 0.254 9.309 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:EN
data required time 55.094
data arrival time - 14.415
slack 40.679
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.963 3.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 4.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 4.326 5 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB10:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.281 4.607 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB10:YR cell ADLIB:RGB + 0.250 4.857 40 r
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB10_rgbr_net_1 + 0.481 5.338 r
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:Q cell ADLIB:SLE + 0.108 5.446 1 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_5:A net MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_Z[12] + 0.311 5.757 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_5:Y cell ADLIB:CFG2 + 0.164 5.921 2 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:C net MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_3_e1_5 + 0.618 6.539 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:Y cell ADLIB:CFG3 + 0.221 6.760 1 r
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:B net MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5_Z + 0.222 6.982 r
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:Y cell ADLIB:CFG4 + 0.225 7.207 4 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:A net MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/N_6 + 0.709 7.916 f
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:Y cell ADLIB:CFG4 + 0.328 8.244 44 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:C net MDDR_Demo_top_0/MDDR_Demo_0/HREADY_i_1 + 2.059 10.303 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:Y cell ADLIB:CFG3 + 0.202 10.505 4 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:A net MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/N_663 + 0.668 11.173 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:Y cell ADLIB:CFG4 + 0.134 11.307 1 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:D net MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/N_70 + 0.227 11.534 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:Y cell ADLIB:CFG4 + 0.198 11.732 1 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:D net MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/N_149 + 0.280 12.012 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:Y cell ADLIB:CFG4 + 0.281 12.293 1 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:D net MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/N_119 + 0.086 12.379 f
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:Y cell ADLIB:CFG4 + 0.095 12.474 32 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:EN net MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/N_40_i + 1.941 14.415 r
data arrival time 14.415
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 Clock Constraint 50.000 50.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 50.000 r
Clock generation + 3.963 53.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 54.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 54.326 5 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB8:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.280 54.606 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB8:YR cell ADLIB:RGB + 0.250 54.856 85 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB8_rgbr_net_1 + 0.492 55.348 r
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:EN Library setup time ADLIB:SLE - 0.254 55.094
data required time 55.094
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N 1.945 46.044 7.310 53.354 2.311 3.956 -0.300 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q1:ALn 2.703 46.949 8.032 54.981 0.353 3.051 -0.005 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:ALn 2.703 46.949 8.032 54.981 0.353 3.051 -0.005 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn 2.703 46.949 8.032 54.981 0.353 3.051 -0.005 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_q1:ALn 2.703 46.949 8.032 54.981 0.353 3.051 -0.005 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N
data required time 53.354
data arrival time - 7.310
slack 46.044
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.963 3.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 4.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 4.325 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.278 4.603 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 4.853 16 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 + 0.512 5.365 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:Q cell ADLIB:SLE + 0.087 5.452 1 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:A net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N + 0.310 5.762 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:Y cell ADLIB:CFG2 + 0.158 5.920 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:B net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N + 0.965 6.885 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPB cell ADLIB:IP_INTERFACE + 0.209 7.094 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/FPGA_MDDR_ARESET_N_net + 0.216 7.310 r
data arrival time 7.310
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 Clock Constraint 50.000 50.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 50.000 r
Clock generation + 3.963 53.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 54.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 54.325 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.284 54.609 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.250 54.859 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.387 55.246 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 55.455 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.210 55.665 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N Library recovery time ADLIB:MSS_010_IP - 2.311 53.354
data required time 53.354
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:D 0.778 9.371 5.713 15.084 0.254 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_q1:D 0.785 9.385 5.711 15.096 0.254 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_q1:D 0.786 9.389 5.707 15.096 0.254 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_q1:D 0.779 9.392 5.692 15.084 0.254 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_q1:D 0.610 9.514 5.570 15.084 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:D
data required time 15.084
data arrival time - 5.713
slack 9.371
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 2.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 2.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 3.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 3.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.300 4.199 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.250 4.449 18 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.486 4.935 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:Q cell ADLIB:SLE + 0.087 5.022 1 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:D net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_Z + 0.691 5.713 r
data arrival time 5.713
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 Clock Constraint 10.000 10.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.963 13.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 14.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 14.325 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.278 14.603 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 14.853 16 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 + 0.485 15.338 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:D Library setup time ADLIB:SLE - 0.254 15.084
data required time 15.084
Operating Conditions WORST

SET MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock to MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0

No Path

SET MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 to MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BREADY 1.030 4.409 6.209 10.618 7.547 WORST
Path 2 MDDR_Demo_top_0/AXI_IF_0/AWVALID:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWVALID_HWRITE0 1.054 4.412 6.207 10.619 7.546 WORST
Path 3 MDDR_Demo_top_0/AXI_IF_0/WVALID:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WVALID 1.141 4.442 6.308 10.750 7.415 WORST
Path 4 MDDR_Demo_top_0/AXI_IF_0/ARVALID:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARVALID_HWRITE1 0.973 4.574 6.141 10.715 7.450 WORST
Path 5 MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:CLK MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[44] 1.054 4.607 6.221 10.828 7.337 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BREADY
data required time 10.618
data arrival time - 6.209
slack 4.409
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 0.000 r
Clock generation + 3.761 3.761
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.201 3.962 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.165 4.127 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.291 4.418 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.250 4.668 157 r
MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.511 5.179 r
MDDR_Demo_top_0/AXI_IF_0/BREADY:Q cell ADLIB:SLE + 0.087 5.266 6 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:C net MDDR_Demo_top_0_BREADY + 0.564 5.830 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPC cell ADLIB:IP_INTERFACE + 0.202 6.032 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BREADY net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/F_BREADY_net + 0.177 6.209 r
data arrival time 6.209
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 Clock Constraint 12.500 12.500
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 12.500 r
Clock generation + 3.963 16.463
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 16.660 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 16.825 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.284 17.109 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.250 17.359 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.387 17.746 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 17.955 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.210 18.165 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BREADY Library setup time ADLIB:MSS_010_IP - 7.547 10.618
data required time 10.618
Operating Conditions WORST

Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 UART_IF_0/UART_IF_FSM_0/rx_en:CLK UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D 4.158 8.072 9.307 17.379 0.254 4.428 WORST
Path 2 UART_IF_0/COREUART_0/genblk1.RXRDY:CLK UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D 4.152 8.085 9.294 17.379 0.254 4.415 WORST
Path 3 UART_IF_0/UART_IF_FSM_0/rx_en:CLK UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:D 4.150 8.108 9.299 17.407 0.254 4.392 WORST
Path 4 UART_IF_0/COREUART_0/genblk1.RXRDY:CLK UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:D 4.144 8.121 9.286 17.407 0.254 4.379 WORST
Path 5 UART_IF_0/UART_IF_FSM_0/rx_en:CLK UART_IF_0/UART_IF_FSM_0/AXI_data_in[62]:D 4.109 8.130 9.258 17.388 0.254 4.370 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: UART_IF_0/UART_IF_FSM_0/rx_en:CLK
To: UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D
data required time 17.379
data arrival time - 9.307
slack 8.072
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 0.000 r
Clock generation + 3.761 3.761
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.201 3.962 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.165 4.127 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB6:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.289 4.416 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB6:YR cell ADLIB:RGB + 0.250 4.666 55 r
UART_IF_0/UART_IF_FSM_0/rx_en:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB6_rgbr_net_1 + 0.483 5.149 r
UART_IF_0/UART_IF_FSM_0/rx_en:Q cell ADLIB:SLE + 0.108 5.257 3 f
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o2[4]:B net UART_IF_0/UART_IF_FSM_0/rx_en_Z + 0.315 5.572 f
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o2[4]:Y cell ADLIB:CFG2 + 0.147 5.719 4 r
UART_IF_0/UART_IF_FSM_0/cnt_data_0_sqmuxa_i_o4_i_a3:A net UART_IF_0/UART_IF_FSM_0/N_393 + 0.707 6.426 r
UART_IF_0/UART_IF_FSM_0/cnt_data_0_sqmuxa_i_o4_i_a3:Y cell ADLIB:CFG2 + 0.074 6.500 66 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:B net UART_IF_0/UART_IF_FSM_0/N_948 + 0.904 7.404 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:UB cell ADLIB:ARI1_CC + 0.209 7.613 1 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_0:UB[3] net NET_CC_CONFIG751 + 0.000 7.613 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_0:CO cell ADLIB:CC_CONFIG + 0.569 8.182 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_1:CI net CI_TO_CO745 + 0.000 8.182 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_1:CO cell ADLIB:CC_CONFIG + 0.185 8.367 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_2:CI net CI_TO_CO746 + 0.000 8.367 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_2:CO cell ADLIB:CC_CONFIG + 0.185 8.552 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_3:CI net CI_TO_CO747 + 0.000 8.552 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_3:CO cell ADLIB:CC_CONFIG + 0.185 8.737 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_4:CI net CI_TO_CO748 + 0.000 8.737 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_4:CO cell ADLIB:CC_CONFIG + 0.185 8.922 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_5:CI net CI_TO_CO749 + 0.000 8.922 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0_CC_5:CC[2] cell ADLIB:CC_CONFIG + 0.252 9.174 1 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:CC net NET_CC_CONFIG929 + 0.000 9.174 f
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:S cell ADLIB:ARI1_CC + 0.056 9.230 1 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D net UART_IF_0/UART_IF_FSM_0/AXI_data_in_14[63] + 0.077 9.307 r
data arrival time 9.307
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 Clock Constraint 12.500 12.500
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 12.500 r
Clock generation + 3.761 16.261
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.201 16.462 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.165 16.627 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.291 16.918 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.250 17.168 157 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.465 17.633 r
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D Library setup time ADLIB:SLE - 0.254 17.379
data required time 17.379
Operating Conditions WORST

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:D 1.894 1.894 0.131 -1.422 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX
To: UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:D
data required time N/C
data arrival time - 1.894
slack N/C
Data arrival time calculation
RX 0.000 0.000 f
RX_ibuf/U0/U_IOPAD:PAD net RX + 0.000 0.000 f
RX_ibuf/U0/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.919 0.919 1 f
RX_ibuf/U0/U_IOINFF:A net RX_ibuf/U0/YIN1 + 0.091 1.010 f
RX_ibuf/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.103 1.113 1 f
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:D net RX_c + 0.781 1.894 f
data arrival time 1.894
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 N/C N/C
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 N/C r
Clock generation + 2.520 N/C
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.134 N/C r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.110 N/C 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB7:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.191 N/C f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB7:YR cell ADLIB:RGB + 0.168 N/C 14 r
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB7_rgbr_net_1 + 0.324 N/C r
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:D Library setup time ADLIB:SLE - 0.131 N/C
Operating Conditions BEST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:CLK TX 4.675 9.843 9.843 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:CLK
To: TX
data required time N/C
data arrival time - 9.843
slack N/C
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 0.000 r
Clock generation + 3.761 3.761
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.201 3.962 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.165 4.127 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB4:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.289 4.416 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB4:YR cell ADLIB:RGB + 0.250 4.666 107 r
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB4_rgbr_net_1 + 0.502 5.168 r
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:Q cell ADLIB:SLE + 0.108 5.276 1 f
TX_obuf/U0/U_IOOUTFF:A net TX_c + 0.935 6.211 f
TX_obuf/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 6.541 1 f
TX_obuf/U0/U_IOPAD:D net TX_obuf/U0/DOUT + 0.636 7.177 f
TX_obuf/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 9.843 0 f
TX net TX + 0.000 9.843 f
data arrival time 9.843
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 N/C N/C
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 N/C r
Clock generation + 3.761 N/C
TX N/C f
Operating Conditions WORST

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 to MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:EN 4.254 7.402 9.925 17.327 0.308 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:EN 4.254 7.402 9.925 17.327 0.308 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:EN 4.254 7.411 9.925 17.336 0.308 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:EN 4.254 7.413 9.925 17.338 0.308 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:EN 4.254 7.413 9.925 17.338 0.308 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
To: UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:EN
data required time 17.327
data arrival time - 9.925
slack 7.402
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.963 3.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 4.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 4.325 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.284 4.609 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.250 4.859 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.387 5.246 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 5.455 1 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 5.671 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RVALID cell ADLIB:MSS_010_IP + 0.993 6.664 6 f
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:D net MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 + 1.067 7.731 f
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:Y cell ADLIB:CFG4 + 0.099 7.830 7 r
UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0:A net UART_IF_0/UART_IF_FSM_0/N_392 + 0.716 8.546 r
UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0:Y cell ADLIB:CFG2 + 0.100 8.646 56 f
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:EN net UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0_Z + 1.279 9.925 f
data arrival time 9.925
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 Clock Constraint 12.500 12.500
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 Clock source + 0.000 12.500 r
Clock generation + 3.761 16.261
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_net + 0.201 16.462 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST:YNn cell ADLIB:GB + 0.165 16.627 9 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB5:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_YNn + 0.291 16.918 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB5:YR cell ADLIB:RGB + 0.250 17.168 53 r
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1_RGB5_rgbr_net_1 + 0.467 17.635 r
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:EN Library setup time ADLIB:SLE - 0.308 17.327
data required time 17.327
Operating Conditions WORST

Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN 2.472 17.188 7.416 24.604 0.308 2.812 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN 2.371 17.278 7.326 24.604 0.308 2.722 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN 2.300 17.360 7.244 24.604 0.308 2.640 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN 2.288 17.360 7.244 24.604 0.308 2.640 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN 2.285 17.375 7.229 24.604 0.308 2.625 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN
data required time 24.604
data arrival time - 7.416
slack 17.188
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 2.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 2.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 3.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 3.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.300 4.199 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.250 4.449 18 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.495 4.944 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:Q cell ADLIB:SLE + 0.108 5.052 2 f
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:A net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_Z[10] + 0.674 5.726 f
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:Y cell ADLIB:CFG4 + 0.287 6.013 1 f
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:B net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7_Z + 0.225 6.238 f
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:Y cell ADLIB:CFG4 + 0.209 6.447 1 f
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_Z + 0.969 7.416 f
data arrival time 7.416
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 22.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 22.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 23.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 23.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.300 24.199 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.250 24.449 18 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.463 24.912 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN Library setup time ADLIB:SLE - 0.308 24.604
data required time 24.604
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:ALn 1.060 18.534 6.020 24.554 0.353 1.466 0.053 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:ALn 1.018 18.597 5.979 24.576 0.353 1.403 0.032 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:ALn 1.018 18.597 5.979 24.576 0.353 1.403 0.032 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:ALn 1.018 18.597 5.979 24.576 0.353 1.403 0.032 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:ALn 1.018 18.597 5.979 24.576 0.353 1.403 0.032 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:ALn
data required time 24.554
data arrival time - 6.020
slack 18.534
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 2.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 2.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 3.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 3.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.303 4.202 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.250 4.452 13 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.508 4.960 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 5.047 1 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:ALn net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc_Z + 0.973 6.020 r
data arrival time 6.020
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 22.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 22.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 23.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 23.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.303 24.202 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.250 24.452 13 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.455 24.907 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:ALn Library recovery time ADLIB:SLE - 0.353 24.554
data required time 24.554
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 to MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:D 0.595 8.714 5.944 14.658 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:D
data required time 14.658
data arrival time - 5.944
slack 8.714
Data arrival time calculation
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.963 3.963
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_net + 0.197 4.160 r
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 4.325 7 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_YNn + 0.277 4.602 f
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.250 4.852 12 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:CLK net MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 + 0.497 5.349 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:Q cell ADLIB:SLE + 0.087 5.436 1 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:D net MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_Z + 0.508 5.944 r
data arrival time 5.944
Data required time calculation
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 10.000 10.000
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 10.000 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.027 12.027 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 12.179 1 r
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 1.500 13.679 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn cell ADLIB:GB + 0.220 13.899 2 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn + 0.300 14.199 f
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.250 14.449 18 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:CLK net MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.463 14.912 r
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:D Library setup time ADLIB:SLE - 0.254 14.658
data required time 14.658
Operating Conditions WORST

Clock Domain MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:EN 2.141 9.951 4.896 14.847 0.308 5.098 WORST
Path 2 MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:EN 2.141 9.961 4.896 14.857 0.308 5.078 WORST
Path 3 MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:EN 2.141 9.961 4.896 14.857 0.308 5.078 WORST
Path 4 MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D 2.110 10.034 4.865 14.899 0.254 4.932 WORST
Path 5 MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 2.028 10.081 4.783 14.864 0.308 4.838 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK
To: MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:EN
data required time 14.847
data arrival time - 4.896
slack 9.951
Data arrival time calculation
MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock 0.000 0.000
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E:An net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB + 1.543 1.543 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E:YNn cell ADLIB:GB + 0.223 1.766 5 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2:An net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_YNn + 0.287 2.053 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.182 2.235 33 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2_rgbr_net_1 + 0.520 2.755 r
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:Q cell ADLIB:SLE + 0.110 2.865 3 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:B net MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel_Z + 0.330 3.195 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:Y cell ADLIB:CFG3 + 0.084 3.279 3 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:D net MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa_Z + 0.602 3.881 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:Y cell ADLIB:CFG4 + 0.084 3.965 17 f
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:EN net MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5_Z + 0.931 4.896 f
data arrival time 4.896
Data required time calculation
MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock Clock Constraint 12.500 12.500
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB Clock source + 0.000 12.500 r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E:An net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB + 1.392 13.892 f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E:YNn cell ADLIB:GB + 0.220 14.112 5 f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2:An net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_YNn + 0.306 14.418 f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 14.668 33 r
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:CLK net MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1_RGB2_rgbr_net_1 + 0.487 15.155 r
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:EN Library setup time ADLIB:SLE - 0.308 14.847
data required time 14.847
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 to MDDR_Demo_HPMS|FIC_2_APB_M_PCLK_inferred_clock

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets