pin,slack
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_16:B,44742
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_16:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_16:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_16:S,44688
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[22]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[22]:B,44624
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[22]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[22]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[22]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[29]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[29]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[29]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[29]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_63:A,47386
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_63:B,47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_63:IPA,47386
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_63:IPB,47360
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:CLK,21421
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:Q,21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_1:A,45971
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_1:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_1:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_8:B,44614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_8:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_8:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_8:S,44816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_1:A,41974
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_1:B,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_1:C,44642
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_1:D,44482
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_1:Y,40690
UART_IF_0/UART_IF_FSM_0/fsm[22]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[22]:CLK,8243
UART_IF_0/UART_IF_FSM_0/fsm[22]:D,9964
UART_IF_0/UART_IF_FSM_0/fsm[22]:Q,8243
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[23]:CLK,45691
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[23]:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[23]:Q,45691
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[28]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[28]:CLK,9720
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[28]:D,8453
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[28]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[28]:Q,9720
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i_1:A,9327
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i_1:B,9304
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i_1:C,9119
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i_1:D,9119
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i_1:Y,9119
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:ALn,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:CLK,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core:Q,4897
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_o2:A,43759
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_o2:B,43638
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_o2:C,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_o2:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_o2:Y,39042
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[8]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[8]:CLK,9400
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[8]:D,8773
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[8]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[8]:Q,9400
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILIT26[5]:B,7866
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILIT26[5]:C,10168
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILIT26[5]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILIT26[5]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILIT26[5]:S,7914
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_12:B,45624
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_12:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_12:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_12:S,45736
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_283:A,24670
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_283:B,25470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_283:IPA,24670
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_283:IPB,25470
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[46]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[46]:CLK,10008
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[46]:D,8165
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[46]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[46]:Q,10008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[26]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[26]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[26]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[26]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[1]:A,45660
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[1]:B,43777
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[1]:C,40126
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[1]:Y,40126
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_58:A,42253
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_58:B,42149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_58:C,42131
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_58:Y,42131
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_s[13]:B,17793
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_s[13]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_s[13]:S,17610
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_2:A,45570
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_2:B,45458
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_2:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_2:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_2:S,45891
MDDR_Demo_top_0/AXI_IF_0/WDATA[38]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[38]:CLK,-1467
MDDR_Demo_top_0/AXI_IF_0/WDATA[38]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[38]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[38]:Q,-1467
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_0:A,43836
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_0:B,43716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_0:C,41769
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_0:D,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_0:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[6]:CLK,44550
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[6]:D,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[6]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[6]:Q,44550
UART_IF_0/UART_IF_FSM_0/un1_fsm_46_i_a4_0_a2_2:A,9501
UART_IF_0/UART_IF_FSM_0/un1_fsm_46_i_a4_0_a2_2:B,9446
UART_IF_0/UART_IF_FSM_0/un1_fsm_46_i_a4_0_a2_2:C,9412
UART_IF_0/UART_IF_FSM_0/un1_fsm_46_i_a4_0_a2_2:D,9312
UART_IF_0/UART_IF_FSM_0/un1_fsm_46_i_a4_0_a2_2:Y,9312
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_0:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_0:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_2:B,44518
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_2:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_2:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_2:S,45040
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_7:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[5]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[5]:CLK,22000
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[5]:D,25221
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[5]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[5]:Q,22000
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_0:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_0:IPCLKn,
UART_IF_0/UART_IF_FSM_0/WRITE_RNO:A,10431
UART_IF_0/UART_IF_FSM_0/WRITE_RNO:B,10386
UART_IF_0/UART_IF_FSM_0/WRITE_RNO:C,10349
UART_IF_0/UART_IF_FSM_0/WRITE_RNO:Y,10349
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[8]:CLK,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[8]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[8]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[8]:Q,46999
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_52:A,47397
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_52:B,47387
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_52:IPA,47397
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_52:IPB,47387
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_15:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_15:C,11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_15:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_15:IPC,11130
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:B,9124
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:C,9081
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:D,7598
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE8D45[2]:S,92
UART_IF_0/UART_IF_FSM_0/AXI_data_in[61]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[61]:CLK,9987
UART_IF_0/UART_IF_FSM_0/AXI_data_in[61]:D,7155
UART_IF_0/UART_IF_FSM_0/AXI_data_in[61]:Q,9987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[14]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[14]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[14]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[14]:Y,46645
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:B,8853
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:C,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:D,9971
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6N8U42[60]:S,7941
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[13]:A,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[13]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[13]:Y,40116
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNITL4U[0]:B,10179
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNITL4U[0]:C,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNITL4U[0]:FCI,9673
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNITL4U[0]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNITL4U[0]:S,9710
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[6]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[6]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[6]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[6]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[6]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[12]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[12]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[12]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[12]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[12]:Y,43758
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:B,8181
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:C,9560
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:D,9293
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEK5JJ[18]:S,8613
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[19]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[19]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[19]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[19]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[3]:CLK,42003
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[3]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[3]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[3]:Q,42003
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_131:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45_FCINST1:CO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45_FCINST1:FCI,41987
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_1_0_a2_0_a3:A,42675
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_1_0_a2_0_a3:B,42619
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_1_0_a2_0_a3:C,42506
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_1_0_a2_0_a3:D,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_1_0_a2_0_a3:Y,39640
UART_IF_0/UART_IF_FSM_0/AXI_data_in[23]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[23]:CLK,9373
UART_IF_0/UART_IF_FSM_0/AXI_data_in[23]:D,7763
UART_IF_0/UART_IF_FSM_0/AXI_data_in[23]:Q,9373
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_0_0:A,10402
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_0_0:B,9170
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_0_0:C,2922
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_0_0:D,2686
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_0_0:Y,2686
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[7]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[7]:CLK,24477
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[7]:D,25223
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[7]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[7]:Q,24477
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:CLK,21419
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:D,8578
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:Q,21419
UART_IF_0/UART_IF_FSM_0/RAM_WD[54]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[54]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[54]:D,3892
UART_IF_0/UART_IF_FSM_0/RAM_WD[54]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[54]:Q,11208
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[1]:CLK,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[1]:D,8096
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[1]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[1]:Q,7362
UART_IF_0/UART_IF_FSM_0/AXI_data_out[59]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[59]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[59]:D,2751
UART_IF_0/UART_IF_FSM_0/AXI_data_out[59]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[59]:Q,9436
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_188:IPA,
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNISSN22[2]:B,9689
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNISSN22[2]:C,10119
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNISSN22[2]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNISSN22[2]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNISSN22[2]:S,9778
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[24]:A,-118
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[24]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[24]:Y,-118
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_69:A,47398
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_69:B,21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_69:IPA,47398
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_69:IPB,21421
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[3]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[3]:CLK,9244
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[3]:D,1666
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[3]:Q,9244
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[28]:A,46524
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[28]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[28]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[28]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[8]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[8]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[8]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[8]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[8]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[9]:CLK,47535
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[9]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[9]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[9]:Q,47535
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[25]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[25]:B,45528
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[25]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[25]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[25]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:A,43152
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:B,42115
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:C,43057
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:D,42796
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_93:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[20]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[20]:B,44656
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[20]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[20]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[20]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:D,2020
UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[47]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_42:A,43530
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_42:B,43267
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_42:IPA,43530
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_42:IPB,43267
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_30:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_30:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI9R7H[0]:A,43630
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI9R7H[0]:B,45805
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI9R7H[0]:Y,43630
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_2:C,10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_2:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_2:IPC,10888
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:A,38196
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:B,40794
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:C,40084
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:D,37644
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIPS2A1:Y,37644
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[41]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[41]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[41]:C,2576
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[41]:Y,2576
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[24]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[24]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[24]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[24]:Q,45970
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIIR5G1[1]:B,9673
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIIR5G1[1]:C,10103
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIIR5G1[1]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIIR5G1[1]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIIR5G1[1]:S,9786
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_1:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[4]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[4]:CLK,47794
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[4]:D,45991
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[4]:Q,47794
UART_IF_0/UART_IF_FSM_0/AXI_data_out[34]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[34]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[34]:D,3015
UART_IF_0/UART_IF_FSM_0/AXI_data_out[34]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[34]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[6]:CLK,41970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[6]:D,43349
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[6]:Q,41970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[28]:CLK,43153
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[28]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[28]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[28]:Q,43153
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2_RNIVOAL:A,1426
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2_RNIVOAL:B,9792
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2_RNIVOAL:Y,1426
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[35]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[35]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[35]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[35]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[35]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[0]:CLK,9272
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[0]:D,8870
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[0]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[0]:Q,9272
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[3]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[3]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[3]:Y,9466
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:B,7544
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:C,9698
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:D,9437
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_27:S,7699
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[24]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[24]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[24]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[24]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:A,43232
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:B,42195
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:C,43137
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:D,42876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_81:FCO,41987
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[2]:CLK,7547
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D,7436
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[2]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[2]:Q,7547
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_2_0_a6:A,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_2_0_a6:B,44869
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_2_0_a6:C,42925
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_2_0_a6:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_23:B,45800
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_23:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_23:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_23:S,45560
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_27:B,45864
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_27:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_27:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_27:S,45496
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[20]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[20]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[20]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[20]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[20]:Y,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[25]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[25]:D,47396
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[25]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[25]:Q,46105
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_9:B,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_9:C,10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_9:IPB,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_9:IPC,10999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:A,43248
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:B,42211
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:C,43153
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:D,42892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_87:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_127:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_127:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[6]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[6]:CLK,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[6]:EN,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[6]:Q,48785
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_1:A,44599
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_1:B,44515
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_1:C,44450
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_1:D,44178
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_1:Y,44178
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_2:A,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_2:B,41008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_2:C,45426
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_2:D,45250
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_2:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[26]:A,47367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[26]:B,47499
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[26]:Y,47367
UART_IF_0/UART_IF_FSM_0/AXI_data_out[32]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[32]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[32]:D,2888
UART_IF_0/UART_IF_FSM_0/AXI_data_out[32]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[32]:Q,9329
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[13]:A,47
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[13]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[13]:Y,47
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:CLK,21480
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:Q,21480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[6]:A,45666
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[6]:B,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[6]:C,45738
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[6]:Y,41252
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_0:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_0:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_16:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_16:IPC,
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_1_i_0_a2:A,9478
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_1_i_0_a2:B,7468
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_1_i_0_a2:C,9363
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_1_i_0_a2:D,9209
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_1_i_0_a2:Y,7468
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2[3]:A,8590
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2[3]:B,8506
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2[3]:C,8461
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2[3]:D,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2[3]:Y,7362
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[55]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[55]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[55]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[55]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[55]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[28]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[28]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[28]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[28]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[28]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[11]:A,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[11]:B,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[11]:C,45905
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[11]:Y,45858
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_0:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_0:IPC,
MDDR_Demo_top_0/AXI_IF_0/WDATA[11]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[11]:CLK,-1511
MDDR_Demo_top_0/AXI_IF_0/WDATA[11]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[11]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[11]:Q,-1511
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIO6JT3[5]:B,10259
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIO6JT3[5]:C,9686
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIO6JT3[5]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIO6JT3[5]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIO6JT3[5]:S,9671
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_0:A,10444
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_0:B,10357
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_0:C,2670
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_0:D,739
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_0:Y,739
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[46]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[46]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[46]:C,2728
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[46]:Y,2728
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[19]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[19]:D,47492
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[19]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[19]:Q,46105
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_9[0]:A,6585
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_9[0]:B,6501
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_9[0]:C,6457
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_9[0]:D,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_9[0]:Y,6389
UART_IF_0/UART_IF_FSM_0/AXI_address[17]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[17]:CLK,9193
UART_IF_0/UART_IF_FSM_0/AXI_address[17]:D,-13
UART_IF_0/UART_IF_FSM_0/AXI_address[17]:Q,9193
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_8:C,10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_8:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_8:IPC,10940
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_162:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_162:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_6_0:A,43493
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_6_0:B,43412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_6_0:C,42444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_6_0:D,41207
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_6_0:Y,41207
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_mask_0_sqmuxa_0_a6:A,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_mask_0_sqmuxa_0_a6:B,45293
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_mask_0_sqmuxa_0_a6:Y,40819
UART_IF_0/UART_IF_FSM_0/fsm_RNIRG291[8]:A,10202
UART_IF_0/UART_IF_FSM_0/fsm_RNIRG291[8]:B,10103
UART_IF_0/UART_IF_FSM_0/fsm_RNIRG291[8]:C,3662
UART_IF_0/UART_IF_FSM_0/fsm_RNIRG291[8]:D,9994
UART_IF_0/UART_IF_FSM_0/fsm_RNIRG291[8]:Y,3662
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_265:A,-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_265:C,24893
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPA,-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPC,24893
UART_IF_0/UART_IF_FSM_0/RAM_WD[43]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[43]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[43]:D,3904
UART_IF_0/UART_IF_FSM_0/RAM_WD[43]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[43]:Q,11208
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:B,8309
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:C,9688
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:D,9421
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8I2VS[26]:S,8485
UART_IF_0/UART_IF_FSM_0/AXI_data_out[27]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[27]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[27]:D,2809
UART_IF_0/UART_IF_FSM_0/AXI_data_out[27]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[27]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_5:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_5:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_clk_base:CLK,47739
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_clk_base:Q,47739
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[21]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[21]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[21]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[21]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[21]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[7]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[7]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[7]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[7]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[0]:A,22303
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[0]:B,22233
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[0]:C,21956
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[0]:D,20826
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[0]:Y,20826
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[25]:A,47119
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[25]:B,47062
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[25]:C,43530
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[25]:D,46643
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[25]:Y,43530
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[25]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[25]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[25]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[25]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNII2UF2[11]:A,47714
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNII2UF2[11]:B,47603
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNII2UF2[11]:C,47364
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNII2UF2[11]:D,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNII2UF2[11]:Y,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[6]:CLK,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[6]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[6]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[6]:Q,47025
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1:A,9382
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1:B,9399
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1:C,9299
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1:Y,9299
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[8]:CLK,42732
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[8]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[8]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[8]:Q,42732
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[17]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[17]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[17]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[17]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[12]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[12]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[12]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[12]:Q,45970
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0_3[2]:A,7522
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0_3[2]:B,7467
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0_3[2]:C,7400
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0_3[2]:D,7322
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0_3[2]:Y,7322
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[25]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[25]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[25]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[25]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[25]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_80:A,21447
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_80:IPA,21447
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_80:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[15]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[15]:CLK,25526
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[15]:D,25264
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[15]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[15]:Q,25526
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[2]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[2]:D,47759
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[2]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[2]:Q,46105
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[43]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[43]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[43]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[43]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[43]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[22]:CLK,43105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[22]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[22]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[22]:Q,43105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[24]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[24]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[24]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[24]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc:Q,18769
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_16:C,11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_16:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_16:IPC,11326
UART_IF_0/UART_IF_FSM_0/RAM_WD[25]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[25]:CLK,11184
UART_IF_0/UART_IF_FSM_0/RAM_WD[25]:D,3951
UART_IF_0/UART_IF_FSM_0/RAM_WD[25]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[25]:Q,11184
UART_IF_0/UART_IF_FSM_0/AXI_address[13]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[13]:CLK,9129
UART_IF_0/UART_IF_FSM_0/AXI_address[13]:D,47
UART_IF_0/UART_IF_FSM_0/AXI_address[13]:Q,9129
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[11]:CLK,44630
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[11]:D,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[11]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[11]:Q,44630
UART_IF_0/COREUART_0/CUARTOO1/CUARTl0:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/CUARTl0:CLK,8152
UART_IF_0/COREUART_0/CUARTOO1/CUARTl0:D,10308
UART_IF_0/COREUART_0/CUARTOO1/CUARTl0:EN,11167
UART_IF_0/COREUART_0/CUARTOO1/CUARTl0:Q,8152
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_5:A,37721
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_5:B,37644
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_5:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/SYSRESET_POR/INST_SYSRESET_FF_IP:DEVRST_N,
MDDR_Demo_top_0/MDDR_Demo_0/SYSRESET_POR/INST_SYSRESET_FF_IP:FF_TO_START,
MDDR_Demo_top_0/MDDR_Demo_0/SYSRESET_POR/INST_SYSRESET_FF_IP:POWER_ON_RESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/SYSRESET_POR/INST_SYSRESET_FF_IP:UTDO,
MDDR_Demo_top_0/AXI_IF_0/ARADDR[3]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[3]:CLK,-1619
MDDR_Demo_top_0/AXI_IF_0/ARADDR[3]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[3]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[3]:Q,-1619
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[31]:A,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[31]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[31]:Y,-228
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[27]:A,46770
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[27]:B,46713
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[27]:C,43181
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[27]:D,46294
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[27]:Y,43181
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:B,8261
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:C,9640
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:D,9373
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQLIEP[23]:S,8533
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_279:A,24668
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_279:B,25317
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_279:IPA,24668
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_279:IPB,25317
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_16:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_16:IPB,
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[23]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[23]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[23]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[23]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA[7]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[7]:CLK,-1484
MDDR_Demo_top_0/AXI_IF_0/WDATA[7]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[7]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[7]:Q,-1484
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[11]:CLK,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[11]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[11]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[11]:Q,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[19]:CLK,47488
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[19]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[19]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[19]:Q,47488
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[23]:A,8261
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[23]:B,10400
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[23]:C,9417
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[23]:Y,8261
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_q1:D,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/RAM_WD[37]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[37]:CLK,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[37]:D,3948
UART_IF_0/UART_IF_FSM_0/RAM_WD[37]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[37]:Q,11194
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_15:B,44726
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_15:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_15:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_15:S,44723
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:CLK,9994
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:D,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in[63]:Q,9994
MDDR_Demo_top_0/MDDR_Demo_0/SYSRESET_POR/IP_INTERFACE_0:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[3]:CLK,47517
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[3]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[3]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[3]:Q,47517
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_2:C,10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_2:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_2:IPC,10888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[2]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[2]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[2]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[2]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[2]:Y,39328
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[0]:A,7360
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[0]:B,9410
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[0]:Y,7360
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[19]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[19]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[19]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[19]:Q,48017
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[9]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[9]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[9]:C,2907
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[9]:Y,2907
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:A,-1403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:B,-1465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:C,-1476
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPA,-1403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPB,-1465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPC,-1476
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_94:A,42237
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_94:B,42133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_94:C,42115
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_94:Y,42115
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[26]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[26]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[26]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[26]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[26]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_0:A,43087
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_0:B,43010
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_0:C,42538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_0:D,42666
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_o2_0:Y,42538
MDDR_Demo_top_0/AXI_IF_0/AWADDR[23]:CLK,-1438
MDDR_Demo_top_0/AXI_IF_0/AWADDR[23]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[23]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[23]:Q,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_257:A,-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_257:B,-1448
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_257:IPA,-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_257:IPB,-1448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[16]:CLK,43057
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[16]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[16]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[16]:Q,43057
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[12]:B,17793
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[12]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[12]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[12]:S,17626
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[12]:A,19190
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[12]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[12]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[12]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[12]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[27]:A,46540
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[27]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[27]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[27]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[0]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[0]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[0]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[0]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_72:A,21437
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_72:IPA,21437
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RAS_N_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RAS_N_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RAS_N_PAD/U_IOPAD:PAD,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_18:C,11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_18:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_18:IPC,11353
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_67:A,47333
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_67:B,21481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_67:IPA,47333
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_67:IPB,21481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_130:IPB,
MDDR_Demo_top_0/AXI_IF_0/AWADDR[13]:CLK,-1491
MDDR_Demo_top_0/AXI_IF_0/AWADDR[13]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[13]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[13]:Q,-1491
UART_IF_0/UART_IF_FSM_0/RAM_WD[40]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[40]:CLK,11217
UART_IF_0/UART_IF_FSM_0/RAM_WD[40]:D,3980
UART_IF_0/UART_IF_FSM_0/RAM_WD[40]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[40]:Q,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[21]:CLK,42147
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[21]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[21]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[21]:Q,42147
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[19]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[19]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[19]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[19]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[19]:Y,44829
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[18]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[18]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[18]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[18]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_19:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_19:C,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_19:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_19:IPC,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_7:B,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_7:IPB,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_7:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[9]:CLK,42173
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[9]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[9]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[9]:Q,42173
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[15]:CLK,47491
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[15]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[15]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[15]:Q,47491
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[30]:CLK,42466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[30]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[30]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[30]:Q,42466
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_32:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_32:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[23]:CLK,47527
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[23]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[23]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[23]:Q,47527
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[2]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[2]:B,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[2]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[2]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_6:A,39301
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_6:B,39253
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_6:C,39179
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_6:D,39084
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_6:Y,39084
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_238:A,-1550
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_238:B,-1647
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_238:IPA,-1550
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_238:IPB,-1647
UART_IF_0/UART_IF_FSM_0/AXI_data_in[28]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[28]:CLK,9453
UART_IF_0/UART_IF_FSM_0/AXI_data_in[28]:D,7683
UART_IF_0/UART_IF_FSM_0/AXI_data_in[28]:Q,9453
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[26]:CLK,42876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[26]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[26]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[26]:Q,42876
MDDR_Demo_top_0/AXI_IF_0/WDATA[55]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[55]:CLK,-1561
MDDR_Demo_top_0/AXI_IF_0/WDATA[55]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[55]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[55]:Q,-1561
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:CLK,45389
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:D,45766
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:Q,45389
MDDR_Demo_top_0/AXI_IF_0/AWADDR[1]:CLK,-1461
MDDR_Demo_top_0/AXI_IF_0/AWADDR[1]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[1]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[1]:Q,-1461
MDDR_Demo_top_0/AXI_IF_0/ARADDR[22]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[22]:CLK,-1539
MDDR_Demo_top_0/AXI_IF_0/ARADDR[22]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[22]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[22]:Q,-1539
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_30:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_30:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[6]:A,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[6]:B,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[6]:C,46722
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[6]:D,42427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[6]:Y,38431
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0_RGB1:YL,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy:CLK,43626
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy:D,47799
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy:EN,48785
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy:Q,43626
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[14]:A,40500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[14]:B,47913
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[14]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[14]:Y,40500
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[5]:A,10510
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[5]:B,9369
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[5]:C,8295
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[5]:Y,8295
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL_RNIK4EE:A,8379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL_RNIK4EE:B,18125
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL_RNIK4EE:Y,8379
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[5]:CLK,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[5]:D,40244
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[5]:Q,39640
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:CLK,46246
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:Q,46246
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:B,7256
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:C,9416
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:D,9149
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_9:S,7987
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_254:A,-1470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_254:B,-1573
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_254:IPA,-1470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_254:IPB,-1573
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CKE_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CKE_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CKE_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[24]:A,47386
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[24]:B,47518
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[24]:Y,47386
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[24]:CLK,42860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[24]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[24]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[24]:Q,42860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO_0[15]:A,43578
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO_0[15]:Y,43578
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6_RNI79SD:A,47455
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6_RNI79SD:B,47419
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6_RNI79SD:C,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6_RNI79SD:D,47209
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6_RNI79SD:Y,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_in[52]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[52]:CLK,9837
UART_IF_0/UART_IF_FSM_0/AXI_data_in[52]:D,7299
UART_IF_0/UART_IF_FSM_0/AXI_data_in[52]:Q,9837
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[21]:A,47420
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[21]:B,47552
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[21]:Y,47420
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[59]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[59]:CLK,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[59]:D,7957
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[59]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[59]:Q,10216
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[9]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[9]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[9]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[9]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[9]:Y,45795
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[37]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[37]:CLK,9864
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[37]:D,8309
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[37]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[37]:Q,9864
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_220:A,-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_220:B,-1515
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_220:IPA,-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_220:IPB,-1515
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a3[5]:A,8525
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a3[5]:B,9511
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a3[5]:Y,8525
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_31:IPENn,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_17:B,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_17:C,11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_17:IPB,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_17:IPC,11293
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[0]:A,9042
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[0]:B,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[0]:C,10329
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[0]:Y,1859
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_211:A,-1409
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_211:IPA,-1409
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_211:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:CLK,9236
UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:D,2837
UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[39]:Q,9236
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_2:A,44652
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_2:B,45539
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_2:Y,44652
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_18:B,45720
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_18:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_18:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_18:S,45640
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI07EQ3[5]:B,9737
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI07EQ3[5]:C,10174
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI07EQ3[5]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI07EQ3[5]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI07EQ3[5]:S,9733
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2:A,8898
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2:B,8841
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2:C,1273
UART_IF_0/UART_IF_FSM_0/RAM_WD_0_sqmuxa_0_a4_0_a2:Y,1273
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[7]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[7]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[7]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[7]:Y,39224
MDDR_Demo_top_0/AXI_IF_0/ARADDR[19]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[19]:CLK,-1440
MDDR_Demo_top_0/AXI_IF_0/ARADDR[19]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[19]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[19]:Q,-1440
UART_IF_0/UART_IF_FSM_0/AXI_data_out[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[4]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[4]:D,4005
UART_IF_0/UART_IF_FSM_0/AXI_data_out[4]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[4]:Q,9443
UART_IF_0/UART_IF_FSM_0/RAM_WD[55]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[55]:CLK,11204
UART_IF_0/UART_IF_FSM_0/RAM_WD[55]:D,3822
UART_IF_0/UART_IF_FSM_0/RAM_WD[55]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[55]:Q,11204
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[30]:A,45946
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[30]:B,44608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[30]:C,44864
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[30]:D,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[30]:Y,40828
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:B,7957
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:C,9336
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:D,9069
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6B1O4[4]:S,8837
MDDR_Demo_top_0/AXI_IF_0/AWADDR[0]:CLK,-1422
MDDR_Demo_top_0/AXI_IF_0/AWADDR[0]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[0]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[0]:Q,-1422
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_24:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_24:IPCLKn,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[12]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[12]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[12]:C,2949
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[12]:Y,2949
UART_IF_0/UART_IF_FSM_0/fsm[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[1]:CLK,9385
UART_IF_0/UART_IF_FSM_0/fsm[1]:D,7322
UART_IF_0/UART_IF_FSM_0/fsm[1]:Q,9385
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[17]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[17]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[17]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[17]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[17]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out[43]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[43]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[43]:D,2926
UART_IF_0/UART_IF_FSM_0/AXI_data_out[43]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[43]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[10]:A,46812
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[10]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[10]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[10]:Y,41092
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_7:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:A,46759
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:B,44552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:C,40238
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:D,46436
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:FCO,40238
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI89641[0]:Y,40552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4_1:A,43309
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4_1:B,43240
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4_1:C,43145
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4_1:Y,43145
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[7]:CLK,6389
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[7]:D,9703
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[7]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[7]:Q,6389
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i:A,44886
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i:C,44847
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i:D,44743
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i:Y,43073
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_12:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_12:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[12]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[12]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[12]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[12]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[12]:Y,43073
UART_IF_0/UART_IF_FSM_0/RAM_WD[61]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[61]:CLK,11203
UART_IF_0/UART_IF_FSM_0/RAM_WD[61]:D,3880
UART_IF_0/UART_IF_FSM_0/RAM_WD[61]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[61]:Q,11203
UART_IF_0/UART_IF_FSM_0/fsm_ns_o2_i_o3[0]:A,9453
UART_IF_0/UART_IF_FSM_0/fsm_ns_o2_i_o3[0]:B,9405
UART_IF_0/UART_IF_FSM_0/fsm_ns_o2_i_o3[0]:C,7322
UART_IF_0/UART_IF_FSM_0/fsm_ns_o2_i_o3[0]:D,9222
UART_IF_0/UART_IF_FSM_0/fsm_ns_o2_i_o3[0]:Y,7322
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[28]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[28]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[28]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[28]:Q,45970
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[14]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[14]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[14]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[14]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[14]:Y,21888
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[28]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[28]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[28]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[28]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[3]:A,10464
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[3]:B,8619
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[3]:C,8920
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[3]:D,1691
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[3]:Y,1691
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_116:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_116:IPB,
UART_IF_0/UART_IF_FSM_0/RAM_WD[29]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[29]:CLK,11184
UART_IF_0/UART_IF_FSM_0/RAM_WD[29]:D,4008
UART_IF_0/UART_IF_FSM_0/RAM_WD[29]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[29]:Q,11184
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN7GA3[4]:B,10243
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN7GA3[4]:C,9671
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN7GA3[4]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN7GA3[4]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN7GA3[4]:S,9686
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HSIZE_1_sqmuxa_1_0_a6:A,46012
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HSIZE_1_sqmuxa_1_0_a6:B,47886
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HSIZE_1_sqmuxa_1_0_a6:Y,46012
MDDR_Demo_top_0/AXI_IF_0/WDATA[28]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[28]:CLK,-1479
MDDR_Demo_top_0/AXI_IF_0/WDATA[28]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[28]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[28]:Q,-1479
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[0]:CLK,9220
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[0]:D,1998
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[0]:Q,9220
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[6]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[6]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[6]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[6]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[19]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[19]:CLK,9576
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[19]:D,8597
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[19]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[19]:Q,9576
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[55]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[55]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[55]:C,2844
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[55]:Y,2844
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_a2:A,9535
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_a2:B,9450
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_a2:C,9398
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_a2:D,8428
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_a2:Y,8428
MDDR_Demo_top_0/AXI_IF_0/WDATA[41]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[41]:CLK,-1544
MDDR_Demo_top_0/AXI_IF_0/WDATA[41]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[41]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[41]:Q,-1544
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[11]:CLK,40530
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[11]:D,40148
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[11]:Q,40530
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:B,7967
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:C,10130
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:D,9869
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_54:S,7267
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2_i:A,10288
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2_i:B,10348
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2_i:Y,10288
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[19]:CLK,42131
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[19]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[19]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[19]:Q,42131
UART_IF_0/UART_IF_FSM_0/AXI_address[18]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[18]:CLK,9209
UART_IF_0/UART_IF_FSM_0/AXI_address[18]:D,-28
UART_IF_0/UART_IF_FSM_0/AXI_address[18]:Q,9209
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[18]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[18]:B,45640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[18]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[18]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[18]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[57]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[57]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[57]:C,2866
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[57]:Y,2866
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[30]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[30]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[30]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[30]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[30]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1_RNIRLE5[1]:A,41708
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1_RNIRLE5[1]:B,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1_RNIRLE5[1]:C,41585
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1_RNIRLE5[1]:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[19]:CLK,47140
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[19]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[19]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[19]:Q,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[16]:A,45853
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[16]:B,44739
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[16]:C,44771
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[16]:D,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[16]:Y,40735
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[2]:A,47577
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[2]:B,47532
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[2]:C,43994
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[2]:D,47113
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[2]:Y,43994
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[15]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[15]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[15]:D,25264
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[15]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[15]:Q,21888
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[38]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[38]:CLK,9880
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[38]:D,8293
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[38]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[38]:Q,9880
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[1]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[1]:B,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[1]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[1]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[1]:Y,45822
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_133:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[23]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[23]:B,45560
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[23]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[23]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[23]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[6]:A,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[6]:B,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[6]:Y,38431
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[4]:A,10504
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[4]:B,2826
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[4]:C,874
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[4]:Y,874
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[49]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[49]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[49]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[49]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[49]:Y,8813
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_4:C,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_4:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_4:IPC,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_34:IPENn,
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[1]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[1]:B,10406
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[1]:C,9836
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[1]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[1]:Y,9028
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[15]:CLK,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[15]:D,47556
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[15]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[15]:Q,46080
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[19]:A,7320
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[19]:B,8306
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[19]:Y,7320
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[7]:A,137
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[7]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[7]:Y,137
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[6]:A,19308
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[6]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[6]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[6]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[6]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[27]:CLK,42317
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[27]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[27]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[27]:Q,42317
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_76:A,42173
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_76:B,42069
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_76:C,42051
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_76:Y,42051
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[0]:CLK,8102
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[0]:D,8922
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[0]:Q,8102
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[21]:CLK,47155
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[21]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[21]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[21]:Q,47155
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_1:A,45554
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_1:B,45448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_1:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_1:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_1:S,45897
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[18]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[18]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[18]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[18]:Y,46645
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_15:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_15:C,11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_15:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_15:IPC,11130
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[25]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[25]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[25]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[25]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[22]:CLK,44806
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[22]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[22]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[22]:Q,44806
UART_IF_0/UART_IF_FSM_0/AXI_data_out[23]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[23]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[23]:D,2814
UART_IF_0/UART_IF_FSM_0/AXI_data_out[23]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[23]:Q,9329
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_1:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[17]:CLK,45554
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[17]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[17]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[17]:Q,45554
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[2]:CLK,42945
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[2]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[2]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[2]:Q,42945
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[31]:A,46476
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[31]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[31]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[31]:Y,41092
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[21]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[21]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[21]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[21]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_clk_base:CLK,46068
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_clk_base:Q,46068
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:B,7989
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:C,9368
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:D,9101
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKSAF6[6]:S,8805
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[14]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[14]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[14]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[14]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[14]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_26:A,43994
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_26:IPA,43994
UART_IF_0/UART_IF_FSM_0/RAM_WD[14]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[14]:CLK,11176
UART_IF_0/UART_IF_FSM_0/RAM_WD[14]:D,3897
UART_IF_0/UART_IF_FSM_0/RAM_WD[14]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[14]:Q,11176
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:B,9428
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:C,9360
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:D,7902
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIPVQBQ[29]:S,-196
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_212:A,-1507
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_212:IPA,-1507
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_212:IPB,
MDDR_Demo_top_0/AXI_IF_0/WDATA[61]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[61]:CLK,-1566
MDDR_Demo_top_0/AXI_IF_0/WDATA[61]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[61]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[61]:Q,-1566
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_96:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[25]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[25]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[25]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[25]:Q,45970
UART_IF_0/UART_IF_FSM_0/AXI_data_in[49]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[49]:CLK,9789
UART_IF_0/UART_IF_FSM_0/AXI_data_in[49]:D,7347
UART_IF_0/UART_IF_FSM_0/AXI_data_in[49]:Q,9789
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[24]:CLK,45043
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[24]:D,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[24]:Q,45043
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_139:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_139:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[9]:CLK,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[9]:D,41267
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[9]:Q,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[3]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[3]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[3]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[3]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[3]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[10]:CLK,43009
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[10]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[10]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[10]:Q,43009
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[22]:CLK,42844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[22]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[22]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[22]:Q,42844
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_3:A,7393
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_3:B,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_3:C,9351
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_3:FCI,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_3:Y,7307
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:CLK,38708
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:Q,38708
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_q1:Q,48867
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[2]:A,10431
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[2]:B,10393
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[2]:C,10336
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[2]:D,10222
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[2]:Y,10222
UART_IF_0/UART_IF_FSM_0/sel:ALn,3352
UART_IF_0/UART_IF_FSM_0/sel:CLK,8726
UART_IF_0/UART_IF_FSM_0/sel:D,11255
UART_IF_0/UART_IF_FSM_0/sel:EN,8852
UART_IF_0/UART_IF_FSM_0/sel:Q,8726
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[0]:CLK,9463
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[0]:D,10346
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[0]:Q,9463
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_13:B,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_13:C,11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_13:IPB,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_13:IPC,11147
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[31]:SLn,45312
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO_0:A,10389
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO_0:B,10319
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO_0:Y,10319
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[2]:A,47421
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[2]:B,47553
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[2]:Y,47421
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:B,7877
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:C,10034
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:D,9773
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_48:S,7363
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[12]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[12]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[12]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[12]:Y,40377
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:B,7400
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:C,9554
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:D,9293
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_18:S,7843
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[14]:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[14]:B,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[14]:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_249:A,-1566
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_249:IPA,-1566
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_249:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[18]:CLK,47470
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[18]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[18]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[18]:Q,47470
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:CLK,46118
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:Q,46118
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[4]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[4]:CLK,9336
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[4]:D,8837
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[4]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[4]:Q,9336
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[19]:A,46668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[19]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[19]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[19]:Y,41092
UART_IF_0/UART_IF_FSM_0/DATA_OUT[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[0]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[0]:D,7360
UART_IF_0/UART_IF_FSM_0/DATA_OUT[0]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[0]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[9]:A,47403
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[9]:B,47535
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[9]:Y,47403
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK,38634
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:Q,38634
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_12_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_12_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_12_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:B,8341
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:C,9720
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:D,9453
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6Q2AV[28]:S,8453
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_193:B,-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_193:C,-1517
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPB,-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPC,-1517
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[35]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[35]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[35]:C,2907
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[35]:Y,2907
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[2]:CLK,8284
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[2]:D,10222
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[2]:EN,10238
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[2]:Q,8284
UART_IF_0/UART_IF_FSM_0/RAM_WD[59]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[59]:CLK,11203
UART_IF_0/UART_IF_FSM_0/RAM_WD[59]:D,3729
UART_IF_0/UART_IF_FSM_0/RAM_WD[59]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[59]:Q,11203
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[37]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[37]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[37]:C,2970
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[37]:Y,2970
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_50:A,47427
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_50:IPA,47427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[28]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[28]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[28]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[28]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[12]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[12]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[12]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[12]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[12]:Y,8813
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_26:C,11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_26:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_26:IPC,11281
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_170:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[6]:A,40228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[6]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[6]:Y,40228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[24]:A,40218
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[24]:B,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[24]:C,46632
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[24]:D,44663
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[24]:Y,39264
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[3]:B,17664
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[3]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[3]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[3]:S,17770
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:CLK,16743
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:D,17770
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[3]:Q,16743
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_64:A,47330
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_64:B,21424
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_64:IPA,47330
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_64:IPB,21424
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[21]:CLK,42165
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[21]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[21]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[21]:Q,42165
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[12]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[12]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[12]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[12]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[28]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[28]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[28]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[28]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_278:A,25186
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_278:B,25570
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_278:IPA,25186
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_278:IPB,25570
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[8]:B,17744
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[8]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[8]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[8]:S,17690
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[16]:A,8648
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[16]:B,1953
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[16]:C,9236
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[16]:D,8644
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[16]:Y,1953
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIT7P35[7]:B,10291
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIT7P35[7]:C,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIT7P35[7]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIT7P35[7]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIT7P35[7]:S,9641
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:CLK,43011
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:D,42410
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:Q,43011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[1]:CLK,42109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[1]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[1]:Q,42109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[23]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[23]:B,44608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[23]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[23]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[23]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[1]:A,47247
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[1]:B,47170
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[1]:C,43638
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[1]:D,46751
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[1]:Y,43638
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[30]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[30]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[30]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[30]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:B,8133
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:C,9512
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:D,9245
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQNR2G[15]:S,8661
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[10]:CLK,47464
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[10]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[10]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[10]:Q,47464
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[40]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[40]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[40]:C,3002
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[40]:Y,3002
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:B,8293
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:C,9672
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:D,9405
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICHIPR[25]:S,8501
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_33:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_0_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_0_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_0_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_13:B,45640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_13:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_13:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_13:S,46610
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_34:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_17:B,45704
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_17:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_17:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_17:S,45682
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[15]:CLK,42221
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[15]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[15]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[15]:Q,42221
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_0_0:A,9000
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_0_0:B,2782
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_0_0:C,10274
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_0_0:Y,2782
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[1]:CLK,47525
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[1]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[1]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[1]:Q,47525
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:CLK,46813
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:Q,46813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[14]:CLK,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[14]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[14]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[14]:Q,46999
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:CLK,46812
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:Q,46812
UART_IF_0/UART_IF_FSM_0/DATA_OUT[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[5]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[5]:D,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT[5]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[5]:Q,11367
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o3[2]:A,7547
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o3[2]:B,7498
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o3[2]:C,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o3[2]:Y,7409
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_199:A,-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_199:B,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_199:IPA,-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_199:IPB,-1569
UART_IF_0/COREUART_0/CUARTO1I[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[2]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[2]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[2]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[2]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_29:B,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_29:C,11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_29:IPB,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_29:IPC,11246
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[4]:A,40635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[4]:B,47886
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[4]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[4]:Y,40635
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_15_PAD/U_IOPAD:Y,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[34]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[34]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[34]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[34]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[34]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[28]:A,48004
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[28]:B,47867
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[28]:C,46888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[28]:D,45736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[28]:Y,45736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i_o2_i_o2:A,43111
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i_o2_i_o2:B,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i_o2_i_o2:C,42996
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_3_i_o2_i_o2:Y,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_2_sqmuxa_i:A,44916
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_2_sqmuxa_i:B,44855
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_2_sqmuxa_i:C,42938
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_2_sqmuxa_i:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_2_sqmuxa_i:Y,39098
MDDR_Demo_top_0/AXI_IF_0/AWADDR[26]:CLK,-1426
MDDR_Demo_top_0/AXI_IF_0/AWADDR[26]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[26]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[26]:Q,-1426
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_clk_base:CLK,47053
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core_clk_base:Q,47053
MDDR_Demo_top_0/AXI_IF_0/ARSIZE_1[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARSIZE_1[0]:CLK,-1572
MDDR_Demo_top_0/AXI_IF_0/ARSIZE_1[0]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARSIZE_1[0]:Q,-1572
UART_IF_0/UART_IF_FSM_0/fsm[14]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[14]:CLK,9351
UART_IF_0/UART_IF_FSM_0/fsm[14]:D,10406
UART_IF_0/UART_IF_FSM_0/fsm[14]:Q,9351
UART_IF_0/COREUART_0/genblk1.RXRDY:ALn,3352
UART_IF_0/COREUART_0/genblk1.RXRDY:CLK,6152
UART_IF_0/COREUART_0/genblk1.RXRDY:D,11354
UART_IF_0/COREUART_0/genblk1.RXRDY:EN,10352
UART_IF_0/COREUART_0/genblk1.RXRDY:Q,6152
UART_IF_0/UART_IF_FSM_0/cnt_1k[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[0]:CLK,7328
UART_IF_0/UART_IF_FSM_0/cnt_1k[0]:D,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k[0]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[0]:Q,7328
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:B,9396
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:C,9360
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:D,7870
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIBSL1O[27]:S,-164
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_40:A,43605
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_40:B,43727
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_40:IPA,43605
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_40:IPB,43727
UART_IF_0/UART_IF_FSM_0/fsm_RNO[19]:A,10477
UART_IF_0/UART_IF_FSM_0/fsm_RNO[19]:B,10400
UART_IF_0/UART_IF_FSM_0/fsm_RNO[19]:C,7320
UART_IF_0/UART_IF_FSM_0/fsm_RNO[19]:D,9739
UART_IF_0/UART_IF_FSM_0/fsm_RNO[19]:Y,7320
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[3]:A,48010
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[3]:B,47926
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[3]:C,47876
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[3]:D,47733
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[3]:Y,47733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[1]:SLn,45312
MDDR_Demo_top_0/AXI_IF_0/AWADDR[16]:CLK,-1586
MDDR_Demo_top_0/AXI_IF_0/AWADDR[16]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[16]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[16]:Q,-1586
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[6]:A,45946
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[6]:B,44992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[6]:C,44864
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[6]:D,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[6]:Y,40828
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILA4N4[4]:B,10195
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILA4N4[4]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILA4N4[4]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNILA4N4[4]:S,7930
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0:YNn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[21]:CLK,47552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[21]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[21]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[21]:Q,47552
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[10],11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[11],11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[1],10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[2],10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[3],10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[4],10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[5],11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[6],11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[7],11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[8],11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ADDR[9],11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_BLK[2],11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_CLK,8181
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[10],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[11],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[14],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[15],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[16],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[4],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[5],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[6],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[7],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DIN[9],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT[0],8181
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT[1],8195
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:A_WEN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[10],11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[11],11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[4],10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[5],11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[6],11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[7],11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[8],11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ADDR[9],11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_BLK[2],11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[0],11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[10],11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[11],11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[12],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[13],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[14],11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[15],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[16],11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[1],11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[2],11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[3],11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[4],11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[5],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[6],11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[7],11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DIN[9],11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/INST_RAM1K18_IP:B_WEN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_7:B,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_7:IPB,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_7:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[3]:A,47944
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[3]:B,46757
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[3]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[3]:Y,43271
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_5:A,45936
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_5:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_5:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1_1:A,43608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1_1:B,43050
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1_1:C,44395
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1_1:Y,43050
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_141:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_141:IPB,
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[1]:CLK,7571
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[1]:D,10325
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[1]:EN,10238
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[1]:Q,7571
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[8]:CLK,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[8]:D,47668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[8]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[8]:Q,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_a3_1:A,42573
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_a3_1:B,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_a3_1:C,42516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_a3_1:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[8]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[8]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[8]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[8]:Y,40377
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[54]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[54]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[54]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[54]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[54]:Y,8813
UART_IF_0/UART_IF_FSM_0/fsm[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[10]:CLK,8232
UART_IF_0/UART_IF_FSM_0/fsm[10]:D,1772
UART_IF_0/UART_IF_FSM_0/fsm[10]:Q,8232
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[21]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[21]:D,47460
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[21]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[21]:Q,46105
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_12:C,11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_12:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_12:IPC,11143
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_227:A,-1511
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_227:B,-1532
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_227:IPA,-1511
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_227:IPB,-1532
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_26:C,11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_26:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_26:IPC,11281
UART_IF_0/UART_IF_FSM_0/RAM_WD[22]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[22]:CLK,11187
UART_IF_0/UART_IF_FSM_0/RAM_WD[22]:D,3941
UART_IF_0/UART_IF_FSM_0/RAM_WD[22]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[22]:Q,11187
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:B,8581
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:C,9960
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:D,9693
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIINTG1[43]:S,8213
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[1]:A,45886
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[1]:B,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[1]:Y,45822
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:B,8613
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:C,9992
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:D,9725
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNICUV8J1[45]:S,8181
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_107:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core:ALn,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core:CLK,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core:Q,4897
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_4_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_4_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_4_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A,
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[19]:CLK,45586
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[19]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[19]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[19]:Q,45586
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[2]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[2]:B,10400
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[2]:C,9836
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[2]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[2]:Y,9028
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[22]:A,46620
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[22]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[22]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[22]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:CLK,21437
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:Q,21437
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[2]:CLK,43040
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[2]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[2]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[2]:Q,43040
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_36:A,43608
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_36:IPA,43608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_0_a6_0_a3:A,44790
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_0_a6_0_a3:B,44686
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_0_a6_0_a3:C,43582
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_0_a6_0_a3:D,43578
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_0_sqmuxa_0_a6_0_a3:Y,43578
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:B,8053
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:C,9432
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:D,9165
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIM6N7A[10]:S,8741
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK,45976
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:EN,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FDDR_CORE_RESET_N_int:Q,45976
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[5]:CLK,47500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[5]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[5]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[5]:Q,47500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[20]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[20]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[20]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[20]:Q,46992
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_27:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_27:C,11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_27:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_27:IPC,11236
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[5]:A,40244
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[5]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[5]:Y,40244
MDDR_Demo_top_0/AXI_IF_0/AWADDR[25]:CLK,-1466
MDDR_Demo_top_0/AXI_IF_0/AWADDR[25]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[25]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[25]:Q,-1466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2:A,42057
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2:B,41151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2:C,41929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2:Y,41151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[0]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[0]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[0]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[0]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[0]:Y,39315
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[17]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[17]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[17]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[17]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:B,8165
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:C,9544
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:D,9277
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGJNDI[17]:S,8629
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_32:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_32:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[4]:A,48004
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[4]:B,45991
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[4]:C,46935
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[4]:Y,45991
UART_IF_0/UART_IF_FSM_0/AXI_address[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[1]:CLK,9108
UART_IF_0/UART_IF_FSM_0/AXI_address[1]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address[1]:Q,9108
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_17:B,44758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_17:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_17:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_17:S,44672
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIS1QK1[1]:B,9721
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIS1QK1[1]:C,10164
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIS1QK1[1]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIS1QK1[1]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIS1QK1[1]:S,9786
MDDR_Demo_top_0/AXI_IF_0/AWADDR[15]:CLK,-1569
MDDR_Demo_top_0/AXI_IF_0/AWADDR[15]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[15]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[15]:Q,-1569
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[30]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[30]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[30]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[30]:Q,45970
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_0:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_0:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_114:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_114:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_18:C,11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_18:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_18:IPC,11353
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[1]:A,47924
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[1]:B,47926
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[1]:C,42455
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[1]:D,44638
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[1]:Y,42455
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[24]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[24]:CLK,9656
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[24]:D,8517
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[24]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[24]:Q,9656
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_29:B,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_29:C,11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_29:IPB,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_29:IPC,11246
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[3]:A,10444
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[3]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[3]:C,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[3]:D,10187
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[3]:Y,8195
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[24]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[24]:B,45544
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[24]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[24]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[24]:Y,40733
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_9:B,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_9:C,10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_9:IPB,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_9:IPC,10999
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_7_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_7_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_7_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/WEN:ALn,3352
UART_IF_0/UART_IF_FSM_0/WEN:CLK,10334
UART_IF_0/UART_IF_FSM_0/WEN:D,1405
UART_IF_0/UART_IF_FSM_0/WEN:EN,1273
UART_IF_0/UART_IF_FSM_0/WEN:Q,10334
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[41]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[41]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[41]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[41]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[41]:Y,8813
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_443_i_i:A,9478
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_443_i_i:B,10403
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_443_i_i:Y,9478
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[6]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[6]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[6]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[6]:Y,39315
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[1]:A,10477
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[1]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[1]:C,7345
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[1]:D,10209
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[1]:Y,7345
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_173:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_173:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[16]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[16]:B,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[16]:C,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[16]:Y,39252
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_224:A,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_224:B,-1537
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_224:IPA,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_224:IPB,-1537
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[2]:A,41140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[2]:B,47890
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[2]:Y,41140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[16]:CLK,47511
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[16]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[16]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[16]:Q,47511
MDDR_Demo_top_0/AXI_IF_0/ARADDR[20]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[20]:CLK,-1455
MDDR_Demo_top_0/AXI_IF_0/ARADDR[20]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[20]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[20]:Q,-1455
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_256:A,-1377
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_256:B,-1593
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_256:IPA,-1377
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_256:IPB,-1593
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTl0Il_4_i_o3[1]:A,9459
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTl0Il_4_i_o3[1]:B,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTl0Il_4_i_o3[1]:C,9342
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTl0Il_4_i_o3[1]:Y,7409
UART_IF_0/UART_IF_FSM_0/WLEN_3_i_0_a3[0]:A,8720
UART_IF_0/UART_IF_FSM_0/WLEN_3_i_0_a3[0]:B,8677
UART_IF_0/UART_IF_FSM_0/WLEN_3_i_0_a3[0]:C,8603
UART_IF_0/UART_IF_FSM_0/WLEN_3_i_0_a3[0]:D,8525
UART_IF_0/UART_IF_FSM_0/WLEN_3_i_0_a3[0]:Y,8525
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[10]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[10]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[10]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[10]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[10]:Y,43073
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_83:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[25]:CLK,42197
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[25]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[25]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[25]:Q,42197
UART_IF_0/UART_IF_FSM_0/AXI_address[19]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[19]:CLK,9225
UART_IF_0/UART_IF_FSM_0/AXI_address[19]:D,-43
UART_IF_0/UART_IF_FSM_0/AXI_address[19]:Q,9225
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[8]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[8]:CLK,16861
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[8]:D,17690
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[8]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[8]:Q,16861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[28]:CLK,42892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[28]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[28]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[28]:Q,42892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[16]:CLK,43152
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[16]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[16]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[16]:Q,43152
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[26]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[26]:CLK,9688
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[26]:D,8485
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[26]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[26]:Q,9688
UART_IF_0/UART_IF_FSM_0/RAM_WD[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[8]:CLK,11176
UART_IF_0/UART_IF_FSM_0/RAM_WD[8]:D,3887
UART_IF_0/UART_IF_FSM_0/RAM_WD[8]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[8]:Q,11176
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[9]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[9]:CLK,24971
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[9]:D,25256
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[9]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[9]:Q,24971
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_2_0_a6:A,45733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_2_0_a6:B,45630
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_2_0_a6:C,43751
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_2_0_a6:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_2_0_a6:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[25]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[25]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[25]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[25]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[25]:Y,39151
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_0:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_0:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[18]:A,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[18]:B,46718
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[18]:C,43186
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[18]:D,46299
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[18]:Y,43186
MDDR_Demo_top_0/AXI_IF_0/ARADDR[4]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[4]:CLK,-1377
MDDR_Demo_top_0/AXI_IF_0/ARADDR[4]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[4]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[4]:Q,-1377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[4]:CLK,43056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[4]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[4]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[4]:Q,43056
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:ALn,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:CLK,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core:Q,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9P7F/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9P7F/U0_RGB1:YL,47268
UART_IF_0/UART_IF_FSM_0/RAM_WD[15]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[15]:CLK,11166
UART_IF_0/UART_IF_FSM_0/RAM_WD[15]:D,3948
UART_IF_0/UART_IF_FSM_0/RAM_WD[15]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[15]:Q,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_11:B,11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_11:IPB,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[6]:CLK,42716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[6]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[6]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[6]:Q,42716
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:B,9421
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:C,7155
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:D,9117
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_7:S,8013
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i_1[1]:A,46873
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i_1[1]:B,45999
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i_1[1]:C,46748
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i_1[1]:Y,45999
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[2]:CLK,8057
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[2]:D,7962
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[2]:Q,8057
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[43]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[43]:CLK,9960
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[43]:D,8213
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[43]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[43]:Q,9960
MDDR_Demo_top_0/AXI_IF_0/AWADDR[21]:CLK,-1517
MDDR_Demo_top_0/AXI_IF_0/AWADDR[21]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[21]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[21]:Q,-1517
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_27:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_27:C,11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_27:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_27:IPC,11236
RX_ibuf/U0/U_IOINFF:A,
RX_ibuf/U0/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6:A,43796
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6:B,41953
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6:C,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6:D,43630
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6:Y,41953
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_179:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[4]:B,17680
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[4]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[4]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[4]:S,17754
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:Q,48867
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[7]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[7]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[7]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[7]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[7]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[13]:A,45872
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[13]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a3[13]:Y,45795
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_70:B,21435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_70:IPB,21435
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[11]:A,46869
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[11]:B,46812
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[11]:C,43280
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[11]:D,46393
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[11]:Y,43280
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_1[0]:A,8058
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_1[0]:B,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_1[0]:C,9442
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_1[0]:D,9354
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_1[0]:Y,6389
MDDR_Demo_top_0/AXI_IF_0/AWADDR[11]:CLK,-1527
MDDR_Demo_top_0/AXI_IF_0/AWADDR[11]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[11]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[11]:Q,-1527
ip_interface_inst:B,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[31]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[31]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[31]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[31]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[31]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[31]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[31]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[31]:Y,39151
UART_IF_0/UART_IF_FSM_0/RAM_WD[52]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[52]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[52]:D,3792
UART_IF_0/UART_IF_FSM_0/RAM_WD[52]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[52]:Q,11208
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[18]:A,46684
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[18]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[18]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[18]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[0]:CLK,47315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[0]:D,46012
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[0]:EN,41469
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[0]:Q,47315
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[0]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[0]:B,10406
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[0]:C,9836
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[0]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[0]:Y,9028
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:B,9268
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:C,9225
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:D,7742
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRU9PE[11]:S,-43
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[1]:A,6129
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[1]:B,791
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[1]:C,10342
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[1]:D,10235
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[1]:Y,791
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[17]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[17]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[17]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[17]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[17]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[9]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[9]:B,44832
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[9]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[9]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[9]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[8]:A,46817
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[8]:B,46760
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[8]:C,43228
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[8]:D,46341
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[8]:Y,43228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[26]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[26]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[26]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[26]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[8]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[8]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[8]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[8]:Q,45970
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[12]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[12]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[12]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[12]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_out[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[2]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[2]:D,3791
UART_IF_0/UART_IF_FSM_0/AXI_data_out[2]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[2]:Q,9443
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[30]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[30]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[30]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[30]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[30]:Y,39151
MDDR_Demo_top_0/AXI_IF_0/AWADDR[31]:CLK,-1435
MDDR_Demo_top_0/AXI_IF_0/AWADDR[31]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[31]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[31]:Q,-1435
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_2:A,42538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_2:B,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_2:C,43792
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_2:D,41804
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_2:Y,40116
MDDR_Demo_top_0/AXI_IF_0/ARADDR[14]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[14]:CLK,-1573
MDDR_Demo_top_0/AXI_IF_0/ARADDR[14]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[14]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[14]:Q,-1573
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_251:A,-1649
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_251:IPA,-1649
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_251:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_263:A,-1418
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_263:B,-1495
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_263:IPA,-1418
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_263:IPB,-1495
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[18]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[18]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[18]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[18]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_s_242:B,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_s_242:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_89:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_89:IPB,
UART_IF_0/UART_IF_FSM_0/fsm[13]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[13]:CLK,8498
UART_IF_0/UART_IF_FSM_0/fsm[13]:D,10206
UART_IF_0/UART_IF_FSM_0/fsm[13]:Q,8498
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_140:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_140:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[14]:CLK,47479
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[14]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[14]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[14]:Q,47479
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_82:A,42317
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_82:B,42213
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_82:C,42195
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_82:Y,42195
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:A,47916
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:B,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:C,47794
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:D,47692
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:Y,47692
UART_IF_0/COREUART_0/CUARTO1I[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[1]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[1]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[1]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[1]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_i_0_a2_0[1]:A,1998
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_i_0_a2_0[1]:B,9465
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_i_0_a2_0[1]:C,2046
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_i_0_a2_0[1]:Y,1998
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_34:IPENn,
MDDR_Demo_top_0/AXI_IF_0/WDATA[31]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[31]:CLK,-1503
MDDR_Demo_top_0/AXI_IF_0/WDATA[31]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[31]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[31]:Q,-1503
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_31:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_o2_0:A,45980
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_o2_0:B,45911
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_o2_0:C,43964
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_o2_0:D,43830
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_o2_0:Y,43830
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_248:A,-1616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_248:IPA,-1616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_248:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_200:A,-1393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_200:B,-1586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_200:IPA,-1393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_200:IPB,-1586
TX_obuf/U0/U_IOPAD:D,
TX_obuf/U0/U_IOPAD:E,
TX_obuf/U0/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_68:A,47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_68:B,21407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_68:IPA,47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_68:IPB,21407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_5_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_5_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_5_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[4]:CLK,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[4]:D,47732
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[4]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[4]:Q,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[10]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[10]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[10]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[10]:Y,40377
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[40]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[40]:CLK,9912
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[40]:D,8261
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[40]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[40]:Q,9912
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[13]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[13]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[13]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[13]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[13]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_156:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_5:B,44566
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_5:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_5:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_5:S,44864
UART_IF_0/UART_IF_FSM_0/AXI_data_in[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[10]:CLK,9165
UART_IF_0/UART_IF_FSM_0/AXI_data_in[10]:D,7971
UART_IF_0/UART_IF_FSM_0/AXI_data_in[10]:Q,9165
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_32:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_32:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[2]:A,19311
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[2]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[2]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[2]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[2]:Y,8534
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[6]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[6]:B,10420
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[6]:C,9122
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[6]:D,9729
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[6]:Y,9122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[0]:CLK,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[0]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[0]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[0]:Q,45432
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[1]:CLK,10369
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[1]:D,9478
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[1]:Q,10369
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[5]:CLK,42019
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[5]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[5]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[5]:Q,42019
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:CLK,21440
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:Q,21440
UART_IF_0/COREUART_0/CUARTO01/CUARTIOll[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTIOll[0]:CLK,8495
UART_IF_0/COREUART_0/CUARTO01/CUARTIOll[0]:EN,9281
UART_IF_0/COREUART_0/CUARTO01/CUARTIOll[0]:Q,8495
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[1]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[1]:B,22212
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[1]:C,20903
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[1]:D,21869
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata[1]:Y,20903
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[7]:A,10444
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[7]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[7]:C,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[7]:D,10187
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[7]:Y,8195
UART_IF_0/UART_IF_FSM_0/AXI_data_in[29]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[29]:CLK,9469
UART_IF_0/UART_IF_FSM_0/AXI_data_in[29]:D,7667
UART_IF_0/UART_IF_FSM_0/AXI_data_in[29]:Q,9469
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_168:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_12:B,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_12:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_12:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_12:S,44880
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[18]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[18]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[18]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[18]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_9:A,45996
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_9:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_9:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[43]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[43]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[43]:C,2926
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[43]:Y,2926
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[8]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[8]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[8]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[8]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[8]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:CLK,38668
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:D,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:Q,38668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[8]:CLK,42993
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[8]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[8]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[8]:Q,42993
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0_0:A,7586
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0_0:B,7464
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0_0:C,9324
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0_0:D,9296
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0_0:Y,7464
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:A,43088
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:B,42051
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:C,42993
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:D,42732
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_75:FCO,41987
MDDR_Demo_top_0/AXI_IF_0/WDATA[12]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[12]:CLK,-1465
MDDR_Demo_top_0/AXI_IF_0/WDATA[12]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[12]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[12]:Q,-1465
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l:CLK,7002
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l:D,11307
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l:EN,9375
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l:Q,7002
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:B,8229
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:C,9608
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:D,9341
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIG2J3N[21]:S,8565
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_1[2]:A,8660
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_1[2]:B,8619
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_1[2]:Y,8619
UART_IF_0/UART_IF_FSM_0/AXI_address[11]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[11]:CLK,9097
UART_IF_0/UART_IF_FSM_0/AXI_address[11]:D,77
UART_IF_0/UART_IF_FSM_0/AXI_address[11]:Q,9097
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_115:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_115:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_10:B,44646
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_10:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_10:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_10:S,44784
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[1]:A,10451
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[1]:B,10396
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[1]:C,8356
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[1]:D,8347
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[1]:Y,8347
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:CLK,47875
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:Q,47875
UART_IF_0/UART_IF_FSM_0/AXI_data_in[30]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[30]:CLK,9485
UART_IF_0/UART_IF_FSM_0/AXI_data_in[30]:D,7651
UART_IF_0/UART_IF_FSM_0/AXI_data_in[30]:Q,9485
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[18]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[18]:B,44688
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[18]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[18]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[18]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:CLK,16906
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:D,17674
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[9]:Q,16906
UART_IF_0/UART_IF_FSM_0/cnt_1k[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[9]:CLK,8513
UART_IF_0/UART_IF_FSM_0/cnt_1k[9]:D,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k[9]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[9]:Q,8513
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[6]:CLK,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[6]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[6]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[6]:Q,43072
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:B,8405
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:C,9784
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:D,9517
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4H8041[32]:S,8389
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_181:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[29]:A,46071
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[29]:B,46246
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[29]:C,46174
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[29]:Y,46071
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[30]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[30]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[30]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[30]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[17]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[17]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[17]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[17]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[17]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_1_PAD/U_IOPAD:Y,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_14:C,11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_14:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_14:IPC,11121
UART_IF_0/UART_IF_FSM_0/RAM_WD[19]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[19]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[19]:D,4009
UART_IF_0/UART_IF_FSM_0/RAM_WD[19]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[19]:Q,11197
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[0]:CLK,11367
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[0]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[0]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[0]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[11]:CLK,42189
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[11]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[11]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[11]:Q,42189
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[19]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[19]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[19]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[19]:Q,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[11]:CLK,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[11]:D,47620
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[11]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[11]:Q,46015
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_13:B,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_13:C,11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_13:IPB,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_13:IPC,11147
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[10]:A,46962
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[10]:B,46905
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[10]:C,43373
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[10]:D,46486
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[10]:Y,43373
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:A,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:B,40148
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:C,44582
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:D,46532
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJVO46[6]:S,40228
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:B,7640
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:C,9794
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:D,9533
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_33:S,7603
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:A,-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:B,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:C,-1572
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPA,-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPB,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPC,-1572
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[22]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[22]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[22]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[22]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[22]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[5]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[5]:CLK,16825
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[5]:D,17738
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[5]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[5]:Q,16825
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[17]:A,46700
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[17]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[17]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[17]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[10]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[10]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[10]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[10]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[10]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[31]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[31]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[31]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[31]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[31]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[24]:CLK,44838
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[24]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[24]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[24]:Q,44838
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[23]:CLK,47137
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[23]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[23]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[23]:Q,47137
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[11]:CLK,42067
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[11]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[11]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[11]:Q,42067
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[12]:CLK,44646
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[12]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[12]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[12]:Q,44646
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[6]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[6]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[6]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[6]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[2]:A,9042
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[2]:B,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[2]:C,10336
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[2]:D,9337
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[2]:Y,1859
MDDR_Demo_top_0/AXI_IF_0/AXI_RBUSY:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/AXI_RBUSY:CLK,9369
MDDR_Demo_top_0/AXI_IF_0/AXI_RBUSY:D,10191
MDDR_Demo_top_0/AXI_IF_0/AXI_RBUSY:EN,2686
MDDR_Demo_top_0/AXI_IF_0/AXI_RBUSY:Q,9369
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:B,8357
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:C,9736
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:D,9469
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI81JF01[29]:S,8437
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_34:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[7]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[7]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[7]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[7]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[7]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_0:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_0:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[20]:A,40507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[20]:B,47705
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[20]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[20]:Y,40507
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[12]:A,47383
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[12]:B,47515
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[12]:Y,47383
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[16]:CLK,42796
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[16]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[16]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[16]:Q,42796
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:A,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:B,40212
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:C,44646
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:D,46596
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI5F2E9[10]:S,40164
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[13]:A,10470
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[13]:B,10390
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[13]:C,10369
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[13]:D,10206
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[13]:Y,10206
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[11]:A,77
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[11]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[11]:Y,77
MDDR_Demo_top_0/AXI_IF_0/ARADDR[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[0]:CLK,-1499
MDDR_Demo_top_0/AXI_IF_0/ARADDR[0]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[0]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[0]:Q,-1499
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[7]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[7]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[7]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[7]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[7]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_13_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_13_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_13_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/WDATA[58]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[58]:CLK,-1438
MDDR_Demo_top_0/AXI_IF_0/WDATA[58]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[58]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[58]:Q,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_143:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4:A,43145
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4:B,43944
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4:C,42081
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4:D,41151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_4:Y,41151
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[3]:CLK,7586
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[3]:D,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[3]:Q,7586
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[3]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[3]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[3]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[3]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[3]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[26]:A,47077
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[26]:B,47020
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[26]:C,43488
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[26]:D,46601
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[26]:Y,43488
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3_RNIAA4D1:A,43078
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3_RNIAA4D1:B,45758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3_RNIAA4D1:C,41131
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3_RNIAA4D1:D,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3_RNIAA4D1:Y,40690
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[9]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[9]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[9]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[9]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[7]:CLK,42035
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[7]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[7]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[7]:Q,42035
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_1:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_87:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_87:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[1]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[1]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[1]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[1]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[17]:A,47376
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[17]:B,47508
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[17]:Y,47376
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[0]:CLK,42223
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[0]:D,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[0]:Q,42223
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[5]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[5]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[5]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[5]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[5]:Y,43758
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[11]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[11]:CLK,8318
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[11]:D,7818
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[11]:Q,8318
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:B,8027
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:C,10194
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:D,9939
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_58:S,7203
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:A,7393
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:B,8547
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:C,8552
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:D,8334
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:FCI,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:FCO,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_2:Y,7393
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[21]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[21]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[21]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[21]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[21]:Y,39321
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_9:B,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_9:C,10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_9:IPB,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_9:IPC,10999
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[7]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[7]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[7]:D,25206
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[7]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[7]:Q,21888
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[29]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[29]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[29]:C,3030
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[29]:Y,3030
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:A,46838
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:B,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:C,44518
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:D,46468
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:FCI,40126
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFJ813[2]:S,40261
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[13]:A,8648
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[13]:B,1978
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[13]:C,9243
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[13]:D,8644
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[13]:Y,1978
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[54]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[54]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[54]:C,2914
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[54]:Y,2914
MDDR_Demo_top_0/AXI_IF_0/ARADDR[18]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[18]:CLK,-1562
MDDR_Demo_top_0/AXI_IF_0/ARADDR[18]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[18]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[18]:Q,-1562
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[14]:CLK,42780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[14]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[14]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[14]:Q,42780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[17]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[17]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[17]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[17]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[17]:Y,39321
UART_IF_0/UART_IF_FSM_0/WRITE_RNO_0:A,9312
UART_IF_0/UART_IF_FSM_0/WRITE_RNO_0:B,9839
UART_IF_0/UART_IF_FSM_0/WRITE_RNO_0:C,10287
UART_IF_0/UART_IF_FSM_0/WRITE_RNO_0:Y,9312
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[58]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[58]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[58]:C,2931
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[58]:Y,2931
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[4]:A,45811
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[4]:B,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[4]:C,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[4]:D,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[4]:Y,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[13]:CLK,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[13]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[13]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[13]:Q,42101
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[27]:A,-164
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[27]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[27]:Y,-164
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE_2:A,10399
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE_2:B,10345
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE_2:C,10271
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE_2:D,10092
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE_2:Y,10092
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_0:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_0:IPCLKn,
MDDR_Demo_top_0/AXI_IF_0/ARLEN[0]:CLK,-1486
MDDR_Demo_top_0/AXI_IF_0/ARLEN[0]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARLEN[0]:EN,3986
MDDR_Demo_top_0/AXI_IF_0/ARLEN[0]:Q,-1486
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_7:B,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_7:IPB,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_7:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_4:A,42109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_4:B,42005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_4:C,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_4:Y,41987
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:B,8549
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:C,9928
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:D,9661
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0FFIE1[41]:S,8245
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RESET_N_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RESET_N_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_RESET_N_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_9:A,16868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_9:B,16825
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_9:C,16743
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_9:D,16636
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_9:Y,16636
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[17]:CLK,44515
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[17]:D,40416
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[17]:Q,44515
MDDR_Demo_top_0/AXI_IF_0/RREADY:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/RREADY:CLK,-1563
MDDR_Demo_top_0/AXI_IF_0/RREADY:D,10424
MDDR_Demo_top_0/AXI_IF_0/RREADY:EN,2764
MDDR_Demo_top_0/AXI_IF_0/RREADY:Q,-1563
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_0[10]:A,9530
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_0[10]:B,9472
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_0[10]:C,9343
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_0[10]:D,8794
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_0[10]:Y,8794
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[12]:A,43440
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[12]:B,47920
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[12]:Y,43440
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[7]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[7]:CLK,8334
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[7]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[7]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[7]:Q,8334
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[9]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[9]:CLK,25306
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[9]:D,25185
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[9]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[9]:Q,25306
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[1]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[1]:B,43744
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[1]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[1]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[1]:Y,43744
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9P7F/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9P7F/U0:YNn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[1]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[1]:CLK,21869
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[1]:D,25211
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[1]:EN,9446
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[1]:Q,21869
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_149:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_149:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_address[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[4]:CLK,9156
UART_IF_0/UART_IF_FSM_0/AXI_address[4]:D,9122
UART_IF_0/UART_IF_FSM_0/AXI_address[4]:Q,9156
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[7]:CLK,46548
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[7]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[7]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[7]:Q,46548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_53:A,47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_53:B,47347
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_53:IPA,47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_53:IPB,47347
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[20]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[20]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[20]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[20]:Y,39224
UART_IF_0/UART_IF_FSM_0/RAM_WD[38]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[38]:CLK,11218
UART_IF_0/UART_IF_FSM_0/RAM_WD[38]:D,3693
UART_IF_0/UART_IF_FSM_0/RAM_WD[38]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[38]:Q,11218
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base_RNIEJ51/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base_RNIEJ51/U0_RGB1:YL,47294
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[25]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[25]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[25]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[25]:Q,11367
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1:A,8318
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1:B,8270
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1:C,8196
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1:D,8102
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1:Y,8102
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[12]:A,62
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[12]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[12]:Y,62
UART_IF_0/UART_IF_FSM_0/AXI_data_in[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[7]:CLK,9117
UART_IF_0/UART_IF_FSM_0/AXI_data_in[7]:D,8013
UART_IF_0/UART_IF_FSM_0/AXI_data_in[7]:Q,9117
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[19]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[19]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[19]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[19]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[9]:A,40180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[9]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[9]:Y,40180
UART_IF_0/UART_IF_FSM_0/DATA_OUT[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[4]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[4]:D,8181
UART_IF_0/UART_IF_FSM_0/DATA_OUT[4]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[4]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[4]:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[4]:B,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[4]:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[13]:A,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[13]:B,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[13]:C,46610
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[13]:D,42391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[13]:Y,38412
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[6]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[6]:CLK,7322
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[6]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[6]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[6]:Q,7322
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_IN_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_IN_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:CLK,38540
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:D,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:Q,38540
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[27]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[27]:D,47364
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[27]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[27]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[0]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[0]:CLK,24700
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[0]:D,25195
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[0]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[0]:Q,24700
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_1:B,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_1:IPB,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_1:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:CLK,46611
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:Q,46611
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[0]:SLn,45312
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0[2]:A,8470
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0[2]:B,7322
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0[2]:C,8345
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_o2_0[2]:Y,7322
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[6]:CLK,40418
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[6]:D,40228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[6]:Q,40418
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CS_N_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CS_N_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CS_N_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_226:A,-1488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_226:B,-1538
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_226:IPA,-1488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_226:IPB,-1538
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTl05_0_a2:A,10504
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTl05_0_a2:B,10426
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTl05_0_a2:C,10369
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTl05_0_a2:D,10308
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTl05_0_a2:Y,10308
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_10:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[24]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[24]:D,47412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[24]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[24]:Q,46105
UART_IF_0/UART_IF_FSM_0/RAM_WD[44]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[44]:CLK,11217
UART_IF_0/UART_IF_FSM_0/RAM_WD[44]:D,3844
UART_IF_0/UART_IF_FSM_0/RAM_WD[44]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[44]:Q,11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_33:IPENn,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[34]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[34]:CLK,9816
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[34]:D,8357
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[34]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[34]:Q,9816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[30]:CLK,43264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[30]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[30]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[30]:Q,43264
CFG0_GND_INST:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[6]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[6]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[6]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[6]:Y,46645
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:B,8533
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:C,9912
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:D,9645
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAGRCD1[40]:S,8261
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int:ALn,48748
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int:CLK,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int:D,47875
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int:Q,47845
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[3]:CLK,44502
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[3]:D,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[3]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[3]:Q,44502
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[8]:A,46011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[8]:B,44976
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[8]:C,44929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[8]:D,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[8]:Y,40861
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:B,7480
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:C,9634
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:D,9373
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_23:S,7763
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIEUTV[0]:B,9705
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIEUTV[0]:C,10148
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIEUTV[0]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIEUTV[0]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIEUTV[0]:S,9786
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[12]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[12]:B,44784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[12]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[12]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[12]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:Q,18868
MDDR_Demo_top_0/AXI_IF_0/AWADDR[4]:CLK,-1393
MDDR_Demo_top_0/AXI_IF_0/AWADDR[4]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[4]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[4]:Q,-1393
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[9]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[9]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[9]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[9]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[9]:Y,21888
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l_1_sqmuxa_i:A,9375
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l_1_sqmuxa_i:B,10334
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l_1_sqmuxa_i:C,10280
UART_IF_0/COREUART_0/CUARTIO1/CUARTOl0l_1_sqmuxa_i:Y,9375
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[3]:CLK,8151
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[3]:D,7946
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[3]:Q,8151
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_43:A,43488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_43:B,43874
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_43:IPA,43488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_43:IPB,43874
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[10]:B,17776
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[10]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[10]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[10]:S,17658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_1:A,42427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_1:B,42381
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_1:C,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_1:D,41151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_1:Y,41151
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:A,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:B,8461
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:C,8466
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:D,8249
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:FCI,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:FCO,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_0:Y,7307
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[15]:CLK,45011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[15]:D,48847
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[15]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[15]:Q,45011
UART_IF_0/UART_IF_FSM_0/fsm_RNO[21]:A,10484
UART_IF_0/UART_IF_FSM_0/fsm_RNO[21]:B,10360
UART_IF_0/UART_IF_FSM_0/fsm_RNO[21]:C,9882
UART_IF_0/UART_IF_FSM_0/fsm_RNO[21]:Y,9882
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_33:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_180:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[21]:CLK,42538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[21]:D,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[21]:Q,42538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[18]:CLK,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[18]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[18]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[18]:Q,43073
UART_IF_0/UART_IF_FSM_0/AXI_data_in[16]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[16]:CLK,9261
UART_IF_0/UART_IF_FSM_0/AXI_data_in[16]:D,7875
UART_IF_0/UART_IF_FSM_0/AXI_data_in[16]:Q,9261
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_25:A,45983
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_25:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_25:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_0:A,46885
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_0:B,40301
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_0:C,46787
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_0:Y,40301
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_207:A,-1466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_207:B,-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_207:IPA,-1466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_207:IPB,-1619
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[10]:A,19261
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[10]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[10]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[10]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[10]:Y,8534
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[34]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[34]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[34]:C,3015
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[34]:Y,3015
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:CLK,46543
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:Q,46543
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[11]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[11]:CLK,25479
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[11]:D,25260
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[11]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[11]:Q,25479
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[21]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[21]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[21]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[21]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[21]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:CLK,45261
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:EN,46638
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:Q,45261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[12]:CLK,42242
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[12]:D,43440
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[12]:Q,42242
MDDR_Demo_top_0/AXI_IF_0/WDATA[42]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[42]:CLK,-1481
MDDR_Demo_top_0/AXI_IF_0/WDATA[42]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[42]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[42]:Q,-1481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_154:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[10]:CLK,46596
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[10]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[10]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[10]:Q,46596
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[20]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[20]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[20]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[20]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[20]:Y,43758
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i_0[2]:A,9357
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i_0[2]:B,9247
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i_0[2]:C,1625
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i_0[2]:D,1460
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i_0[2]:Y,1460
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[38]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[38]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[38]:C,2715
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[38]:Y,2715
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_2_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_2_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_2_PAD/U_IOPAD:PAD,
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[1]:CLK,8461
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[1]:D,11347
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[1]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[1]:Q,8461
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[2]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[2]:CLK,24668
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[2]:D,25058
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[2]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[2]:Q,24668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[22]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[22]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[22]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[22]:Q,46992
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[36]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[36]:CLK,9848
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[36]:D,8325
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[36]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[36]:Q,9848
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[27]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[27]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[27]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[27]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[27]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:B,7752
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:C,9906
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:D,9645
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_40:S,7491
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[5]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[5]:CLK,25570
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[5]:D,25221
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[5]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[5]:Q,25570
UART_IF_0/UART_IF_FSM_0/RAM_WD[31]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[31]:CLK,11184
UART_IF_0/UART_IF_FSM_0/RAM_WD[31]:D,3946
UART_IF_0/UART_IF_FSM_0/RAM_WD[31]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[31]:Q,11184
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[10]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[10]:CLK,24909
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[10]:D,25260
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[10]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[10]:Q,24909
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[16]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[16]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[16]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[16]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:B,7272
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:C,9432
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:D,9165
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_10:S,7971
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_34:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_59:B,47375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_59:IPB,47375
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_35:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_4:A,45819
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_4:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_4:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:CLK,46944
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:Q,46944
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_137:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_137:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[2]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[2]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[2]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[2]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[2]:Y,39315
MDDR_Demo_top_0/AXI_IF_0/ARADDR[30]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[30]:CLK,-1476
MDDR_Demo_top_0/AXI_IF_0/ARADDR[30]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[30]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[30]:Q,-1476
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[0]:CLK,42606
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[0]:D,40552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[0]:Q,42606
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[3]:CLK,9248
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[3]:D,8111
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[3]:Q,9248
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:CLK,21881
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:D,25176
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[3]:Q,21881
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[31]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[31]:D,47300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[31]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[31]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[26]:A,46556
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[26]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[26]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[26]:Y,41092
UART_IF_0/UART_IF_FSM_0/RAM_WD[12]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[12]:CLK,11176
UART_IF_0/UART_IF_FSM_0/RAM_WD[12]:D,3927
UART_IF_0/UART_IF_FSM_0/RAM_WD[12]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[12]:Q,11176
UART_IF_0/UART_IF_FSM_0/RAM_WD[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[4]:CLK,11153
UART_IF_0/UART_IF_FSM_0/RAM_WD[4]:D,4005
UART_IF_0/UART_IF_FSM_0/RAM_WD[4]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[4]:Q,11153
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[7]:CLK,42258
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[7]:D,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[7]:Q,42258
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[20]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[20]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[20]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[20]:Q,48017
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_11:B,11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_11:IPB,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[9]:CLK,44598
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[9]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[9]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[9]:Q,44598
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_o2:A,-228
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_o2:B,7247
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_o2:C,-192
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_o2:Y,-228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[0]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[0]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[0]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[0]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[0]:Y,39042
MDDR_Demo_top_0/AXI_IF_0/ARADDR[29]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[29]:CLK,-1487
MDDR_Demo_top_0/AXI_IF_0/ARADDR[29]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[29]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[29]:Q,-1487
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[12]:CLK,42764
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[12]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[12]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[12]:Q,42764
UART_IF_0/UART_IF_FSM_0/AXI_data_in[36]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[36]:CLK,9581
UART_IF_0/UART_IF_FSM_0/AXI_data_in[36]:D,7555
UART_IF_0/UART_IF_FSM_0/AXI_data_in[36]:Q,9581
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNI5T1N1[2]:A,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNI5T1N1[2]:B,47623
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNI5T1N1[2]:Y,43149
UART_IF_0/UART_IF_FSM_0/AXI_data_out[58]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[58]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[58]:D,2931
UART_IF_0/UART_IF_FSM_0/AXI_data_out[58]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[58]:Q,9436
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[28]:CLK,43248
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[28]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[28]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[28]:Q,43248
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[5]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[5]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[5]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[5]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[5]:Y,44829
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[10]:A,1772
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[10]:B,8794
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[10]:Y,1772
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_2:A,7493
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_2:B,7416
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_2:Y,7416
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_221:A,-1434
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_221:B,-1551
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_221:IPA,-1434
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_221:IPB,-1551
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[0]:A,875
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[0]:B,10403
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[0]:C,7148
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[0]:Y,875
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[12]:A,46861
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[12]:B,46804
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[12]:C,43272
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[12]:D,46385
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[12]:Y,43272
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_RNO[1]:A,3007
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_RNO[1]:B,2010
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_RNO[1]:C,10378
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_RNO[1]:D,10215
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_RNO[1]:Y,2010
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:CLK,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D,-212
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:Q,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[5]:CLK,9172
UART_IF_0/UART_IF_FSM_0/AXI_address[5]:D,9122
UART_IF_0/UART_IF_FSM_0/AXI_address[5]:Q,9172
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[6]:CLK,46532
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[6]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[6]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[6]:Q,46532
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[13]:A,47387
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[13]:B,47519
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[13]:Y,47387
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:A,-1537
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:B,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:C,-1986
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPA,-1537
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPB,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPC,-1986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_19:B,44790
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_19:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_19:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_19:S,44640
MDDR_Demo_top_0/AXI_IF_0/WDATA[21]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[21]:CLK,-1481
MDDR_Demo_top_0/AXI_IF_0/WDATA[21]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[21]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[21]:Q,-1481
MDDR_Demo_top_0/AXI_IF_0/BREADY:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK,-2020
MDDR_Demo_top_0/AXI_IF_0/BREADY:D,2945
MDDR_Demo_top_0/AXI_IF_0/BREADY:EN,10319
MDDR_Demo_top_0/AXI_IF_0/BREADY:Q,-2020
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[17]:CLK,47508
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[17]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[17]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[17]:Q,47508
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[1]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[1]:D,43744
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[1]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[1]:Q,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[9]:CLK,42051
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[9]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[9]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[9]:Q,42051
MDDR_Demo_top_0/AXI_IF_0/WDATA[62]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[62]:CLK,-1450
MDDR_Demo_top_0/AXI_IF_0/WDATA[62]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[62]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[62]:Q,-1450
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[45]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[45]:CLK,9992
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[45]:D,8181
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[45]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[45]:Q,9992
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIRBIU2[3]:B,9753
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIRBIU2[3]:C,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIRBIU2[3]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIRBIU2[3]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIRBIU2[3]:S,9763
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[15]:A,17
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[15]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[15]:Y,17
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[1]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[1]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[1]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[1]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNIAS7H[0]:A,43848
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNIAS7H[0]:B,46071
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNIAS7H[0]:Y,43848
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_49:A,47385
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_49:IPA,47385
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0[1]:A,41218
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0[1]:B,44273
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0[1]:Y,41218
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT,
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI71GA7[9]:B,10275
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI71GA7[9]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI71GA7[9]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI71GA7[9]:S,7850
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[4]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[4]:CLK,24841
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[4]:D,25202
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[4]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[4]:Q,24841
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[23]:A,-103
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[23]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[23]:Y,-103
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE:CLK,12563
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE:D,10092
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PENABLE:Q,12563
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:A,43120
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:B,42083
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:C,43025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:D,42764
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_39:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:A,39084
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:B,38196
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:C,40050
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:D,38859
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i:Y,38196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[12]:CLK,43025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[12]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[12]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[12]:Q,43025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[10]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[10]:B,44816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[10]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[10]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[10]:Y,40733
MDDR_Demo_top_0/AXI_IF_0/ARADDR[6]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[6]:CLK,-1431
MDDR_Demo_top_0/AXI_IF_0/ARADDR[6]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[6]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[6]:Q,-1431
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[2]:CLK,9222
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[2]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[2]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[2]:Q,9222
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:B,7847
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:C,10002
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:D,9741
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_46:S,7395
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc_q1:Q,18868
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:B,7368
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:C,9522
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:D,9261
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_16:S,7875
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_2:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_data_out[15]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[15]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[15]:D,2970
UART_IF_0/UART_IF_FSM_0/AXI_data_out[15]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[15]:Q,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[19]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[19]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[19]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[19]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[19]:Y,8813
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:A,7655
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:B,7571
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:C,7566
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:D,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:FCO,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_0_wmux:Y,7307
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_126:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_126:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[16]:A,24151
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[16]:B,24178
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[16]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[16]:D,21754
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[16]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_state:ALn,48748
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_state:CLK,47852
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_state:EN,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_state:Q,47852
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_23:B,44854
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_23:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_23:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_23:S,44576
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2:A,10335
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2:B,10334
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2:C,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2:D,9194
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2:Y,8353
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_9:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_9:IPB,
UART_IF_0/UART_IF_FSM_0/un1_fsm_37_0_0:A,10396
UART_IF_0/UART_IF_FSM_0/un1_fsm_37_0_0:B,9887
UART_IF_0/UART_IF_FSM_0/un1_fsm_37_0_0:C,10287
UART_IF_0/UART_IF_FSM_0/un1_fsm_37_0_0:Y,9887
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_30:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_30:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i:A,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i:B,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i:C,43844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i:Y,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[29]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[29]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[29]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[29]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[29]:Y,44829
TX_obuf/U0/U_IOENFF:A,
TX_obuf/U0/U_IOENFF:Y,
MDDR_Demo_top_0/AXI_IF_0/ARADDR[17]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[17]:CLK,-1448
MDDR_Demo_top_0/AXI_IF_0/ARADDR[17]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[17]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[17]:Q,-1448
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_24:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_24:IPCLKn,
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIMKE13[2]:B,10163
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIMKE13[2]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIMKE13[2]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIMKE13[2]:S,7962
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_26:C,11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_26:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_26:IPC,11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_32:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[0]:A,46902
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[0]:B,46848
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[0]:C,43313
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[0]:D,46429
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[0]:Y,43313
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_197:A,-1461
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_197:B,-1491
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_197:IPA,-1461
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_197:IPB,-1491
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:Q,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:A,16983
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:B,16906
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:C,16861
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:D,16783
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_7:Y,16783
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNISNMM6[7]:B,10243
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNISNMM6[7]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNISNMM6[7]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNISNMM6[7]:S,7882
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[5]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[5]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[5]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[5]:Q,48017
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[31]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[31]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[31]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[31]:Q,11367
UART_IF_0/UART_IF_FSM_0/fsm[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[0]:CLK,7783
UART_IF_0/UART_IF_FSM_0/fsm[0]:D,6389
UART_IF_0/UART_IF_FSM_0/fsm[0]:Q,7783
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1_RNO[0]:A,2674
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1_RNO[0]:B,10279
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1_RNO[0]:Y,2674
UART_IF_0/UART_IF_FSM_0/AXI_data_in[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[3]:CLK,9059
UART_IF_0/UART_IF_FSM_0/AXI_data_in[3]:D,11354
UART_IF_0/UART_IF_FSM_0/AXI_data_in[3]:EN,9070
UART_IF_0/UART_IF_FSM_0/AXI_data_in[3]:Q,9059
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[10]:CLK,45127
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[10]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[10]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[10]:Q,45127
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[11]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[11]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[11]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[11]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[11]:Y,45795
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[20]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[20]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[20]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[20]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[20]:Y,39098
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[7]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[7]:D,47684
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[7]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[7]:Q,46105
UART_IF_0/UART_IF_FSM_0/cnt_data[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_data[0]:CLK,8305
UART_IF_0/UART_IF_FSM_0/cnt_data[0]:D,875
UART_IF_0/UART_IF_FSM_0/cnt_data[0]:Q,8305
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_84:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_84:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:B,7672
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:C,9826
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:D,9565
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_35:S,7571
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:B,7608
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:C,9762
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:D,9501
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_31:S,7635
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_27:A,46090
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_27:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_27:Y,43758
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[2]:CLK,7665
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[2]:D,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[2]:Q,7665
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_15:A,45964
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_15:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_15:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_73:A,21485
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_73:IPA,21485
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[1]:CLK,45448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[1]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[1]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[1]:Q,45448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[3]:CLK,46484
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[3]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[3]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[3]:Q,46484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_183:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_183:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[0]:CLK,42668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[0]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[0]:Q,42668
MDDR_Demo_top_0/AXI_IF_0/AWADDR[3]:CLK,-1433
MDDR_Demo_top_0/AXI_IF_0/AWADDR[3]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[3]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[3]:Q,-1433
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[3]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[3]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[3]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[3]:Q,46058
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[2]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[2]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[2]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[2]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[0]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[0]:B,46016
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[0]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[0]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[0]:Y,40801
UART_IF_0/UART_IF_FSM_0/AXI_address[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[6]:CLK,9188
UART_IF_0/UART_IF_FSM_0/AXI_address[6]:D,9122
UART_IF_0/UART_IF_FSM_0/AXI_address[6]:Q,9188
UART_IF_0/UART_IF_FSM_0/RAM_WD[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[9]:CLK,11166
UART_IF_0/UART_IF_FSM_0/RAM_WD[9]:D,3885
UART_IF_0/UART_IF_FSM_0/RAM_WD[9]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[9]:Q,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_29:B,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_29:C,11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_29:IPB,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_29:IPC,11246
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[51]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[51]:CLK,10088
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[51]:D,8085
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[51]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[51]:Q,10088
UART_IF_0/UART_IF_FSM_0/AXI_data_in[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[5]:CLK,9085
UART_IF_0/UART_IF_FSM_0/AXI_data_in[5]:D,8013
UART_IF_0/UART_IF_FSM_0/AXI_data_in[5]:Q,9085
UART_IF_0/UART_IF_FSM_0/AXI_data_in[50]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[50]:CLK,9805
UART_IF_0/UART_IF_FSM_0/AXI_data_in[50]:D,7331
UART_IF_0/UART_IF_FSM_0/AXI_data_in[50]:Q,9805
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[31]:A,47360
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[31]:B,47492
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[31]:Y,47360
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIQ21M1[25]:A,43338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIQ21M1[25]:B,47839
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIQ21M1[25]:Y,43338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:A,45462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:B,43191
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:C,43050
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:D,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_1:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_222:A,-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_222:B,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_222:IPA,-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_222:IPB,-1478
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2_RNO:A,46880
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2_RNO:B,46844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2_RNO:Y,46844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[16]:A,39346
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[16]:B,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[16]:C,45760
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[16]:D,43791
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[16]:Y,39098
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[12]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[12]:CLK,9254
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[12]:D,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[12]:Q,9254
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[22]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[22]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[22]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[22]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[22]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[21]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[21]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[21]:C,2948
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[21]:Y,2948
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[12]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[12]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[12]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[12]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[12]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0:A,42205
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0:B,43146
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0:C,40466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0:D,41052
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0:Y,40466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[8]:CLK,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[8]:D,40196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[8]:Q,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[31]:CLK,43670
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[31]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[31]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[31]:Q,43670
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[4]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[4]:B,10420
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[4]:C,9122
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[4]:D,9729
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[4]:Y,9122
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_57:A,47393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_57:B,47338
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_57:IPA,47393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_57:IPB,47338
UART_IF_0/UART_IF_FSM_0/fsm[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[2]:CLK,7665
UART_IF_0/UART_IF_FSM_0/fsm[2]:D,8478
UART_IF_0/UART_IF_FSM_0/fsm[2]:Q,7665
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[12]:A,46780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[12]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[12]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[12]:Y,41092
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[26]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[26]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[26]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[26]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[26]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[23]:CLK,44822
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[23]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[23]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[23]:Q,44822
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:CLK,-1733
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:EN,2674
MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:Q,-1733
UART_IF_0/UART_IF_FSM_0/RAM_WD[63]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[63]:CLK,11203
UART_IF_0/UART_IF_FSM_0/RAM_WD[63]:D,3906
UART_IF_0/UART_IF_FSM_0/RAM_WD[63]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[63]:Q,11203
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO_0:A,10356
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO_0:B,2751
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO_0:C,1606
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO_0:Y,1606
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[27]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[27]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[27]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[27]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_189:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/next_state4:A,22538
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/next_state4:B,22478
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/next_state4:Y,22478
UART_IF_0/UART_IF_FSM_0/AXI_data_in[11]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[11]:CLK,9181
UART_IF_0/UART_IF_FSM_0/AXI_data_in[11]:D,7955
UART_IF_0/UART_IF_FSM_0/AXI_data_in[11]:Q,9181
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_112:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_112:IPB,
MDDR_Demo_top_0/AXI_IF_0/ARADDR[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[1]:CLK,-1432
MDDR_Demo_top_0/AXI_IF_0/ARADDR[1]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[1]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[1]:Q,-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_215:A,-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_215:IPA,-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_215:IPB,
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[2]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[2]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[2]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[2]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_230:A,-1479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_230:B,-1661
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_230:IPA,-1479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_230:IPB,-1661
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_q1:D,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG2_DONE_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/fsm_RNISOVN[19]:A,9850
UART_IF_0/UART_IF_FSM_0/fsm_RNISOVN[19]:B,10266
UART_IF_0/UART_IF_FSM_0/fsm_RNISOVN[19]:Y,9850
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[8]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[8]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[8]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[8]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[8]:Y,8813
UART_IF_0/UART_IF_FSM_0/fsm[11]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[11]:CLK,8622
UART_IF_0/UART_IF_FSM_0/fsm[11]:D,9882
UART_IF_0/UART_IF_FSM_0/fsm[11]:Q,8622
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[1]:A,10493
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[1]:B,10406
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[1]:C,10325
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[1]:Y,10325
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[21]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[21]:B,44640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[21]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[21]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[21]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[26]:CLK,44870
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[26]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[26]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[26]:Q,44870
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[2]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[2]:CLK,25186
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[2]:D,25070
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[2]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[2]:Q,25186
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL:A,20969
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL:B,20915
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL:C,20841
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL:D,8379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/MDDR_PSEL:Y,8379
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[12]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[12]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[12]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[12]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[12]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_155:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[5]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[17]:CLK,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[17]:D,47524
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[17]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[17]:Q,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:A,43104
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:B,42067
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:C,43009
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:D,42748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_33:FCO,41987
UART_IF_0/UART_IF_FSM_0/RAM_WD[45]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[45]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[45]:D,3957
UART_IF_0/UART_IF_FSM_0/RAM_WD[45]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[45]:Q,11208
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[14]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[14]:CLK,25246
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[14]:D,25097
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[14]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[14]:Q,25246
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[11]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[11]:CLK,9448
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[11]:D,8725
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[11]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[11]:Q,9448
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_27:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_27:C,11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_27:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_27:IPC,11236
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_14_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_14_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_14_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_q1:D,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_q1:Q,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:CLK,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_rcosc:Q,18663
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[26]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[26]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[26]:C,2944
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[26]:Y,2944
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_count_ddr_enable_0_sqmuxa_0_a3:A,47019
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_count_ddr_enable_0_sqmuxa_0_a3:B,46935
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_count_ddr_enable_0_sqmuxa_0_a3:Y,46935
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[14]:A,19354
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[14]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[14]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[14]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[14]:Y,8534
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_32:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_79:A,21441
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_79:IPA,21441
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_79:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[20]:CLK,42828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[20]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[20]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[20]:Q,42828
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[29]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[29]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[29]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[29]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_26:C,11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_26:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_26:IPC,11281
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[8]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[8]:CLK,24558
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[8]:D,25089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[8]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[8]:Q,24558
MDDR_Demo_top_0/AXI_IF_0/WDATA[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[1]:CLK,-1596
MDDR_Demo_top_0/AXI_IF_0/WDATA[1]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[1]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[1]:Q,-1596
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:A,46988
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:B,40228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:C,44662
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:D,46612
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI12NCA[11]:S,40148
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:CLK,21441
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:Q,21441
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[4]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[4]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[4]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[4]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_47:B,47393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_47:IPB,47393
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[11]:A,45811
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[11]:B,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[11]:C,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[11]:D,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[11]:Y,40861
UART_IF_0/UART_IF_FSM_0/AXI_data_in[31]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[31]:CLK,9501
UART_IF_0/UART_IF_FSM_0/AXI_data_in[31]:D,7635
UART_IF_0/UART_IF_FSM_0/AXI_data_in[31]:Q,9501
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[14]:CLK,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[14]:D,47572
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[14]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[14]:Q,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[29]:CLK,47500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[29]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[29]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[29]:Q,47500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[23]:A,46604
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[23]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[23]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[23]:Y,41092
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[52]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[52]:CLK,10104
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[52]:D,8069
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[52]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[52]:Q,10104
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[25]:A,46572
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[25]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[25]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[25]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_11:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[40]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[40]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[40]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[40]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[40]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[18]:CLK,42812
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[18]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[18]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[18]:Q,42812
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_i_0_o2[3]:A,8305
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_i_0_o2[3]:B,8284
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_i_0_o2[3]:C,8190
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_i_0_o2[3]:Y,8190
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[6]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[6]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[6]:D,24879
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[6]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[6]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_3:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_3:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[27]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_24:B,44870
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_24:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_24:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_24:S,44560
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_7:A,38756
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_7:B,38708
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_7:C,38634
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_7:D,38540
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_7:Y,38540
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[5]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[5]:D,47716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[5]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[5]:Q,46105
UART_IF_0/UART_IF_FSM_0/RAM_WD[60]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[60]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[60]:D,3809
UART_IF_0/UART_IF_FSM_0/RAM_WD[60]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[60]:Q,11197
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[27]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[27]:B,44544
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[27]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[27]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[27]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:B,8057
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:C,10210
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:D,9971
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_60:S,7171
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[23]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[23]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[23]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[23]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_17:A,45995
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_17:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_17:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[25]:CLK,47462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[25]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[25]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[25]:Q,47462
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:B,8870
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:C,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:D,9994
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS6P972[62]:S,7909
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_177:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_177:IPB,
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[4]:CLK,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[4]:D,9748
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[4]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[4]:Q,10196
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOINFF:Y,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_29:B,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_29:C,11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_29:IPB,11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_29:IPC,11246
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[20]:A,47375
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[20]:B,47507
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[20]:Y,47375
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[0]:A,7391
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[0]:B,657
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[0]:C,8143
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[0]:D,7783
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[0]:Y,657
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_10:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[24]:A,47175
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[24]:B,47118
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[24]:C,43586
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[24]:D,46699
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[24]:Y,43586
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[14]:CLK,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[14]:D,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[14]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[14]:Q,44678
UART_IF_0/UART_IF_FSM_0/RAM_WD[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[0]:CLK,11153
UART_IF_0/UART_IF_FSM_0/RAM_WD[0]:D,3944
UART_IF_0/UART_IF_FSM_0/RAM_WD[0]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[0]:Q,11153
UART_IF_0/UART_IF_FSM_0/AXI_data_out[38]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[38]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[38]:D,2715
UART_IF_0/UART_IF_FSM_0/AXI_data_out[38]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[38]:Q,9329
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[1]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[1]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[1]:Y,9466
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:B,7512
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:C,9666
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:D,9405
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_25:S,7731
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:B,7448
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:C,9602
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:D,9341
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_21:S,7795
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[63]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[63]:CLK,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[63]:D,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[63]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[63]:Q,10216
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[10]:A,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[10]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[10]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[10]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[10]:Y,45795
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o2_0[0]:A,8474
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o2_0[0]:B,8462
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o2_0[0]:C,7911
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o2_0[0]:D,7391
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o2_0[0]:Y,7391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[17]:CLK,42237
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[17]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[17]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[17]:Q,42237
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0:A,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0:B,39539
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0:C,40301
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0:D,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0:Y,39193
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:A,7741
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:B,7657
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:C,7652
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:D,7393
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:FCI,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:FCO,
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_2_u_i_m3_2_1_wmux_1:Y,7393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_2_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[2]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[2]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[2]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[2]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[2]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[21]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[21]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[21]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[21]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[4]:A,40260
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[4]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[4]:Y,40260
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[18]:CLK,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[18]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[18]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[18]:Q,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[0]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[0]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[0]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[0]:Y,39315
UART_IF_0/UART_IF_FSM_0/AXI_address[24]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[24]:CLK,9312
UART_IF_0/UART_IF_FSM_0/AXI_address[24]:D,-118
UART_IF_0/UART_IF_FSM_0/AXI_address[24]:Q,9312
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[0]:CLK,7592
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[0]:D,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[0]:Q,7592
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[3]:CLK,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[3]:D,9763
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[3]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[3]:Q,10196
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[3]:A,47385
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[3]:B,47517
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[3]:Y,47385
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[12]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[12]:CLK,9464
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[12]:D,8709
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[12]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[12]:Q,9464
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_0:A,39724
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_0:B,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_0:Y,39640
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[23]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[23]:CLK,9640
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[23]:D,8533
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[23]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[23]:Q,9640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[30]:CLK,44934
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[30]:D,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[30]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[30]:Q,44934
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o3:A,9539
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o3:B,9462
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o3:C,9411
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o3:D,9326
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o3:Y,9326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_5:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CLK_PAD/U_IOPADN:OIN_P,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CLK_PAD/U_IOPADN:PAD_P,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[3]:CLK,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[3]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[3]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[3]:Q,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[8]:A,46844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[8]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[8]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[8]:Y,41092
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_1:B,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_1:IPB,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_1:IPC,
UART_IF_0/COREUART_0/genblk1.RXRDY4:A,10424
UART_IF_0/COREUART_0/genblk1.RXRDY4:B,10352
UART_IF_0/COREUART_0/genblk1.RXRDY4:Y,10352
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i:A,41892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i:B,42821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i:C,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i:D,39339
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i:Y,38412
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[11]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[11]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[11]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[11]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[11]:Y,8813
UART_IF_0/UART_IF_FSM_0/fsm[15]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[15]:CLK,8352
UART_IF_0/UART_IF_FSM_0/fsm[15]:D,8277
UART_IF_0/UART_IF_FSM_0/fsm[15]:Q,8352
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[26]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[26]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[26]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[26]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[26]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[19]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[19]:B,45624
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[19]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[19]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[19]:Y,40733
UART_IF_0/UART_IF_FSM_0/un1_fsm_40_i_i_a2:A,10409
UART_IF_0/UART_IF_FSM_0/un1_fsm_40_i_i_a2:B,10339
UART_IF_0/UART_IF_FSM_0/un1_fsm_40_i_i_a2:C,10267
UART_IF_0/UART_IF_FSM_0/un1_fsm_40_i_i_a2:D,10168
UART_IF_0/UART_IF_FSM_0/un1_fsm_40_i_i_a2:Y,10168
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[8]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[8]:CLK,7985
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[8]:D,7866
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[8]:Q,7985
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[4]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[4]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[4]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[4]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[4]:Y,43758
UART_IF_0/UART_IF_FSM_0/fsm[18]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[18]:CLK,8389
UART_IF_0/UART_IF_FSM_0/fsm[18]:D,8100
UART_IF_0/UART_IF_FSM_0/fsm[18]:Q,8389
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o2:A,9397
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o2:B,8847
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o2:C,9295
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0_o2:Y,8847
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[10]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[10]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[10]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[10]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_5:B,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_5:IPB,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_5:IPC,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_27:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_27:C,11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_27:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_27:IPC,11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_15:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_15:C,11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_15:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_15:IPC,11130
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[21]:A,45025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[21]:B,46571
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[21]:C,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[21]:D,42234
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[21]:Y,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[13]:CLK,44934
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[13]:D,45711
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[13]:Q,44934
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[0]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[0]:B,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[0]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[0]:Y,39224
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO[0]:A,9958
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO[0]:B,9340
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO[0]:Y,9340
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_124:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_124:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[52]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[52]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[52]:C,2814
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[52]:Y,2814
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[1]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[1]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[1]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[1]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[1]:Y,39328
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[38]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[38]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[38]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[38]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[38]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:CLK,21956
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:D,25195
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[0]:Q,21956
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[4]:CLK,44450
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[4]:D,40635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[4]:Q,44450
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[9]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[9]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[9]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[9]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_34:A,42189
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_34:B,42085
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_34:C,42067
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_34:Y,42067
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:B,7973
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:C,9352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:D,9085
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIS2MJ5[5]:S,8821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[29]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[29]:B,44512
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[29]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[29]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[29]:Y,40733
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[2]:A,10444
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[2]:B,10396
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[2]:C,8313
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[2]:D,10288
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[2]:Y,8313
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_24:A,46076
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_24:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_24:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[2]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[2]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[2]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[2]:Q,46058
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[60]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[60]:CLK,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[60]:D,7941
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[60]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[60]:Q,10216
UART_IF_0/UART_IF_FSM_0/AXI_data_in[13]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[13]:CLK,9213
UART_IF_0/UART_IF_FSM_0/AXI_data_in[13]:D,7923
UART_IF_0/UART_IF_FSM_0/AXI_data_in[13]:Q,9213
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[14]:CLK,46651
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[14]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[14]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[14]:Q,46651
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:B,8021
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:C,9400
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:D,9133
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIAMK68[8]:S,8773
UART_IF_0/UART_IF_FSM_0/RAM_WD[49]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[49]:CLK,11204
UART_IF_0/UART_IF_FSM_0/RAM_WD[49]:D,3647
UART_IF_0/UART_IF_FSM_0/RAM_WD[49]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[49]:Q,11204
UART_IF_0/UART_IF_FSM_0/RAM_WD[36]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[36]:CLK,11218
UART_IF_0/UART_IF_FSM_0/RAM_WD[36]:D,3647
UART_IF_0/UART_IF_FSM_0/RAM_WD[36]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[36]:Q,11218
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[3]:CLK,10342
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[3]:D,9399
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[3]:Q,10342
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_35:IPB,
UART_IF_0/COREUART_0/CUARTO1I[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[0]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[0]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[0]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[0]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[58]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[58]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[58]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[58]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[58]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_77:A,21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_77:B,21419
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_77:IPA,21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_77:IPB,21419
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[17]:A,45956
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[17]:B,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[17]:C,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[17]:D,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[17]:Y,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[2]:CLK,41162
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[2]:D,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[2]:EN,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[2]:Q,41162
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[20]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[20]:CLK,9592
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[20]:D,8581
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[20]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[20]:Q,9592
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[8]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[8]:CLK,24873
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[8]:D,25197
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[8]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[8]:Q,24873
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_32:IPENn,
MDDR_Demo_top_0/AXI_IF_0/WDATA[32]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[32]:CLK,-1430
MDDR_Demo_top_0/AXI_IF_0/WDATA[32]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[32]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[32]:Q,-1430
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[1]:CLK,9405
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[1]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[1]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[1]:Q,9405
UART_IF_0/UART_IF_FSM_0/AXI_data_in[56]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[56]:CLK,9907
UART_IF_0/UART_IF_FSM_0/AXI_data_in[56]:D,7235
UART_IF_0/UART_IF_FSM_0/AXI_data_in[56]:Q,9907
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[1]:CLK,45374
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[1]:D,42455
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[1]:Q,45374
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_88:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_88:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:CLK,44774
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[20]:Q,44774
UART_IF_0/UART_IF_FSM_0/AXI_data_out[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[6]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[6]:D,3619
UART_IF_0/UART_IF_FSM_0/AXI_data_out[6]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[6]:Q,9443
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[11]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[11]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[11]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[11]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[11]:Y,43073
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2_0:A,8371
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2_0:B,8336
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2_0:C,8243
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2_0:Y,8243
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_8:A,45943
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_8:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_8:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_206:A,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_206:B,-1541
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_206:IPA,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_206:IPB,-1541
MDDR_Demo_top_0/AXI_IF_0/WDATA[16]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[16]:CLK,-1515
MDDR_Demo_top_0/AXI_IF_0/WDATA[16]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[16]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[16]:Q,-1515
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q1:CLK,23868
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q1:D,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q1:Q,23868
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_20:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_20:IPC,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_5:B,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_5:IPB,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_5:IPC,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[33]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[33]:CLK,9533
UART_IF_0/UART_IF_FSM_0/AXI_data_in[33]:D,7603
UART_IF_0/UART_IF_FSM_0/AXI_data_in[33]:Q,9533
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[28]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[28]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[28]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[28]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_4:C,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_4:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_4:IPC,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_5:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[29]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[3]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[3]:D,4031
UART_IF_0/UART_IF_FSM_0/AXI_data_out[3]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[3]:Q,9443
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[3]:A,45946
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[3]:B,45031
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[3]:C,44864
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[3]:D,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[3]:Y,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1[1]:A,40767
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1[1]:B,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_1[1]:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[11]:B,17792
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[11]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[11]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[11]:S,17642
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[8]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[8]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[8]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[8]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA[9]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[9]:CLK,-1450
MDDR_Demo_top_0/AXI_IF_0/WDATA[9]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[9]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[9]:Q,-1450
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[8]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[8]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[8]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[8]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[8]:Y,43073
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_54:A,47364
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_54:B,47359
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_54:IPA,47364
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_54:IPB,47359
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_13:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_13:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_11:B,44662
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_11:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_11:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_11:S,44896
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[1]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[1]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[1]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[1]:Q,10426
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:B,8565
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:C,9944
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:D,9677
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOF3OF1[42]:S,8229
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_269:A,-1487
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_269:B,-1933
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_269:IPA,-1487
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_269:IPB,-1933
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[0]:A,40238
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[0]:B,45596
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[0]:C,43740
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0[0]:Y,40238
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[31]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[31]:B,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[31]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[31]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[31]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:CLK,21447
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:Q,21447
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[45]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[45]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[45]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[45]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[45]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_1_1:A,45127
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_1_1:B,45043
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_1_1:C,45011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_1_1:Y,45011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[12]:CLK,47515
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[12]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[12]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[12]:Q,47515
MDDR_Demo_top_0/AXI_IF_0/ARADDR[24]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[24]:CLK,-1685
MDDR_Demo_top_0/AXI_IF_0/ARADDR[24]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[24]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[24]:Q,-1685
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[45]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[45]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[45]:C,2979
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[45]:Y,2979
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_270:A,-1476
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_270:B,-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_270:IPA,-1476
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_270:IPB,-1563
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_33:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_33:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[7]:A,19417
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[7]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[7]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[7]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[7]:Y,8534
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[47]:A,10510
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[47]:B,9926
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[47]:C,9677
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[47]:D,2020
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[47]:Y,2020
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[27]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[27]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[27]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[27]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[12]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[12]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[12]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[12]:Y,39224
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:B,7907
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:C,10066
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:D,9805
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_50:S,7331
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[27]:CLK,46713
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[27]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[27]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[27]:Q,46713
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[32]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[32]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[32]:C,2888
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[32]:Y,2888
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIKQ7D4[3]:B,7834
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIKQ7D4[3]:C,10136
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIKQ7D4[3]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIKQ7D4[3]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIKQ7D4[3]:S,7946
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_21:B,43706
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_21:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_21:IPB,43706
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_66:A,47384
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_66:B,21495
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_66:IPA,47384
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_66:IPB,21495
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[16]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[16]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[16]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[16]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[16]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_237:A,-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_237:B,-1593
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_237:IPA,-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_237:IPB,-1593
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[28]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[28]:B,45480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[28]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[28]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[28]:Y,40733
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[1]:CLK,8506
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[1]:D,9786
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[1]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[1]:Q,8506
UART_IF_0/UART_IF_FSM_0/AXI_data_out[61]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[61]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[61]:D,2902
UART_IF_0/UART_IF_FSM_0/AXI_data_out[61]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[61]:Q,9436
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_9:B,44630
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_9:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_9:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_9:S,44928
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[14]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[14]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[14]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[14]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0_a3_0[2]:A,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0_a3_0[2]:B,46891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0_a3_0[2]:Y,41457
UART_IF_0/UART_IF_FSM_0/AXI_data_out[11]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[11]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[11]:D,2978
UART_IF_0/UART_IF_FSM_0/AXI_data_out[11]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[11]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[14]:A,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[14]:B,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[14]:C,46594
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[14]:D,42391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[14]:Y,38412
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[6]:CLK,6569
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[6]:D,9718
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[6]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[6]:Q,6569
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_1:A,43024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_1:B,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_1:C,42929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_1:D,42668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_1:FCO,41987
UART_IF_0/UART_IF_FSM_0/rx_en:ALn,3352
UART_IF_0/UART_IF_FSM_0/rx_en:CLK,6129
UART_IF_0/UART_IF_FSM_0/rx_en:D,8428
UART_IF_0/UART_IF_FSM_0/rx_en:EN,10168
UART_IF_0/UART_IF_FSM_0/rx_en:Q,6129
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_a6_1[1]:A,46969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_a6_1[1]:B,45024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_a6_1[1]:C,46870
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_a6_1[1]:Y,45024
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK,45305
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:D,44529
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:Q,45305
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[2]:B,17648
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[2]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[2]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[2]:S,17786
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[27]:CLK,44886
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[27]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[27]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[27]:Q,44886
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[30]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[30]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[30]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[30]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_out[45]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[45]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[45]:D,2979
UART_IF_0/UART_IF_FSM_0/AXI_data_out[45]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[45]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_44:A,43181
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_44:B,46942
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_44:IPA,43181
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_44:IPB,46942
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[0]:A,42280
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[0]:B,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[0]:C,47776
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[0]:D,45809
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[0]:Y,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[5]:CLK,44178
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[5]:D,42327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[5]:Q,44178
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[0]:A,7465
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[0]:B,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[0]:C,9876
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[0]:D,7250
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[0]:Y,6389
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[28]:CLK,47465
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[28]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[28]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[28]:Q,47465
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[13]:A,46668
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[13]:B,46611
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[13]:C,43079
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[13]:D,46192
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[13]:Y,43079
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwrite:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwrite:CLK,24893
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwrite:D,25164
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwrite:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwrite:Q,24893
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_8:A,38829
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_8:B,38752
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_8:C,38678
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_8:D,37644
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_8:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[5]:CLK,44534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[5]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[5]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[5]:Q,44534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[13]:A,46011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[13]:B,44896
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[13]:C,44929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[13]:D,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[13]:Y,40861
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0:YNn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_14:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_14:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_14:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[62]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[62]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[62]:C,2780
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[62]:Y,2780
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_201:A,-1493
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_201:B,-1590
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_201:IPA,-1493
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_201:IPB,-1590
MDDR_Demo_top_0/AXI_IF_0/WDATA[14]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[14]:CLK,-1450
MDDR_Demo_top_0/AXI_IF_0/WDATA[14]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[14]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[14]:Q,-1450
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_20:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_20:IPC,
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIJ2S73[4]:B,9721
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIJ2S73[4]:C,10158
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIJ2S73[4]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIJ2S73[4]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIJ2S73[4]:S,9748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[4]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[4]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[4]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[4]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[4]:Y,39328
UART_IF_0/UART_IF_FSM_0/OEN:ALn,3352
UART_IF_0/UART_IF_FSM_0/OEN:CLK,10430
UART_IF_0/UART_IF_FSM_0/OEN:D,9011
UART_IF_0/UART_IF_FSM_0/OEN:EN,8847
UART_IF_0/UART_IF_FSM_0/OEN:Q,10430
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[30]:A,-212
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[30]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[30]:Y,-212
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:CLK,16868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:D,17722
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[6]:Q,16868
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[4]:CLK,46500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[4]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[4]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[4]:Q,46500
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:B,9204
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:C,9161
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:D,7678
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITC5CA[7]:S,17
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[2]:A,10490
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[2]:B,10413
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[2]:C,8478
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[2]:D,9739
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[2]:Y,8478
UART_IF_0/UART_IF_FSM_0/AXI_data_out[16]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[16]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[16]:D,1953
UART_IF_0/UART_IF_FSM_0/AXI_data_out[16]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[16]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ODT_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ODT_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ODT_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:CLK,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:EN,16636
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled:Q,4897
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNI1ASM5[8]:B,10292
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNI1ASM5[8]:C,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNI1ASM5[8]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNI1ASM5[8]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNI1ASM5[8]:S,9626
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:A,43216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:B,42179
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:C,43121
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:D,42860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_69:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[2]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[2]:B,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[2]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[2]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[2]:Y,40801
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_34:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_147:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_147:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_26:B,44902
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_26:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_26:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_26:S,44528
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[11]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[11]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[11]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[11]:Y,40377
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:B,7997
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:C,10162
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:D,9907
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_56:S,7235
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[20]:CLK,47507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[20]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[20]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[20]:Q,47507
MDDR_Demo_top_0/AXI_IF_0/WDATA[10]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[10]:CLK,-1488
MDDR_Demo_top_0/AXI_IF_0/WDATA[10]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[10]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[10]:Q,-1488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_234:A,-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_234:B,-1784
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_234:IPA,-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_234:IPB,-1784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:A,43200
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:B,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:C,43105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:D,42844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_21:FCO,41987
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:B,8741
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:C,10120
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:D,9853
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIST9MS1[53]:S,8053
MDDR_Demo_top_0/AXI_IF_0/WDATA[13]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[13]:CLK,-1494
MDDR_Demo_top_0/AXI_IF_0/WDATA[13]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[13]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[13]:Q,-1494
UART_IF_0/COREUART_0/CUARTOO1/CUARTll_0_o3:A,8111
UART_IF_0/COREUART_0/CUARTOO1/CUARTll_0_o3:B,8152
UART_IF_0/COREUART_0/CUARTOO1/CUARTll_0_o3:Y,8111
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[30]:A,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[30]:B,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[30]:C,45833
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[30]:Y,45780
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_25:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[11]:A,48010
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[11]:B,47920
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[11]:C,47876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[11]:D,43177
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[11]:Y,43177
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:A,43136
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:B,42099
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:C,43041
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:D,42780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_27:FCO,41987
UART_IF_0/UART_IF_FSM_0/DATA_OUT[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[1]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[1]:D,7345
UART_IF_0/UART_IF_FSM_0/DATA_OUT[1]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[1]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_106:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[2]:A,47795
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[2]:B,47906
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[2]:C,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[2]:D,43177
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[2]:Y,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i_o2:A,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i_o2:B,44625
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_1_sqmuxa_3_i_o2:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20:A,38668
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20:B,37644
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20:C,38540
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20:Y,37644
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_18:C,11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_18:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_18:IPC,11353
UART_IF_0/UART_IF_FSM_0/AXI_address[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[8]:CLK,9049
UART_IF_0/UART_IF_FSM_0/AXI_address[8]:D,122
UART_IF_0/UART_IF_FSM_0/AXI_address[8]:Q,9049
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_35:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q1:Q,48867
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[22]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[22]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[22]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[22]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_125:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_125:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[1]:CLK,41108
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[1]:D,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[1]:EN,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[1]:Q,41108
UART_IF_0/UART_IF_FSM_0/cnt_1k[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[8]:CLK,8436
UART_IF_0/UART_IF_FSM_0/cnt_1k[8]:D,9626
UART_IF_0/UART_IF_FSM_0/cnt_1k[8]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[8]:Q,8436
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_7:A,8273
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_7:B,8225
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_7:C,8151
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_7:D,8057
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_7:Y,8057
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[23]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[23]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[23]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[23]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[23]:Y,39157
UART_IF_0/UART_IF_FSM_0/AXI_data_in[18]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[18]:CLK,9293
UART_IF_0/UART_IF_FSM_0/AXI_data_in[18]:D,7843
UART_IF_0/UART_IF_FSM_0/AXI_data_in[18]:Q,9293
UART_IF_0/UART_IF_FSM_0/AXI_data_out[25]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[25]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[25]:D,2973
UART_IF_0/UART_IF_FSM_0/AXI_data_out[25]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[25]:Q,9329
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[49]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[49]:CLK,10056
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[49]:D,8117
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[49]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[49]:Q,10056
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:D,2838
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_q1:Q,18868
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[8]:CLK,47496
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[8]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[8]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[8]:Q,47496
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0_o3:A,8409
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0_o3:B,7409
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0_o3:C,8362
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0_o3:Y,7409
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[17]:CLK,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[17]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[17]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[17]:Q,46775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[8]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[20]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[20]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[20]:C,2926
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[20]:Y,2926
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNO[7]:B,9786
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNO[7]:C,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNO[7]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNO[7]:S,9703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_4:A,44773
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_4:B,43629
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_4:C,42573
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_4:D,42459
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_4:Y,42459
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[16]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[16]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[16]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[16]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[16]:Y,39098
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:B,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:C,9272
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:D,9011
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:FCI,9257
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI21F91[0]:S,8870
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[6]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[6]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[6]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[6]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[6]:Q,10426
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_8:C,10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_8:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_8:IPC,10940
UART_IF_0/UART_IF_FSM_0/AXI_data_in[51]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[51]:CLK,9821
UART_IF_0/UART_IF_FSM_0/AXI_data_in[51]:D,7315
UART_IF_0/UART_IF_FSM_0/AXI_data_in[51]:Q,9821
UART_IF_0/UART_IF_FSM_0/RAM_WD[42]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[42]:CLK,11217
UART_IF_0/UART_IF_FSM_0/RAM_WD[42]:D,3680
UART_IF_0/UART_IF_FSM_0/RAM_WD[42]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[42]:Q,11217
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[23]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[23]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[23]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[23]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[23]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/WDATA[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[0]:CLK,-1403
MDDR_Demo_top_0/AXI_IF_0/WDATA[0]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[0]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[0]:Q,-1403
MDDR_Demo_top_0/AXI_IF_0/WDATA[51]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[51]:CLK,-1469
MDDR_Demo_top_0/AXI_IF_0/WDATA[51]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[51]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[51]:Q,-1469
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[8]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[8]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[8]:D,25197
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[8]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[8]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[11]:CLK,42085
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[11]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[11]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[11]:Q,42085
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[4]:A,46011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[4]:B,45040
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[4]:C,44929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[4]:D,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[4]:Y,40861
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[5]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[5]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[5]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[5]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep:CLK,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep:EN,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep:Q,
UART_IF_0/UART_IF_FSM_0/fsm[19]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[19]:CLK,10266
UART_IF_0/UART_IF_FSM_0/fsm[19]:D,7320
UART_IF_0/UART_IF_FSM_0/fsm[19]:Q,10266
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP11M1[24]:A,43344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP11M1[24]:B,47825
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP11M1[24]:Y,43344
UART_IF_0/UART_IF_FSM_0/AXI_data_in[38]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[38]:CLK,9613
UART_IF_0/UART_IF_FSM_0/AXI_data_in[38]:D,7523
UART_IF_0/UART_IF_FSM_0/AXI_data_in[38]:Q,9613
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_32:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_32:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_152:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_152:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_255:A,-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_255:B,-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_255:IPA,-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_255:IPB,-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_202:A,-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_202:B,-1491
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_202:IPA,-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_202:IPB,-1491
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[31]:CLK,47492
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[31]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[31]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[31]:Q,47492
UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0:A,1388
UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0:B,9886
UART_IF_0/UART_IF_FSM_0/un1_fsm_34_0_0:Y,1388
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/FIC_2_APB_M_PRESET_N_keep_RNI58GF/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/FIC_2_APB_M_PRESET_N_keep_RNI58GF/U0:YNn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[6]:A,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[6]:B,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[6]:C,45833
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[6]:Y,45780
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[3]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[3]:CLK,9320
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[3]:D,8853
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[3]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[3]:Q,9320
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:A,45976
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:B,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:Y,45976
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_11:EN,11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_11:IPENn,11442
UART_IF_0/UART_IF_FSM_0/fsm[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[7]:CLK,9312
UART_IF_0/UART_IF_FSM_0/fsm[7]:D,10382
UART_IF_0/UART_IF_FSM_0/fsm[7]:Q,9312
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_31:A,43216
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_31:B,43154
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_31:IPA,43216
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_31:IPB,43154
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_18:B,44774
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_18:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_18:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_18:S,44656
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[13]:CLK,44662
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[13]:D,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[13]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[13]:Q,44662
MDDR_Demo_top_0/AXI_IF_0/WDATA[4]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[4]:CLK,-1548
MDDR_Demo_top_0/AXI_IF_0/WDATA[4]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[4]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[4]:Q,-1548
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[1]:CLK,8196
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[1]:D,7947
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[1]:Q,8196
MDDR_Demo_top_0/AXI_IF_0/WDATA[46]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[46]:CLK,-1551
MDDR_Demo_top_0/AXI_IF_0/WDATA[46]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[46]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[46]:Q,-1551
MDDR_Demo_top_0/AXI_IF_0/ARADDR[28]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[28]:CLK,-1475
MDDR_Demo_top_0/AXI_IF_0/ARADDR[28]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[28]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[28]:Q,-1475
UART_IF_0/UART_IF_FSM_0/AXI_data_out[60]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[60]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[60]:D,2831
UART_IF_0/UART_IF_FSM_0/AXI_data_out[60]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[60]:Q,9436
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_74:A,21464
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_74:IPA,21464
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD[0]:B,9310
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD[0]:C,9257
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD[0]:FCO,9257
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_12:C,11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_12:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_12:IPC,11143
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[1]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[1]:B,45994
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[1]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[1]:D,44733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[1]:Y,40801
UART_IF_0/UART_IF_FSM_0/AXI_data_out[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[10]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[10]:D,2930
UART_IF_0/UART_IF_FSM_0/AXI_data_out[10]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[10]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[9]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[9]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[9]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[9]:Y,40377
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[6]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[6]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[6]:Y,9466
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI2L8H[0]:A,43727
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI2L8H[0]:B,45915
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI2L8H[0]:Y,43727
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[22]:CLK,43200
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[22]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[22]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[22]:Q,43200
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[16]:A,46716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[16]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[16]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[16]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK,21424
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:D,23704
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN,8379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:Q,21424
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:CLK,46957
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:Q,46957
MDDR_Demo_top_0/AXI_IF_0/WLAST:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WLAST:CLK,-1445
MDDR_Demo_top_0/AXI_IF_0/WLAST:D,739
MDDR_Demo_top_0/AXI_IF_0/WLAST:EN,1495
MDDR_Demo_top_0/AXI_IF_0/WLAST:Q,-1445
UART_IF_0/UART_IF_FSM_0/RAM_WD[27]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[27]:CLK,11184
UART_IF_0/UART_IF_FSM_0/RAM_WD[27]:D,3787
UART_IF_0/UART_IF_FSM_0/RAM_WD[27]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[27]:Q,11184
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI7V9L2[3]:B,9705
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI7V9L2[3]:C,10142
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI7V9L2[3]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI7V9L2[3]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI7V9L2[3]:S,9763
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:B,8117
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:C,9496
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:D,9229
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI2TDTE[14]:S,8677
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[1]:A,9094
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[1]:B,2668
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[1]:C,10309
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[1]:D,10248
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_0[1]:Y,2668
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:A,43184
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:B,42147
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:C,43089
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:D,42828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_63:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[16]:CLK,44710
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[16]:D,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[16]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[16]:Q,44710
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI9RJT[0]:B,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI9RJT[0]:C,10087
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI9RJT[0]:FCI,9658
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI9RJT[0]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNI9RJT[0]:S,9786
UART_IF_0/UART_IF_FSM_0/AXI_data_out[57]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[57]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[57]:D,2866
UART_IF_0/UART_IF_FSM_0/AXI_data_out[57]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[57]:Q,9436
UART_IF_0/UART_IF_FSM_0/AXI_address[22]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[22]:CLK,9273
UART_IF_0/UART_IF_FSM_0/AXI_address[22]:D,-88
UART_IF_0/UART_IF_FSM_0/AXI_address[22]:Q,9273
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[27]:CLK,42213
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[27]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[27]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[27]:Q,42213
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0:A,39339
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0:B,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0:Y,39339
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[26]:CLK,47499
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[26]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[26]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[26]:Q,47499
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:CLK,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:Q,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[17]:SLn,45312
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_1_0[15]:A,9536
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_1_0[15]:B,9466
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_1_0[15]:Y,9466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_15:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_15:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_31:B,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_31:IPB,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_31:IPC,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_0_sqmuxa_0_a4_0_a2:A,8562
UART_IF_0/UART_IF_FSM_0/AXI_data_in_0_sqmuxa_0_a4_0_a2:B,8498
UART_IF_0/UART_IF_FSM_0/AXI_data_in_0_sqmuxa_0_a4_0_a2:Y,8498
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[13]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[13]:CLK,10271
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[13]:D,25201
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[13]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[13]:Q,10271
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_29:IPENn,
UART_IF_0/UART_IF_FSM_0/cnt_1k[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[3]:CLK,7250
UART_IF_0/UART_IF_FSM_0/cnt_1k[3]:D,9701
UART_IF_0/UART_IF_FSM_0/cnt_1k[3]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[3]:Q,7250
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_6:A,45985
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_6:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_6:Y,43758
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_1[3]:A,9536
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_1[3]:B,9452
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_1[3]:C,9381
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_1[3]:D,9310
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_1[3]:Y,9310
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[16]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[16]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[16]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[16]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[16]:Y,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[29]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[29]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[29]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[29]:Q,45970
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_32:IPENn,
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[0]:A,10504
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[0]:B,10426
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[0]:C,9348
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[0]:D,9792
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[0]:Y,9348
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST:A,46002
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST:B,43744
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST:Y,43744
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep:ALn,48748
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep:D,47875
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_rep:Q,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[1]:CLK,42029
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[1]:D,40358
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count[1]:Q,42029
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[33]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[33]:CLK,9800
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[33]:D,8373
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[33]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[33]:Q,9800
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:B,9092
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:C,9049
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:D,7566
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNITSO43[0]:S,122
UART_IF_0/UART_IF_FSM_0/WLEN_1[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/WLEN_1[0]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WLEN_1[0]:D,9340
UART_IF_0/UART_IF_FSM_0/WLEN_1[0]:EN,9916
UART_IF_0/UART_IF_FSM_0/WLEN_1[0]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_58:B,47356
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_58:IPB,47356
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:A,-1505
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:B,-1630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:C,-1885
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPA,-1505
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPB,-1630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPC,-1885
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[10]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[10]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[10]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[10]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[10]:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:B,7784
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:C,9938
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:D,9677
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_42:S,7459
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0_0:A,43146
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0_0:B,46748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0_0:C,44885
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_5_0_0:Y,43146
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:B,7304
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:C,9458
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:D,9197
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_12:S,7939
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_160:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_160:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[5]:CLK,46516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[5]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[5]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[5]:Q,46516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[20]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[20]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[20]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[20]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[20]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_1:A,45691
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_1:B,45643
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_1:C,45374
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_1:D,44178
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_1:Y,44178
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0[1]:A,22854
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0[1]:B,8450
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0[1]:C,22870
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0[1]:Y,8450
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[30]:A,46492
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[30]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[30]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[30]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_277:A,24757
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_277:B,24841
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_277:IPA,24757
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_277:IPB,24841
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_s_1_243:B,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_s_1_243:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2[5]:A,42606
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2[5]:B,39718
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2[5]:C,42491
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2[5]:Y,39718
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[25]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[25]:CLK,9672
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[25]:D,8501
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[25]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[25]:Q,9672
MDDR_Demo_top_0/AXI_IF_0/ARADDR[13]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[13]:CLK,-1471
MDDR_Demo_top_0/AXI_IF_0/ARADDR[13]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[13]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[13]:Q,-1471
MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:CLK,-1784
MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[44]:Q,-1784
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3_RNIMH5N:A,43736
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3_RNIMH5N:B,43093
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3_RNIMH5N:C,46530
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3_RNIMH5N:D,45290
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3_RNIMH5N:Y,43093
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[0]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[0]:CLK,16636
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[0]:D,17974
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[0]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[0]:Q,16636
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[31]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[31]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[31]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[31]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[31]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:A,-1475
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPA,-1475
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[24]:A,46588
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[24]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[24]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[24]:Y,41092
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:B,8789
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:C,10168
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:D,9907
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISUC702[56]:S,8005
MDDR_Demo_top_0/AXI_IF_0/WDATA[22]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[22]:CLK,-1538
MDDR_Demo_top_0/AXI_IF_0/WDATA[22]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[22]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[22]:Q,-1538
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK,47916
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/CONFIG1_DONE_clk_base:Q,47916
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[4]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[4]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[4]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[4]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc_q1:Q,18868
MDDR_Demo_top_0/AXI_IF_0/WDATA[40]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[40]:CLK,-1661
MDDR_Demo_top_0/AXI_IF_0/WDATA[40]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[40]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[40]:Q,-1661
UART_IF_0/UART_IF_FSM_0/option[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/option[2]:CLK,8720
UART_IF_0/UART_IF_FSM_0/option[2]:D,8313
UART_IF_0/UART_IF_FSM_0/option[2]:EN,10779
UART_IF_0/UART_IF_FSM_0/option[2]:Q,8720
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[27]:CLK,42266
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[27]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[27]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[27]:Q,42266
MDDR_Demo_top_0/AXI_IF_0/WDATA[43]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[43]:CLK,-1558
MDDR_Demo_top_0/AXI_IF_0/WDATA[43]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[43]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[43]:Q,-1558
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[15]:CLK,42117
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[15]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[15]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[15]:Q,42117
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[3]:A,10454
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[3]:B,9310
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[3]:C,2779
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[3]:D,1666
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[3]:Y,1666
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_7:B,44598
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_7:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_7:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_7:S,44832
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[2]:CLK,10180
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[2]:D,9778
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[2]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[2]:Q,10180
UART_IF_0/UART_IF_FSM_0/AXI_address[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[0]:CLK,9092
UART_IF_0/UART_IF_FSM_0/AXI_address[0]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address[0]:Q,9092
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[16]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[16]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[16]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[16]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_48:A,47421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_48:IPA,47421
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_25:B,44886
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_25:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_25:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_25:S,44544
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_a3_0_a2[1]:A,9964
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_a3_0_a2[1]:B,10420
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_a3_0_a2[1]:Y,9964
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[4]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[4]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[4]:D,25202
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[4]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[4]:Q,21888
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[30]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[30]:CLK,9752
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[30]:D,8421
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[30]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[30]:Q,9752
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_213:A,-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_213:IPA,-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_213:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[24]:CLK,47518
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[24]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[24]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[24]:Q,47518
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[3]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[3]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[3]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[3]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[3]:Y,39315
UART_IF_0/UART_IF_FSM_0/AXI_data_in[53]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[53]:CLK,9853
UART_IF_0/UART_IF_FSM_0/AXI_data_in[53]:D,7283
UART_IF_0/UART_IF_FSM_0/AXI_data_in[53]:Q,9853
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_13:B,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_13:C,11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_13:IPB,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_13:IPC,11147
UART_IF_0/UART_IF_FSM_0/RAM_WD[57]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[57]:CLK,11203
UART_IF_0/UART_IF_FSM_0/RAM_WD[57]:D,3844
UART_IF_0/UART_IF_FSM_0/RAM_WD[57]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[57]:Q,11203
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[14]:CLK,44599
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[14]:D,40500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[14]:Q,44599
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_274:A,-1420
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_274:B,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_274:IPA,-1420
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_274:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[4]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[4]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[4]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[4]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[23]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[23]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[23]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[23]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK,37721
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:Q,37721
MDDR_Demo_top_0/AXI_IF_0/AXI_WBUSY:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/AXI_WBUSY:CLK,9226
MDDR_Demo_top_0/AXI_IF_0/AXI_WBUSY:D,9944
MDDR_Demo_top_0/AXI_IF_0/AXI_WBUSY:EN,2782
MDDR_Demo_top_0/AXI_IF_0/AXI_WBUSY:Q,9226
UART_IF_0/UART_IF_FSM_0/AXI_data_in[47]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[47]:CLK,9757
UART_IF_0/UART_IF_FSM_0/AXI_data_in[47]:D,7379
UART_IF_0/UART_IF_FSM_0/AXI_data_in[47]:Q,9757
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[5]:A,46892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[5]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[5]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[5]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4_RNI0GKM[5]:A,43761
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4_RNI0GKM[5]:B,40096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4_RNI0GKM[5]:C,43740
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4_RNI0GKM[5]:Y,40096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_64:A,42269
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_64:B,42165
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_64:C,42147
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_64:Y,42147
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[29]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[29]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[29]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[29]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[29]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[17]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[17]:B,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[17]:C,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[17]:Y,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[28]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[28]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[28]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[28]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[28]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[3]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[3]:B,10420
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[3]:C,9122
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[3]:D,9729
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[3]:Y,9122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n4_i_m2:A,47997
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n4_i_m2:B,47920
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n4_i_m2:C,46887
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n4_i_m2:D,46735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n4_i_m2:Y,46735
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_187:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[26]:CLK,47020
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[26]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[26]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[26]:Q,47020
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_104:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_104:IPB,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:B,8869
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:C,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:D,9987
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0U0462[61]:S,7925
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[3]:A,9431
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[3]:B,10376
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[3]:C,8232
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[3]:D,8247
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[3]:Y,8232
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[15]:A,46754
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[15]:B,46697
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[15]:C,43165
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[15]:D,46278
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[15]:Y,43165
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_clk_base:CLK,45991
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_clk_base:Q,45991
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_33:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_33:IPC,
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[14]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[14]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[14]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[14]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[18]:CLK,46718
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[18]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[18]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[18]:Q,46718
UART_IF_0/UART_IF_FSM_0/un1_fsm_41_0_0:A,10396
UART_IF_0/UART_IF_FSM_0/un1_fsm_41_0_0:B,9416
UART_IF_0/UART_IF_FSM_0/un1_fsm_41_0_0:C,9794
UART_IF_0/UART_IF_FSM_0/un1_fsm_41_0_0:D,8852
UART_IF_0/UART_IF_FSM_0/un1_fsm_41_0_0:Y,8852
MDDR_Demo_top_0/AXI_IF_0/WDATA[60]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[60]:CLK,-1616
MDDR_Demo_top_0/AXI_IF_0/WDATA[60]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[60]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[60]:Q,-1616
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[5]:CLK,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[5]:D,9733
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[5]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[5]:Q,10196
MDDR_Demo_top_0/AXI_IF_0/WDATA[63]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[63]:CLK,-1649
MDDR_Demo_top_0/AXI_IF_0/WDATA[63]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[63]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[63]:Q,-1649
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:B,7941
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:C,9320
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:D,9059
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIILCS3[3]:S,8853
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_17:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_17:IPC,
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[10]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[10]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[10]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[10]:Q,11367
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[7]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[7]:CLK,7903
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[7]:D,7882
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[7]:Q,7903
UART_IF_0/UART_IF_FSM_0/OEN_1_0_0_0:A,9011
UART_IF_0/UART_IF_FSM_0/OEN_1_0_0_0:B,10390
UART_IF_0/UART_IF_FSM_0/OEN_1_0_0_0:Y,9011
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:A,24208
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:B,24078
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:C,22905
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:D,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg5:Y,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_rcosc:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_rcosc:CLK,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable_rcosc:Q,18707
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[21]:A,-73
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[21]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[21]:Y,-73
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_118:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[1]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[1]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[1]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[1]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[1]:Y,39315
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[1]:CLK,7375
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[1]:D,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[1]:Q,7375
UART_IF_0/UART_IF_FSM_0/AXI_address[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[2]:CLK,9124
UART_IF_0/UART_IF_FSM_0/AXI_address[2]:D,9028
UART_IF_0/UART_IF_FSM_0/AXI_address[2]:Q,9124
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[19]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[5]:A,47368
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[5]:B,47500
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[5]:Y,47368
MDDR_Demo_top_0/AXI_IF_0/AWADDR[8]:CLK,-1472
MDDR_Demo_top_0/AXI_IF_0/AWADDR[8]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[8]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[8]:Q,-1472
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[17]:A,46832
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[17]:B,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[17]:C,43243
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[17]:D,46356
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[17]:Y,43243
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[11]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[11]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[11]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[11]:Q,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[15]:A,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[15]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[15]:Y,40084
MDDR_Demo_top_0/AXI_IF_0/ARADDR[27]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[27]:CLK,-1586
MDDR_Demo_top_0/AXI_IF_0/ARADDR[27]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[27]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[27]:Q,-1586
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep_RNI4KI6/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep_RNI4KI6/U0_RGB1:YL,3352
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[10]:CLK,42748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[10]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[10]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[10]:Q,42748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[16]:CLK,45538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[16]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[16]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[16]:Q,45538
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[8]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[8]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[8]:C,2909
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[8]:Y,2909
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_30:B,45912
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_30:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_30:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_30:S,46338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[13]:A,46764
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[13]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[13]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[13]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[10]:CLK,44614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[10]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[10]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[10]:Q,44614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[15]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[15]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[15]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[15]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[15]:A,46732
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[15]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[15]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[15]:Y,41092
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:B,8469
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:C,9848
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:D,9581
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGOGM81[36]:S,8325
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:B,8373
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:C,9752
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:D,9485
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQP4L11[30]:S,8421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_9_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_9_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_9_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/AWADDR[6]:CLK,-1472
MDDR_Demo_top_0/AXI_IF_0/AWADDR[6]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[6]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[6]:Q,-1472
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[3]:CLK,42021
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[3]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[3]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[3]:Q,42021
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[20]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[44]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[44]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[44]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[44]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[44]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[16]:A,45956
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[16]:B,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[16]:C,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[16]:D,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[16]:Y,44821
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[23]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[23]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[23]:C,2814
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[23]:Y,2814
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_34:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[27]:CLK,42195
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[27]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[27]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[27]:Q,42195
UART_IF_0/UART_IF_FSM_0/RAM_WD[33]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[33]:CLK,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[33]:D,3995
UART_IF_0/UART_IF_FSM_0/RAM_WD[33]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[33]:Q,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[2]:CLK,11153
UART_IF_0/UART_IF_FSM_0/RAM_WD[2]:D,3791
UART_IF_0/UART_IF_FSM_0/RAM_WD[2]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[2]:Q,11153
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[19]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[19]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[19]:C,3031
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[19]:Y,3031
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_30:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_25:A,43412
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_25:IPA,43412
UART_IF_0/UART_IF_FSM_0/AXI_data_out[41]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[41]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[41]:D,2576
UART_IF_0/UART_IF_FSM_0/AXI_data_out[41]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[41]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_236:A,-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_236:B,-1551
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_236:IPA,-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_236:IPB,-1551
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:A,43485
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:B,39718
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:C,38871
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2_0_a2[2]:Y,38871
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:B,9380
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:C,9344
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:D,7854
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIE5KSM[26]:S,-148
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_i_0_a2_0[3]:A,9366
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_i_0_a2_0[3]:B,9248
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_i_0_a2_0[3]:C,8190
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_i_0_a2_0[3]:D,8111
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_i_0_a2_0[3]:Y,8111
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_a2_0:A,9220
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_a2_0:B,9170
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_a2_0:Y,9170
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[0]:CLK,7405
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[0]:D,7464
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[0]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTll0[0]:Q,7405
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:CLK,21441
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:Q,21441
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[1]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[1]:CLK,10092
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[1]:D,8450
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[1]:Q,10092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_24:B,45816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_24:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_24:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_24:S,45544
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:B,7240
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:C,9400
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:D,9133
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_8:S,8003
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[30]:CLK,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[30]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[30]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[30]:Q,47025
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:B,7892
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:C,10050
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:D,9789
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_49:S,7347
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOINFF:Y,
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[26]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[26]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[26]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[26]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/ARLEN_0_sqmuxa_0_a2:A,3986
MDDR_Demo_top_0/AXI_IF_0/ARLEN_0_sqmuxa_0_a2:B,10332
MDDR_Demo_top_0/AXI_IF_0/ARLEN_0_sqmuxa_0_a2:C,10260
MDDR_Demo_top_0/AXI_IF_0/ARLEN_0_sqmuxa_0_a2:Y,3986
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:B,7416
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:C,9570
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:D,9309
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_19:S,7827
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[5]:CLK,42037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[5]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[5]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[5]:Q,42037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[7]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[7]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[7]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[7]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[7]:Y,39328
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK,47919
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/RESET_N_M2F_clk_base:Q,47919
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:A,46860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:B,40100
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:C,44534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:D,46484
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDJ4Q3[3]:S,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[0]:CLK,47799
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[0]:EN,43338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[0]:Q,47799
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o3:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o3:B,9382
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o3:C,9337
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o3:D,8096
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o3:Y,8096
UART_IF_0/UART_IF_FSM_0/AXI_data_out[37]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[37]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[37]:D,2970
UART_IF_0/UART_IF_FSM_0/AXI_data_out[37]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[37]:Q,9329
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_5:IPENn,
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[22]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[22]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[22]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[22]:Q,11367
UART_IF_0/UART_IF_FSM_0/option[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/option[0]:CLK,8336
UART_IF_0/UART_IF_FSM_0/option[0]:D,8313
UART_IF_0/UART_IF_FSM_0/option[0]:EN,10779
UART_IF_0/UART_IF_FSM_0/option[0]:Q,8336
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_14:C,11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_14:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_14:IPC,11121
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[15]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[15]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[15]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[15]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[15]:Y,43073
UART_IF_0/UART_IF_FSM_0/AXI_data_out[53]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[53]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[53]:D,2797
UART_IF_0/UART_IF_FSM_0/AXI_data_out[53]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[53]:Q,9329
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[18]:A,10490
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[18]:B,10393
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[18]:C,9882
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[18]:D,8100
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[18]:Y,8100
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[0]:A,43940
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[0]:B,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[0]:C,46632
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[0]:D,44663
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[0]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_5:B,45512
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_5:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_5:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_5:S,45848
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_78:A,21482
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_78:IPA,21482
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_78:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[22]:A,-88
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[22]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[22]:Y,-88
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI3M8H[0]:A,43787
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI3M8H[0]:B,46054
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_RNI3M8H[0]:Y,43787
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[21]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[21]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[21]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[21]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[21]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_169:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[12]:CLK,46628
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[12]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[12]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[12]:Q,46628
UART_IF_0/UART_IF_FSM_0/AXI_data_out[46]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[46]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[46]:D,2728
UART_IF_0/UART_IF_FSM_0/AXI_data_out[46]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[46]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[0]:CLK,46436
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[0]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[0]:Q,46436
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:B,8421
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:C,9800
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:D,9533
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNISFQ551[33]:S,8373
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[16]:CLK,46715
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[16]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[16]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[16]:Q,46715
MDDR_Demo_top_0/AXI_IF_0/WVALID:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WVALID:CLK,-1885
MDDR_Demo_top_0/AXI_IF_0/WVALID:D,2670
MDDR_Demo_top_0/AXI_IF_0/WVALID:EN,1606
MDDR_Demo_top_0/AXI_IF_0/WVALID:Q,-1885
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[29]:CLK,42389
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[29]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[29]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[29]:Q,42389
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_11_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_11_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_11_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_m2[3]:A,9352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_m2[3]:B,1666
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_m2[3]:C,9244
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_m2[3]:Y,1666
UART_IF_0/UART_IF_FSM_0/AXI_data_in[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[8]:CLK,9133
UART_IF_0/UART_IF_FSM_0/AXI_data_in[8]:D,8003
UART_IF_0/UART_IF_FSM_0/AXI_data_in[8]:Q,9133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_9:A,40658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_9:B,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_9:C,40530
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_9:D,40462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_9:Y,39640
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_22:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_22:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:CLK,44726
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:D,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[17]:Q,44726
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[5]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[5]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[5]:Y,9466
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[8]:A,19398
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[8]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[8]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[8]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[8]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[10]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[10]:B,45768
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[10]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[10]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[10]:Y,40733
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:A,9254
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:B,8102
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:C,8057
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:D,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:FCO,8730
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_1_RNIUMS11:Y,7802
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[1]:A,7345
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[1]:B,9382
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[1]:Y,7345
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[1]:CLK,42491
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[1]:D,40311
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[1]:Q,42491
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns_a3[6]:A,47922
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns_a3[6]:B,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns_a3[6]:Y,47845
MDDR_Demo_top_0/AXI_IF_0/ARADDR[5]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[5]:CLK,-1622
MDDR_Demo_top_0/AXI_IF_0/ARADDR[5]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[5]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[5]:Q,-1622
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[2]:A,8305
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[2]:B,8270
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[2]:Y,8270
UART_IF_0/UART_IF_FSM_0/RAM_WD[30]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[30]:CLK,11182
UART_IF_0/UART_IF_FSM_0/RAM_WD[30]:D,3994
UART_IF_0/UART_IF_FSM_0/RAM_WD[30]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[30]:Q,11182
UART_IF_0/UART_IF_FSM_0/AXI_data_in[45]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[45]:CLK,9725
UART_IF_0/UART_IF_FSM_0/AXI_data_in[45]:D,7411
UART_IF_0/UART_IF_FSM_0/AXI_data_in[45]:Q,9725
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_11:EN,11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_11:IPENn,11442
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:B,8066
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:C,10210
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:D,9994
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_62:S,7139
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_122:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[11]:CLK,46612
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[11]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[11]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[11]:Q,46612
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_5_1:A,43213
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_5_1:B,41301
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_5_1:C,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_5_1:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_225:A,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_225:B,-1481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_225:IPA,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_225:IPB,-1481
UART_IF_0/UART_IF_FSM_0/AXI_data_out[21]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[21]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[21]:D,2948
UART_IF_0/UART_IF_FSM_0/AXI_data_out[21]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[21]:Q,9329
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_35:EN,11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_35:IPENn,11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_3:B,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_3:IPB,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_3:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[9]:A,46828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[9]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[9]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[9]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[27]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[27]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[27]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[27]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[27]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6:A,43546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6:B,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6:C,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6:D,40096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6:Y,38412
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[0]:CLK,7563
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[0]:D,9786
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[0]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[0]:Q,7563
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[26]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[26]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[26]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[26]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_data_in[58]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[58]:CLK,9939
UART_IF_0/UART_IF_FSM_0/AXI_data_in[58]:D,7203
UART_IF_0/UART_IF_FSM_0/AXI_data_in[58]:Q,9939
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_a3_2[5]:A,45826
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_a3_2[5]:B,42943
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_a3_2[5]:C,41212
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_a3_2[5]:Y,41212
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_231:A,-1582
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_231:B,-1544
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_231:IPA,-1582
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_231:IPB,-1544
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[17]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[17]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[17]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[17]:Q,11367
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_a3:A,7990
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_a3:B,8308
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_a3:Y,7990
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_23:A,46078
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_23:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_23:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_247:A,-1389
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_247:B,-1733
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_247:IPA,-1389
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_247:IPB,-1733
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[10]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[10]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[10]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[10]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[10]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[7]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[7]:B,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[7]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[7]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[7]:Y,45822
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[19]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[19]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[19]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[19]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_280:A,24273
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_280:B,25417
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_280:IPA,24273
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_280:IPB,25417
MDDR_Demo_top_0/AXI_IF_0/WDATA[19]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[19]:CLK,-1560
MDDR_Demo_top_0/AXI_IF_0/WDATA[19]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[19]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[19]:Q,-1560
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[7]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[7]:CLK,16903
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[7]:D,17706
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[7]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[7]:Q,16903
UART_IF_0/UART_IF_FSM_0/AXI_data_in[44]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[44]:CLK,9709
UART_IF_0/UART_IF_FSM_0/AXI_data_in[44]:D,7427
UART_IF_0/UART_IF_FSM_0/AXI_data_in[44]:Q,9709
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_16:C,11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_16:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_16:IPC,11326
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[2]:A,10431
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[2]:B,7436
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[2]:C,10322
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[2]:D,10222
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[2]:Y,7436
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[3]:CLK,8249
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[3]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[3]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[3]:Q,8249
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_33:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_33:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:A,38871
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:B,41207
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:C,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:D,37650
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_2:Y,37644
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNO[3]:A,10490
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNO[3]:B,10393
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNO[3]:C,9348
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNO[3]:D,8111
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNO[3]:Y,8111
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_11:B,11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_11:IPB,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[27]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[27]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[27]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[27]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[27]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_data_out[26]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[26]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[26]:D,2944
UART_IF_0/UART_IF_FSM_0/AXI_data_out[26]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[26]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[6]:CLK,47529
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[6]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[6]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[6]:Q,47529
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_6:B,44582
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_6:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_6:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_6:S,44976
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1_1:A,40578
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1_1:B,39002
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1_1:C,44370
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1_1:D,42355
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1_1:Y,39002
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[1]:CLK,42005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[1]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[1]:Q,42005
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[44]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[44]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[44]:C,2859
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[44]:Y,2859
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0:A,43138
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0:B,45378
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0:C,45661
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0:Y,43138
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_3:A,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_3:B,43950
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_0_3:Y,42101
UART_IF_0/UART_IF_FSM_0/AXI_data_in[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[9]:CLK,9149
UART_IF_0/UART_IF_FSM_0/AXI_data_in[9]:D,7987
UART_IF_0/UART_IF_FSM_0/AXI_data_in[9]:Q,9149
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[1]:A,22304
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[1]:B,22302
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[1]:C,22111
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[1]:D,20903
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[1]:Y,20903
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNO[10]:B,9786
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNO[10]:C,10190
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNO[10]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNO[10]:S,9657
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[48]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[48]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[48]:C,2899
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[48]:Y,2899
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_12:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[0]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[0]:D,43744
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[0]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[0]:Q,46058
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_a2_0:A,7375
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_a2_0:B,739
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_a2_0:C,9203
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_current_state_0_sqmuxa_0_0_a2_0:Y,739
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_105:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_105:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:B,9252
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:C,9209
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:D,7726
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI5G9KD[10]:S,-28
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_136:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_136:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[1]:A,47001
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[1]:B,46944
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[1]:C,43412
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[1]:D,46525
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[1]:Y,43412
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[19]:A,-43
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[19]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[19]:Y,-43
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_22:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_22:IPC,
MDDR_Demo_top_0/AXI_IF_0/WDATA[36]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[36]:CLK,-1550
MDDR_Demo_top_0/AXI_IF_0/WDATA[36]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[36]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[36]:Q,-1550
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[16]:A,9427
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[16]:B,9369
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[16]:Y,9369
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:CLK,46907
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:Q,46907
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[15]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[15]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[15]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[15]:Y,40377
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_31:B,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_31:IPB,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_31:IPC,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_19:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_19:C,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_19:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_19:IPC,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_5:B,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_5:IPB,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_5:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[7]:A,40212
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[7]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[7]:Y,40212
MDDR_Demo_top_0/AXI_IF_0/ARADDR[16]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[16]:CLK,-1593
MDDR_Demo_top_0/AXI_IF_0/ARADDR[16]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[16]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[16]:Q,-1593
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_21:B,45768
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_21:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_21:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_21:S,45592
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[28]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[28]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[28]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[28]:Y,39224
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[4]:A,9481
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[4]:B,9376
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[4]:C,8391
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[4]:D,8291
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[4]:Y,8291
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[21]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[21]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[21]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[21]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[21]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:B,7656
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:C,9810
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:D,9549
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_34:S,7587
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_244:A,-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_244:B,-1648
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_244:IPA,-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_244:IPB,-1648
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[29]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[29]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[29]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[29]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[29]:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:B,7862
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:C,10018
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:D,9757
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_47:S,7379
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:B,7384
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:C,9538
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:D,9277
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_17:S,7859
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[10]:A,39335
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[10]:B,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[10]:C,46632
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[10]:D,44663
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA[10]:Y,39042
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNII4VQ[1]:A,7592
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNII4VQ[1]:B,7469
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNII4VQ[1]:C,7482
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNII4VQ[1]:D,7375
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNII4VQ[1]:Y,7375
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_8:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:A,44178
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:B,39943
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:C,39002
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:D,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:A,46991
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:B,40244
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:C,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:D,46628
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVMBBB[12]:S,40132
UART_IF_0/UART_IF_FSM_0/AXI_data_out[40]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[40]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[40]:D,3002
UART_IF_0/UART_IF_FSM_0/AXI_data_out[40]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[40]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_35:B,43186
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_35:IPB,43186
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[22]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[22]:D,47444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[22]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[22]:Q,46105
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_s0_0_a2_0_a3:A,7405
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_s0_0_a2_0_a3:B,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_s0_0_a2_0_a3:Y,7362
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:CLK,20903
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:D,25211
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[1]:Q,20903
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[25]:CLK,47062
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[25]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[25]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[25]:Q,47062
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[25]:A,-133
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[25]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[25]:Y,-133
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[3]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[3]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[3]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[3]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_address[25]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[25]:CLK,9328
UART_IF_0/UART_IF_FSM_0/AXI_address[25]:D,-133
UART_IF_0/UART_IF_FSM_0/AXI_address[25]:Q,9328
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[15]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[15]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[15]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[15]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[15]:Y,45795
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0:A,42850
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0:B,42374
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0:C,46809
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0:D,45786
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0:Y,42374
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:B,9172
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:C,9129
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:D,7646
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHU198[5]:S,47
UART_IF_0/UART_IF_FSM_0/AXI_address[20]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[20]:CLK,9241
UART_IF_0/UART_IF_FSM_0/AXI_address[20]:D,-58
UART_IF_0/UART_IF_FSM_0/AXI_address[20]:Q,9241
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o2:A,42466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o2:B,42389
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o2:C,42344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o2:D,42266
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o2:Y,42266
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[8]:CLK,43088
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[8]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[8]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[8]:Q,43088
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[2]:A,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[2]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[2]:Y,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[23]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[23]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[23]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[23]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[23]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:A,47700
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:B,47428
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:C,41023
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:D,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a3_RNIANJ51:Y,37644
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_20:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_20:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[15]:A,45956
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[15]:B,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[15]:C,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[15]:D,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[15]:Y,44821
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[13]:A,19516
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[13]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[13]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[13]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[13]:Y,8534
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[0]:A,10359
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[0]:B,7360
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[0]:C,10382
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[0]:D,10199
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[0]:Y,7360
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_q1:D,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_q1:Q,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:A,21052
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:B,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:C,20884
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_sel_0_sqmuxa:Y,8534
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o2[0]:A,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o2[0]:B,7416
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_o2[0]:Y,7362
UART_IF_0/UART_IF_FSM_0/fsm[12]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[12]:CLK,8304
UART_IF_0/UART_IF_FSM_0/fsm[12]:D,7449
UART_IF_0/UART_IF_FSM_0/fsm[12]:Q,8304
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[7]:A,10504
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[7]:B,10413
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[7]:C,10369
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[7]:D,9237
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[7]:Y,9237
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[5]:CLK,6653
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[5]:D,9733
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[5]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[5]:Q,6653
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[5]:A,23274
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[5]:B,22000
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[5]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[5]:D,23112
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[5]:Y,22000
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:CLK,43219
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:Q,43219
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:B,8277
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:C,9656
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:D,9389
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIII2KQ[24]:S,8517
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_2_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_2_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_2_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[9]:B,17760
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[9]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[9]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[9]:S,17674
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2_i_o2[13]:A,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2_i_o2[13]:B,44137
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2_i_o2[13]:Y,41987
UART_IF_0/UART_IF_FSM_0/AXI_data_out[14]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[14]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[14]:D,2919
UART_IF_0/UART_IF_FSM_0/AXI_data_out[14]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[14]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[24]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[24]:B,44592
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[24]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[24]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[24]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_7:B,45544
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_7:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_7:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_7:S,45816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[2]:CLK,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[2]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[2]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[2]:Q,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_40:A,42205
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_40:B,42101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_40:C,42083
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_40:Y,42083
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_232:A,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_232:B,-1481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_232:IPA,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_232:IPB,-1481
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[6]:A,47397
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[6]:B,47529
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[6]:Y,47397
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD_0[0]:A,7943
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD_0[0]:B,7893
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIMJQD_0[0]:Y,7893
MDDR_Demo_top_0/AXI_IF_0/ARADDR[15]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[15]:CLK,-1527
MDDR_Demo_top_0/AXI_IF_0/ARADDR[15]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[15]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[15]:Q,-1527
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_17:B,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_17:C,11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_17:IPB,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_17:IPC,11293
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[2]:A,10405
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[2]:B,7375
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[2]:C,10382
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[2]:D,10252
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[2]:Y,7375
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q2:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q2:CLK,20915
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q2:D,23868
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/INIT_DONE_q2:Q,20915
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[22]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[22]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[22]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[22]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[22]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[19]:A,47197
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[19]:B,47140
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[19]:C,43608
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[19]:D,46721
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[19]:Y,43608
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]:CLK,38829
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]:D,46700
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]:Q,38829
MDDR_Demo_top_0/AXI_IF_0/ARADDR[7]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[7]:CLK,-1506
MDDR_Demo_top_0/AXI_IF_0/ARADDR[7]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[7]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[7]:Q,-1506
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[35]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[35]:CLK,9832
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[35]:D,8341
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[35]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[35]:Q,9832
UART_IF_0/UART_IF_FSM_0/AXI_data_out[62]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[62]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[62]:D,2780
UART_IF_0/UART_IF_FSM_0/AXI_data_out[62]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[62]:Q,9436
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_196:A,-1422
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_196:B,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_196:IPA,-1422
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_196:IPB,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_8_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_8_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_8_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[4]:A,10444
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[4]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[4]:C,8181
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[4]:D,10187
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0[4]:Y,8181
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2_1[0]:A,7796
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2_1[0]:B,8192
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2_1[0]:Y,7796
MDDR_Demo_top_0/AXI_IF_0/WDATA[34]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[34]:CLK,-1563
MDDR_Demo_top_0/AXI_IF_0/WDATA[34]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[34]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[34]:Q,-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_13:A,46000
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_13:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_13:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[24]:CLK,43121
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[24]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[24]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[24]:Q,43121
UART_IF_0/UART_IF_FSM_0/AXI_data_out[12]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[12]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[12]:D,2949
UART_IF_0/UART_IF_FSM_0/AXI_data_out[12]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[12]:Q,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_in[19]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[19]:CLK,9309
UART_IF_0/UART_IF_FSM_0/AXI_data_in[19]:D,7827
UART_IF_0/UART_IF_FSM_0/AXI_data_in[19]:Q,9309
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[8]:A,47364
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[8]:B,47496
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[8]:Y,47364
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[4]:A,19383
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[4]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[4]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[4]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[4]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[27]:CLK,47516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[27]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[27]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[27]:Q,47516
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[0]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[0]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[0]:Y,9466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_26:A,46073
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_26:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_26:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:B,9140
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:C,9097
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:D,7614
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIDOU56[3]:S,77
UART_IF_0/UART_IF_FSM_0/AXI_data_out[20]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[20]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[20]:D,2926
UART_IF_0/UART_IF_FSM_0/AXI_data_out[20]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[20]:Q,9329
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_6:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_86:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_86:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[6]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[6]:CLK,25317
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[6]:D,24879
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[6]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[6]:Q,25317
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:B,8725
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:C,10104
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:D,9837
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0NJGR1[52]:S,8069
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:A,24700
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:B,25111
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:C,25526
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPA,24700
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPB,25111
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPC,25526
UART_IF_0/UART_IF_FSM_0/RAM_WD[17]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[17]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[17]:D,3946
UART_IF_0/UART_IF_FSM_0/RAM_WD[17]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[17]:Q,11197
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:B,9284
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:C,9241
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:D,7758
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIA7BUF[12]:S,-58
MDDR_Demo_top_0/AXI_IF_0/WDATA[30]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[30]:CLK,-1443
MDDR_Demo_top_0/AXI_IF_0/WDATA[30]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[30]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[30]:Q,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOPAD:Y,
UART_IF_0/UART_IF_FSM_0/fsm_RNO[11]:A,10490
UART_IF_0/UART_IF_FSM_0/fsm_RNO[11]:B,10321
UART_IF_0/UART_IF_FSM_0/fsm_RNO[11]:C,9882
UART_IF_0/UART_IF_FSM_0/fsm_RNO[11]:Y,9882
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep_RNI4KI6/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int_rep_RNI4KI6/U0:YNn,
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[4]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[4]:CLK,8225
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[4]:D,7930
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[4]:Q,8225
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_30:IPENn,
MDDR_Demo_top_0/AXI_IF_0/WDATA[33]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[33]:CLK,-1443
MDDR_Demo_top_0/AXI_IF_0/WDATA[33]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[33]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[33]:Q,-1443
UART_IF_0/UART_IF_FSM_0/AXI_address[14]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[14]:CLK,9145
UART_IF_0/UART_IF_FSM_0/AXI_address[14]:D,32
UART_IF_0/UART_IF_FSM_0/AXI_address[14]:Q,9145
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_0:A,10382
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_0:B,2859
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_0:C,10287
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_0:D,10178
MDDR_Demo_top_0/AXI_IF_0/un1_ARADDR_0_sqmuxa_1_0_0:Y,2859
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_0_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_0_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_0_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:B,8501
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:C,9880
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:D,9613
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNII8L1B1[38]:S,8293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_31:IPENn,
UART_IF_0/UART_IF_FSM_0/AXI_data_out[33]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[33]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[33]:D,3017
UART_IF_0/UART_IF_FSM_0/AXI_data_out[33]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[33]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_6:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_6:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_88:A,42333
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_88:B,42229
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_88:C,42211
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_88:Y,42211
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_1_0_a6:A,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_1_0_a6:B,46935
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_1_0_a6:C,46696
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_1_0_a6:D,42205
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_HREADY_1_0_a6:Y,42205
UART_IF_0/UART_IF_FSM_0/AXI_data_in[27]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[27]:CLK,9437
UART_IF_0/UART_IF_FSM_0/AXI_data_in[27]:D,7699
UART_IF_0/UART_IF_FSM_0/AXI_data_in[27]:Q,9437
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_8:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_q1:D,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:B,7937
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:C,10098
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:D,9837
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_52:S,7299
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_27:B,44918
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_27:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_27:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_27:S,44512
UART_IF_0/UART_IF_FSM_0/AXI_data_in[39]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[39]:CLK,9629
UART_IF_0/UART_IF_FSM_0/AXI_data_in[39]:D,7507
UART_IF_0/UART_IF_FSM_0/AXI_data_in[39]:Q,9629
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[30]:A,47398
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[30]:B,47530
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[30]:Y,47398
MDDR_Demo_top_0/AXI_IF_0/WDATA[17]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[17]:CLK,-1551
MDDR_Demo_top_0/AXI_IF_0/WDATA[17]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[17]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[17]:Q,-1551
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[11]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[11]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[11]:C,2978
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[11]:Y,2978
UART_IF_0/UART_IF_FSM_0/AXI_data_out[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[7]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[7]:D,3910
UART_IF_0/UART_IF_FSM_0/AXI_data_out[7]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[7]:Q,9443
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[4]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[4]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[4]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[4]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[4]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_22:A,42285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_22:B,42181
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_22:C,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_22:Y,42163
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:CLK,46697
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:Q,46697
UART_IF_0/UART_IF_FSM_0/fsm_RNO[4]:A,10504
UART_IF_0/UART_IF_FSM_0/fsm_RNO[4]:B,10393
UART_IF_0/UART_IF_FSM_0/fsm_RNO[4]:C,8291
UART_IF_0/UART_IF_FSM_0/fsm_RNO[4]:D,8243
UART_IF_0/UART_IF_FSM_0/fsm_RNO[4]:Y,8243
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[30]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[30]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[30]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[30]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[30]:Y,39151
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[5]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[5]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[5]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[5]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[15]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[15]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[15]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[15]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[15]:Y,8813
UART_IF_0/UART_IF_FSM_0/fsm_RNO[16]:A,10477
UART_IF_0/UART_IF_FSM_0/fsm_RNO[16]:B,10386
UART_IF_0/UART_IF_FSM_0/fsm_RNO[16]:C,9369
UART_IF_0/UART_IF_FSM_0/fsm_RNO[16]:D,1853
UART_IF_0/UART_IF_FSM_0/fsm_RNO[16]:Y,1853
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[4]:CLK,42112
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[4]:D,46735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[4]:EN,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[4]:Q,42112
UART_IF_0/UART_IF_FSM_0/AXI_data_out[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[9]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[9]:D,2907
UART_IF_0/UART_IF_FSM_0/AXI_data_out[9]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[9]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[2]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[2]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[2]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[2]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[2]:Y,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:A,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:B,42035
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:C,42977
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:D,42716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_51:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[18]:CLK,43168
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[18]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[18]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[18]:Q,43168
MDDR_Demo_top_0/AXI_IF_0/ARADDR[11]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[11]:CLK,-1418
MDDR_Demo_top_0/AXI_IF_0/ARADDR[11]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[11]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[11]:Q,-1418
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[10]:A,92
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[10]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[10]:Y,92
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:A,43168
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:B,42131
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:D,42812
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_57:FCO,41987
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[5]:A,10398
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[5]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[5]:C,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[5]:D,10134
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[5]:Y,8195
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[4]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[4]:CLK,8470
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[4]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[4]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[4]:Q,8470
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[18]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[18]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[18]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[18]:Q,48017
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_20:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_20:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[11]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[11]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[11]:D,25260
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[11]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[11]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[10]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[10]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[10]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[10]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[10]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[15]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[15]:B,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[15]:C,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[15]:Y,39252
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO[0]:A,44529
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO[0]:B,47049
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO[0]:Y,44529
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:A,-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:B,-1471
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:C,-1497
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPA,-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPB,-1471
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPC,-1497
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4[5]:A,40096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4[5]:B,42846
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_o2_4[5]:Y,40096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[13]:CLK,46644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[13]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[13]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[13]:Q,46644
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:B,7496
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:C,9650
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:D,9389
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_24:S,7747
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQ6MG4[6]:B,10275
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQ6MG4[6]:C,9701
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQ6MG4[6]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQ6MG4[6]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQ6MG4[6]:S,9656
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[12]:CLK,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[12]:D,40132
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[12]:Q,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[19]:CLK,43010
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[19]:D,48639
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[19]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[19]:Q,43010
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_24:C,11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_24:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_24:IPC,11335
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[2]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[2]:D,41140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[2]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[2]:Q,48017
MDDR_Demo_top_0/AXI_IF_0/WDATA[49]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[49]:CLK,-1453
MDDR_Demo_top_0/AXI_IF_0/WDATA[49]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[49]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[49]:Q,-1453
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[3]:A,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[3]:B,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[3]:C,46770
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[3]:D,42427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[3]:Y,38431
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[57]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[57]:CLK,10184
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[57]:D,7989
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[57]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[57]:Q,10184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_31:B,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_31:IPB,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_31:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[13]:CLK,40614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[13]:D,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[13]:Q,40614
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2_RNI1KD51:A,9126
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2_RNI1KD51:B,-228
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2_RNI1KD51:C,7810
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2_RNI1KD51:D,8756
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2_RNI1KD51:FCO,-228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[27]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[27]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[27]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[27]:Y,39224
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNI8FI21[2]:A,10355
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNI8FI21[2]:B,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNI8FI21[2]:C,10253
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_RNI8FI21[2]:Y,10180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[19]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[19]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[19]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[19]:Y,46645
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_5:IPENn,
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTI0:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTI0:CLK,8111
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTI0:D,9027
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTI0:Q,8111
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[5]:A,19268
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[5]:B,22000
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[5]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[5]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[5]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[31]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[31]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[31]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[31]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[31]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[16]:A,10510
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[16]:B,9926
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[16]:C,9677
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[16]:D,1953
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[16]:Y,1953
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[4]:A,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[4]:B,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[4]:C,46754
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[4]:D,42391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[4]:Y,38412
UART_IF_0/UART_IF_FSM_0/AXI_data_out[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[5]:CLK,9243
UART_IF_0/UART_IF_FSM_0/AXI_data_out[5]:D,3873
UART_IF_0/UART_IF_FSM_0/AXI_data_out[5]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[5]:Q,9243
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[29]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[29]:CLK,9736
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[29]:D,8437
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[29]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[29]:Q,9736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[0]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[0]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[0]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[0]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[0]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:A,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:B,45976
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPA,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPB,45976
MDDR_Demo_top_0/AXI_IF_0/AWADDR[22]:CLK,-1537
MDDR_Demo_top_0/AXI_IF_0/AWADDR[22]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[22]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[22]:Q,-1537
UART_IF_0/UART_IF_FSM_0/RAM_REN:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_REN:CLK,11442
UART_IF_0/UART_IF_FSM_0/RAM_REN:D,11347
UART_IF_0/UART_IF_FSM_0/RAM_REN:EN,9887
UART_IF_0/UART_IF_FSM_0/RAM_REN:Q,11442
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int:CLK,3662
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int:EN,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/INIT_DONE_int:Q,3662
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_22:B,43638
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_22:IPB,43638
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[1]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[1]:CLK,47882
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[1]:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[1]:Q,47882
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1_0:A,39539
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1_0:B,39609
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1_0:C,46829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1_0:D,46718
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1_0:Y,39539
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[11]:A,46011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[11]:B,44928
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[11]:C,44929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[11]:D,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[11]:Y,40861
MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:CLK,-1470
MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:Q,-1470
MDDR_Demo_top_0/AXI_IF_0/AWADDR[12]:CLK,-1569
MDDR_Demo_top_0/AXI_IF_0/AWADDR[12]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[12]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[12]:Q,-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_6:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[1]:CLK,47170
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[1]:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[1]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[1]:Q,47170
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIN6IN2[1]:B,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIN6IN2[1]:C,10104
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIN6IN2[1]:FCI,8730
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIN6IN2[1]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIN6IN2[1]:S,7947
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_18_i_o6:A,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_18_i_o6:B,43667
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_18_i_o6:Y,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[24]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[13]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[13]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[13]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[13]:Q,45970
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:CLK,16783
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:D,17754
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[4]:Q,16783
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[24]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[24]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[24]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[24]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[24]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_38_0_0:A,41469
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_38_0_0:B,47798
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_38_0_0:C,43222
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_38_0_0:Y,41469
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_287:A,24909
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_287:B,25246
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_287:IPA,24909
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_287:IPB,25246
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_0_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_1_0_0:A,9000
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_1_0_0:B,2597
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_1_0_0:C,10234
MDDR_Demo_top_0/AXI_IF_0/un1_AWBURST_0_sqmuxa_1_0_0:Y,2597
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_158:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[1]:CLK,9027
UART_IF_0/UART_IF_FSM_0/AXI_data_in[1]:D,11340
UART_IF_0/UART_IF_FSM_0/AXI_data_in[1]:EN,9070
UART_IF_0/UART_IF_FSM_0/AXI_data_in[1]:Q,9027
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[22]:A,47422
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[22]:B,47554
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[22]:Y,47422
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_8_0[0]:A,6653
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_8_0[0]:B,6569
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_8_0[0]:Y,6569
UART_IF_0/UART_IF_FSM_0/cnt_1k[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[2]:CLK,7451
UART_IF_0/UART_IF_FSM_0/cnt_1k[2]:D,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k[2]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[2]:Q,7451
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_16:A,45814
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_16:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_16:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[0]:CLK,47487
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[0]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[0]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[0]:Q,47487
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[28]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[28]:D,47348
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[28]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[28]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_176:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_176:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[23]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[23]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[23]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[23]:Y,39224
MDDR_Demo_top_0/AXI_IF_0/WDATA[52]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[52]:CLK,-1505
MDDR_Demo_top_0/AXI_IF_0/WDATA[52]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[52]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[52]:Q,-1505
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_29:B,45896
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_29:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_29:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_29:S,45464
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[17]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[17]:CLK,9544
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[17]:D,8629
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[17]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[17]:Q,9544
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:A,21779
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:B,8379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:C,22644
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:Y,8379
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[26]:CLK,48785
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[26]:D,43427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[26]:Q,48785
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[1]:B,17632
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[1]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[1]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[1]:S,17808
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[27]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[27]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[27]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[27]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[27]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_134:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[20]:CLK,43184
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[20]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[20]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[20]:Q,43184
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:B,8629
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:C,10008
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:D,9741
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC7KEK1[46]:S,8165
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[12]:A,7250
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[12]:B,9351
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0[12]:Y,7250
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPC,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[58]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[58]:CLK,10200
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[58]:D,7973
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[58]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[58]:Q,10200
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_14:B,45656
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_14:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_14:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_14:S,46594
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[27]:A,47384
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[27]:B,47516
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[27]:Y,47384
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[10]:SLn,45312
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_24:C,11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_24:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_24:IPC,11335
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[0]:CLK,44180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[0]:D,47903
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[0]:Q,44180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[17]:A,45853
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[17]:B,44723
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[17]:C,44771
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[17]:D,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[17]:Y,40735
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_1:B,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_1:IPB,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_1:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[29]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[29]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[29]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[29]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1[1]:CLK,43168
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1[1]:D,42374
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1[1]:EN,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1[1]:Q,43168
UART_IF_0/UART_IF_FSM_0/AXI_data_out[19]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[19]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[19]:D,3031
UART_IF_0/UART_IF_FSM_0/AXI_data_out[19]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[19]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[23]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[23]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[23]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[23]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[23]:Y,39321
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[4]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[4]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[4]:Y,9466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[9]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[9]:B,45784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[9]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[9]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[9]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_284:A,24477
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_284:B,25479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_284:IPA,24477
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_284:IPB,25479
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[15]:A,47359
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[15]:B,47491
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[15]:Y,47359
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[8]:CLK,46564
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[8]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[8]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[8]:Q,46564
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_7_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[25]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[25]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[25]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[25]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[25]:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_in[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[4]:CLK,9069
UART_IF_0/UART_IF_FSM_0/AXI_data_in[4]:D,8185
UART_IF_0/UART_IF_FSM_0/AXI_data_in[4]:Q,9069
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[12]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[12]:D,47604
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[12]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[12]:Q,46105
UART_IF_0/UART_IF_FSM_0/AXI_data_in[25]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[25]:CLK,9405
UART_IF_0/UART_IF_FSM_0/AXI_data_in[25]:D,7731
UART_IF_0/UART_IF_FSM_0/AXI_data_in[25]:Q,9405
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[1]:CLK,47971
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[1]:EN,43344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[1]:Q,47971
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_3:B,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_3:IPB,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_3:IPC,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[10],11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[11],11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[1],10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[2],10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[3],10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[4],10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[5],11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[6],11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[7],11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[8],11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[9],11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_BLK[2],11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK,7345
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[10],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[11],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[14],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[15],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[16],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[4],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[5],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[6],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[7],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DIN[9],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT[0],7360
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT[1],7345
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_WEN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[10],11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[11],11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[4],10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[5],11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[6],11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[7],11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[8],11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[9],11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_BLK[2],11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[0],11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[10],11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[11],11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[12],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[13],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[14],11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[15],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[16],11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[1],11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[2],11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[3],11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[4],11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[5],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[6],11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[7],11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DIN[9],11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_WEN[1],
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[18]:CLK,45570
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[18]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[18]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[18]:Q,45570
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:B,8069
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:C,9448
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:D,9181
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6P4DB[11]:S,8725
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[6]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[6]:CLK,8552
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[6]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[6]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[6]:Q,8552
MDDR_Demo_top_0/AXI_IF_0/ARADDR[8]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[8]:CLK,-1458
MDDR_Demo_top_0/AXI_IF_0/ARADDR[8]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[8]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[8]:Q,-1458
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[7]:CLK,44566
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[7]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[7]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[7]:Q,44566
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[12]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[12]:B,45736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[12]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[12]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[12]:Y,40733
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:B,8005
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:C,9384
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:D,9117
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEOVA7[7]:S,8789
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:B,8757
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:C,10136
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:D,9869
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQ60ST1[54]:S,8037
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_272:A,-1452
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_272:IPA,-1452
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_272:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[14]:A,40100
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[14]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[14]:Y,40100
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:B,8042
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:C,10210
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:D,9955
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_59:S,7187
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_9:B,45576
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_9:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_9:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_9:S,45784
UART_IF_0/UART_IF_FSM_0/WEN_RNO:A,9964
UART_IF_0/UART_IF_FSM_0/WEN_RNO:B,1724
UART_IF_0/UART_IF_FSM_0/WEN_RNO:C,1405
UART_IF_0/UART_IF_FSM_0/WEN_RNO:Y,1405
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[4]:CLK,7631
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[4]:D,9748
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[4]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[4]:Q,7631
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[18]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[18]:CLK,9560
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[18]:D,8613
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[18]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[18]:Q,9560
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_22:B,44838
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_22:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_22:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_22:S,44592
UART_IF_0/UART_IF_FSM_0/AXI_data_in[24]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[24]:CLK,9389
UART_IF_0/UART_IF_FSM_0/AXI_data_in[24]:D,7747
UART_IF_0/UART_IF_FSM_0/AXI_data_in[24]:Q,9389
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:B,8837
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:C,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:D,9955
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEIGO32[59]:S,7957
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[14]:A,46748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[14]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[14]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[14]:Y,41092
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[10],11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[11],11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[1],10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[2],10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[3],10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[4],10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[5],11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[6],11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[7],11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[8],11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ADDR[9],11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_BLK[2],11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_CLK,8181
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[10],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[11],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[14],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[15],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[16],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[4],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[5],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[6],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[7],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DIN[9],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT[0],8181
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT[1],8195
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:A_WEN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[10],11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[11],11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[4],10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[5],11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[6],11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[7],11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[8],11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[9],11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_BLK[2],11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[0],11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[10],11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[11],11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[12],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[13],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[14],11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[15],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[16],11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[1],11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[2],11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[3],11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[4],11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[5],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[6],11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[7],11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DIN[9],11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/INST_RAM1K18_IP:B_WEN[1],
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[24]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[24]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[24]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[24]:Q,11367
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[1]:A,10438
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[1]:B,10383
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[1]:C,8363
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[1]:D,8134
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[1]:Y,8134
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[0]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[0]:D,47884
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[0]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[0]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[7]:A,46860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[7]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[7]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[7]:Y,41092
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[2]:A,10458
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[2]:B,8528
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[2]:C,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[2]:Y,7409
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[11]:CLK,47714
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[11]:D,43177
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[11]:Q,47714
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[0]:CLK,42929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[0]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[0]:Q,42929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[4]:CLK,42961
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[4]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[4]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[4]:Q,42961
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_16:C,11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_16:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_16:IPC,11326
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[13]:A,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[13]:B,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[13]:C,45905
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[13]:Y,45858
MDDR_Demo_top_0/AXI_IF_0/WDATA[26]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[26]:CLK,-1480
MDDR_Demo_top_0/AXI_IF_0/WDATA[26]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[26]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[26]:Q,-1480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[21]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[21]:B,45592
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[21]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[21]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[21]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_194:B,-1547
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_194:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_194:IPB,-1547
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[1]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[1]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[1]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[1]:Q,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[6]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[6]:D,8181
UART_IF_0/UART_IF_FSM_0/DATA_OUT[6]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[6]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_10:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_20:B,44806
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_20:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_20:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_20:S,44624
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/AXI_IF_0/WDATA[8]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[8]:CLK,-1458
MDDR_Demo_top_0/AXI_IF_0/WDATA[8]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[8]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[8]:Q,-1458
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[5]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[5]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[5]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[5]:Q,10426
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:CLK,21407
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:Q,21407
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[20]:CLK,41585
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[20]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[20]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[20]:Q,41585
MDDR_Demo_top_0/AXI_IF_0/WDATA[47]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[47]:CLK,-1593
MDDR_Demo_top_0/AXI_IF_0/WDATA[47]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[47]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[47]:Q,-1593
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[0]:CLK,10416
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[0]:D,9348
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[0]:Q,10416
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[6]:CLK,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[6]:D,9718
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[6]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[6]:Q,10196
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[14]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[14]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[14]:D,25097
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[14]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[14]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[31]:CLK,42227
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[31]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[31]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[31]:Q,42227
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[19]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[19]:B,44672
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[19]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[19]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[19]:Y,40733
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[8]:A,10484
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[8]:B,10400
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[8]:C,9425
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[8]:D,9295
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[8]:Y,9295
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:B,8213
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:C,9592
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:D,9325
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIUB3UL[20]:S,8581
MDDR_Demo_top_0/AXI_IF_0/ARVALID:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARVALID:CLK,-1933
MDDR_Demo_top_0/AXI_IF_0/ARVALID:D,11320
MDDR_Demo_top_0/AXI_IF_0/ARVALID:EN,2859
MDDR_Demo_top_0/AXI_IF_0/ARVALID:Q,-1933
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[21]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[21]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[21]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[21]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[21]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_32:A,43228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_32:B,43165
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_32:IPA,43228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_32:IPB,43165
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_246:A,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_246:B,-1631
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_246:IPA,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_246:IPB,-1631
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[5]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[5]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[5]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[5]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[1]:A,40311
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[1]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[1]:Y,40311
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[4]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[4]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[4]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[4]:Q,46058
UART_IF_0/UART_IF_FSM_0/WRITE:ALn,3352
UART_IF_0/UART_IF_FSM_0/WRITE:CLK,7893
UART_IF_0/UART_IF_FSM_0/WRITE:D,10349
UART_IF_0/UART_IF_FSM_0/WRITE:EN,9312
UART_IF_0/UART_IF_FSM_0/WRITE:Q,7893
UART_IF_0/UART_IF_FSM_0/RAM_WD[28]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[28]:CLK,11182
UART_IF_0/UART_IF_FSM_0/RAM_WD[28]:D,3951
UART_IF_0/UART_IF_FSM_0/RAM_WD[28]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[28]:Q,11182
UART_IF_0/UART_IF_FSM_0/RAM_WD[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[6]:CLK,11153
UART_IF_0/UART_IF_FSM_0/RAM_WD[6]:D,3619
UART_IF_0/UART_IF_FSM_0/RAM_WD[6]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[6]:Q,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_11:EN,11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_11:IPENn,11442
UART_IF_0/UART_IF_FSM_0/RAM_WD[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[1]:CLK,11163
UART_IF_0/UART_IF_FSM_0/RAM_WD[1]:D,3465
UART_IF_0/UART_IF_FSM_0/RAM_WD[1]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[1]:Q,11163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_3:B,44534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_3:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_3:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_3:S,44896
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[3]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[3]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[3]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[3]:Y,39315
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[1]:CLK,9465
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[1]:D,2010
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state[1]:Q,9465
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_19:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_19:C,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_19:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_19:IPC,11313
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[16]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[16]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[16]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[16]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:CLK,46799
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:Q,46799
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[25]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[25]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[25]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[25]:Y,39151
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:B,8677
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:C,10056
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:D,9789
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIOEHVN1[49]:S,8117
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_35:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_102:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_102:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[25]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[25]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[25]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[25]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:A,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:B,-1520
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:C,-1445
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPA,-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPB,-1520
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPC,-1445
UART_IF_0/UART_IF_FSM_0/AXI_data_in[42]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[42]:CLK,9677
UART_IF_0/UART_IF_FSM_0/AXI_data_in[42]:D,7459
UART_IF_0/UART_IF_FSM_0/AXI_data_in[42]:Q,9677
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_11:B,45608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_11:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_11:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_11:S,46642
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[62]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[62]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[62]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[62]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[62]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/WDATA[6]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[6]:CLK,-1499
MDDR_Demo_top_0/AXI_IF_0/WDATA[6]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[6]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[6]:Q,-1499
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6:A,46140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6:B,46109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6:C,45025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6:D,45904
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount6_i_o6:Y,45025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[11]:A,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[11]:B,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[11]:C,46642
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[11]:D,42391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[11]:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[10]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[10]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[10]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[10]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[10]:Y,21888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_4:C,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_4:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_4:IPC,10920
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[0]:CLK,7566
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[0]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[0]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[0]:Q,7566
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_56:A,47332
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_56:B,47376
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_56:IPA,47332
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_56:IPB,47376
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[3]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[3]:B,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[3]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[3]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[3]:Y,45822
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[7]:CLK,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[7]:D,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[7]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[7]:Q,10196
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_33:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[1]:A,47393
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[1]:B,47525
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[1]:Y,47393
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[3]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[3]:CLK,24273
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[3]:D,25112
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[3]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[3]:Q,24273
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[4]:CLK,42700
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[4]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[4]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[4]:Q,42700
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_7:B,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_7:IPB,11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_7:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[5]:CLK,42141
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[5]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[5]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[5]:Q,42141
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[29]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[29]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[29]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[29]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[29]:Y,39151
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[1]:A,10458
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[1]:B,10403
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[1]:C,9122
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[1]:D,7796
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[1]:Y,7796
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_15:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_15:C,11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_15:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_15:IPC,11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_6:C,10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_6:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_6:IPC,10875
RX_ibuf/U0/U_IOPAD:PAD,
RX_ibuf/U0/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2:A,42284
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2:B,42242
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2:C,37650
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2:D,41970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2:Y,37650
MDDR_Demo_top_0/AXI_IF_0/WDATA[24]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[24]:CLK,-1476
MDDR_Demo_top_0/AXI_IF_0/WDATA[24]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[24]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[24]:Q,-1476
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[41]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[41]:CLK,9928
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[41]:D,8245
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[41]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[41]:Q,9928
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_1_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:CLK,47532
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:D,48834
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:Q,47532
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[3]:A,8247
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[3]:B,9313
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[3]:Y,8247
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0:A,46611
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0:B,46627
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0:C,42139
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0:D,43739
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0:Y,42139
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[0]:A,7563
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[0]:B,7002
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[0]:C,7442
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[0]:Y,7002
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[29]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[29]:B,45464
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[29]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[29]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[29]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[42]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[42]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[42]:C,2702
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[42]:Y,2702
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base_RNIEJ51/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base_RNIEJ51/U0:YNn,
MDDR_Demo_top_0/AXI_IF_0/ARADDR[23]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[23]:CLK,-1495
MDDR_Demo_top_0/AXI_IF_0/ARADDR[23]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[23]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[23]:Q,-1495
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[27]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[27]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[27]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[27]:Q,48017
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[9]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[9]:CLK,9416
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[9]:D,8757
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[9]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[9]:Q,9416
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[11]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[11]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[11]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[11]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[9]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[9]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[9]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[9]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[9]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[23]:A,47395
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[23]:B,47527
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[23]:Y,47395
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[29]:CLK,42229
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[29]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[29]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[29]:Q,42229
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[37]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[37]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[37]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[37]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[37]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPC,
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_read_state_2_0_0:A,10402
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_read_state_2_0_0:B,10305
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_read_state_2_0_0:C,2764
MDDR_Demo_top_0/AXI_IF_0/un1_axi_fsm_read_state_2_0_0:Y,2764
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[7]:CLK,42053
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[7]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[7]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[7]:Q,42053
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_17:B,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_17:C,11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_17:IPB,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_17:IPC,11293
UART_IF_0/UART_IF_FSM_0/READ_RNO:A,10438
UART_IF_0/UART_IF_FSM_0/READ_RNO:B,10386
UART_IF_0/UART_IF_FSM_0/READ_RNO:C,10356
UART_IF_0/UART_IF_FSM_0/READ_RNO:Y,10356
MDDR_Demo_top_0/AXI_IF_0/WDATA[20]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[20]:CLK,-1537
MDDR_Demo_top_0/AXI_IF_0/WDATA[20]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[20]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[20]:Q,-1537
UART_IF_0/UART_IF_FSM_0/RAM_WD[21]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[21]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[21]:D,3926
UART_IF_0/UART_IF_FSM_0/RAM_WD[21]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[21]:Q,11197
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:A,-1577
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:B,-1662
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:C,-2020
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA,-1577
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPB,-1662
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPC,-2020
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_135:B,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_135:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_135:IPB,
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_o2[1]:A,9399
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_o2[1]:B,9463
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_o2[1]:Y,9399
MDDR_Demo_top_0/AXI_IF_0/WDATA[23]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[23]:CLK,-1532
MDDR_Demo_top_0/AXI_IF_0/WDATA[23]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[23]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[23]:Q,-1532
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:B,8012
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:C,10178
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:D,9923
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_57:S,7219
UART_IF_0/UART_IF_FSM_0/AXI_data_out[44]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[44]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[44]:D,2859
UART_IF_0/UART_IF_FSM_0/AXI_data_out[44]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[44]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP1UP[2]:A,42650
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP1UP[2]:B,42573
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIP1UP[2]:Y,42573
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_46:B,47355
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_46:IPB,47355
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_s_31:B,45897
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_s_31:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_s_31:S,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:B,44567
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:C,40126
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:D,46452
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:FCI,40238
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:FCO,40126
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIJLC82[1]:S,40311
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[17]:A,47977
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[17]:B,47906
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[17]:C,40416
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[17]:D,43168
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[17]:Y,40416
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B_1[0]:B,9658
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B_1[0]:FCO,9658
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI410N7[11]:B,10292
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI410N7[11]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI410N7[11]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI410N7[11]:S,7818
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[1]:CLK,46452
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[1]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[1]:Q,46452
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_0_0[0]:A,10470
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_0_0[0]:B,1998
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_0_0[0]:C,10329
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_read_state_ns_0_0[0]:Y,1998
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[0]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[0]:CLK,10348
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[0]:D,22679
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state[0]:Q,10348
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_2[2]:A,8619
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_2[2]:B,9476
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2_2[2]:Y,8619
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_3:B,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_3:IPB,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_3:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[25]:CLK,42179
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[25]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[25]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[25]:Q,42179
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[22]:CLK,47554
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[22]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[22]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[22]:Q,47554
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[7]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[7]:B,44864
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[7]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[7]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[7]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[57]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[57]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[57]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[57]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[57]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[11]:A,19322
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[11]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[11]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[11]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[11]:Y,8534
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[2]:A,9473
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[2]:B,8478
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[2]:C,9358
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[2]:Y,8478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_219:A,-1599
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_219:B,-1574
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_219:IPA,-1599
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_219:IPB,-1574
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[17]:CLK,42115
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[17]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[17]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[17]:Q,42115
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[17]:A,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[17]:B,45682
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[17]:C,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[17]:D,41448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[17]:Y,40735
UART_IF_0/UART_IF_FSM_0/AXI_address[12]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[12]:CLK,9113
UART_IF_0/UART_IF_FSM_0/AXI_address[12]:D,62
UART_IF_0/UART_IF_FSM_0/AXI_address[12]:Q,9113
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[18]:A,47338
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[18]:B,47470
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[18]:Y,47338
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_6:A,17068
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_6:B,17025
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_6:Y,17025
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK,48748
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q,48748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[14]:CLK,40658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[14]:D,40100
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[14]:Q,40658
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[3]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[3]:CLK,46935
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[3]:D,47733
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[3]:Q,46935
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B_0[0]:B,9673
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B_0[0]:FCO,9673
UART_IF_0/UART_IF_FSM_0/AXI_data_out[42]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[42]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[42]:D,2702
UART_IF_0/UART_IF_FSM_0/AXI_data_out[42]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[42]:Q,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_in[59]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[59]:CLK,9955
UART_IF_0/UART_IF_FSM_0/AXI_data_in[59]:D,7187
UART_IF_0/UART_IF_FSM_0/AXI_data_in[59]:Q,9955
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_haddr_fetch_2_sqmuxa_0:A,42058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_haddr_fetch_2_sqmuxa_0:B,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_haddr_fetch_2_sqmuxa_0:C,46515
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_haddr_fetch_2_sqmuxa_0:D,46527
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_haddr_fetch_2_sqmuxa_0:Y,40819
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i[2]:A,10470
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i[2]:B,10367
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i[2]:C,8397
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i[2]:D,1460
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_ns_i_i[2]:Y,1460
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[0]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[0]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[0]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[0]:Q,11367
UART_IF_0/UART_IF_FSM_0/RAM_WD[58]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[58]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[58]:D,3916
UART_IF_0/UART_IF_FSM_0/RAM_WD[58]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[58]:Q,11197
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_146:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_20:B,45752
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_20:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_20:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_20:S,45608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[0]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[0]:B,43744
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[0]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[0]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[0]:Y,43744
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_445_i_i:A,10451
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_445_i_i:B,9399
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_445_i_i:C,10336
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_445_i_i:Y,9399
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_174:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_174:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_167:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_61:A,47422
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_61:IPA,47422
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[9]:A,19329
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[9]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[9]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[9]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[9]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[16]:A,46772
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[16]:B,46715
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[16]:C,43183
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[16]:D,46296
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[16]:Y,43183
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[20]:CLK,46878
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[20]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[20]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[20]:Q,46878
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[18]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[18]:D,47508
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[18]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[18]:Q,46105
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:B,8245
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:C,9624
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:D,9357
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI4R29O[22]:S,8549
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_223:A,-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_223:B,-1560
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_223:IPA,-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_223:IPB,-1560
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[42]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[42]:CLK,9944
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[42]:D,8229
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[42]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[42]:Q,9944
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CAN_RXBUS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CAN_TXBUS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CAN_TX_EBL_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE,-228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB,22111
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_MDDR_APB,18125
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:COLF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CONFIG_PRESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CRSF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DM_IN[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DM_IN[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DM_OE[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DM_OE[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ADDR[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_BA[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_BA[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_BA[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CASN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CKE,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CLK,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_CSN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DM_RDQS_OUT[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DM_RDQS_OUT[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_IN[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_IN[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_OE[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_OE[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_OUT[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQS_OUT[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_IN[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OE[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_DQ_OUT[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_FIFO_WE_IN[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_FIFO_WE_OUT[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_ODT,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_RASN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_RSTN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:DRAM_WEN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2HCALIB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2H_INTERRUPT[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2_DMAREADY[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F2_DMAREADY[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_AVALID,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_HOSTDISCON,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_IDDIG,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_LINESTATE[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_LINESTATE[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_M3_RESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_PLL_LOCK,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_RXACTIVE,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_RXERROR,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_RXVALID,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_RXVALIDH,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_SESSEND,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_TXREADY,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VBUSVALID,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_VSTATUS[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FAB_XDATAIN[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N,45976
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_RESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[0],-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[10],-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[11],-1418
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[12],-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[13],-1471
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[14],-1573
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[15],-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[16],-1593
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[17],-1448
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[18],-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[19],-1440
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[1],-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[20],-1455
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[21],-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[22],-1539
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[23],-1495
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[24],-1685
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[25],-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[26],-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[27],-1586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[28],-1475
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[29],-1487
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[2],-1470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[30],-1476
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[31],-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[3],-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[4],-1377
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[5],-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[6],-1431
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[7],-1506
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[8],-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARADDR_HADDR1[9],-1618
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARBURST_HTRANS1[0],-1380
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARBURST_HTRANS1[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARID_HSEL1[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARID_HSEL1[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARID_HSEL1[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARID_HSEL1[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLEN_HBURST1[0],-1452
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLEN_HBURST1[1],-1486
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLEN_HBURST1[2],-1420
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLEN_HBURST1[3],-1414
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLOCK_HMASTLOCK1[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARLOCK_HMASTLOCK1[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARREADY_HREADYOUT1,2859
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARSIZE_HSIZE1[0],-1572
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARSIZE_HSIZE1[1],-1497
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_ARVALID_HWRITE1,-1933
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[0],-1422
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[10],-1547
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[11],-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[12],-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[13],-1491
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[14],-1555
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[15],-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[16],-1586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[17],-1590
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[18],-1491
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[19],-1470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[1],-1461
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[20],-1490
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[21],-1517
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[22],-1537
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[23],-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[24],-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[25],-1466
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[26],-1426
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[27],-1407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[28],-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[29],-1409
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[2],-1406
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[30],-1507
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[31],-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[3],-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[4],-1393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[5],-1493
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[6],-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[7],-1404
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[8],-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[9],-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWBURST_HTRANS0[0],-1479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWBURST_HTRANS0[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWID_HSEL0[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWID_HSEL0[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWID_HSEL0[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWID_HSEL0[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLEN_HBURST0[0],-1569
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLEN_HBURST0[1],-1520
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLEN_HBURST0[2],-1541
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLEN_HBURST0[3],-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLOCK_HMASTLOCK0[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWLOCK_HMASTLOCK0[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWREADY_HREADYOUT0,845
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWSIZE_HSIZE0[0],-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWSIZE_HSIZE0[1],-1432
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWVALID_HWRITE0,-1986
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BREADY,-2020
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_BVALID,2779
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_DMAREADY[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_DMAREADY[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[0],43313
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[10],43373
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[11],43280
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[12],43272
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[13],43079
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[14],43154
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[15],43165
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[16],43183
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[17],43243
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[18],43186
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[19],43608
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[1],43412
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[20],43346
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[21],43616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[22],43326
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[23],43605
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[24],43586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[25],43530
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[26],43488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[27],43181
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[28],43630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[29],43848
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[2],43994
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[30],43727
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[31],43787
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[3],43281
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[4],43011
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[5],43375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[6],43107
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[7],43216
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[8],43228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ADDR[9],43425
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_ENABLE,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_MASTLOCK,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[0],46002
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[10],45996
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[11],45890
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[12],45954
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[13],45986
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[14],46000
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[15],45992
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[16],45964
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[17],45814
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[18],45995
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[19],45865
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[1],45922
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[20],46079
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[21],46113
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[22],46096
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[23],46089
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[24],46078
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[25],46076
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[26],45983
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[27],46073
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[28],46090
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[29],46087
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[2],45971
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[30],45852
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[31],45968
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[3],45928
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[4],45934
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[5],45819
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[6],45936
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[7],45985
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[8],45974
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[9],45943
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_READY,46942
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_READYOUT,40084
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_SEL,43874
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_SIZE[0],43706
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_SIZE[1],43638
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_TRANS1,43093
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[0],47355
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[10],47332
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[11],47393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[12],47383
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[13],47387
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[14],47347
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[15],47359
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[16],47379
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[17],47376
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[18],47338
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[19],47356
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[1],47393
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[20],47375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[21],47420
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[22],47422
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[23],47395
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[24],47386
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[25],47330
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[26],47367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[27],47384
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[28],47333
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[29],47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[2],47421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[30],47398
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[31],47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[3],47385
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[4],47427
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[5],47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[6],47397
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[7],47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[8],47364
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WDATA[9],47403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_WRITE,43267
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[10],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[11],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[12],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[13],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[14],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[15],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[16],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[17],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[18],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[19],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[20],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[21],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[22],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[23],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[24],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[25],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[26],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[27],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[28],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[29],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[30],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[31],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_READY,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RESP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[0],3944
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[10],2930
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[11],2978
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[12],2949
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[13],1978
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[14],2919
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[15],2970
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[16],1953
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[17],2968
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[18],2928
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[19],3031
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[1],3465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[20],2926
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[21],2948
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[22],2963
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[23],2814
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[24],2922
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[25],2973
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[26],2944
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[27],2809
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[28],2973
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[29],3030
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[2],3791
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[30],3016
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[31],2968
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[32],2888
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[33],3017
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[34],3015
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[35],2907
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[36],2669
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[37],2970
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[38],2715
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[39],2837
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[3],4031
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[40],3002
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[41],2576
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[42],2702
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[43],2926
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[44],2859
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[45],2979
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[46],2728
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[47],2020
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[48],2899
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[49],2669
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[4],4005
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[50],2696
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[51],2946
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[52],2814
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[53],2797
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[54],2914
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[55],2844
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[56],2767
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[57],2866
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[58],2931
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[59],2751
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[5],3873
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[60],2831
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[61],2902
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[62],2780
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[63],2928
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[6],3619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[7],3910
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[8],2909
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[9],2907
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RLAST,-192
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RMW_AXI,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RREADY,-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RVALID,-228
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[0],-1403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[10],-1488
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[11],-1511
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[12],-1465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[13],-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[14],-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[15],-1574
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[16],-1515
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[17],-1551
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[18],-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[19],-1560
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[1],-1596
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[20],-1537
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[21],-1481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[22],-1538
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[23],-1532
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[24],-1476
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[25],-1419
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[26],-1480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[27],-1635
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[28],-1479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[29],-1582
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[2],-1371
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[30],-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[31],-1503
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[32],-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[33],-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[34],-1563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[35],-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[36],-1550
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[37],-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[38],-1467
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[39],-1513
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[3],-1599
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[40],-1661
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[41],-1544
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[42],-1481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[43],-1558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[44],-1784
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[45],-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[46],-1551
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[47],-1593
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[48],-1647
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[49],-1453
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[4],-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[50],-1444
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[51],-1469
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[52],-1505
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[53],-1577
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[54],-1558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[55],-1561
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[56],-1622
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[57],-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[58],-1438
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[59],-1389
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[5],-1434
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[60],-1616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[61],-1566
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[62],-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[63],-1649
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[6],-1499
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[7],-1484
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[8],-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[9],-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WID_HREADY01[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WID_HREADY01[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WID_HREADY01[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WID_HREADY01[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WLAST,-1445
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WREADY,739
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[0],-1630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[1],-1662
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[2],-1717
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[3],-1657
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[4],-1648
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[5],-1498
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[6],-1631
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WSTRB[7],-1733
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WVALID,-1885
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:GTX_CLKPF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C0_BCLK,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C0_SCL_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C0_SDA_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C1_BCLK,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C1_SCL_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:I2C1_SDA_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[10],24909
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[2],24668
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[3],24273
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[4],24465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[5],24528
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[6],24670
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[7],24477
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[8],24558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[9],24971
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PENABLE,12563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[0],19403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[10],19261
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[11],19322
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[12],19190
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[13],19516
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[14],19354
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[15],19316
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[1],19362
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[2],19311
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[3],19351
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[4],19383
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[5],19268
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[6],19308
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[7],19417
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[8],19398
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PRDATA[9],19329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PREADY,18125
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PSEL,10344
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PSLVERR,20211
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[0],24700
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[10],25470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[11],25479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[12],25412
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[13],25541
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[14],25246
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[15],25526
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[1],24757
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[2],25186
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[3],25111
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[4],24841
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[5],25570
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[6],25317
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[7],25417
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[8],24873
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[9],25306
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWRITE,24893
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDIF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO0A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO10A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO11A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO11B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO12A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO13A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO14A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO15A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO16A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO17B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO18B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO19B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO1A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO20B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO21B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO22B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO24B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO25B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO26B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO27B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO28B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO29B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO2A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO30B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO31B_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO3A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO4A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO5A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO6A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO7A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO8A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MGPIO9A_F2H_GPIN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_CTS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_DCD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_DSR_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_DTR_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_RI_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_RTS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_RXD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_SCK_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_TXD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_CTS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_DCD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_DSR_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_RI_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_RTS_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_RXD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_SCK_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART1_TXD_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[10],25260
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[12],25179
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[13],25201
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[15],25185
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[2],22148
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[3],22302
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[4],22111
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[5],25220
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[6],25195
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[7],25223
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[8],25089
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PADDR[9],25256
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PENABLE,22538
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[0],21495
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[10],21440
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[11],21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[12],21482
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[13],21441
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[14],21447
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[15],21443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[16],21441
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[17],21458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[18],21419
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[19],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[1],21481
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[20],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[21],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[22],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[23],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[24],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[25],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[26],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[27],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[28],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[29],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[2],21407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[30],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[31],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[3],21421
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[4],21435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[5],21439
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[6],21437
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[7],21485
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[8],21464
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PRDATA[9],21480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PREADY,21424
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PSEL,22478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PSLVERR,21523
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[0],25195
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[10],25164
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[11],25260
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[12],25218
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[13],25236
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[14],25097
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[15],25264
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[16],25273
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[1],25211
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[2],25070
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[3],25176
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[4],25202
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[5],25221
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[6],24879
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[7],25206
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[8],25197
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWDATA[9],25185
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PWRITE,23114
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PRESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[8],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RCGF[9],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[0],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[1],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[2],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[3],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[4],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[5],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[6],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RXDF[7],
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RX_CLKPF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RX_DVF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RX_ERRF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:RX_EV,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SLEEPHOLDREQ,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SMBALERT_NI0,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SMBALERT_NI1,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SMBSUS_NI0,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SMBSUS_NI1,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_CLK_IN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SDI_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SDO_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SS0_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SS1_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SS2_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI0_SS3_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_CLK_IN,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SDI_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SDO_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SS0_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SS1_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SS2_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:SPI1_SS3_F2H_SCP,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:TX_CLKPF,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:USER_MSS_GPIO_RESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:USER_MSS_RESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:XCLK_FAB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_WE_N_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_WE_N_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_WE_N_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[3]:A,9553
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[3]:B,10386
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[3]:C,9122
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[3]:D,9792
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[3]:Y,9122
UART_IF_0/UART_IF_FSM_0/DATA_OUT[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[2]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[2]:D,7375
UART_IF_0/UART_IF_FSM_0/DATA_OUT[2]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[2]:Q,11367
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNO[12]:B,10292
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNO[12]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNO[12]:S,7802
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[23]:CLK,42285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[23]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[23]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[23]:Q,42285
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[3]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[3]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[3]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[3]:Q,10426
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[20]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[20]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[20]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[20]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[0]:CLK,41027
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[0]:D,45833
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[0]:EN,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[0]:Q,41027
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[25]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[25]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[25]:C,2973
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[25]:Y,2973
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[27]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[27]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[27]:C,2809
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[27]:Y,2809
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select:ALn,48748
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select:CLK,48010
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select:EN,47852
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select:Q,48010
UART_IF_0/UART_IF_FSM_0/AXI_address[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[7]:CLK,9033
UART_IF_0/UART_IF_FSM_0/AXI_address[7]:D,137
UART_IF_0/UART_IF_FSM_0/AXI_address[7]:Q,9033
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount_0_sqmuxa_0_o6:A,44410
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount_0_sqmuxa_0_o6:B,46273
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount_0_sqmuxa_0_o6:C,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount_0_sqmuxa_0_o6:D,41813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_bytecount_0_sqmuxa_0_o6:Y,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[15]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[15]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[15]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[15]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[15]:Y,39042
UART_IF_0/UART_IF_FSM_0/AXI_data_out[24]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[24]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[24]:D,2922
UART_IF_0/UART_IF_FSM_0/AXI_data_out[24]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[24]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_195:B,-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_195:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_195:IPB,-1527
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_30:A,45968
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_30:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_30:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1:A,42459
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1:B,39002
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1:C,45402
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1:D,43355
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_o2_0_1:Y,39002
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[10]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[10]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[10]:C,2930
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[10]:Y,2930
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR_RNO:A,9406
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR_RNO:B,20211
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR_RNO:Y,9406
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:B,7720
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:C,9874
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:D,9613
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_38:S,7523
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_22:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_22:IPC,
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[3]:CLK,8260
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[3]:D,8232
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[3]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[3]:Q,8260
UART_IF_0/UART_IF_FSM_0/RLEN_1[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RLEN_1[0]:CLK,11367
UART_IF_0/UART_IF_FSM_0/RLEN_1[0]:D,9422
UART_IF_0/UART_IF_FSM_0/RLEN_1[0]:EN,8426
UART_IF_0/UART_IF_FSM_0/RLEN_1[0]:Q,11367
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_9:B,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_9:C,10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_9:IPB,11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_9:IPC,10999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[17]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[17]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[17]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[17]:Q,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[4]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[4]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[4]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[4]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[4]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_0_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/AXI_IF_0/WDATA[39]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[39]:CLK,-1513
MDDR_Demo_top_0/AXI_IF_0/WDATA[39]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[39]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[39]:Q,-1513
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[16]:A,23140
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[16]:B,23046
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[16]:C,23072
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[16]:D,21754
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1[16]:Y,21754
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[2]:CLK,46468
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[2]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[2]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[2]:Q,46468
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_111:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_111:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy_RNI7KLL:A,46887
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy_RNI7KLL:B,46892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/busy_RNI7KLL:Y,46887
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0:YNn,
UART_IF_0/UART_IF_FSM_0/AXI_data_out[22]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[22]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[22]:D,2963
UART_IF_0/UART_IF_FSM_0/AXI_data_out[22]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[22]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_242:A,-1558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_242:B,-1717
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_242:IPA,-1558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_242:IPB,-1717
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:B,8453
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:C,9832
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:D,9565
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIJUG71[35]:S,8341
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[7]:CLK,47492
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[7]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[7]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[7]:Q,47492
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_128:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_128:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[14]:A,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[14]:B,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[14]:C,45905
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[14]:Y,45858
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[0]:A,8499
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[0]:B,8428
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[0]:C,7416
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[0]:D,8267
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a3[0]:Y,7416
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[0]:CLK,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[0]:D,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[0]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[0]:Q,7409
MDDR_Demo_top_0/AXI_IF_0/AWADDR[20]:CLK,-1490
MDDR_Demo_top_0/AXI_IF_0/AWADDR[20]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[20]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[20]:Q,-1490
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIDQ4I5[8]:B,9785
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIDQ4I5[8]:C,10190
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIDQ4I5[8]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIDQ4I5[8]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIDQ4I5[8]:S,9688
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[14]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[14]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[14]:C,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[14]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[14]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[39]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[39]:CLK,9896
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[39]:D,8277
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[39]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[39]:Q,9896
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_8:A,8028
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_8:B,7985
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_8:C,7903
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_8:D,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTIOI.CUARTO08_8:Y,7802
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n:A,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n:B,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n:Y,47845
UART_IF_0/UART_IF_FSM_0/RAM_WD[51]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[51]:CLK,11204
UART_IF_0/UART_IF_FSM_0/RAM_WD[51]:D,3924
UART_IF_0/UART_IF_FSM_0/RAM_WD[51]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[51]:Q,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_29:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[4]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[4]:CLK,24465
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[4]:D,25001
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[4]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[4]:Q,24465
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6:A,44180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6:B,44103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6:Y,44103
MDDR_Demo_top_0/AXI_IF_0/AWADDR[10]:CLK,-1547
MDDR_Demo_top_0/AXI_IF_0/AWADDR[10]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[10]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[10]:Q,-1547
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[7]:A,46939
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[7]:B,45038
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[7]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[7]:D,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO[7]:Y,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_8:B,45560
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_8:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_8:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_8:S,46690
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:A,8396
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:B,7656
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:C,909
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:D,657
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3[9]:Y,657
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[7]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[7]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[7]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[7]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[7]:Y,39042
MDDR_Demo_top_0/AXI_IF_0/WDATA[5]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[5]:CLK,-1434
MDDR_Demo_top_0/AXI_IF_0/WDATA[5]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[5]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[5]:Q,-1434
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[1]:A,44638
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[1]:B,46827
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[1]:Y,44638
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[7]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[7]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[7]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[7]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[28]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[28]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[28]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[28]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[28]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[32]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[32]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[32]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[32]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[32]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[21]:A,46636
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[21]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[21]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[21]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:D,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif3_core_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_o3:A,9589
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_o3:B,9553
UART_IF_0/UART_IF_FSM_0/rx_en_1_0_0_i_0_o3:Y,9553
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:CLK,21439
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:Q,21439
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[30]:CLK,47530
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[30]:D,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[30]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[30]:Q,47530
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:CLK,46760
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:Q,46760
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[2]:CLK,42650
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[2]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[2]:Q,42650
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[1]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[1]:CLK,16720
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[1]:D,17808
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[1]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[1]:Q,16720
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_3:A,45934
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_3:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_3:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[36]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[36]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[36]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[36]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[36]:Y,8813
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_8:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_76:A,21440
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_76:B,21458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_76:IPA,21440
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_76:IPB,21458
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1:A,44103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1:B,44558
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1:C,44934
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1:D,44635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_1:Y,44103
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[9]:A,107
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[9]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[9]:Y,107
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1_0[0]:A,22148
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1_0[0]:B,20915
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1_0[0]:C,20826
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/int_prdata_1_0[0]:Y,20826
UART_IF_0/UART_IF_FSM_0/RAM_WD[62]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[62]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[62]:D,3758
UART_IF_0/UART_IF_FSM_0/RAM_WD[62]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[62]:Q,11197
MDDR_Demo_top_0/AXI_IF_0/AWADDR[30]:CLK,-1507
MDDR_Demo_top_0/AXI_IF_0/AWADDR[30]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[30]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[30]:Q,-1507
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2_INST/U0_RGB1:YL,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[6]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[6]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[6]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[6]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[6]:Y,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[24]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[24]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[24]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[24]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[24]:Y,39151
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_18:C,11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_18:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_18:IPC,11353
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[7]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[7]:CLK,9384
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[7]:D,8789
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[7]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[7]:Q,9384
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:CLK,46905
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:Q,46905
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[14]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[52]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[52]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[52]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[52]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[52]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_busy_3:A,47971
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_busy_3:B,47923
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_busy_3:C,47889
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_busy_3:D,47799
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_busy_3:Y,47799
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:B,9083
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:C,9033
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:D,7550
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIB1M62[7]:S,137
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_19:B,45736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_19:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_19:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_19:S,45624
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[19]:A,47356
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[19]:B,47488
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[19]:Y,47356
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[0]:CLK,10148
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[0]:D,9786
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[0]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[0]:Q,10148
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_RNO[0]:A,17974
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_RNO[0]:Y,17974
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[23]:CLK,42163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[23]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[23]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[23]:Q,42163
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_286:A,24971
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_286:B,25541
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_286:IPA,24971
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_286:IPB,25541
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:CLK,38678
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:D,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:Q,38678
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[56]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[56]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[56]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[56]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[56]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_10:A,42125
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_10:B,42021
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_10:C,42003
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_10:Y,42003
MDDR_Demo_top_0/AXI_IF_0/WDATA[2]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[2]:CLK,-1371
MDDR_Demo_top_0/AXI_IF_0/WDATA[2]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[2]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[2]:Q,-1371
UART_IF_0/UART_IF_FSM_0/cnt_1k[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[7]:CLK,7450
UART_IF_0/UART_IF_FSM_0/cnt_1k[7]:D,9641
UART_IF_0/UART_IF_FSM_0/cnt_1k[7]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[7]:Q,7450
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[12]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[12]:CLK,25412
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[12]:D,25218
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[12]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[12]:Q,25412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[17]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[17]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[17]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[17]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[17]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[4]:CLK,44518
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[4]:D,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[4]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[4]:Q,44518
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2:A,9356
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2:B,9279
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2:C,8243
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0_a2:Y,8243
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_1:B,44502
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_1:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_1:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_1:S,45031
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[2]:A,10438
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[2]:B,8764
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[2]:C,6173
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[2]:D,657
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0[2]:Y,657
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[22]:CLK,46865
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[22]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[22]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[22]:Q,46865
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_20:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_20:IPB,
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[5]:A,10477
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[5]:B,9367
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[5]:C,10369
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[5]:D,10259
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[5]:Y,9367
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[20]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[20]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[20]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[20]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[20]:Y,8813
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQG7H1[1]:B,10195
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQG7H1[1]:C,9626
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQG7H1[1]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQG7H1[1]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIQG7H1[1]:S,9710
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[9]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[9]:B,46037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[9]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[9]:D,41267
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[9]:Y,41267
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_11:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_11:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_90:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_90:IPB,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:B,8517
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:C,9896
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:D,9629
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMJ77C1[39]:S,8277
MDDR_Demo_top_0/AXI_IF_0/AWADDR_0_sqmuxa_0_a2:A,8791
MDDR_Demo_top_0/AXI_IF_0/AWADDR_0_sqmuxa_0_a2:B,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR_0_sqmuxa_0_a2:Y,3700
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:B,8066
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:C,10210
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:D,9994
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_s_63:S,7123
UART_IF_0/UART_IF_FSM_0/fsm[20]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[20]:CLK,9257
UART_IF_0/UART_IF_FSM_0/fsm[20]:D,9916
UART_IF_0/UART_IF_FSM_0/fsm[20]:Q,9257
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[9]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[9]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[9]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[9]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_28_0:A,45972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_28_0:B,47847
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_28_0:Y,45972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:A,46876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:B,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:C,44550
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:D,46500
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIDL0J4[4]:S,40260
UART_IF_0/UART_IF_FSM_0/AXI_data_out[49]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[49]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[49]:D,2669
UART_IF_0/UART_IF_FSM_0/AXI_data_out[49]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[49]:Q,9329
UART_IF_0/UART_IF_FSM_0/RAM_WD[47]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[47]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[47]:D,4062
UART_IF_0/UART_IF_FSM_0/RAM_WD[47]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[47]:Q,11208
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_7:A,39075
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_7:B,39027
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_7:C,38953
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_7:D,38859
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_7:Y,38859
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[2]:CLK,41465
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[2]:D,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[2]:Q,41465
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_22:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_22:IPC,
UART_IF_0/COREUART_0/CUARTO1I[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[5]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[5]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[5]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[5]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[15]:CLK,46998
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[15]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[15]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[15]:Q,46998
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[20]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[20]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[20]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[20]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[5]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[5]:CLK,24528
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[5]:D,25220
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[5]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[5]:Q,24528
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_260:A,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_260:B,-1455
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_260:IPA,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_260:IPB,-1455
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[21]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[21]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[21]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[21]:Q,46992
UART_IF_0/UART_IF_FSM_0/RAM_WD[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[3]:CLK,11163
UART_IF_0/UART_IF_FSM_0/RAM_WD[3]:D,4031
UART_IF_0/UART_IF_FSM_0/RAM_WD[3]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[3]:Q,11163
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:CLK,21481
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:Q,21481
UART_IF_0/UART_IF_FSM_0/RAM_WD[34]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[34]:CLK,11218
UART_IF_0/UART_IF_FSM_0/RAM_WD[34]:D,3993
UART_IF_0/UART_IF_FSM_0/RAM_WD[34]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[34]:Q,11218
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2[0]:A,8726
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2[0]:B,8622
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2[0]:C,8058
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2[0]:Y,8058
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_6[15]:A,7536
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_6[15]:B,7451
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_6[15]:C,7406
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_6[15]:D,7328
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_6[15]:Y,7328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[24]:CLK,43216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[24]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[24]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[24]:Q,43216
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[48]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[48]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[48]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[48]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[48]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[26]:SLn,45312
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_6:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[31]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[31]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[31]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[31]:Q,45970
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[2]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[2]:CLK,8331
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[2]:D,1460
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[2]:Q,8331
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n1_i_m2:A,47958
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n1_i_m2:B,47903
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n1_i_m2:C,46887
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n1_i_m2:D,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n1_i_m2:Y,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[21]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[21]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[21]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[21]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNO[0]:A,47967
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNO[0]:B,46947
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNO[0]:C,45833
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNO[0]:Y,45833
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:CLK,38884
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:Q,38884
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNIORT01[3]:A,7375
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNIORT01[3]:B,8433
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNIORT01[3]:Y,7375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[6]:CLK,42977
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[6]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[6]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[6]:Q,42977
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_25:B,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_25:C,11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_25:IPB,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_25:IPC,11309
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[7]:CLK,40462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[7]:D,40212
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[7]:Q,40462
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:B,7560
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:C,9714
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:D,9453
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_28:S,7683
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[29]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[29]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[29]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[29]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_5_PAD/U_IOPAD:Y,
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:B,9236
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:C,9193
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:D,7710
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIH39FC[9]:S,-13
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_28:A,46087
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_28:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_28:Y,43758
UART_IF_0/UART_IF_FSM_0/rx_en_RNO:A,9553
UART_IF_0/UART_IF_FSM_0/rx_en_RNO:B,8428
UART_IF_0/UART_IF_FSM_0/rx_en_RNO:C,9124
UART_IF_0/UART_IF_FSM_0/rx_en_RNO:Y,8428
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[24]:CLK,42444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[24]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[24]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[24]:Q,42444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[10]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[10]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[10]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[10]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[19]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[19]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[19]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[19]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[19]:Y,43758
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[3]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[3]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[3]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[3]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[18]:A,-28
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[18]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[18]:Y,-28
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[0]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[0]:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[0]:Q,48867
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_281:A,24465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_281:B,24873
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_281:IPA,24465
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_281:IPB,24873
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_9_PAD/U_IOINFF:Y,
UART_IF_0/COREUART_0/CUARTO1I[4]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[4]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[4]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[4]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[4]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_1:A,39609
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_1:B,45775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_1:C,41380
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_1:Y,39609
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[25]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[25]:B,44576
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[25]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[25]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[25]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[26]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[26]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[26]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[26]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[26]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[13]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[13]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[13]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[13]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[13]:Y,43758
MDDR_Demo_top_0/AXI_IF_0/WDATA[37]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[37]:CLK,-1443
MDDR_Demo_top_0/AXI_IF_0/WDATA[37]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[37]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[37]:Q,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_22:A,46089
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_22:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_22:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[7]:B,17728
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[7]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[7]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[7]:S,17706
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[9]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[9]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[9]:D,25185
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[9]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[9]:Q,21888
MDDR_Demo_top_0/AXI_IF_0/ARADDR[26]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[26]:CLK,-1435
MDDR_Demo_top_0/AXI_IF_0/ARADDR[26]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[26]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[26]:Q,-1435
UART_IF_0/UART_IF_FSM_0/AXI_data_out[29]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[29]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[29]:D,3030
UART_IF_0/UART_IF_FSM_0/AXI_data_out[29]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[29]:Q,9329
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[9]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[9]:CLK,8028
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[9]:D,7850
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[9]:Q,8028
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_110:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[22]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[22]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[22]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[22]:Y,39224
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0:A,9326
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0:B,10305
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0:C,8847
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0:D,9704
UART_IF_0/UART_IF_FSM_0/un1_fsm_49_0_0:Y,8847
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_144:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_144:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[22]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[22]:CLK,9357
UART_IF_0/UART_IF_FSM_0/AXI_data_in[22]:D,7779
UART_IF_0/UART_IF_FSM_0/AXI_data_in[22]:Q,9357
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[12]:CLK,43120
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[12]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[12]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[12]:Q,43120
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[22]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[7]:A,46805
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[7]:B,46748
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[7]:C,43216
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[7]:D,46329
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[7]:Y,43216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[29]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[29]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[29]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[29]:D,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[29]:Y,39151
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[5]:CLK,10426
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[5]:D,8295
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[5]:Q,10426
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_8:C,10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_8:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_8:IPC,10940
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_218:A,-1371
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_218:B,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_218:IPA,-1371
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_218:IPB,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_186:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[25]:CLK,44854
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[25]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[25]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[25]:Q,44854
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[28]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[28]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[28]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[28]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[28]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:CLK,46804
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:Q,46804
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[17]:CLK,42133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[17]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[17]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[17]:Q,42133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[1]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[1]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[1]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[1]:Y,46645
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_a3_0_a2[0]:A,10493
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_a3_0_a2[0]:B,10406
UART_IF_0/COREUART_0/CUARTIO1/CUARTI10l.CUARTll0l_3_a3_0_a2[0]:Y,10406
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il:CLK,10334
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il:EN,9119
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il:Q,10334
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[17]:A,24208
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[17]:B,8578
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[17]:C,24023
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[17]:D,24046
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[17]:Y,8578
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:CLK,8506
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:D,
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[2]:Q,8506
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIBTJ11[28]:A,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIBTJ11[28]:B,47812
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNIBTJ11[28]:Y,46908
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNI1V8H1[0]:A,9986
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNI1V8H1[0]:B,845
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNI1V8H1[0]:C,9891
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNI1V8H1[0]:Y,845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:CLK,2838
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:D,47913
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:EN,47692
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_enable:Q,2838
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[24]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[24]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[24]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[24]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_52:A,42157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_52:B,42053
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_52:C,42035
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_52:Y,42035
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[10]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[10]:CLK,8270
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[10]:D,7834
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[10]:Q,8270
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[2]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[2]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[2]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[2]:Q,10426
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_8:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_8:IPB,
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[0]:CLK,9453
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[0]:D,11367
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[0]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[0]:Q,9453
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_9:IPENn,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_25:B,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_25:C,11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_25:IPB,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_25:IPC,11309
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[12]:A,40132
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[12]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[12]:Y,40132
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2:A,47015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2:B,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2:C,47842
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2:D,46844
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n2_i_m2:Y,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[29]:CLK,44918
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[29]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[29]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[29]:Q,44918
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_6_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DM_RDQS_0_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[4]:A,40635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[4]:B,47013
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[4]:C,45999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[4]:Y,40635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[21]:SLn,45312
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNO[63]:B,8870
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNO[63]:C,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNO[63]:D,9994
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNO[63]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNO[63]:S,7893
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_1_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_1_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_BA_1_PAD/U_IOPAD:PAD,
UART_IF_0/COREUART_0/CUARTO1I[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[3]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[3]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[3]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[3]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:CLK0,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:CLK1,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:CLK2,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:CLK3,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL2,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GPD0_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GPD1_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GPD2_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GPD3_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:LOCK,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_HOLD_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_SEL,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_HOLD_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_SEL,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_HOLD_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_SEL,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_HOLD_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_SEL,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[2],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[3],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[4],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[5],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[6],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[7],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PCLK,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PENABLE,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_ARST_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_BYPASS_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_POWERDOWN_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PRESET_N,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PSEL,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[0],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[1],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[2],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[3],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[4],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[5],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[6],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[7],
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:PWRITE,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:RCOSC_25_50MHZ,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[13]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[13]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[13]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[13]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[13]:Y,43073
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[5]:A,46964
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[5]:B,46907
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[5]:C,43375
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[5]:D,46488
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[5]:Y,43375
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select4:A,47922
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select4:B,47852
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/mss_ready_select4:Y,47852
MDDR_Demo_top_0/AXI_IF_0/ARADDR[25]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[25]:CLK,-1430
MDDR_Demo_top_0/AXI_IF_0/ARADDR[25]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[25]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[25]:Q,-1430
UART_IF_0/UART_IF_FSM_0/RAM_WD[26]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[26]:CLK,11182
UART_IF_0/UART_IF_FSM_0/RAM_WD[26]:D,3922
UART_IF_0/UART_IF_FSM_0/RAM_WD[26]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[26]:Q,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_24:C,11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_24:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_24:IPC,11335
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[5]:CLK,8273
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[5]:D,7914
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[5]:Q,8273
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_30:A,43107
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_30:B,43079
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_30:IPA,43107
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_30:IPB,43079
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_33:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_33:IPC,
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[2]:A,10510
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[2]:B,10406
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[2]:C,9295
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l_ns_0[2]:Y,9295
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_32_0_a6:A,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_32_0_a6:B,44716
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_32_0_a6:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[0]:CLK,47923
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[0]:EN,43344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_soft_reset[0]:Q,47923
UART_IF_0/UART_IF_FSM_0/fsm_RNO[12]:A,8525
UART_IF_0/UART_IF_FSM_0/fsm_RNO[12]:B,7449
UART_IF_0/UART_IF_FSM_0/fsm_RNO[12]:C,10342
UART_IF_0/UART_IF_FSM_0/fsm_RNO[12]:D,9118
UART_IF_0/UART_IF_FSM_0/fsm_RNO[12]:Y,7449
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[63]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[63]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[63]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[63]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[63]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[13]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[13]:CLK,25541
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[13]:D,25236
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[13]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[13]:Q,25541
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:CLK,16983
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:D,17658
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[10]:Q,16983
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[19]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[19]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[19]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[19]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[3]:A,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[3]:B,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[3]:Y,38431
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_282:A,24528
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_282:B,25306
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_282:IPA,24528
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_282:IPB,25306
UART_IF_0/UART_IF_FSM_0/fsm[23]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[23]:CLK,9328
UART_IF_0/UART_IF_FSM_0/fsm[23]:D,8261
UART_IF_0/UART_IF_FSM_0/fsm[23]:Q,9328
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[4]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[4]:CLK,7652
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[4]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[4]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[4]:Q,7652
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:A,46991
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:B,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:C,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:D,46651
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI17L8D[14]:S,40100
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[13]:A,10510
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[13]:B,9926
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[13]:C,9677
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[13]:D,1978
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[13]:Y,1978
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_13:B,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_13:C,11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_13:IPB,11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_13:IPC,11147
UART_IF_0/UART_IF_FSM_0/RAM_WD[18]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[18]:CLK,11187
UART_IF_0/UART_IF_FSM_0/RAM_WD[18]:D,3906
UART_IF_0/UART_IF_FSM_0/RAM_WD[18]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[18]:Q,11187
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_18:A,45865
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_18:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_18:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[25]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[25]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[25]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[25]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[25]:Y,8813
UART_IF_0/UART_IF_FSM_0/fsm[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[9]:CLK,7656
UART_IF_0/UART_IF_FSM_0/fsm[9]:D,1581
UART_IF_0/UART_IF_FSM_0/fsm[9]:Q,7656
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_132:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_address[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[3]:CLK,9140
UART_IF_0/UART_IF_FSM_0/AXI_address[3]:D,9122
UART_IF_0/UART_IF_FSM_0/AXI_address[3]:Q,9140
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[2]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[2]:CLK,7482
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[2]:D,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[2]:Q,7482
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_235:A,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_235:B,-1458
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_235:IPA,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_235:IPB,-1458
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIR2PB1[0]:B,10131
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIR2PB1[0]:FCI,8730
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIR2PB1[0]:FCO,8730
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIR2PB1[0]:S,8922
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:B,8037
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:C,9416
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:D,9149
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI8M929[9]:S,8757
MDDR_Demo_top_0/AXI_IF_0/AWADDR[9]:CLK,-1484
MDDR_Demo_top_0/AXI_IF_0/AWADDR[9]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[9]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[9]:Q,-1484
UART_IF_0/UART_IF_FSM_0/fsm[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[5]:CLK,8143
UART_IF_0/UART_IF_FSM_0/fsm[5]:D,9367
UART_IF_0/UART_IF_FSM_0/fsm[5]:Q,8143
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[7]:SLn,45312
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[54]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[54]:CLK,10136
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[54]:D,8037
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[54]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[54]:Q,10136
MDDR_Demo_top_0/AXI_IF_0/WDATA[56]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[56]:CLK,-1622
MDDR_Demo_top_0/AXI_IF_0/WDATA[56]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[56]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[56]:Q,-1622
UART_IF_0/UART_IF_FSM_0/AXI_address[15]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[15]:CLK,9161
UART_IF_0/UART_IF_FSM_0/AXI_address[15]:D,17
UART_IF_0/UART_IF_FSM_0/AXI_address[15]:Q,9161
UART_IF_0/UART_IF_FSM_0/AXI_address[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[10]:CLK,9081
UART_IF_0/UART_IF_FSM_0/AXI_address[10]:D,92
UART_IF_0/UART_IF_FSM_0/AXI_address[10]:Q,9081
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[2]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[2]:B,45978
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[2]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[2]:D,44733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[2]:Y,40801
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_12:A,45986
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_12:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_12:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_6:A,38884
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_6:B,38836
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_6:C,38762
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_6:D,38668
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/un1_SDATASELInt_20_6:Y,38668
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_29:A,45852
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_29:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_29:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_10:B,45592
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_10:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_10:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_10:S,45768
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_i_o2[1]:A,42779
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_i_o2[1]:B,41769
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_i_o2[1]:C,42654
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o2_i_o2[1]:Y,41769
MDDR_Demo_top_0/AXI_IF_0/AWADDR[2]:CLK,-1406
MDDR_Demo_top_0/AXI_IF_0/AWADDR[2]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[2]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[2]:Q,-1406
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0:A,8426
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0:B,9839
UART_IF_0/UART_IF_FSM_0/un1_fsm_35_0_0:Y,8426
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[5]:B,17696
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[5]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[5]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[5]:S,17738
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_1:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_1:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_259:A,-1506
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_259:B,-1440
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_259:IPA,-1506
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_259:IPB,-1440
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[12]:A,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[12]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[12]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[12]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[12]:Y,45795
MDDR_Demo_top_0/AXI_IF_0/ARADDR[21]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[21]:CLK,-1430
MDDR_Demo_top_0/AXI_IF_0/ARADDR[21]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[21]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[21]:Q,-1430
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_0_sqmuxa_0_a4_0_a2:A,8347
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_0_sqmuxa_0_a4_0_a2:B,9150
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_0_sqmuxa_0_a4_0_a2:Y,8347
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_113:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_113:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:CLK,21435
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:Q,21435
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIH27T4[6]:B,9786
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIH27T4[6]:C,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIH27T4[6]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIH27T4[6]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIH27T4[6]:S,9718
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_9:IPENn,
MDDR_Demo_top_0/AXI_IF_0/WDATA[29]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[29]:CLK,-1582
MDDR_Demo_top_0/AXI_IF_0/WDATA[29]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[29]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[29]:Q,-1582
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_6:B,45528
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_6:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_6:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_6:S,46722
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[59]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[59]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[59]:C,2751
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[59]:Y,2751
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_0_sqmuxa_0_a4_0_a2:A,8270
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_0_sqmuxa_0_a4_0_a2:B,9308
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_0_sqmuxa_0_a4_0_a2:C,9267
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_0_sqmuxa_0_a4_0_a2:Y,8270
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:B,7800
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:C,9954
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:D,9693
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_43:S,7443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_13:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:B,7320
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:C,9474
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:D,9213
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_13:S,7923
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_6_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_6_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_6_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[56]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[56]:CLK,10168
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[56]:D,8005
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[56]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[56]:Q,10168
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNI2D821:A,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNI2D821:B,46899
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNI2D821:C,44848
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNI2D821:Y,44650
MDDR_Demo_top_0/AXI_IF_0/un1_WSTRB_0_sqmuxa_2_i_o3_0_a2:A,9225
MDDR_Demo_top_0/AXI_IF_0/un1_WSTRB_0_sqmuxa_2_i_o3_0_a2:B,1495
MDDR_Demo_top_0/AXI_IF_0/un1_WSTRB_0_sqmuxa_2_i_o3_0_a2:C,9163
MDDR_Demo_top_0/AXI_IF_0/un1_WSTRB_0_sqmuxa_2_i_o3_0_a2:D,9026
MDDR_Demo_top_0/AXI_IF_0/un1_WSTRB_0_sqmuxa_2_i_o3_0_a2:Y,1495
UART_IF_0/UART_IF_FSM_0/AXI_data_in[62]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[62]:CLK,9994
UART_IF_0/UART_IF_FSM_0/AXI_data_in[62]:D,7139
UART_IF_0/UART_IF_FSM_0/AXI_data_in[62]:Q,9994
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_28:C,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_28:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_28:IPC,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0_RNIND5O:A,44652
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0_RNIND5O:B,47425
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0_RNIND5O:C,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0_RNIND5O:D,43138
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5_0_RNIND5O:Y,42103
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0_a3[0]:A,22478
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0_a3[0]:B,22005
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0_a3[0]:C,21779
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_ns_0_a3[0]:Y,21779
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[14]:A,46743
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[14]:B,46686
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[14]:C,43154
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[14]:D,46267
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[14]:Y,43154
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:B,9429
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:C,9360
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:D,7917
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIACUGR[30]:S,-212
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_65:A,47367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_65:B,21523
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_65:IPA,47367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_65:IPB,21523
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[9]:CLK,40658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[9]:D,40180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[9]:Q,40658
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:B,9188
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:C,9145
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:D,7662
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIMKJA9[6]:S,32
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_4:A,41201
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_4:B,46784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_4:C,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_4:D,41218
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_4:Y,39193
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_8:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[13]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[13]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[13]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[13]:Y,40377
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[16]:A,47379
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[16]:B,47511
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[16]:Y,47379
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[25]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[25]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[25]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[25]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[25]:Y,44829
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[8]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[8]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[8]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[8]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2:A,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2:B,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2:C,41465
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2:D,40350
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2:Y,39640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[5]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[5]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[5]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[5]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[7]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[7]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[7]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[7]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[7]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[2]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[2]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[2]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[2]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[2]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[31]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[31]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[31]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[31]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[31]:Y,39151
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:B,7925
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:C,9304
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:D,9043
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI02O03[2]:S,8869
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[14]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[14]:CLK,9496
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[14]:D,8677
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[14]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[14]:Q,9496
UART_IF_0/UART_IF_FSM_0/RAM_WD[35]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[35]:CLK,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[35]:D,3885
UART_IF_0/UART_IF_FSM_0/RAM_WD[35]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[35]:Q,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[11]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[11]:CLK,11166
UART_IF_0/UART_IF_FSM_0/RAM_WD[11]:D,3956
UART_IF_0/UART_IF_FSM_0/RAM_WD[11]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[11]:Q,11166
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2[0]:A,9345
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2[0]:B,9262
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2[0]:C,9203
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2[0]:D,7796
UART_IF_0/UART_IF_FSM_0/cnt_addr_5_i_0_o2[0]:Y,7796
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:B,8645
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:C,10024
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:D,9757
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEI8KL1[47]:S,8149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_1:A,41953
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_1:B,43699
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_1:C,42689
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_1:Y,41953
UART_IF_0/UART_IF_FSM_0/RAM_WD[56]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[56]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[56]:D,3745
UART_IF_0/UART_IF_FSM_0/RAM_WD[56]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[56]:Q,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_24:C,11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_24:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_24:IPC,11335
UART_IF_0/UART_IF_FSM_0/fsm[16]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[16]:CLK,8093
UART_IF_0/UART_IF_FSM_0/fsm[16]:D,1853
UART_IF_0/UART_IF_FSM_0/fsm[16]:Q,8093
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[26]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[26]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[26]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[26]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_267:A,-1586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_267:IPA,-1586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_267:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_192:B,-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_192:C,-1490
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPB,-1472
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPC,-1490
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[8]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[8]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[8]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[8]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[8]:Y,21888
UART_IF_0/UART_IF_FSM_0/cnt_data[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_data[1]:CLK,8270
UART_IF_0/UART_IF_FSM_0/cnt_data[1]:D,791
UART_IF_0/UART_IF_FSM_0/cnt_data[1]:Q,8270
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0:An,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNICL0E/U0:YNn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_119:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[4]:A,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[4]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[4]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[4]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[2]:A,48010
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[2]:B,47916
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[2]:C,47882
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[2]:Y,47882
MDDR_Demo_top_0/AXI_IF_0/WDATA[54]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[54]:CLK,-1558
MDDR_Demo_top_0/AXI_IF_0/WDATA[54]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[54]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[54]:Q,-1558
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_2:A,22366
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_2:B,22212
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_2:Y,22212
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:A,44942
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:B,47692
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:C,42410
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:D,43382
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:Y,42410
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_145:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:CLK,21464
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:Q,21464
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_203:A,-1404
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_203:B,-1470
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_203:IPA,-1404
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_203:IPB,-1470
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[13]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[13]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[13]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[13]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[29]:CLK,42333
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[29]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[29]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[29]:Q,42333
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[16]:A,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[16]:B,45698
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[16]:C,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[16]:D,41448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[16]:Y,40735
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[29]:A,-196
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[29]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[29]:Y,-196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2_0[5]:A,44874
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2_0[5]:B,42943
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2_0[5]:C,44775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i_o2_0[5]:Y,42943
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[8]:A,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[8]:B,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[8]:C,46690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[8]:D,42391
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[8]:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[4]:A,47427
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[4]:B,47559
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[4]:Y,47427
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0:A,8937
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0:B,7990
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0:C,1617
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0:D,1273
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0:Y,1273
MDDR_Demo_top_0/AXI_IF_0/WDATA[15]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[15]:CLK,-1574
MDDR_Demo_top_0/AXI_IF_0/WDATA[15]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[15]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[15]:Q,-1574
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:A,39258
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:B,39210
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:C,38196
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_5:Y,38196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[16]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[16]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[16]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[16]:Q,46992
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/SOFT_RESET_F2M_keep_RNI1CUD:A,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/SOFT_RESET_F2M_keep_RNI1CUD:Y,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[16]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[16]:CLK,9528
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[16]:D,8645
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[16]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[16]:Q,9528
UART_IF_0/UART_IF_FSM_0/un1_fsm_26_i_a4_0_a2_1:A,8069
UART_IF_0/UART_IF_FSM_0/un1_fsm_26_i_a4_0_a2_1:B,7822
UART_IF_0/UART_IF_FSM_0/un1_fsm_26_i_a4_0_a2_1:C,8420
UART_IF_0/UART_IF_FSM_0/un1_fsm_26_i_a4_0_a2_1:Y,7822
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_clk_base:CLK,46846
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled_clk_base:Q,46846
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_21:B,44822
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_21:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_21:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_21:S,44608
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_151:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_151:IPB,
MDDR_Demo_top_0/AXI_IF_0/WDATA[50]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[50]:CLK,-1444
MDDR_Demo_top_0/AXI_IF_0/WDATA[50]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[50]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[50]:Q,-1444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[22]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[22]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[22]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[22]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3_1_0:A,46193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3_1_0:B,45256
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3_1_0:C,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3_1_0:D,44588
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3_1_0:Y,44588
MDDR_Demo_top_0/AXI_IF_0/WDATA[53]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[53]:CLK,-1577
MDDR_Demo_top_0/AXI_IF_0/WDATA[53]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[53]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[53]:Q,-1577
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[15]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[15]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[15]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[15]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[15]:Y,43758
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[24]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[24]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[24]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[24]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_19:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_19:IPB,
MDDR_Demo_top_0/AXI_IF_0/AWADDR[29]:CLK,-1409
MDDR_Demo_top_0/AXI_IF_0/AWADDR[29]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[29]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[29]:Q,-1409
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_28:C,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_28:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_28:IPC,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_6:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[14]:CLK,43041
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[14]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[14]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[14]:Q,43041
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[20]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[20]:D,47476
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[20]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[20]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[24]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[24]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[24]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[24]:Q,48017
MDDR_Demo_top_0/AXI_IF_0/AWADDR[19]:CLK,-1470
MDDR_Demo_top_0/AXI_IF_0/AWADDR[19]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[19]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[19]:Q,-1470
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[9]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[9]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[9]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[9]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[9]:Y,43073
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:A,-1685
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:B,-1380
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:C,12563
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPA,-1685
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPB,-1380
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPC,12563
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:B,8773
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:C,10152
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:D,9885
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIQHM1V1[55]:S,8021
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[0]:A,47315
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[0]:B,47238
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[0]:C,43706
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[0]:D,46819
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE[0]:Y,43706
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[39]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[39]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[39]:C,2837
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[39]:Y,2837
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_19:A,46079
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_19:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_19:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[33]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[33]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[33]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[33]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[33]:Y,8813
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIB6M92[2]:B,9737
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIB6M92[2]:C,10180
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIB6M92[2]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIB6M92[2]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIB6M92[2]:S,9778
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_108:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_184:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_184:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[9]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[9]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[9]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[9]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[23]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_5_0:A,44245
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_5_0:B,42427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_5_0:C,44240
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_5_0:D,44131
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_5_0:Y,42427
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_31:B,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_31:IPB,11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_31:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[18]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[18]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[18]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[18]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[18]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[23]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[23]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[23]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[23]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:A,17025
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:B,16783
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:C,16720
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:D,16636
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4:Y,16636
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:B,8693
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:C,10072
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:D,9805
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEF75P1[50]:S,8101
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:A,46991
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:B,40260
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:C,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:D,46644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIVD0AC[13]:S,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[20]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[20]:B,45608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[20]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[20]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[20]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_int_sel_0_sqmuxa:A,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_int_sel_0_sqmuxa:B,9387
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/un1_int_sel_0_sqmuxa:Y,8534
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[53]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[53]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[53]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[53]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[53]:Y,8813
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[7]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[7]:CLK,7400
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[7]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[7]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[7]:Q,7400
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[61]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[61]:CLK,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[61]:D,7925
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[61]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[61]:Q,10216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[3]:A,45775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[3]:B,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[3]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[3]:D,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[3]:Y,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_s_29:B,44919
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_s_29:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_s_29:S,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[2]:CLK,42684
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[2]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[2]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[2]:Q,42684
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[13]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[13]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[13]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[13]:Q,11367
UART_IF_0/UART_IF_FSM_0/cnt_1k[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[1]:CLK,7406
UART_IF_0/UART_IF_FSM_0/cnt_1k[1]:D,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k[1]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[1]:Q,7406
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_11:B,11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_11:IPB,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[2]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:D,2844
UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[55]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[11]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[11]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[11]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[11]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[11]:Y,43758
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0_1[19]:A,8506
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0_1[19]:B,8429
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0_1[19]:C,8389
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0_1[19]:D,8306
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2_0_1[19]:Y,8306
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0_INST/U0_RGB1:YL,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_25:B,45832
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_25:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_25:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_25:S,45528
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0_0[9]:A,46037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0_0[9]:B,46939
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0_0[9]:Y,46037
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[24]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[24]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[24]:C,2922
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[24]:Y,2922
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[21]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[21]:CLK,9608
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[21]:D,8565
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[21]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[21]:Q,9608
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[16]:A,2
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[16]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[16]:Y,2
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[1]:A,9042
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[1]:B,1859
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[1]:C,10336
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[1]:D,10235
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_RNO[1]:Y,1859
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_expected_0_sqmuxa_0_a6:A,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_expected_0_sqmuxa_0_a6:B,47637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_expected_0_sqmuxa_0_a6:Y,43149
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:CLK,38762
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:D,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:Q,38762
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[23]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[23]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[23]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[23]:Q,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[8]:A,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[8]:B,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[8]:C,45944
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[8]:Y,45858
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[30]:A,45915
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[30]:B,46118
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[30]:C,46047
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[30]:Y,45915
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[28]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[28]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[28]:C,2973
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[28]:Y,2973
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[22]:A,9964
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[22]:B,10386
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[22]:Y,9964
MDDR_Demo_top_0/AXI_IF_0/WDATA[27]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[27]:CLK,-1635
MDDR_Demo_top_0/AXI_IF_0/WDATA[27]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[27]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[27]:Q,-1635
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6_0_1:A,44699
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6_0_1:B,44640
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6_0_1:C,41763
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6_0_1:D,42584
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a6_0_1:Y,41763
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[14]:A,46011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[14]:B,44880
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[14]:C,44929
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[14]:D,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[14]:Y,40861
UART_IF_0/UART_IF_FSM_0/fsm[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[3]:CLK,9203
UART_IF_0/UART_IF_FSM_0/fsm[3]:D,9122
UART_IF_0/UART_IF_FSM_0/fsm[3]:Q,9203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_29:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1_RNO[1]:A,43197
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1_RNO[1]:B,47876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1_RNO[1]:C,42374
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1_RNO[1]:D,43680
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HTRANS_1_RNO[1]:Y,42374
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3_RNI7DVD1[16]:A,9403
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3_RNI7DVD1[16]:B,9779
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3_RNI7DVD1[16]:C,10212
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3_RNI7DVD1[16]:D,10122
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o3_RNI7DVD1[16]:Y,9403
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[14]:A,47347
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[14]:B,47479
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[14]:Y,47347
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPB,
UART_IF_0/UART_IF_FSM_0/RAM_WD[39]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[39]:CLK,11194
UART_IF_0/UART_IF_FSM_0/RAM_WD[39]:D,3815
UART_IF_0/UART_IF_FSM_0/RAM_WD[39]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[39]:Q,11194
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[11]:A,47393
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[11]:B,47525
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[11]:Y,47393
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[15]:CLK,42099
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[15]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[15]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[15]:Q,42099
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0_1:A,46045
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0_1:B,45999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0_1:C,42850
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0_1:D,44598
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_0_1:Y,42850
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_4_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:CLK,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:Q,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[16]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_0:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_172:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_172:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_12_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[7]:A,47360
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[7]:B,47492
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[7]:Y,47360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_275:A,-1414
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_275:B,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_275:IPA,-1414
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_275:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_46:A,42349
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_46:B,42245
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_46:C,42227
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_46:Y,42227
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_pause_count_0_sqmuxa_1_0_a6_0_o2:A,42189
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_pause_count_0_sqmuxa_1_0_a6_0_o2:B,42112
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_pause_count_0_sqmuxa_1_0_a6_0_o2:C,41027
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_pause_count_0_sqmuxa_1_0_a6_0_o2:D,41982
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_pause_count_0_sqmuxa_1_0_a6_0_o2:Y,41027
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:ALn,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:CLK,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:Q,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0_o2[1]:A,42258
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0_o2[1]:B,42223
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0_o2[1]:C,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0_o2[1]:D,42029
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un15_i_0_o2[1]:Y,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[7]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[7]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[7]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[7]:Q,46058
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_23:B,43093
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_23:IPB,43093
UART_IF_0/UART_IF_FSM_0/option[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/option[1]:CLK,8677
UART_IF_0/UART_IF_FSM_0/option[1]:D,8313
UART_IF_0/UART_IF_FSM_0/option[1]:EN,10779
UART_IF_0/UART_IF_FSM_0/option[1]:Q,8677
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14:A,24121
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14:B,9446
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14:C,23023
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14:D,23114
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14:Y,9446
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:B,7592
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:C,9746
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:D,9485
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_30:S,7651
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:CLK,21495
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:Q,21495
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_2:A,42266
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_2:B,43252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_2:C,37650
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_2:D,41027
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_2:Y,37650
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_93:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[20]:A,-58
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[20]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[20]:Y,-58
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[3]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[3]:CLK,25111
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[3]:D,25176
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[3]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[3]:Q,25111
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[24]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[24]:CLK,47118
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[24]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[24]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[24]:Q,47118
UART_IF_0/UART_IF_FSM_0/AXI_data_out[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[0]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[0]:D,3944
UART_IF_0/UART_IF_FSM_0/AXI_data_out[0]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[0]:Q,9443
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[3]:A,46915
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[3]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[3]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[3]:Y,41092
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIO4QC6[6]:B,10227
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIO4QC6[6]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIO4QC6[6]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIO4QC6[6]:S,7914
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_4:B,44550
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_4:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_4:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_4:S,44992
UART_IF_0/UART_IF_FSM_0/cnt_1k[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[5]:CLK,7328
UART_IF_0/UART_IF_FSM_0/cnt_1k[5]:D,9671
UART_IF_0/UART_IF_FSM_0/cnt_1k[5]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[5]:Q,7328
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:CLK,38752
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:Q,38752
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_23:B,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_23:IPB,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_23:IPC,
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[0]:A,8576
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[0]:B,10396
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[0]:C,8356
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[0]:Y,8356
UART_IF_0/UART_IF_FSM_0/AXI_data_out[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[1]:CLK,9443
UART_IF_0/UART_IF_FSM_0/AXI_data_out[1]:D,3465
UART_IF_0/UART_IF_FSM_0/AXI_data_out[1]:EN,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out[1]:Q,9443
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[62]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[62]:CLK,10216
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[62]:D,7909
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[62]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[62]:Q,10216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:A,43040
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:B,42003
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:C,42945
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:D,42684
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_9:FCO,41987
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_3_1[0]:A,8232
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_3_1[0]:B,7783
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_3_1[0]:C,8182
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_3_1[0]:D,8088
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_3_1[0]:Y,7783
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_21:A,46096
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_21:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_21:Y,43758
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[27]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[27]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[27]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[27]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_17:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_17:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[15]:A,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[15]:B,45714
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[15]:C,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[15]:D,41448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[15]:Y,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_20_i_a6:A,45037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_20_i_a6:B,44996
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_20_i_a6:C,44895
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_20_i_a6:D,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_20_i_a6:Y,44821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[18]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[18]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[18]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[18]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[18]:Y,39098
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_25:IPCLKn,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[22]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[22]:CLK,9624
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[22]:D,8549
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[22]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[22]:Q,9624
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_81:A,21443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_81:IPA,21443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_81:IPB,
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[7]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[7]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[7]:D,9237
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[7]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[7]:Q,10426
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[28]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[12]:SLn,45312
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[5]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[5]:CLK,9352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[5]:D,8821
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[5]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[5]:Q,9352
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_6:C,10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_6:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_6:IPC,10875
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[12]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[12]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[12]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[12]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_address[31]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[31]:CLK,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[31]:D,-228
UART_IF_0/UART_IF_FSM_0/AXI_address[31]:Q,9360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_150:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_150:IPB,
UART_IF_0/UART_IF_FSM_0/cnt_1k[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[6]:CLK,7373
UART_IF_0/UART_IF_FSM_0/cnt_1k[6]:D,9656
UART_IF_0/UART_IF_FSM_0/cnt_1k[6]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[6]:Q,7373
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[15]:A,19316
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[15]:B,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[15]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[15]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[15]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_0:A,45538
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_0:B,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_0:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_0:Y,46016
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_4:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_4:IPC,
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[0]:CLK,8590
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[0]:D,11347
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[0]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTI1Il[0]:Q,8590
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_28:B,44934
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_28:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_28:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_28:S,44608
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_25:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_258:A,-1431
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_258:B,-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_258:IPA,-1431
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_258:IPB,-1562
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[31]:A,43124
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[31]:B,43288
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[31]:C,43216
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[31]:Y,43124
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[51]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[51]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[51]:C,2946
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[51]:Y,2946
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[6]:A,10398
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[6]:B,10426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[6]:C,8181
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[6]:D,10134
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_i[6]:Y,8181
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[0]:A,40552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[0]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[0]:Y,40552
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[26]:CLK,42516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[26]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[26]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[26]:Q,42516
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_0:A,45922
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_0:B,43744
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_0:Y,43744
MDDR_Demo_top_0/AXI_IF_0/WDATA[45]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[45]:CLK,-1458
MDDR_Demo_top_0/AXI_IF_0/WDATA[45]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[45]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[45]:Q,-1458
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[1]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[1]:D,47765
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[1]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[1]:Q,46105
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:B,7688
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:C,9842
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:D,9581
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_36:S,7555
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:B,8821
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:C,10200
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:D,9939
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6VPI22[58]:S,7973
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[13]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[13]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[13]:D,25236
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[13]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[13]:Q,21888
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[13]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[13]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[13]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[13]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[16]:A,43124
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[16]:B,43011
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[16]:C,43016
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[16]:Y,43011
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[2]:A,8352
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[2]:B,8304
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[2]:C,8250
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[2]:D,8143
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_a2_2[2]:Y,8143
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:A,46998
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:B,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:C,46866
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:D,43578
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount_RNO[15]:S,40084
UART_IF_0/UART_IF_FSM_0/fsm_RNIQU0E1[5]:A,10195
UART_IF_0/UART_IF_FSM_0/fsm_RNIQU0E1[5]:B,10103
UART_IF_0/UART_IF_FSM_0/fsm_RNIQU0E1[5]:C,3662
UART_IF_0/UART_IF_FSM_0/fsm_RNIQU0E1[5]:D,9987
UART_IF_0/UART_IF_FSM_0/fsm_RNIQU0E1[5]:Y,3662
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[11]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[5]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[5]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[5]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[5]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[11]:A,46796
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[11]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[11]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[11]:Y,41092
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[8]:A,122
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[8]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[8]:Y,122
MDDR_Demo_top_0/AXI_IF_0/AWADDR[7]:CLK,-1404
MDDR_Demo_top_0/AXI_IF_0/AWADDR[7]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[7]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[7]:Q,-1404
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_29:A,43375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_29:B,43272
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_29:IPA,43375
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_29:IPB,43272
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNILPLN1[4]:A,46856
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNILPLN1[4]:B,46806
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNILPLN1[4]:C,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNILPLN1[4]:Y,45719
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[10]:CLK,40462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[10]:D,40164
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[10]:Q,40462
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:B,7832
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:C,9986
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:D,9725
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_45:S,7411
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:B,7768
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:C,9922
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:D,9661
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_41:S,7475
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_6:C,10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_6:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_6:IPC,10875
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:CLK,44694
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:D,39252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[15]:Q,44694
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:B,7352
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:C,9506
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:D,9245
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_15:S,7891
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:B,7288
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:C,9448
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:D,9181
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_11:S,7955
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc:Q,18769
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[3]:CLK,7522
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[3]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[3]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[3]:Q,7522
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_99:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_99:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[9]:A,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[9]:B,43754
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a2[9]:Y,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[23]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[23]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[23]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[23]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[23]:Y,44829
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[39]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[39]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[39]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[39]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[39]:Y,8813
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_23:B,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_23:IPB,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_23:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[23]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[23]:D,47428
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[23]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[23]:Q,46105
UART_IF_0/UART_IF_FSM_0/AXI_address[26]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[26]:CLK,9344
UART_IF_0/UART_IF_FSM_0/AXI_address[26]:D,-148
UART_IF_0/UART_IF_FSM_0/AXI_address[26]:Q,9344
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc:Q,18769
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3:A,44588
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3:B,43197
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3:C,46905
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3:D,43830
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_44_i_0_a3:Y,43197
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25_1:A,46068
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25_1:B,45991
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25_1:Y,45991
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[21]:A,47205
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[21]:B,47155
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[21]:C,43616
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[21]:D,46754
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[21]:Y,43616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_185:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_185:IPB,
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI1CJ07[8]:B,10259
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI1CJ07[8]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI1CJ07[8]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNI1CJ07[8]:S,7866
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:A,-1635
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:B,-1513
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:C,-1469
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPA,-1635
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPB,-1513
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPC,-1469
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[15]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[15]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[15]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[15]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[15]:Y,21888
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[56]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[56]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[56]:C,2767
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[56]:Y,2767
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[0]:CLK,7943
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[0]:D,2861
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[0]:Q,7943
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:CLK,40050
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:D,45982
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:Q,40050
UART_IF_0/UART_IF_FSM_0/RAM_WD[5]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[5]:CLK,11163
UART_IF_0/UART_IF_FSM_0/RAM_WD[5]:D,3873
UART_IF_0/UART_IF_FSM_0/RAM_WD[5]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[5]:Q,11163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[18]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[18]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[18]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[18]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[18]:Y,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:CLK,44758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[19]:Q,44758
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[0]:A,19403
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[0]:B,20826
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[0]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[0]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[0]:Y,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[10]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[10]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[10]:D,25164
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[10]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[10]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:CLK,46686
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:Q,46686
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[6]:A,46876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[6]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[6]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[6]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[24]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[24]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[24]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[24]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[24]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[31]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[31]:B,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[31]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[31]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[31]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[59]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[59]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[59]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[59]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[59]:Y,8813
UART_IF_0/UART_IF_FSM_0/cnt_1k[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_1k[4]:CLK,7536
UART_IF_0/UART_IF_FSM_0/cnt_1k[4]:D,9686
UART_IF_0/UART_IF_FSM_0/cnt_1k[4]:EN,9403
UART_IF_0/UART_IF_FSM_0/cnt_1k[4]:Q,7536
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[22]:CLK,40767
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[22]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[22]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[22]:Q,40767
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:B,9364
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:C,9328
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:D,7838
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIJGINL[25]:S,-133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[13]:CLK,42083
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[13]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[13]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[13]:Q,42083
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[12]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[12]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[12]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[12]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[6]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[6]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[6]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[6]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[6]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_62:A,47395
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_62:IPA,47395
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q2:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q2:CLK,47019
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q2:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_spll_lock_q2:Q,47019
UART_IF_0/UART_IF_FSM_0/RAM_WD[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[7]:CLK,11163
UART_IF_0/UART_IF_FSM_0/RAM_WD[7]:D,3910
UART_IF_0/UART_IF_FSM_0/RAM_WD[7]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[7]:Q,11163
UART_IF_0/UART_IF_FSM_0/AXI_data_out[18]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[18]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[18]:D,2928
UART_IF_0/UART_IF_FSM_0/AXI_data_out[18]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[18]:Q,9329
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[2]:CLK,8466
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[2]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[2]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[2]:Q,8466
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[61]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[61]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[61]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[61]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[61]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o6[0]:A,46988
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o6[0]:B,46919
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o6[0]:C,46772
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o6[0]:D,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_o6[0]:Y,41252
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[29]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[29]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[29]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[29]:Y,39224
UART_IF_0/UART_IF_FSM_0/AXI_data_in[40]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[40]:CLK,9645
UART_IF_0/UART_IF_FSM_0/AXI_data_in[40]:D,7491
UART_IF_0/UART_IF_FSM_0/AXI_data_in[40]:Q,9645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:A,46940
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:B,40180
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:C,44614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:D,46564
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNI1IHM7[8]:S,40196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[10]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[10]:D,47636
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[10]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[10]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[22]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[22]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[22]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[22]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[22]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[13]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[13]:CLK,16938
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[13]:D,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[13]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[13]:Q,16938
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[24]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[24]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[24]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[24]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[24]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[0]:A,9042
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[0]:B,2861
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[0]:C,10356
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[0]:D,10259
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNO[0]:Y,2861
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.N_301_i:A,10424
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.N_301_i:B,10376
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.N_301_i:C,8096
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.N_301_i:D,8414
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.N_301_i:Y,8096
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[3]:CLK,42573
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[3]:D,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[3]:Q,42573
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[0]:A,10424
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[0]:B,10383
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[0]:C,7362
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[0]:D,9114
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl_RNO[0]:Y,7362
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:B,7432
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:C,9586
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:D,9325
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_20:S,7811
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_33:A,43425
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_33:B,43183
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_33:IPA,43425
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_33:IPB,43183
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[9]:CLK,6501
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[9]:D,9673
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[9]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[9]:Q,6501
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_11:A,45954
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_11:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_11:Y,43758
UART_IF_0/COREUART_0/CUARTO01/CUARTO1ll.CUARTI0I_9_i_a2_0:A,7665
UART_IF_0/COREUART_0/CUARTO01/CUARTO1ll.CUARTI0I_9_i_a2_0:B,7586
UART_IF_0/COREUART_0/CUARTO01/CUARTO1ll.CUARTI0I_9_i_a2_0:Y,7586
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_10:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[11]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[11]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[11]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[11]:D,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[11]:Y,21888
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:B,8805
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:C,10184
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:D,9923
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI0E3D12[57]:S,7989
UART_IF_0/UART_IF_FSM_0/cnt_addr[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_addr[0]:CLK,9473
UART_IF_0/UART_IF_FSM_0/cnt_addr[0]:D,7903
UART_IF_0/UART_IF_FSM_0/cnt_addr[0]:Q,9473
UART_IF_0/UART_IF_FSM_0/RAM_WD[16]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[16]:CLK,11187
UART_IF_0/UART_IF_FSM_0/RAM_WD[16]:D,3995
UART_IF_0/UART_IF_FSM_0/RAM_WD[16]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[16]:Q,11187
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[31]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[31]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[31]:C,2968
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[31]:Y,2968
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_16:C,11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_16:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_16:IPC,11326
UART_IF_0/COREUART_0/CUARTO01/CUARTllll.CUARTll019_NE_i_a2:A,8590
UART_IF_0/COREUART_0/CUARTO01/CUARTllll.CUARTll019_NE_i_a2:B,7586
UART_IF_0/COREUART_0/CUARTO01/CUARTllll.CUARTll019_NE_i_a2:C,8495
UART_IF_0/COREUART_0/CUARTO01/CUARTllll.CUARTll019_NE_i_a2:D,8373
UART_IF_0/COREUART_0/CUARTO01/CUARTllll.CUARTll019_NE_i_a2:Y,7586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_7:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_7:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[14]:A,32
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[14]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[14]:Y,32
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:A,46956
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:B,40196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:C,44630
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:D,46580
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIBUDF8[9]:S,40180
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_1:A,23244
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_1:B,23114
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_14_1:Y,23114
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:CLK,38836
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:Q,38836
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[21]:CLK,41708
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[21]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[21]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[21]:Q,41708
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[14]:A,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[14]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[14]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[14]:D,46605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[14]:Y,45795
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:B,9220
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:C,9177
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:D,7694
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI67NDB[8]:S,2
UART_IF_0/UART_IF_FSM_0/AXI_data_out[35]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[35]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[35]:D,2907
UART_IF_0/UART_IF_FSM_0/AXI_data_out[35]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[35]:Q,9329
MDDR_Demo_top_0/AXI_IF_0/ARADDR[31]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[31]:CLK,-1458
MDDR_Demo_top_0/AXI_IF_0/ARADDR[31]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[31]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[31]:Q,-1458
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[23]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[23]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[23]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[23]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[23]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL,
UART_IF_0/UART_IF_FSM_0/RAM_WD[32]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[32]:CLK,11218
UART_IF_0/UART_IF_FSM_0/RAM_WD[32]:D,3866
UART_IF_0/UART_IF_FSM_0/RAM_WD[32]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[32]:Q,11218
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[1]:A,10490
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[1]:B,10390
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[1]:C,8313
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[1]:Y,8313
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_clk_base:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_clk_base:CLK,46976
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_clk_base:D,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif1_core_clk_base:Q,46976
UART_IF_0/UART_IF_FSM_0/RAM_WEN_RNO:A,10402
UART_IF_0/UART_IF_FSM_0/RAM_WEN_RNO:B,10312
UART_IF_0/UART_IF_FSM_0/RAM_WEN_RNO:C,10260
UART_IF_0/UART_IF_FSM_0/RAM_WEN_RNO:Y,10260
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:B,8149
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:C,9528
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:D,9261
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIKK98H[16]:S,8645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[3]:A,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[3]:B,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[3]:C,45833
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[3]:Y,45780
UART_IF_0/UART_IF_FSM_0/RAM_WD[23]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[23]:CLK,11197
UART_IF_0/UART_IF_FSM_0/RAM_WD[23]:D,3792
UART_IF_0/UART_IF_FSM_0/RAM_WD[23]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[23]:Q,11197
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_153:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_153:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CAS_N_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CAS_N_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CAS_N_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[21]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[21]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[21]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[21]:Q,11367
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIEC0D4[6]:B,9753
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIEC0D4[6]:C,10190
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIEC0D4[6]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIEC0D4[6]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIEC0D4[6]:S,9718
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[2]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[2]:CLK,47553
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[2]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[2]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[2]:Q,47553
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_121:IPA,
UART_IF_0/UART_IF_FSM_0/fsm[21]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[21]:CLK,7442
UART_IF_0/UART_IF_FSM_0/fsm[21]:D,9882
UART_IF_0/UART_IF_FSM_0/fsm[21]:Q,7442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_3:B,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_3:IPB,11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_3:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[6]:B,17712
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[6]:FCI,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[6]:FCO,17610
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr_cry[6]:S,17722
UART_IF_0/UART_IF_FSM_0/AXI_data_out[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[8]:CLK,9236
UART_IF_0/UART_IF_FSM_0/AXI_data_out[8]:D,2909
UART_IF_0/UART_IF_FSM_0/AXI_data_out[8]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[8]:Q,9236
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[61]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[61]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[61]:C,2902
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[61]:Y,2902
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_4:B,45496
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_4:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_4:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_4:S,46754
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[22]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[22]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[22]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[22]:Y,46645
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o2:A,8351
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o2:B,8260
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o2:C,8196
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o2:D,8096
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m21_i_o2:Y,8096
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/POWER_ON_RESET_N_q1:Q,48867
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[1]:CLK,10300
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[1]:D,9964
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[1]:Q,10300
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_19:B,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_19:C,11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_19:IPB,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_19:IPC,11313
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[5]:CLK,7393
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[5]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[5]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[5]:Q,7393
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[4]:CLK,39724
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[4]:D,40260
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[4]:Q,39724
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[8]:A,45811
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[8]:B,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[8]:C,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[8]:D,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[8]:Y,40861
MDDR_Demo_top_0/AXI_IF_0/AWVALID:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/AWVALID:CLK,-1986
MDDR_Demo_top_0/AXI_IF_0/AWVALID:D,9944
MDDR_Demo_top_0/AXI_IF_0/AWVALID:EN,2597
MDDR_Demo_top_0/AXI_IF_0/AWVALID:Q,-1986
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[1]:CLK,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[1]:D,11367
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[1]:EN,10180
UART_IF_0/COREUART_0/CUARTIO1/CUARTIl0l[1]:Q,7307
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:B,7952
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:C,10114
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:D,9853
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_53:S,7283
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[36]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[36]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[36]:C,2669
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[36]:Y,2669
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_25:B,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_25:C,11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_25:IPB,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_25:IPC,11309
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_7:A,45974
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_7:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_7:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[30]:A,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[30]:B,47025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO_0[30]:Y,38431
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_21:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_21:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_21:IPC,
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[0]:CLK,8590
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[0]:D,8356
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[0]:Q,8590
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:B,7528
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:C,9682
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:D,9421
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_26:S,7715
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]:CLK,40794
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]:D,45379
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]:EN,47918
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]:Q,40794
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_1:B,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_1:IPB,11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_1:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_266:A,-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_266:IPA,-1435
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_266:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_2:A,45011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_2:B,44103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_2:C,44557
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_2:D,41201
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_2:Y,41201
UART_IF_0/COREUART_0/CUARTO1I[6]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[6]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[6]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[6]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[6]:Q,11367
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIOCA42[2]:B,10211
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIOCA42[2]:C,9641
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIOCA42[2]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIOCA42[2]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIOCA42[2]:S,9710
UART_IF_0/UART_IF_FSM_0/AXI_data_in[0]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[0]:CLK,9011
UART_IF_0/UART_IF_FSM_0/AXI_data_in[0]:D,11340
UART_IF_0/UART_IF_FSM_0/AXI_data_in[0]:EN,9070
UART_IF_0/UART_IF_FSM_0/AXI_data_in[0]:Q,9011
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_142:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[13]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[13]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[13]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[13]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[13]:Y,45795
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_245:A,-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_245:B,-1498
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_245:IPA,-1433
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_245:IPB,-1498
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[3]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[3]:CLK,9366
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[3]:D,9375
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[3]:EN,10238
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[3]:Q,9366
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[3]:CLK,40350
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[3]:D,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[3]:Q,40350
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_159:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_159:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[8]:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[8]:B,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[8]:Y,38412
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2_0[0]:A,8487
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2_0[0]:B,8450
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2_0[0]:C,8348
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2_0[0]:D,8247
UART_IF_0/COREUART_0/CUARTO01/CUARTlIll.CUARTIlIl_3_i_0_a2_0[0]:Y,8247
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i:A,10430
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i:B,10374
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i:C,9353
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i:D,9119
UART_IF_0/COREUART_0/CUARTO01/CUARTO1Il_1_sqmuxa_i:Y,9119
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_27:A,43281
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_27:B,43373
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_27:IPA,43281
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_27:IPB,43373
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[30]:CLK,42908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[30]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[30]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[30]:Q,42908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[26]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[26]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[26]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[26]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[26]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_39:A,43326
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_39:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_39:IPA,43326
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_39:IPB,43848
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_97:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[20]:A,46935
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[20]:B,46878
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[20]:C,43346
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[20]:D,46459
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[20]:Y,43346
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_9:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[10]:CLK,43104
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[10]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[10]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[10]:Q,43104
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[0]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[0]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[0]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[0]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[31]:CLK,42245
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[31]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[31]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[31]:Q,42245
UART_IF_0/UART_IF_FSM_0/RAM_WD[20]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[20]:CLK,11187
UART_IF_0/UART_IF_FSM_0/RAM_WD[20]:D,3904
UART_IF_0/UART_IF_FSM_0/RAM_WD[20]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[20]:Q,11187
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[5]:A,48004
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[5]:B,46014
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[5]:C,47882
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[5]:D,47739
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state_ns[5]:Y,46014
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[11]:A,40148
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[11]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[11]:Y,40148
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[13]:CLK,47519
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[13]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[13]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[13]:Q,47519
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE:A,46876
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE:B,46799
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE:C,43267
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE:D,46380
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE:Y,43267
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_15_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_15_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_15_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/cnt_data[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_data[2]:CLK,9331
UART_IF_0/UART_IF_FSM_0/cnt_data[2]:D,657
UART_IF_0/UART_IF_FSM_0/cnt_data[2]:Q,9331
MDDR_Demo_top_0/AXI_IF_0/AWADDR[24]:CLK,-1438
MDDR_Demo_top_0/AXI_IF_0/AWADDR[24]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[24]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[24]:Q,-1438
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_17:B,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_17:C,11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_17:IPB,11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_17:IPC,11293
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:CLK,-1562
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:EN,9863
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:Q,-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_14:IPA,
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[5]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[5]:CLK,8345
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[5]:D,11360
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[5]:EN,8353
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl[5]:Q,8345
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_13_PAD/U_IOINFF:Y,
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[11]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[11]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[11]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[11]:Q,11367
UART_IF_0/UART_IF_FSM_0/RAM_WD[48]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[48]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[48]:D,3877
UART_IF_0/UART_IF_FSM_0/RAM_WD[48]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[48]:Q,11208
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[18]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[18]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[18]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[18]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[18]:Y,8813
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_6:C,10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_6:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_6:IPC,10875
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[27]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[27]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[27]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[27]:Q,45970
MDDR_Demo_top_0/AXI_IF_0/AWADDR[14]:CLK,-1555
MDDR_Demo_top_0/AXI_IF_0/AWADDR[14]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[14]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[14]:Q,-1555
UART_IF_0/UART_IF_FSM_0/AXI_data_out_439_0_0:A,10270
UART_IF_0/UART_IF_FSM_0/AXI_data_out_439_0_0:B,9593
UART_IF_0/UART_IF_FSM_0/AXI_data_out_439_0_0:C,1570
UART_IF_0/UART_IF_FSM_0/AXI_data_out_439_0_0:Y,1570
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO_0[7]:A,46904
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO_0[7]:B,45038
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO_0[7]:C,46870
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO_0[7]:D,46743
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_RNO_0[7]:Y,45038
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[1]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[1]:B,45897
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[1]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[1]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[1]:Y,40801
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:B,9412
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:C,9360
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:D,7886
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI1DO6P[28]:S,-180
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_12:C,11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_12:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_12:IPC,11143
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[2]:CLK,10280
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[2]:D,9295
UART_IF_0/COREUART_0/CUARTIO1/CUARTlI0l[2]:Q,10280
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_233:A,-1503
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_233:B,-1558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_233:IPA,-1503
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_233:IPB,-1558
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[22]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[22]:B,45576
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[22]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[22]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[22]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[2]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[2]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[2]:D,25070
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[2]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[2]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[14]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[14]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[14]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[14]:Q,45970
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[6]:A,10431
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[6]:B,10393
UART_IF_0/UART_IF_FSM_0/fsm_ns_a4_0_a2[6]:Y,10393
MDDR_Demo_top_0/AXI_IF_0/WDATA[59]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[59]:CLK,-1389
MDDR_Demo_top_0/AXI_IF_0/WDATA[59]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[59]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[59]:Q,-1389
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[13]:CLK,42205
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[13]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[13]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[13]:Q,42205
UART_IF_0/UART_IF_FSM_0/RAM_WD[53]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[53]:CLK,11204
UART_IF_0/UART_IF_FSM_0/RAM_WD[53]:D,3777
UART_IF_0/UART_IF_FSM_0/RAM_WD[53]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[53]:Q,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_21:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_21:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_21:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[13]:SLn,45312
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2_2[0]:A,7631
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2_2[0]:B,7547
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2_2[0]:C,6569
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2_2[0]:D,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_2_2[0]:Y,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[15]:A,10444
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[15]:B,9466
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[15]:C,8277
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[15]:D,8343
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[15]:Y,8277
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_7:A,42573
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_7:B,43670
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_46_0_i_a2_7:Y,42573
UART_IF_0/UART_IF_FSM_0/cnt_addr[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/cnt_addr[1]:CLK,9358
UART_IF_0/UART_IF_FSM_0/cnt_addr[1]:D,7796
UART_IF_0/UART_IF_FSM_0/cnt_addr[1]:Q,9358
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i[1]:A,48010
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i[1]:B,45766
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i[1]:C,47067
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i[1]:D,45999
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_i[1]:Y,45766
UART_IF_0/UART_IF_FSM_0/DATA_OUT[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[3]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[3]:D,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT[3]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[3]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_261:A,-1618
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_261:B,-1430
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_261:IPA,-1618
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_261:IPB,-1430
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[21]:A,42362
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[21]:B,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[21]:C,47849
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[21]:D,47761
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns[21]:Y,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[18]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[18]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[18]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[18]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[18]:Y,44829
UART_IF_0/UART_IF_FSM_0/cnt_data_0_sqmuxa_i_o4_i_a3:A,6129
UART_IF_0/UART_IF_FSM_0/cnt_data_0_sqmuxa_i_o4_i_a3:B,6985
UART_IF_0/UART_IF_FSM_0/cnt_data_0_sqmuxa_i_o4_i_a3:Y,6129
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[3]:A,40261
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[3]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[3]:Y,40261
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:D,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif1_areset_n_rcosc:Q,18769
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[13]:A,45811
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[13]:B,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[13]:C,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[13]:D,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[13]:Y,40861
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[31]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[31]:CLK,9768
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[31]:D,8405
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[31]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[31]:Q,9768
UART_IF_0/UART_IF_FSM_0/AXI_data_out[51]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[51]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[51]:D,2946
UART_IF_0/UART_IF_FSM_0/AXI_data_out[51]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[51]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2_0:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2_0:B,43873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2_0:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_3:A,41151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_3:B,41264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_3:C,39539
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o2_3_3:Y,39539
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[1]:CLK,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[1]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[1]:Q,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[24]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[24]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[24]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[24]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[24]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_15:B,45672
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_15:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_15:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_15:S,45714
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:CLK,21485
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:Q,21485
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:B,8066
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:C,10210
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:D,9987
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_61:S,7155
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[31]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[31]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[31]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[31]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[31]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_51:A,47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_51:B,47383
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_51:IPA,47368
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_51:IPB,47383
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[11]:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[11]:B,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[11]:Y,38412
UART_IF_0/UART_IF_FSM_0/AXI_data_in[17]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[17]:CLK,9277
UART_IF_0/UART_IF_FSM_0/AXI_data_in[17]:D,7859
UART_IF_0/UART_IF_FSM_0/AXI_data_in[17]:Q,9277
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO_0[0]:A,9916
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO_0[0]:B,10332
UART_IF_0/UART_IF_FSM_0/WLEN_1_RNO_0[0]:Y,9916
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[18]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[18]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[18]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[18]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[18]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_14_PAD/U_IOINFF:Y,
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:B,9348
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:C,9312
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:D,7822
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIQTGIK[24]:S,-118
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_29:IPENn,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_25:IPCLKn,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[47]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[47]:CLK,10024
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[47]:D,8149
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[47]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[47]:Q,10024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[9]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[9]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[9]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[9]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[9]:Y,43758
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_25:B,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_25:C,11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_25:IPB,11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_25:IPC,11309
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2[4]:A,42516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2[4]:B,42444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_o2[4]:Y,42444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[13]:CLK,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[13]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[13]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[13]:Q,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[7]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[7]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[7]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[7]:Q,48017
UART_IF_0/UART_IF_FSM_0/fsm[17]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[17]:CLK,8250
UART_IF_0/UART_IF_FSM_0/fsm[17]:D,2024
UART_IF_0/UART_IF_FSM_0/fsm[17]:Q,8250
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25:A,47053
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25:B,46976
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25:C,45991
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25:D,46846
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/next_sm0_state25:Y,45991
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_26:B,45848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_26:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_26:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_26:S,45512
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PADDR_keep_RNIOJLK[3]:A,22360
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PADDR_keep_RNIOJLK[3]:B,22423
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PADDR_keep_RNIOJLK[3]:C,22303
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PADDR_keep_RNIOJLK[3]:Y,22303
UART_IF_0/UART_IF_FSM_0/AXI_data_out[56]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[56]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[56]:D,2767
UART_IF_0/UART_IF_FSM_0/AXI_data_out[56]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[56]:Q,9436
MDDR_Demo_top_0/AXI_IF_0/WLAST_RNO:A,10356
MDDR_Demo_top_0/AXI_IF_0/WLAST_RNO:B,7468
MDDR_Demo_top_0/AXI_IF_0/WLAST_RNO:C,2707
MDDR_Demo_top_0/AXI_IF_0/WLAST_RNO:D,1495
MDDR_Demo_top_0/AXI_IF_0/WLAST_RNO:Y,1495
MDDR_Demo_top_0/AXI_IF_0/RREADY_RNO:A,10424
MDDR_Demo_top_0/AXI_IF_0/RREADY_RNO:Y,10424
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_166:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[30]:CLK,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[30]:D,47316
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[30]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[30]:Q,45986
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[51]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[51]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[51]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[51]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[51]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_138:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_138:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2:A,43028
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2:B,42972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2:C,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_o2:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[13]:CLK,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[13]:D,47588
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[13]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[13]:Q,46015
UART_IF_0/UART_IF_FSM_0/RAM_WD[41]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[41]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[41]:D,3554
UART_IF_0/UART_IF_FSM_0/RAM_WD[41]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[41]:Q,11208
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[3]:A,23282
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[3]:B,23280
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[3]:C,23089
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[3]:D,21881
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv_RNO[3]:Y,21881
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[0]:A,10490
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[0]:B,10390
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[0]:C,8313
UART_IF_0/UART_IF_FSM_0/option_4_a4_0_a2[0]:Y,8313
UART_IF_0/UART_IF_FSM_0/fsm_RNO[1]:A,9958
UART_IF_0/UART_IF_FSM_0/fsm_RNO[1]:B,10406
UART_IF_0/UART_IF_FSM_0/fsm_RNO[1]:C,7322
UART_IF_0/UART_IF_FSM_0/fsm_RNO[1]:D,9802
UART_IF_0/UART_IF_FSM_0/fsm_RNO[1]:Y,7322
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[28]:CLK,43175
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[28]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[28]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[28]:Q,43175
UART_IF_0/UART_IF_FSM_0/fsm[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[8]:CLK,9262
UART_IF_0/UART_IF_FSM_0/fsm[8]:D,9295
UART_IF_0/UART_IF_FSM_0/fsm[8]:Q,9262
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:B,8437
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:C,9816
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:D,9549
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIMGCB61[34]:S,8357
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[26]:CLK,43137
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[26]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[26]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[26]:Q,43137
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPC,
UART_IF_0/UART_IF_FSM_0/AXI_address[27]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[27]:CLK,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[27]:D,-164
UART_IF_0/UART_IF_FSM_0/AXI_address[27]:Q,9360
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[6]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[6]:CLK,24670
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[6]:D,25195
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[6]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[6]:Q,24670
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_120:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[37]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[37]:CLK,9597
UART_IF_0/UART_IF_FSM_0/AXI_data_in[37]:D,7539
UART_IF_0/UART_IF_FSM_0/AXI_data_in[37]:Q,9597
UART_IF_0/UART_IF_FSM_0/RAM_WD[50]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[50]:CLK,11208
UART_IF_0/UART_IF_FSM_0/RAM_WD[50]:D,3674
UART_IF_0/UART_IF_FSM_0/RAM_WD[50]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[50]:Q,11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_4:C,10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_4:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_4:IPC,10920
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[15]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[15]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[15]:C,2970
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[15]:Y,2970
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_30:IPENn,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[46]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[46]:CLK,9741
UART_IF_0/UART_IF_FSM_0/AXI_data_in[46]:D,7395
UART_IF_0/UART_IF_FSM_0/AXI_data_in[46]:Q,9741
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[17]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[17]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[17]:C,2968
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[17]:Y,2968
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:B,8709
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:C,10088
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:D,9821
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6ITAQ1[51]:S,8085
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:B,9316
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:C,9273
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:D,7790
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEUD8I[14]:S,-88
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_41:A,43586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_41:B,43787
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_41:IPA,43586
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_41:IPB,43787
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:A,43264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:B,42227
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:C,43169
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:D,42908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_45:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:A,-1480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:B,-1467
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:C,-1444
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPA,-1480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPB,-1467
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPC,-1444
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[26]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[26]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[26]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[26]:Y,39224
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_10:IPENn,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[22]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[22]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[22]:C,2963
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[22]:Y,2963
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[23]:CLK,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[23]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[23]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[23]:Q,40690
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_37:A,43346
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_37:IPA,43346
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2[0]:A,739
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2[0]:B,8331
MDDR_Demo_top_0/AXI_IF_0/burst_cnt_5_i_o2[0]:Y,739
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[1]:A,9588
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[1]:B,8408
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[1]:C,7822
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[1]:D,6129
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[1]:Y,6129
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[6]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[6]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[6]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[6]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[6]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[6]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[25]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[22]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[22]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[22]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[22]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[22]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[28]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[28]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[28]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[28]:Y,39151
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[32]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[32]:CLK,9784
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[32]:D,8389
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[32]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[32]:Q,9784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[9]:CLK,46580
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[9]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[9]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[9]:Q,46580
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_7:A,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_7:B,40462
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_7:C,40418
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_7:D,40350
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_7:Y,40350
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_70:A,42301
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_70:B,42197
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_70:C,42179
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_70:Y,42179
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_3:A,45586
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_3:B,45480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_3:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_3:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_3:S,46770
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:CLK,
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:D,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:EN,9298
UART_IF_0/COREUART_0/CUARTIO1/CUARTll1:Q,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_0:A,44920
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_0:B,41212
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_0:C,41133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_0:D,41052
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_o6_0:Y,41052
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[0]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[0]:B,45994
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[0]:C,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[0]:D,44733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[0]:Y,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[9]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[9]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[9]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[9]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[9]:Y,44829
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[4]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[4]:CLK,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[4]:D,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[4]:EN,8365
UART_IF_0/COREUART_0/CUARTO01/CUARTO0Il[4]:Q,10426
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CLK_PAD/U_IOPADP:OIN_P,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_CLK_PAD/U_IOPADP:PAD_P,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[3]:CLK,42125
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[3]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[3]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[3]:Q,42125
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[48]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[48]:CLK,10040
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[48]:D,8133
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[48]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[48]:Q,10040
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[26]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[26]:B,44560
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[26]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[26]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[26]:Y,40733
UART_IF_0/UART_IF_FSM_0/AXI_address[23]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[23]:CLK,9289
UART_IF_0/UART_IF_FSM_0/AXI_address[23]:D,-103
UART_IF_0/UART_IF_FSM_0/AXI_address[23]:Q,9289
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_28:C,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_28:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_28:IPC,11283
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:B,9405
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:C,7139
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:D,9101
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_6:S,8013
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[4]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[4]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[4]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[4]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[4]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[31]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[31]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[31]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[31]:Q,48017
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_117:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_117:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[14]:A,45842
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[14]:B,45764
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[14]:C,39193
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[14]:D,45614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[14]:Y,39193
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_262:A,-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_262:B,-1539
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_262:IPA,-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_262:IPB,-1539
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIBBE31[2]:A,1080
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIBBE31[2]:B,845
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIBBE31[2]:C,8508
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIBBE31[2]:D,8368
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state_RNIBBE31[2]:Y,845
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[31]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[31]:D,11354
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[31]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[31]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:CLK,46646
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:Q,46646
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNIGVC11[2]:A,41162
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNIGVC11[2]:B,41108
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNIGVC11[2]:C,41027
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_RNIGVC11[2]:Y,41027
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_28:A,42221
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_28:B,42117
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_28:C,42099
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_28:Y,42099
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:B,8197
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:C,9576
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:D,9309
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENJOK[19]:S,8597
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN9DN2[3]:B,10227
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN9DN2[3]:C,9656
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN9DN2[3]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN9DN2[3]:FCO,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNIN9DN2[3]:S,9701
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:CLK,38756
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:EN,44650
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:Q,38756
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[18]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3:A,43016
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3:B,43219
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3:C,43168
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS_i_m3:Y,43016
UART_IF_0/UART_IF_FSM_0/AXI_address[9]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[9]:CLK,9065
UART_IF_0/UART_IF_FSM_0/AXI_address[9]:D,107
UART_IF_0/UART_IF_FSM_0/AXI_address[9]:Q,9065
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[19]:CLK,42149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[19]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[19]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[19]:Q,42149
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[1]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[1]:CLK,24757
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[1]:D,25211
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[1]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[1]:Q,24757
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[20]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[20]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[20]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[20]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[20]:Y,39157
MDDR_Demo_top_0/AXI_IF_0/WDATA[35]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[35]:CLK,-1548
MDDR_Demo_top_0/AXI_IF_0/WDATA[35]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[35]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[35]:Q,-1548
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_85:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_85:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_35:EN,11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_35:IPENn,11414
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[53]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[53]:CLK,10120
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[53]:D,8053
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[53]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[53]:Q,10120
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_198:A,-1406
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B,-1555
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPA,-1406
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB,-1555
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNO[9]:B,10292
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNO[9]:C,9710
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNO[9]:FCI,9611
UART_IF_0/UART_IF_FSM_0/cnt_1k_RNO[9]:S,9611
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[3]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[3]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[3]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[3]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[3]:Y,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[6]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[6]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[6]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[6]:Q,46058
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o2[4]:A,6152
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o2[4]:B,6129
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_o2[4]:Y,6129
MDDR_Demo_top_0/AXI_IF_0/AWADDR[28]:CLK,-1478
MDDR_Demo_top_0/AXI_IF_0/AWADDR[28]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[28]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[28]:Q,-1478
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[50]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[50]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[50]:C,2696
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[50]:Y,2696
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[1]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[1]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[1]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[1]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[1]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_8:A,16938
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_8:B,16903
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_8:C,16821
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_8:D,16720
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/ddr_settled4_8:Y,16720
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPC,
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO:A,10444
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO:B,10386
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO:C,2670
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO:D,10243
MDDR_Demo_top_0/AXI_IF_0/WVALID_RNO:Y,2670
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:B,8325
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:C,9704
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:D,9437
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNI6LI4U[27]:S,8469
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_35:EN,11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_35:IPENn,11414
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[27]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[27]:B,45496
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[27]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[27]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[27]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[6]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[6]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[6]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[6]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[6]:Y,39042
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_m2:A,9533
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_m2:B,9462
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_m2:C,8937
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_m2:D,9257
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_m2:Y,8937
MDDR_Demo_top_0/AXI_IF_0/AWADDR[18]:CLK,-1491
MDDR_Demo_top_0/AXI_IF_0/AWADDR[18]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[18]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[18]:Q,-1491
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:A,8498
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:B,7176
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:C,9330
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:D,9069
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:FCO,7176
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_4_0:Y,8185
MDDR_Demo_top_0/AXI_IF_0/WDATA[18]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[18]:CLK,-1478
MDDR_Demo_top_0/AXI_IF_0/WDATA[18]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[18]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[18]:Q,-1478
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[7]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[7]:B,45816
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[7]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[7]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[7]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[16]:CLK,43087
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[16]:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[16]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[16]:Q,43087
MDDR_Demo_top_0/AXI_IF_0/WDATA[57]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[57]:CLK,-1433
MDDR_Demo_top_0/AXI_IF_0/WDATA[57]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[57]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[57]:Q,-1433
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[22]:A,46915
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[22]:B,46865
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[22]:C,43326
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[22]:D,46460
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[22]:Y,43326
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_IN_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_IN_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWRITE:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWRITE:CLK,46876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWRITE:D,43170
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWRITE:EN,40466
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWRITE:Q,46876
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[0]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[0]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[0]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[0]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[0]:Y,39328
UART_IF_0/UART_IF_FSM_0/AXI_data_out[50]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[50]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[50]:D,2696
UART_IF_0/UART_IF_FSM_0/AXI_data_out[50]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[50]:Q,9329
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B[0]:B,9703
UART_IF_0/UART_IF_FSM_0/fsm_RNI1S1B[0]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNITIIV4[7]:B,9769
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNITIIV4[7]:C,10190
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNITIIV4[7]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNITIIV4[7]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNITIIV4[7]:S,9703
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_24:A,43313
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_24:IPA,43313
UART_IF_0/UART_IF_FSM_0/AXI_data_in[15]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[15]:CLK,9245
UART_IF_0/UART_IF_FSM_0/AXI_data_in[15]:D,7891
UART_IF_0/UART_IF_FSM_0/AXI_data_in[15]:Q,9245
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_7:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_182:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:CLK,37644
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:D,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:EN,44666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:Q,37644
UART_IF_0/UART_IF_FSM_0/AXI_data_in[20]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[20]:CLK,9325
UART_IF_0/UART_IF_FSM_0/AXI_data_in[20]:D,7811
UART_IF_0/UART_IF_FSM_0/AXI_data_in[20]:Q,9325
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_285:A,24558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_285:B,25412
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_285:IPA,24558
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_285:IPB,25412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[27]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[27]:B,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[27]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[27]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[27]:Y,39151
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:CLK,21523
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:D,9406
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:Q,21523
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[13]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[13]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[13]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[13]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[13]:Y,39042
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[13]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[13]:CLK,9480
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[13]:D,8693
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[13]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[13]:Q,9480
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_2:C,10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_2:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_2:IPC,10888
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:B,9332
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:C,9289
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:D,7806
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNI3DFDJ[15]:S,-103
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[2]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[2]:CLK,10242
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[2]:D,9399
UART_IF_0/COREUART_0/CUARTOO1/CUARTO1[2]:Q,10242
UART_IF_0/UART_IF_FSM_0/AXI_data_in[14]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[14]:CLK,9229
UART_IF_0/UART_IF_FSM_0/AXI_data_in[14]:D,7907
UART_IF_0/UART_IF_FSM_0/AXI_data_in[14]:Q,9229
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_123:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_123:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:B,7982
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:C,10146
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:D,9885
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_55:S,7251
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:B,7922
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:C,10082
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:D,9821
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_51:S,7315
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2:A,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2:B,22692
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/state_s0_0_a2:Y,22591
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[0]:CLK,47238
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[0]:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[0]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE_Z[0]:Q,47238
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_24:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_24:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[28]:CLK,42344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[28]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[28]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[28]:Q,42344
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[50]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[50]:CLK,10072
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[50]:D,8101
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[50]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[50]:Q,10072
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:B,8085
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:C,9464
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:D,9197
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIODIIC[12]:S,8709
UART_IF_0/UART_IF_FSM_0/AXI_data_out[48]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[48]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[48]:D,2899
UART_IF_0/UART_IF_FSM_0/AXI_data_out[48]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[48]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[28]:CLK,43103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[28]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[28]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[28]:Q,43103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[1]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[1]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[1]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[1]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[1]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_71:B,21439
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_71:IPB,21439
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[8]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[8]:CLK,44582
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[8]:D,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[8]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[8]:Q,44582
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[18]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[18]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[18]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[18]:Q,11367
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2[12]:A,9384
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2[12]:B,9328
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2[12]:C,9226
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2[12]:D,9118
UART_IF_0/UART_IF_FSM_0/fsm_ns_i_0_a2[12]:Y,9118
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[15]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[15]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[15]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[15]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_data_in[35]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[35]:CLK,9565
UART_IF_0/UART_IF_FSM_0/AXI_data_in[35]:D,7571
UART_IF_0/UART_IF_FSM_0/AXI_data_in[35]:Q,9565
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_273:A,-1486
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_273:B,10344
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_273:IPA,-1486
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_273:IPB,10344
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[19]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[19]:B,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[19]:C,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[19]:D,46637
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[19]:Y,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[11]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[11]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[11]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[11]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[11]:Y,39042
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_28:C,11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_28:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_28:IPC,11283
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_18:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_18:IPB,
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_1:A,9449
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_1:B,9385
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_1:C,7990
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_1:D,9242
UART_IF_0/UART_IF_FSM_0/un1_fsm_50_0_0_1:Y,7990
UART_IF_0/COREUART_0/CUARTIO1/CUARTO10l.CUARTI00l4_i_a3_i:A,10416
UART_IF_0/COREUART_0/CUARTIO1/CUARTO10l.CUARTI00l4_i_a3_i:B,9298
UART_IF_0/COREUART_0/CUARTIO1/CUARTO10l.CUARTI00l4_i_a3_i:C,10300
UART_IF_0/COREUART_0/CUARTIO1/CUARTO10l.CUARTI00l4_i_a3_i:Y,9298
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[18]:CLK,46992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[18]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[18]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[18]:Q,46992
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[2]:A,9466
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[2]:B,10426
UART_IF_0/COREUART_0/CUARTO01/CUARTO0ll.CUARTO0Il_11[2]:Y,9466
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_5[15]:A,7450
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_5[15]:B,7373
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_5[15]:C,7328
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_5[15]:D,7250
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3_5[15]:Y,7250
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[25]:A,47330
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[25]:B,47462
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[25]:Y,47330
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[14]:A,45811
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[14]:B,40861
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[14]:C,47032
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[14]:D,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[14]:Y,40861
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_209:A,-1407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_209:IPA,-1407
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_209:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[4]:A,46600
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[4]:B,46543
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[4]:C,43011
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[4]:D,46124
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[4]:Y,43011
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_14:C,11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_14:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_14:IPC,11121
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[9]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[9]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[9]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[9]:Q,45970
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_9:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3:A,42734
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3:B,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3:C,44499
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_0_3:Y,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[30]:CLK,43169
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[30]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[30]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[30]:Q,43169
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_16:A,42141
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_16:B,42037
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_16:C,42019
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_16:Y,42019
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[11]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[11]:CLK,47525
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[11]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[11]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[11]:Q,47525
UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:D,2968
UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[31]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:CLK,21443
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:Q,21443
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[28]:A,-180
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[28]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[28]:Y,-180
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[6]:ALn,3352
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[6]:CLK,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[6]:D,7914
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0[6]:Q,7802
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_1:A,44872
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_1:B,44928
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_1:C,43468
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_1:D,42821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a6_1:Y,42821
MDDR_Demo_top_0/AXI_IF_0/WDATA[3]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[3]:CLK,-1599
MDDR_Demo_top_0/AXI_IF_0/WDATA[3]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[3]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[3]:Q,-1599
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:CLK,8379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:D,10288
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/psel:Q,8379
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[2]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[2]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[2]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[2]:Y,46645
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[15]:A,8513
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[15]:B,8436
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[15]:C,7328
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[15]:D,7250
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_o3[15]:Y,7250
UART_IF_0/UART_IF_FSM_0/AXI_data_in[34]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[34]:CLK,9549
UART_IF_0/UART_IF_FSM_0/AXI_data_in[34]:D,7587
UART_IF_0/UART_IF_FSM_0/AXI_data_in[34]:Q,9549
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[30]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[30]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[30]:C,3016
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[30]:Y,3016
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[11]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[11]:CLK,17068
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[11]:D,17642
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[11]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[11]:Q,17068
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_1:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[30]:SLn,45312
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[29]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[29]:D,11354
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[29]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[29]:Q,11367
UART_IF_0/UART_IF_FSM_0/AXI_data_in[41]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[41]:CLK,9661
UART_IF_0/UART_IF_FSM_0/AXI_data_in[41]:D,7475
UART_IF_0/UART_IF_FSM_0/AXI_data_in[41]:Q,9661
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_129:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_129:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[16]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[16]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[16]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[16]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[8]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[8]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[8]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[8]:Y,46645
MDDR_Demo_top_0/AXI_IF_0/ARADDR[12]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[12]:CLK,-1478
MDDR_Demo_top_0/AXI_IF_0/ARADDR[12]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[12]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[12]:Q,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_60:A,47420
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_60:IPA,47420
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[26]:CLK,43232
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[26]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[26]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[26]:Q,43232
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[21]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[21]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[21]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[21]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[20]:CLK,43089
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[20]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[20]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[20]:Q,43089
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i:A,45658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i:B,41953
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i:C,41763
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i:D,41448
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i:Y,41448
UART_IF_0/UART_IF_FSM_0/fsm[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[4]:CLK,6985
UART_IF_0/UART_IF_FSM_0/fsm[4]:D,8243
UART_IF_0/UART_IF_FSM_0/fsm[4]:Q,6985
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[26]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[26]:D,47380
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[26]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[26]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[0]:A,43608
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[0]:B,43626
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6[0]:Y,43608
UART_IF_0/UART_IF_FSM_0/AXI_address[28]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[28]:CLK,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[28]:D,-180
UART_IF_0/UART_IF_FSM_0/AXI_address[28]:Q,9360
UART_IF_0/UART_IF_FSM_0/AXI_data_out[36]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[36]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[36]:D,2669
UART_IF_0/UART_IF_FSM_0/AXI_data_out[36]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[36]:Q,9329
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[15]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[15]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[15]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[15]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[10]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[10]:CLK,9432
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[10]:D,8741
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[10]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[10]:Q,9432
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[15]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[15]:CLK,10345
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[15]:D,25185
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[15]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[15]:Q,10345
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_2:C,10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_2:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_2:IPC,10888
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_210:A,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_210:IPA,-1478
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_210:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_7:IPENn,
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_x2[0]:A,10346
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_x2[0]:B,10410
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.SUM_0_x2[0]:Y,10346
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_178:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_13:B,44694
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_13:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_13:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_13:S,44755
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_8:C,10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_8:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_8:IPC,10940
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[3]:A,10477
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[3]:B,9375
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[3]:C,10342
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l_RNO[3]:Y,9375
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[60]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[60]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[60]:C,2831
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[60]:Y,2831
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2[0]:A,45389
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2[0]:B,45305
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2[0]:C,45261
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2[0]:D,43011
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2[0]:Y,43011
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1_RNIQNFL1:A,9299
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1_RNIQNFL1:B,9798
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1_RNIQNFL1:C,10233
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1_RNIQNFL1:D,10142
UART_IF_0/UART_IF_FSM_0/un1_fsm_1_0_a4_i_a2_1_RNIQNFL1:Y,9299
UART_IF_0/UART_IF_FSM_0/AXI_data_out[28]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[28]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[28]:D,2973
UART_IF_0/UART_IF_FSM_0/AXI_data_out[28]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[28]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[11]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[11]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[11]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[11]:Y,46645
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[7]:A,10504
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[7]:B,10390
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[7]:C,10382
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[7]:Y,10382
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[25]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[25]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[25]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[25]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:B,9389
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:C,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:D,9085
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:FCI,7176
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_5:S,8013
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[15]:A,45853
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[15]:B,44755
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[15]:C,44771
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[15]:D,40735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[15]:Y,40735
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_4_iv_i_a2:A,10444
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_4_iv_i_a2:B,10383
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_4_iv_i_a2:C,7307
UART_IF_0/COREUART_0/CUARTIO1/CUARTl10l.CUARTll1_4_iv_i_a2:Y,7307
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[2]:A,45992
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[2]:B,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[2]:C,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[2]:D,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[2]:Y,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[27]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[27]:CLK,42284
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[27]:D,48860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[27]:Q,42284
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[1]:A,41300
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[1]:B,45024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[1]:C,40358
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[1]:D,41058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/count_RNO[1]:Y,40358
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[2]:A,7375
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[2]:B,9426
UART_IF_0/UART_IF_FSM_0/DATA_OUT_9_0_iv_0_a2[2]:Y,7375
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[15]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[15]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[15]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[15]:Q,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[2]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[2]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[2]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[2]:Y,39315
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:B,8101
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:C,9480
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:D,9213
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIC40OD[13]:S,8693
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_6:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_6:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[31]:CLK,43288
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[31]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[31]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[31]:Q,43288
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIL0OG7[10]:B,10291
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIL0OG7[10]:FCI,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIL0OG7[10]:FCO,7802
UART_IF_0/COREUART_0/CUARTOO1/genblk1.CUARTO0_RNIL0OG7[10]:S,7834
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_2[1]:A,41295
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_2[1]:B,40358
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_2[1]:C,46765
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_2[1]:D,44775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_count_i_2[1]:Y,40358
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2_1:A,9194
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2_1:B,9237
UART_IF_0/COREUART_0/CUARTO01/CUARTlOl_1_sqmuxa_0_a2_1:Y,9194
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:B,7909
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:C,9288
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:D,9027
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGG352[1]:S,8870
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_23:B,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_23:IPB,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_23:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[5]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[5]:CLK,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[5]:D,46014
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[5]:Q,47845
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[4]:CLK,47559
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[4]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[4]:EN,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HWDATA[4]:Q,47559
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[13]:A,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[13]:B,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_RNO[13]:Y,38412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[3]:CLK,41982
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[3]:D,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[3]:EN,46908
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count[3]:Q,41982
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[0]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[0]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[0]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[0]:Q,48017
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_10:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[6]:A,45775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[6]:B,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[6]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[6]:D,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[6]:Y,40828
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_34:B,43243
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_34:IPB,43243
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[25]:CLK,42301
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[25]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[25]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[25]:Q,42301
UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:CLK,9971
UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:D,7171
UART_IF_0/UART_IF_FSM_0/AXI_data_in[60]:Q,9971
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[1]:CLK,47247
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[1]:D,45972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[1]:EN,41469
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HSIZE[1]:Q,47247
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_11:EN,11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_11:IPENn,11442
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_10_PAD/U_IOPAD:Y,
UART_IF_0/UART_IF_FSM_0/RAM_WD[13]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[13]:CLK,11166
UART_IF_0/UART_IF_FSM_0/RAM_WD[13]:D,4020
UART_IF_0/UART_IF_FSM_0/RAM_WD[13]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[13]:Q,11166
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[10]:A,40164
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[10]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[10]:Y,40164
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[16]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[16]:CLK,21754
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[16]:D,25273
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[16]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[16]:Q,21754
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[19]:A,47140
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[19]:B,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[19]:C,39463
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[19]:D,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[19]:Y,39098
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:B,9300
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:C,9257
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:D,7774
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIRHC3H[13]:S,-73
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[47]:A,8648
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[47]:B,2020
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[47]:C,9236
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[47]:D,8644
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[47]:Y,2020
MDDR_Demo_top_0/AXI_IF_0/AWADDR[27]:CLK,-1407
MDDR_Demo_top_0/AXI_IF_0/AWADDR[27]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[27]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[27]:Q,-1407
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_12:C,11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_12:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_12:IPC,11143
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[0]:A,10451
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[0]:B,9168
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[0]:C,7903
UART_IF_0/UART_IF_FSM_0/cnt_addr_RNO[0]:Y,7903
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:CLK,21482
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:Q,21482
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[15]:CLK,40742
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[15]:D,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/bytecount[15]:Q,40742
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[9]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[9]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[9]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[9]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[9]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_7:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/CCC_INST/IP_INTERFACE_7:IPC,
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[0]:ALn,3352
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[0]:CLK,7655
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[0]:D,10406
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[0]:EN,10238
UART_IF_0/COREUART_0/CUARTIO1/CUARTll0l[0]:Q,7655
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a2_0_a2:A,43629
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a2_0_a2:B,43659
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa_i_a2_0_a2:Y,43629
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_490_i_i:A,10451
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_490_i_i:B,9399
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_490_i_i:C,10342
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_490_i_i:D,10242
UART_IF_0/COREUART_0/CUARTOO1/CUARTlOI.CUARTO1_3_1.N_490_i_i:Y,9399
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_22:B,45784
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_22:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_22:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_22:S,45576
MDDR_Demo_top_0/AXI_IF_0/AWADDR[17]:CLK,-1590
MDDR_Demo_top_0/AXI_IF_0/AWADDR[17]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[17]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[17]:Q,-1590
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[8]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[8]:CLK,6457
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[8]:D,9688
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[8]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[8]:Q,6457
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_1:IPCLKn,
UART_IF_0/UART_IF_FSM_0/READ_RNO_0:A,10382
UART_IF_0/UART_IF_FSM_0/READ_RNO_0:B,8725
UART_IF_0/UART_IF_FSM_0/READ_RNO_0:C,10274
UART_IF_0/UART_IF_FSM_0/READ_RNO_0:Y,8725
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[14]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[14]:CLK,43136
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[14]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[14]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[14]:Q,43136
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[5]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[5]:CLK,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[5]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[5]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[5]:Q,46058
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[3]:A,19351
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[3]:B,21881
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[3]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[3]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[3]:Y,8534
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:B,7624
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:C,9778
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:D,9517
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_32:S,7619
MDDR_Demo_top_0/AXI_IF_0/WDATA[48]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[48]:CLK,-1647
MDDR_Demo_top_0/AXI_IF_0/WDATA[48]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[48]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[48]:Q,-1647
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[21]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[21]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[21]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[21]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[5]:A,10497
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[5]:B,10420
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[5]:C,9122
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[5]:D,9729
UART_IF_0/UART_IF_FSM_0/AXI_address_RNO[5]:Y,9122
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_30:IPENn,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[10]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[10]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[10]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[10]:Y,39224
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:B,8661
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:C,10040
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:D,9773
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIIVSPM1[48]:S,8133
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[26]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[26]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[26]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[26]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[26]:Q,45970
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNICIEJ3[4]:B,9769
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNICIEJ3[4]:C,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNICIEJ3[4]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNICIEJ3[4]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNICIEJ3[4]:S,9748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[25]:CLK,47839
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[25]:D,48847
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[25]:EN,44214
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[25]:Q,47839
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[24]:A,47997
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[24]:B,47906
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[24]:C,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_0[24]:Y,43271
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[5]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[5]:B,44896
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[5]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[5]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[5]:Y,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[31]:CLK,43216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[31]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[31]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[31]:Q,43216
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_3_sqmuxa_0_a6:A,39264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_3_sqmuxa_0_a6:B,45701
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_3_sqmuxa_0_a6:C,43822
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_3_sqmuxa_0_a6:Y,39264
TX_obuf/U0/U_IOOUTFF:A,
TX_obuf/U0/U_IOOUTFF:Y,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[1]:CLK,9288
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[1]:D,8870
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[1]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[1]:Q,9288
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[28]:A,43011
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[28]:B,43175
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[28]:C,43103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[28]:Y,43011
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[3]:SLn,45312
UART_IF_0/UART_IF_FSM_0/AXI_data_out[30]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[30]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[30]:D,3016
UART_IF_0/UART_IF_FSM_0/AXI_data_out[30]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[30]:Q,9329
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0:A,8218
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0:B,9445
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0:C,7464
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0:D,8270
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_0:Y,7464
UART_IF_0/UART_IF_FSM_0/RAM_WD[46]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[46]:CLK,11217
UART_IF_0/UART_IF_FSM_0/RAM_WD[46]:D,3706
UART_IF_0/UART_IF_FSM_0/RAM_WD[46]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[46]:Q,11217
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[22]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[22]:CLK,44103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[22]:D,46802
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[22]:Q,44103
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[7]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[7]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[7]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[7]:Y,46645
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_0:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/CFG_0:IPC,
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[2]:A,8329
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[2]:B,6173
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[2]:C,9331
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[2]:D,8270
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_1[2]:Y,6173
UART_IF_0/UART_IF_FSM_0/RAM_WD[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[10]:CLK,11176
UART_IF_0/UART_IF_FSM_0/RAM_WD[10]:D,3908
UART_IF_0/UART_IF_FSM_0/RAM_WD[10]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[10]:Q,11176
UART_IF_0/UART_IF_FSM_0/AXI_data_in[57]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[57]:CLK,9923
UART_IF_0/UART_IF_FSM_0/AXI_data_in[57]:D,7219
UART_IF_0/UART_IF_FSM_0/AXI_data_in[57]:Q,9923
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:CLK,46748
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:Q,46748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_16:B,45688
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_16:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_16:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_16:S,45698
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/FIC_2_APB_M_PRESET_N_keep_RNI58GF/U0_RGB1:An,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/FIC_2_APB_M_PRESET_N_keep_RNI58GF/U0_RGB1:YL,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:A,46892
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:B,40132
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:C,44566
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:D,46516
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIFPSB5[5]:S,40244
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[19]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[19]:CLK,42253
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[19]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[19]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[19]:Q,42253
UART_IF_0/UART_IF_FSM_0/AXI_data_in[26]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[26]:CLK,9421
UART_IF_0/UART_IF_FSM_0/AXI_data_in[26]:D,7715
UART_IF_0/UART_IF_FSM_0/AXI_data_in[26]:Q,9421
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[28]:A,47333
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[28]:B,47465
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[28]:Y,47333
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[9]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[9]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[9]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[9]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_data_out[17]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[17]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[17]:D,2968
UART_IF_0/UART_IF_FSM_0/AXI_data_out[17]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[17]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[10]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[10]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[10]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[10]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_55:A,47403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_55:B,47379
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_55:IPA,47403
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_55:IPB,47379
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[0]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[0]:CLK,20826
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[0]:D,25195
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[0]:EN,9446
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/control_reg_1[0]:Q,20826
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[14]:A,45877
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[14]:B,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[14]:C,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[14]:D,45860
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[14]:Y,43073
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[2]:CLK,8306
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[2]:D,9778
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[2]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[2]:Q,8306
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_4:A,48010
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_4:B,47919
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_4:C,47875
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_4:Y,47875
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[19]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[19]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[19]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[19]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[19]:Y,39321
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[53]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[53]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[53]:C,2797
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[53]:Y,2797
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:B,8389
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:C,9768
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:D,9501
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIEKMQ21[31]:S,8405
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[3]:A,10458
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[3]:B,10416
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[3]:C,7409
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[3]:D,8347
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il_RNO[3]:Y,7409
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:B,8597
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:C,9976
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:D,9709
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIENB3I1[44]:S,8197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_35:EN,11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/FF_35:IPENn,11414
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/AXI_data_in[43]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[43]:CLK,9693
UART_IF_0/UART_IF_FSM_0/AXI_data_in[43]:D,7443
UART_IF_0/UART_IF_FSM_0/AXI_data_in[43]:Q,9693
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_8:A,40742
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_8:B,40658
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_8:C,40614
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_8:D,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_i_o2_2_8:Y,40546
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[3]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[3]:CLK,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[3]:D,47748
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[3]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[3]:Q,45986
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[7]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[7]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[7]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[7]:Q,11367
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[1]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[1]:CLK,10164
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[1]:D,9786
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[1]:EN,1426
UART_IF_0/UART_IF_FSM_0/RAM_WADDR[1]:Q,10164
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[9]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[9]:D,47652
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[9]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[9]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[17]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[17]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[17]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[17]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_28:A,43011
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_28:B,43280
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_28:IPA,43011
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_28:IPB,43280
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:CLK,16821
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:D,17786
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[2]:Q,16821
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_14:B,44710
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_14:FCI,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_14:FCO,44480
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un11_d_HADDR_1_cry_14:S,44739
MDDR_Demo_top_0/AXI_IF_0/ARADDR[9]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[9]:CLK,-1618
MDDR_Demo_top_0/AXI_IF_0/ARADDR[9]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[9]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[9]:Q,-1618
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_23:B,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_23:IPB,11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_23:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_98:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_1_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_1_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_1_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[5]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[5]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[5]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[5]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[5]:Y,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:A,46924
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:B,40164
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:C,44598
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:D,46548
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:FCI,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:FCO,40084
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1_RNIP7LT6[7]:S,40212
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_10_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_10_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_10_PAD/U_IOPAD:PAD,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[60]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[60]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[60]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[60]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[60]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[20]:A,46652
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[20]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[20]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[20]:Y,41092
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[8]:A,9519
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[8]:B,9425
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0_0[8]:Y,9425
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[7]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[7]:CLK,25417
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[7]:D,25206
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[7]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[7]:Q,25417
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[2]:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[2]:CLK,48010
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[2]:D,47882
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_state[2]:Q,48010
MDDR_Demo_top_0/AXI_IF_0/WDATA[25]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA[25]:CLK,-1419
MDDR_Demo_top_0/AXI_IF_0/WDATA[25]:D,11360
MDDR_Demo_top_0/AXI_IF_0/WDATA[25]:EN,2188
MDDR_Demo_top_0/AXI_IF_0/WDATA[25]:Q,-1419
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_82:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[1]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[1]:B,40801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[1]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[1]:Y,39224
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_30:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_30:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[10]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[10]:CLK,45970
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[10]:D,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[10]:EN,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/acc[10]:Q,45970
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:A,-1561
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:B,-1657
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:IPA,-1561
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:IPB,-1657
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[23]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[23]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[23]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[23]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[12]:A,47990
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[12]:B,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[12]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[12]:D,39042
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[12]:Y,39042
UART_IF_0/UART_IF_FSM_0/fsm_RNO[9]:A,10500
UART_IF_0/UART_IF_FSM_0/fsm_RNO[9]:B,10406
UART_IF_0/UART_IF_FSM_0/fsm_RNO[9]:C,9693
UART_IF_0/UART_IF_FSM_0/fsm_RNO[9]:D,1581
UART_IF_0/UART_IF_FSM_0/fsm_RNO[9]:Y,1581
UART_IF_0/UART_IF_FSM_0/option[4]:ALn,3352
UART_IF_0/UART_IF_FSM_0/option[4]:CLK,8371
UART_IF_0/UART_IF_FSM_0/option[4]:D,8300
UART_IF_0/UART_IF_FSM_0/option[4]:EN,10779
UART_IF_0/UART_IF_FSM_0/option[4]:Q,8371
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[6]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[6]:CLK,45986
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[6]:D,47700
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[6]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[6]:Q,45986
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_11_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_45:A,43630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_45:IPA,43630
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_45:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a2:A,42915
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a2:B,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a2:C,42909
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a2:D,42762
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1_i_a2:Y,40116
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[29]:CLK,42211
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[29]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[29]:EN,43142
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/mask[29]:Q,42211
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[21]:CLK,44790
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[21]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[21]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[21]:Q,44790
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_3_PAD/U_IOPAD:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:CLK,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:Q,45962
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[15]:SLn,45312
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[15]:CLK,11367
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[15]:D,11347
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[15]:EN,3662
UART_IF_0/UART_IF_FSM_0/READ_ADDRESS[15]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[14]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[14]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[14]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[14]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[14]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_165:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_165:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[42]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[42]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[42]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[42]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[42]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i[5]:A,44207
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i[5]:B,47682
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i[5]:C,42327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i[5]:D,43164
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_i_i[5]:Y,42327
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:CLK,18868
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:Q,18868
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[1]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[1]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[1]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[1]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[20]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[20]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[20]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[20]:Y,46645
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_5:B,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_5:IPB,11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/CFG_5:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[9]:CLK,42069
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[9]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[9]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[9]:Q,42069
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[30]:A,45775
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[30]:B,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[30]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[30]:D,45780
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[30]:Y,40828
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPB,
UART_IF_0/COREUART_0/CUARTO01/CUARTI00:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTI00:CLK,10352
UART_IF_0/COREUART_0/CUARTO01/CUARTI00:D,9376
UART_IF_0/COREUART_0/CUARTO01/CUARTI00:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTI00:Q,10352
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[46]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[46]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[46]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[46]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[46]:Y,8813
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[10]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[10]:CLK,25470
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[10]:D,25164
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[10]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/pwdata[10]:Q,25470
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_q1:ALn,47294
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_q1:D,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif2_core_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2:A,-228
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2:B,8093
UART_IF_0/UART_IF_FSM_0/un1_AXI_data_in_0_sqmuxa_0_a4_0_a2:Y,-228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[27]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[27]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[27]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[27]:Y,46645
UART_IF_0/UART_IF_FSM_0/AXI_data_in[2]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[2]:CLK,9043
UART_IF_0/UART_IF_FSM_0/AXI_data_in[2]:D,11334
UART_IF_0/UART_IF_FSM_0/AXI_data_in[2]:EN,9070
UART_IF_0/UART_IF_FSM_0/AXI_data_in[2]:Q,9043
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_157:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_3_PAD/U_IOPAD:D,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_3_PAD/U_IOPAD:E,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_ADDR_3_PAD/U_IOPAD:PAD,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_208:A,-1426
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_208:B,-1479
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_208:IPA,-1426
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_208:IPB,-1479
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[20]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[20]:CLK,42666
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[20]:D,40507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[20]:Q,42666
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[1]:CLK,8373
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[1]:D,8347
UART_IF_0/COREUART_0/CUARTO01/CUARTl0Il[1]:Q,8373
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2[0]:A,8609
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2[0]:B,8525
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2[0]:C,6389
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2[0]:D,7002
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2[0]:Y,6389
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:B,7464
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:C,9618
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:D,9357
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_22:S,7779
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2_RNO[31]:B,9429
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2_RNO[31]:C,9360
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2_RNO[31]:D,7917
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2_RNO[31]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2_RNO[31]:S,-228
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[23]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[23]:CLK,42181
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[23]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[23]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[23]:Q,42181
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0[15]:A,9365
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0[15]:B,8343
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0[15]:C,9283
UART_IF_0/UART_IF_FSM_0/fsm_ns_0_a2_0[15]:Y,8343
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:CLK,46848
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:D,48840
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:EN,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:Q,46848
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[1]:ALn,3352
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[1]:CLK,7498
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[1]:D,8134
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[1]:EN,11167
UART_IF_0/COREUART_0/CUARTO01/CUARTIlIl[1]:Q,7498
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_20:A,46113
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_20:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_20:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_1_PAD/U_IOINFF:Y,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_26_0:A,47299
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_26_0:B,43072
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_26_0:C,47598
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_26_0:D,47275
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_26_0:Y,43072
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[3]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[3]:CLK,8433
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[3]:D,1691
MDDR_Demo_top_0/AXI_IF_0/burst_cnt[3]:Q,8433
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[4]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[4]:CLK,9163
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[4]:D,874
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[4]:Q,9163
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[16]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[16]:CLK,46080
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[16]:D,47540
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[16]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[16]:Q,46080
UART_IF_0/UART_IF_FSM_0/RAM_WEN:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WEN:CLK,11414
UART_IF_0/UART_IF_FSM_0/RAM_WEN:D,2383
UART_IF_0/UART_IF_FSM_0/RAM_WEN:EN,10260
UART_IF_0/UART_IF_FSM_0/RAM_WEN:Q,11414
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:CLK,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:Q,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[4]:SLn,45312
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[0]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[0]:CLK,43024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[0]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[0]:EN,42873
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/rdata[0]:Q,43024
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[5]:A,46122
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[5]:B,46058
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[5]:C,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[5]:D,45703
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_0[5]:Y,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[28]:A,45883
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[28]:B,44528
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[28]:C,44801
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[28]:D,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO[28]:Y,40733
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[20]:A,10444
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[20]:B,9916
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[20]:C,10369
UART_IF_0/UART_IF_FSM_0/fsm_ns_0[20]:Y,9916
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_21:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_21:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_21:IPC,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_148:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_148:IPB,
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[55]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[55]:CLK,10152
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[55]:D,8021
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[55]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[55]:Q,10152
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[33]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[33]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[33]:C,3017
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[33]:Y,3017
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:B,7736
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:C,9890
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:D,9629
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_39:S,7507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[20]:A,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[20]:B,39157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[20]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv[20]:Y,39098
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[14]:A,40377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[14]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[14]:C,43073
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[14]:Y,40377
UART_IF_0/UART_IF_FSM_0/AXI_address[29]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[29]:CLK,9360
UART_IF_0/UART_IF_FSM_0/AXI_address[29]:D,-196
UART_IF_0/UART_IF_FSM_0/AXI_address[29]:Q,9360
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:A,-1596
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:B,-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:C,-1419
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPA,-1596
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPB,-1494
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPC,-1419
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[49]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[49]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[49]:C,2669
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[49]:Y,2669
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[4]:A,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[4]:B,46015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[4]:C,45944
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_0[4]:Y,45858
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n3_i_m2:A,47015
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n3_i_m2:B,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n3_i_m2:C,47829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n3_i_m2:D,46735
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/pause_count_n3_i_m2:Y,45891
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[22]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[22]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[22]:C,39321
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[22]:D,43823
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_2[22]:Y,39321
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:B,9156
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:C,9113
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:D,7630
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIEAG77[4]:S,62
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO:A,2945
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO:B,10400
MDDR_Demo_top_0/AXI_IF_0/BREADY_RNO:Y,2945
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOINFF:A,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MDDR_DQ_8_PAD/U_IOINFF:Y,
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIU2N46[9]:B,9786
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIU2N46[9]:C,10190
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIU2N46[9]:FCI,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIU2N46[9]:FCO,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR_RNIU2N46[9]:S,9673
UART_IF_0/UART_IF_FSM_0/AXI_data_in[55]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[55]:CLK,9885
UART_IF_0/UART_IF_FSM_0/AXI_data_in[55]:D,7251
UART_IF_0/UART_IF_FSM_0/AXI_data_in[55]:Q,9885
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[29]:A,47368
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[29]:B,47500
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[29]:Y,47368
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[5]:A,47005
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[5]:B,46921
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[5]:C,39328
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[5]:D,39901
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_3[5]:Y,39328
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:B,9108
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:C,9065
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:D,7582
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:FCI,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:FCO,-228
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIHQR24[1]:S,107
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[63]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[63]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[63]:C,2928
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[63]:Y,2928
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[25]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[25]:CLK,43412
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[25]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[25]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins1[25]:Q,43412
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[3]:A,46870
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[3]:B,46813
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[3]:C,43281
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[3]:D,46394
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[3]:Y,43281
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[0]:A,47355
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[0]:B,47487
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[0]:Y,47355
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:CLK,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:EN,43123
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:Q,46008
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/ins2[9]:SLn,45312
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[22]:CLK,11367
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[22]:D,11347
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[22]:EN,3662
UART_IF_0/UART_IF_FSM_0/WRITE_ADDRESS[22]:Q,11367
UART_IF_0/UART_IF_FSM_0/fsm[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/fsm[6]:CLK,9412
UART_IF_0/UART_IF_FSM_0/fsm[6]:D,10393
UART_IF_0/UART_IF_FSM_0/fsm[6]:Q,9412
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[26]:A,-148
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[26]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[26]:Y,-148
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[29]:A,46508
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[29]:B,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[29]:C,47862
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_haddr_fetch[29]:Y,41092
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_2:A,45928
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_2:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_2:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[31]:A,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[31]:B,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[31]:C,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv[31]:Y,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[3]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[3]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[3]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[3]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[12]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[12]:CLK,21888
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[12]:D,25218
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[12]:EN,9224
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/soft_reset_reg[12]:Q,21888
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[9]:A,47014
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[9]:B,46957
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[9]:C,43425
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[9]:D,46538
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[9]:Y,43425
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[8]:A,46775
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[8]:B,45795
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[8]:C,46666
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[8]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[8]:Y,45795
UART_IF_0/UART_IF_FSM_0/AXI_data_out[54]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[54]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[54]:D,2914
UART_IF_0/UART_IF_FSM_0/AXI_data_out[54]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[54]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[23]:A,47194
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[23]:B,47137
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[23]:C,43605
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[23]:D,46718
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[23]:Y,43605
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[12]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[12]:CLK,10399
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[12]:D,25179
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[12]:EN,22591
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/paddr[12]:Q,10399
UART_IF_0/UART_IF_FSM_0/AXI_data_in[54]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[54]:CLK,9869
UART_IF_0/UART_IF_FSM_0/AXI_data_in[54]:D,7267
UART_IF_0/UART_IF_FSM_0/AXI_data_in[54]:Q,9869
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[8]:A,40196
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[8]:B,43848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_bytecount[8]:Y,40196
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_38:A,43616
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_38:IPA,43616
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[5]:A,46788
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[5]:B,45822
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[5]:C,46673
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[5]:D,46572
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a5[5]:Y,45822
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[15]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[15]:CLK,9512
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[15]:D,8661
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[15]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[15]:Q,9512
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[14]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[14]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[14]:C,2919
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[14]:Y,2919
UART_IF_0/UART_IF_FSM_0/AXI_address[16]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[16]:CLK,9177
UART_IF_0/UART_IF_FSM_0/AXI_address[16]:D,2
UART_IF_0/UART_IF_FSM_0/AXI_address[16]:Q,9177
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_14:C,11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_14:IPB,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/CFG_14:IPC,11121
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_214:A,-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_214:IPA,-1562
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_214:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[30]:A,40828
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[30]:B,38431
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[30]:C,46338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[30]:D,42427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR_RNO[30]:Y,38431
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[18]:A,9759
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[18]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[18]:C,2928
UART_IF_0/UART_IF_FSM_0/AXI_data_out_RNO[18]:Y,2928
UART_IF_0/UART_IF_FSM_0/AXI_data_in[21]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[21]:CLK,9341
UART_IF_0/UART_IF_FSM_0/AXI_data_in[21]:D,7795
UART_IF_0/UART_IF_FSM_0/AXI_data_in[21]:Q,9341
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[16]:A,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[16]:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[16]:C,47621
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[16]:D,47327
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc[16]:Y,43758
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[12]:ALn,18663
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[12]:CLK,17025
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[12]:D,17626
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[12]:EN,18707
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/count_ddr[12]:Q,17025
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[29]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[29]:CLK,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[29]:D,47332
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[29]:EN,40690
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_write[29]:Q,46105
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[7]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[7]:CLK,42157
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[7]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[7]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[7]:Q,42157
UART_IF_0/UART_IF_FSM_0/AXI_data_out[52]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[52]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[52]:D,2814
UART_IF_0/UART_IF_FSM_0/AXI_data_out[52]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[52]:Q,9329
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C3/FF_34:IPENn,
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[10]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[10]:CLK,6585
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[10]:D,9657
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[10]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[10]:Q,6585
UART_IF_0/UART_IF_FSM_0/AXI_data_in[48]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[48]:CLK,9773
UART_IF_0/UART_IF_FSM_0/AXI_data_in[48]:D,7363
UART_IF_0/UART_IF_FSM_0/AXI_data_in[48]:Q,9773
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_75:A,21480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_75:B,21441
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_75:IPA,21480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_75:IPB,21441
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[31]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[31]:CLK,42349
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[31]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[31]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[31]:Q,42349
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[1]:A,19362
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[1]:B,20903
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[1]:C,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[1]:D,9188
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/prdata_0_iv[1]:Y,8534
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[6]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[6]:CLK,9368
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[6]:D,8805
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[6]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[6]:Q,9368
MDDR_Demo_top_0/AXI_IF_0/ARADDR[10]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/ARADDR[10]:CLK,-1494
MDDR_Demo_top_0/AXI_IF_0/ARADDR[10]:D,11367
MDDR_Demo_top_0/AXI_IF_0/ARADDR[10]:EN,10110
MDDR_Demo_top_0/AXI_IF_0/ARADDR[10]:Q,-1494
UART_IF_0/UART_IF_FSM_0/AXI_data_in[12]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[12]:CLK,9197
UART_IF_0/UART_IF_FSM_0/AXI_data_in[12]:D,7939
UART_IF_0/UART_IF_FSM_0/AXI_data_in[12]:Q,9197
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[10]:A,47332
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[10]:B,47464
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWDATA[10]:Y,47332
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[26]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[26]:B,45512
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[26]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[26]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[26]:Y,40733
UART_IF_0/UART_IF_FSM_0/rx_en_RNI6LRJ:A,7665
UART_IF_0/UART_IF_FSM_0/rx_en_RNI6LRJ:B,7604
UART_IF_0/UART_IF_FSM_0/rx_en_RNI6LRJ:C,7550
UART_IF_0/UART_IF_FSM_0/rx_en_RNI6LRJ:Y,7550
UART_IF_0/UART_IF_FSM_0/DATA_OUT[7]:ALn,3352
UART_IF_0/UART_IF_FSM_0/DATA_OUT[7]:CLK,11367
UART_IF_0/UART_IF_FSM_0/DATA_OUT[7]:D,8195
UART_IF_0/UART_IF_FSM_0/DATA_OUT[7]:EN,9299
UART_IF_0/UART_IF_FSM_0/DATA_OUT[7]:Q,11367
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0_RNIMLQM:A,42139
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0_RNIMLQM:B,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0_RNIMLQM:C,47377
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_42_i_0_RNIMLQM:Y,41969
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[20]:A,47127
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[20]:B,47050
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[20]:C,40507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[20]:D,46845
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state_ns_a6_0[20]:Y,40507
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[4]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[4]:CLK,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[4]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[4]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[4]:Q,46999
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:A,43056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:B,42019
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:C,42961
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:D,42700
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:FCI,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_state152_0_I_15:FCO,41987
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[30]:A,39285
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[30]:B,46972
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[30]:C,39151
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[30]:Y,39151
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[30]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[30]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[30]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[30]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[30]:Y,8813
MDDR_Demo_top_0/AXI_IF_0/AWLEN[0]:CLK,-1619
MDDR_Demo_top_0/AXI_IF_0/AWLEN[0]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWLEN[0]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWLEN[0]:Q,-1619
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_103:IPA,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_103:IPB,
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[1]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[1]:CLK,47889
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[1]:D,44678
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[1]:EN,43338
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/envm_busy[1]:Q,47889
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[21]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[21]:CLK,42269
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[21]:D,44692
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[21]:EN,43149
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/expected[21]:Q,42269
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5:A,42103
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5:B,46626
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_i_o5:Y,42103
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[27]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[27]:CLK,9704
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[27]:D,8469
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[27]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[27]:Q,9704
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:CLK,44742
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:D,39224
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:EN,37644
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/HADDR[18]:Q,44742
UART_IF_0/UART_IF_FSM_0/AXI_data_in[6]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[6]:CLK,9101
UART_IF_0/UART_IF_FSM_0/AXI_data_in[6]:D,8013
UART_IF_0/UART_IF_FSM_0/AXI_data_in[6]:Q,9101
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[28]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[28]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[28]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[28]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[28]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:B,7816
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:C,9970
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:D,9709
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_44:S,7427
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[4]:A,47056
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[4]:B,39315
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[4]:C,39372
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HWDATA_0_iv_1[4]:Y,39315
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:CLK,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:D,2928
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[63]:Q,9436
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_21:B,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_21:IPB,11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C0/CFG_21:IPC,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:B,7336
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:C,9490
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:D,9229
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_14:S,7907
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_28:B,45880
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_28:FCI,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_28:FCO,45432
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un32_d_HADDR_cry_28:S,45480
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_10:A,45890
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_10:B,43758
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST_RNIG8ST_10:Y,43758
UART_IF_0/UART_IF_FSM_0/AXI_data_out[13]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_out[13]:CLK,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out[13]:D,1978
UART_IF_0/UART_IF_FSM_0/AXI_data_out[13]:EN,1388
UART_IF_0/UART_IF_FSM_0/AXI_data_out[13]:Q,9329
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[16]:A,47109
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[16]:B,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[16]:C,46984
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_acc_1_0[16]:Y,46645
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[5]:A,44829
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[5]:B,45848
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[5]:C,40733
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[5]:D,41457
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/d_HADDR_0_iv_2[5]:Y,40733
MDDR_Demo_top_0/AXI_IF_0/AWADDR[5]:CLK,-1493
MDDR_Demo_top_0/AXI_IF_0/AWADDR[5]:D,11367
MDDR_Demo_top_0/AXI_IF_0/AWADDR[5]:EN,3700
MDDR_Demo_top_0/AXI_IF_0/AWADDR[5]:Q,-1493
UART_IF_0/COREUART_0/CUARTO1I[7]:ALn,3352
UART_IF_0/COREUART_0/CUARTO1I[7]:CLK,11367
UART_IF_0/COREUART_0/CUARTO1I[7]:D,11367
UART_IF_0/COREUART_0/CUARTO1I[7]:EN,11253
UART_IF_0/COREUART_0/CUARTO1I[7]:Q,11367
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[1]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[1]:CLK,8368
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[1]:D,2668
MDDR_Demo_top_0/AXI_IF_0/axi_fsm_current_state[1]:Q,8368
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[50]:A,9053
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[50]:B,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[50]:C,9436
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[50]:D,9329
UART_IF_0/UART_IF_FSM_0/AXI_data_out_13_i_0[50]:Y,8813
UART_IF_0/UART_IF_FSM_0/AXI_data_in[32]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_data_in[32]:CLK,9517
UART_IF_0/UART_IF_FSM_0/AXI_data_in[32]:D,7619
UART_IF_0/UART_IF_FSM_0/AXI_data_in[32]:Q,9517
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[0]:A,8395
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[0]:B,8373
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[0]:C,6129
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[0]:D,7804
UART_IF_0/UART_IF_FSM_0/cnt_data_8_0_o3[0]:Y,6129
UART_IF_0/UART_IF_FSM_0/RAM_WD[24]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_WD[24]:CLK,11182
UART_IF_0/UART_IF_FSM_0/RAM_WD[24]:D,3900
UART_IF_0/UART_IF_FSM_0/RAM_WD[24]:EN,2336
UART_IF_0/UART_IF_FSM_0/RAM_WD[24]:Q,11182
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_3:A,45135
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_3:B,44954
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_3:C,43127
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_3:D,41264
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/un1_state_49_0_a2_3:Y,41264
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_q1:ALn,47845
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_q1:CLK,48867
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/sm0_areset_n_q1:Q,48867
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[17]:A,-13
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[17]:B,9910
UART_IF_0/UART_IF_FSM_0/AXI_address_13_1_a2[17]:Y,-13
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIUPA84[5]:B,9785
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIUPA84[5]:C,10196
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIUPA84[5]:FCI,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIUPA84[5]:FCO,9703
UART_IF_0/UART_IF_FSM_0/RAM_WADDR_RNIUPA84[5]:S,9733
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[2]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[2]:CLK,9304
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[2]:D,8869
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[2]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[2]:Q,9304
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[3]:ALn,3352
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[3]:CLK,7547
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[3]:D,9763
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[3]:EN,9850
UART_IF_0/UART_IF_FSM_0/RAM_RADDR[3]:Q,7547
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:B,7704
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:C,9858
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:D,9597
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_37:S,7539
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0:A,10257
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0:B,10258
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0:C,8365
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0:D,9086
UART_IF_0/COREUART_0/CUARTO01/un1_CUARTI1Il7_1_0_0:Y,8365
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core:ALn,18769
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core:CLK,4897
MDDR_Demo_top_0/MDDR_Demo_0/CORERESETP_0/release_sdif0_core:Q,4897
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[17]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[17]:CLK,48017
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[17]:D,41092
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[17]:EN,40819
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/haddr_fetch[17]:Q,48017
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[10],11281
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[11],11283
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[1],10888
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[2],10920
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[3],10875
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[4],10940
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[5],11143
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[6],11121
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[7],11326
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[8],11353
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ADDR[9],11335
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_BLK[2],11442
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_CLK,7375
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[10],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[11],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[14],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[15],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[16],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[4],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[5],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[6],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[7],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DIN[9],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT[0],7375
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT[1],8195
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:A_WEN[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[10],11236
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[11],11246
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[12],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[13],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[2],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[3],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[4],10999
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[5],11147
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[6],11130
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[7],11293
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[8],11313
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ADDR[9],11309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_BLK[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_BLK[1],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_BLK[2],11414
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[0],11153
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[10],11194
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[11],11217
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[12],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[13],11208
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[14],11204
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[15],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[16],11203
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[17],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[1],11163
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[2],11176
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[3],11166
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[4],11187
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[5],11197
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[6],11182
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[7],11184
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[8],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DIN[9],11218
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DOUT_ARST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DOUT_CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DOUT_EN,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_DOUT_SRST_N,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_WEN[0],
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/INST_RAM1K18_IP:B_WEN[1],
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[28]:ALn,47268
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[28]:CLK,42189
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[28]:D,45736
MDDR_Demo_top_0/MDDR_Demo_0/ConfigMaster_0/state[28]:Q,42189
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_239:A,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_239:B,-1453
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_239:IPA,-1443
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_239:IPB,-1453
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_250:A,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_250:IPA,-1450
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_250:IPB,
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:B,7576
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:C,9730
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:D,9469
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:FCI,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:FCO,7123
UART_IF_0/UART_IF_FSM_0/AXI_data_in_14_cry_29:S,7667
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[44]:ALn,3352
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[44]:CLK,9976
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[44]:D,8197
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[44]:EN,845
MDDR_Demo_top_0/AXI_IF_0/WDATA_int[44]:Q,9976
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:B,8485
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:C,9864
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:D,9597
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:FCI,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:FCO,7893
MDDR_Demo_top_0/AXI_IF_0/WDATA_int_RNIGV2S91[37]:S,8309
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_24:CLK,
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C1/FF_24:IPCLKn,
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_109:IPA,
UART_IF_0/UART_IF_FSM_0/AXI_address[21]:ALn,3352
UART_IF_0/UART_IF_FSM_0/AXI_address[21]:CLK,9257
UART_IF_0/UART_IF_FSM_0/AXI_address[21]:D,-73
UART_IF_0/UART_IF_FSM_0/AXI_address[21]:Q,9257
UART_IF_0/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM_R0C2/FF_31:IPENn,
UART_IF_0/UART_IF_FSM_0/READ:ALn,3352
UART_IF_0/UART_IF_FSM_0/READ:CLK,9170
UART_IF_0/UART_IF_FSM_0/READ:D,10356
UART_IF_0/UART_IF_FSM_0/READ:EN,8725
UART_IF_0/UART_IF_FSM_0/READ:Q,9170
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[6]:A,46696
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[6]:B,46646
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[6]:C,43107
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[6]:D,46238
MDDR_Demo_top_0/MDDR_Demo_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR[6]:Y,43107
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_1:A,8551
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_1:B,7464
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_1:C,8423
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_1:D,8289
UART_IF_0/COREUART_0/CUARTO01/CUARTll0_ns_1_0_.m18_0_a2_1:Y,7464
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:ALn,
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:CLK,21421
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:D,8534
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:EN,23629
MDDR_Demo_top_0/MDDR_Demo_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:Q,21421
MDDR_ADDR[15],
MDDR_ADDR[14],
MDDR_ADDR[13],
MDDR_ADDR[12],
MDDR_ADDR[11],
MDDR_ADDR[10],
MDDR_ADDR[9],
MDDR_ADDR[8],
MDDR_ADDR[7],
MDDR_ADDR[6],
MDDR_ADDR[5],
MDDR_ADDR[4],
MDDR_ADDR[3],
MDDR_ADDR[2],
MDDR_ADDR[1],
MDDR_ADDR[0],
MDDR_BA[2],
MDDR_BA[1],
MDDR_BA[0],
MDDR_DM_RDQS[1],
MDDR_DM_RDQS[0],
MDDR_DQ[15],
MDDR_DQ[14],
MDDR_DQ[13],
MDDR_DQ[12],
MDDR_DQ[11],
MDDR_DQ[10],
MDDR_DQ[9],
MDDR_DQ[8],
MDDR_DQ[7],
MDDR_DQ[6],
MDDR_DQ[5],
MDDR_DQ[4],
MDDR_DQ[3],
MDDR_DQ[2],
MDDR_DQ[1],
MDDR_DQ[0],
MDDR_DQS[1],
MDDR_DQS[0],
DEVRST_N,
MDDR_DQS_TMATCH_0_IN,
RX,
MDDR_CAS_N,
MDDR_CKE,
MDDR_CLK,
MDDR_CLK_N,
MDDR_CS_N,
MDDR_DQS_TMATCH_0_OUT,
MDDR_ODT,
MDDR_RAS_N,
MDDR_RESET_N,
MDDR_WE_N,
TX,
