set_device -family {IGLOO2} -die {M2GL010TS} -speed {-1}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\CCC_0\MDDR_Demo_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\FABOSC_0\MDDR_Demo_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_HPMS\MDDR_Demo_HPMS.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\COREAXI_0\rtl\vlog\core\coreaxi.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo\MDDR_Demo.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\AXI_IF.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\MDDR_Demo_top\MDDR_Demo_top.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\UART_IF\UART_IF.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\component\work\top\top.v}
set_top_level {top}
map_netlist
read_sdc {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\constraint\top_derived_constraints.sdc}
check_constraints {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\constraint\synthesis_sdc_errors.log}
write_fdc {C:\Users\I63442\Desktop\v12.6 updates\Igloo2\DG0534_IGL2_MDDR_Demo_DF_1\Final\m2gl_dg0534_df\Libero_Project\designer\top\synthesis.fdc}
