//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Nov 03 19:33:08 2015
// Version: v11.6 11.6.0.34
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// AXI_LPDDR_Simulation
module AXI_LPDDR_Simulation(
    // Outputs
    RDATA
);

//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [63:0] RDATA;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [63:0]  AXI_testbench_0_DATA_IN;
wire           AXI_testbench_0_READ;
wire   [31:0]  AXI_testbench_0_READ_ADDRESS;
wire   [3:0]   AXI_testbench_0_RLEN;
wire   [3:0]   AXI_testbench_0_WLEN;
wire           AXI_testbench_0_WRITE;
wire   [31:0]  AXI_testbench_0_WRITE_ADDRESS;
wire   [63:0]  MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0;
wire           MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0;
wire           MDDR_Demo_top_0_AXI_RBUSY;
wire           MDDR_Demo_top_0_AXI_WBUSY;
wire           MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK;
wire   [13:0]  MDDR_Demo_top_0_MDDR_ADDR13to0;
wire   [1:0]   MDDR_Demo_top_0_MDDR_BA1to0;
wire           MDDR_Demo_top_0_MDDR_CAS_N;
wire           MDDR_Demo_top_0_MDDR_CKE;
wire           MDDR_Demo_top_0_MDDR_CLK;
wire           MDDR_Demo_top_0_MDDR_CLK_N;
wire           MDDR_Demo_top_0_MDDR_CS_N;
wire           MDDR_Demo_top_0_MDDR_DQS_TMATCH_0_OUT;
wire           MDDR_Demo_top_0_MDDR_RAS_N;
wire           MDDR_Demo_top_0_MDDR_WE_N;
wire           MDDR_Demo_top_0_RREADY;
wire   [1:0]   net_5;
wire   [15:0]  net_6;
wire   [1:0]   net_16;
wire   [63:0]  RDATA_net_0;
wire           RESET_GEN_0_RESET;
wire   [63:0]  RDATA_net_1;
wire   [15:14] MDDR_ADDR_slice_0;
wire   [2:2]   MDDR_BA_slice_0;
wire   [15:0]  MDDR_ADDR_net_0;
wire   [2:0]   MDDR_BA_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign RDATA_net_1 = RDATA_net_0;
assign RDATA[63:0] = RDATA_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign MDDR_Demo_top_0_MDDR_ADDR13to0 = MDDR_ADDR_net_0[13:0];
assign MDDR_Demo_top_0_MDDR_BA1to0    = MDDR_BA_net_0[1:0];
assign MDDR_ADDR_slice_0              = MDDR_ADDR_net_0[15:14];
assign MDDR_BA_slice_0[2]             = MDDR_BA_net_0[2:2];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AXI_testbench
AXI_testbench AXI_testbench_0(
        // Inputs
        .RBUSY         ( MDDR_Demo_top_0_AXI_RBUSY ),
        .WBUSY         ( MDDR_Demo_top_0_AXI_WBUSY ),
        .RDATA_input   ( MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0 ),
        .RVALID        ( MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 ),
        .RREADY        ( MDDR_Demo_top_0_RREADY ),
        .CLK           ( MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        // Outputs
        .WLEN          ( AXI_testbench_0_WLEN ),
        .RLEN          ( AXI_testbench_0_RLEN ),
        .READ          ( AXI_testbench_0_READ ),
        .WRITE         ( AXI_testbench_0_WRITE ),
        .READ_ADDRESS  ( AXI_testbench_0_READ_ADDRESS ),
        .WRITE_ADDRESS ( AXI_testbench_0_WRITE_ADDRESS ),
        .DATA_IN       ( AXI_testbench_0_DATA_IN ),
        .RDATA         ( RDATA_net_0 ) 
        );

//--------dram
dram dram_0(
        // Inputs
        .CLK   ( MDDR_Demo_top_0_MDDR_CLK ),
        .CLK_N ( MDDR_Demo_top_0_MDDR_CLK_N ),
        .CKE   ( MDDR_Demo_top_0_MDDR_CKE ),
        .CS_N  ( MDDR_Demo_top_0_MDDR_CS_N ),
        .RAS_N ( MDDR_Demo_top_0_MDDR_RAS_N ),
        .CAS_N ( MDDR_Demo_top_0_MDDR_CAS_N ),
        .WE_N  ( MDDR_Demo_top_0_MDDR_WE_N ),
        .ADDR  ( MDDR_Demo_top_0_MDDR_ADDR13to0 ),
        .BA    ( MDDR_Demo_top_0_MDDR_BA1to0 ),
        .DM    ( net_16 ),
        // Inouts
        .DQ    ( net_6 ),
        .DQS   ( net_5 ) 
        );

//--------MDDR_Demo_top
MDDR_Demo_top MDDR_Demo_top_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN       ( MDDR_Demo_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .DEVRST_N                   ( RESET_GEN_0_RESET ),
        .read_start                 ( AXI_testbench_0_READ ),
        .write_start                ( AXI_testbench_0_WRITE ),
        .RLEN                       ( AXI_testbench_0_RLEN ),
        .WLEN                       ( AXI_testbench_0_WLEN ),
        .ARADDR_int                 ( AXI_testbench_0_READ_ADDRESS ),
        .AWADDR_int                 ( AXI_testbench_0_WRITE_ADDRESS ),
        .WDATA_int_input            ( AXI_testbench_0_DATA_IN ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT      ( MDDR_Demo_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .MDDR_CAS_N                 ( MDDR_Demo_top_0_MDDR_CAS_N ),
        .MDDR_CLK                   ( MDDR_Demo_top_0_MDDR_CLK ),
        .MDDR_CLK_N                 ( MDDR_Demo_top_0_MDDR_CLK_N ),
        .MDDR_CKE                   ( MDDR_Demo_top_0_MDDR_CKE ),
        .MDDR_CS_N                  ( MDDR_Demo_top_0_MDDR_CS_N ),
        .MDDR_ODT                   (  ),
        .MDDR_RAS_N                 ( MDDR_Demo_top_0_MDDR_RAS_N ),
        .MDDR_RESET_N               (  ),
        .MDDR_WE_N                  ( MDDR_Demo_top_0_MDDR_WE_N ),
        .HPMS_DDR_FIC_SUBSYSTEM_CLK ( MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .INIT_DONE                  (  ),
        .AXI_RBUSY                  ( MDDR_Demo_top_0_AXI_RBUSY ),
        .AXI_WBUSY                  ( MDDR_Demo_top_0_AXI_WBUSY ),
        .AMBA_MASTER_0_RLAST_M0     (  ),
        .AMBA_MASTER_0_RVALID_M0    ( MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 ),
        .RREADY                     ( MDDR_Demo_top_0_RREADY ),
        .BREADY                     (  ),
        .MDDR_ADDR                  ( MDDR_ADDR_net_0 ),
        .MDDR_BA                    ( MDDR_BA_net_0 ),
        .AMBA_MASTER_0_RDATA_M0     ( MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0 ),
        // Inouts
        .MDDR_DM_RDQS               ( net_16 ),
        .MDDR_DQ                    ( net_6 ),
        .MDDR_DQS                   ( net_5 ) 
        );

//--------RESET_GEN   -   Actel:Simulation:RESET_GEN:1.0.1
RESET_GEN #( 
        .DELAY       ( 1000 ),
        .LOGIC_LEVEL ( 0 ) )
RESET_GEN_0(
        // Outputs
        .RESET ( RESET_GEN_0_RESET ) 
        );


endmodule
