Project Settings
Project Name | top_syn | Device Name | synthesis: Microchip IGLOO2 : M2GL010TS
Implementation Name | synthesis | Top Module | top
Retiming | 0 | Resource Sharing | 1
Fanout Guide | 10000 | Disable I/O Insertion | 0
Disable Sequential Optimizations | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 172 | 373 | 0 | - | 00m:17s | - | 4/8/2021 5:23:22 PM
(premap) | Complete | 70 | 38 | 0 | 0m:04s | 0m:05s | 221MB | 4/8/2021 5:23:30 PM
(fpga_mapper) | Complete | 62 | 44 | 0 | 0m:14s | 0m:18s | 227MB | 4/8/2021 5:23:49 PM
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 4/8/2021 5:23:24 PM
Area Summary
Carry Cells | 310 | Sequential Cells | 1242
DSP Blocks (dsp_used) | 0 | I/O Cells | 51
Global Clock Buffers | 10 | RAM1K18 (v_ram) | 4
LUTs (total_luts) | 1437 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL0 | 20.0 MHz | 33.1 MHz | 4.949
MDDR_Demo_top_0/MDDR_Demo_0/CCC_0/GL2 | 80.0 MHz | 132.4 MHz | 7.492
MDDR_Demo_top_0/MDDR_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 502.7 MHz | 18.011
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_HPMS_0/CLK_CONFIG_APB | 20.0 MHz | 145.3 MHz | 21.793
Optimizations Summary
Combined Clock Conversion | 2 / 2 |  |