//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Apr  8 17:21:18 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// UART_IF
module UART_IF(
    // Inputs
    AXI_RBUSY,
    AXI_WBUSY,
    BREADY,
    CLK,
    DATA_OUTPUT,
    RESET_N,
    RLAST,
    RREADY,
    RVALID,
    RX,
    // Outputs
    DATA_INPUT,
    READ,
    READ_ADDRESS,
    RLEN,
    TX,
    WLEN,
    WRITE,
    WRITE_ADDRESS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         AXI_RBUSY;
input         AXI_WBUSY;
input         BREADY;
input         CLK;
input  [63:0] DATA_OUTPUT;
input         RESET_N;
input         RLAST;
input         RREADY;
input         RVALID;
input         RX;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [63:0] DATA_INPUT;
output        READ;
output [31:0] READ_ADDRESS;
output [3:0]  RLEN;
output        TX;
output [3:0]  WLEN;
output        WRITE;
output [31:0] WRITE_ADDRESS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          AXI_RBUSY;
wire          AXI_WBUSY;
wire          BREADY;
wire          CLK;
wire   [7:0]  COREUART_0_DATA_OUT;
wire          COREUART_0_RXRDY;
wire          COREUART_0_TXRDY;
wire   [63:0] DATA_INPUT_net_0;
wire   [63:0] DATA_OUTPUT;
wire          READ_net_0;
wire   [31:0] READ_ADDRESS_net_0;
wire          RESET_N;
wire          RLAST;
wire   [3:0]  RLEN_net_0;
wire          RREADY;
wire          RVALID;
wire          RX;
wire   [7:0]  TPSRAM_0_RD;
wire          TX_net_0;
wire   [7:0]  UART_IF_FSM_0_DATA_OUT;
wire          UART_IF_FSM_0_OEN;
wire   [10:0] UART_IF_FSM_0_RAM_RADDR;
wire          UART_IF_FSM_0_RAM_REN;
wire   [7:0]  UART_IF_FSM_0_RAM_WADDR;
wire   [63:0] UART_IF_FSM_0_RAM_WD;
wire          UART_IF_FSM_0_RAM_WEN;
wire          UART_IF_FSM_0_WEN;
wire   [3:0]  WLEN_net_0;
wire          WRITE_net_0;
wire   [31:0] WRITE_ADDRESS_net_0;
wire          READ_net_1;
wire          WRITE_net_1;
wire          TX_net_1;
wire   [31:0] WRITE_ADDRESS_net_1;
wire   [31:0] READ_ADDRESS_net_1;
wire   [63:0] DATA_INPUT_net_1;
wire   [3:0]  WLEN_net_1;
wire   [3:0]  RLEN_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [12:0] BAUD_VAL_const_net_0;
wire          VCC_net;
wire          GND_net;
wire   [2:0]  BAUD_VAL_FRACTION_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign BAUD_VAL_const_net_0          = 13'h002A;
assign VCC_net                       = 1'b1;
assign GND_net                       = 1'b0;
assign BAUD_VAL_FRACTION_const_net_0 = 3'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign READ_net_1          = READ_net_0;
assign READ                = READ_net_1;
assign WRITE_net_1         = WRITE_net_0;
assign WRITE               = WRITE_net_1;
assign TX_net_1            = TX_net_0;
assign TX                  = TX_net_1;
assign WRITE_ADDRESS_net_1 = WRITE_ADDRESS_net_0;
assign WRITE_ADDRESS[31:0] = WRITE_ADDRESS_net_1;
assign READ_ADDRESS_net_1  = READ_ADDRESS_net_0;
assign READ_ADDRESS[31:0]  = READ_ADDRESS_net_1;
assign DATA_INPUT_net_1    = DATA_INPUT_net_0;
assign DATA_INPUT[63:0]    = DATA_INPUT_net_1;
assign WLEN_net_1          = WLEN_net_0;
assign WLEN[3:0]           = WLEN_net_1;
assign RLEN_net_1          = RLEN_net_0;
assign RLEN[3:0]           = RLEN_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------UART_IF_COREUART_0_COREUART   -   Actel:DirectCore:COREUART:5.7.100
UART_IF_COREUART_0_COREUART #( 
        .BAUD_VAL_FRCTN_EN ( 1 ),
        .FAMILY            ( 24 ),
        .RX_FIFO           ( 0 ),
        .RX_LEGACY_MODE    ( 0 ),
        .TX_FIFO           ( 0 ) )
COREUART_0(
        // Inputs
        .BAUD_VAL          ( BAUD_VAL_const_net_0 ),
        .BIT8              ( VCC_net ),
        .CLK               ( CLK ),
        .CSN               ( GND_net ),
        .DATA_IN           ( UART_IF_FSM_0_DATA_OUT ),
        .ODD_N_EVEN        ( GND_net ),
        .OEN               ( UART_IF_FSM_0_OEN ),
        .PARITY_EN         ( GND_net ),
        .RESET_N           ( RESET_N ),
        .RX                ( RX ),
        .WEN               ( UART_IF_FSM_0_WEN ),
        .BAUD_VAL_FRACTION ( BAUD_VAL_FRACTION_const_net_0 ), // tied to 3'h0 from definition
        // Outputs
        .DATA_OUT          ( COREUART_0_DATA_OUT ),
        .OVERFLOW          (  ),
        .PARITY_ERR        (  ),
        .RXRDY             ( COREUART_0_RXRDY ),
        .TX                ( TX_net_0 ),
        .TXRDY             ( COREUART_0_TXRDY ),
        .FRAMING_ERR       (  ) 
        );

//--------UART_IF_TPSRAM_0_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
UART_IF_TPSRAM_0_TPSRAM TPSRAM_0(
        // Inputs
        .WEN   ( UART_IF_FSM_0_RAM_WEN ),
        .REN   ( UART_IF_FSM_0_RAM_REN ),
        .CLK   ( CLK ),
        .WD    ( UART_IF_FSM_0_RAM_WD ),
        .WADDR ( UART_IF_FSM_0_RAM_WADDR ),
        .RADDR ( UART_IF_FSM_0_RAM_RADDR ),
        // Outputs
        .RD    ( TPSRAM_0_RD ) 
        );

//--------UART_IF_FSM
UART_IF_FSM UART_IF_FSM_0(
        // Inputs
        .CLK           ( CLK ),
        .RESET_N       ( RESET_N ),
        .TX_RDY        ( COREUART_0_TXRDY ),
        .RX_RDY        ( COREUART_0_RXRDY ),
        .AXI_WBUSY     ( AXI_WBUSY ),
        .AXI_RBUSY     ( AXI_RBUSY ),
        .RVALID        ( RVALID ),
        .RLAST         ( RLAST ),
        .BREADY        ( BREADY ),
        .RREADY        ( RREADY ),
        .DATA_IN       ( COREUART_0_DATA_OUT ),
        .DATA_OUTPUT   ( DATA_OUTPUT ),
        .RAM_RD        ( TPSRAM_0_RD ),
        // Outputs
        .WEN           ( UART_IF_FSM_0_WEN ),
        .OEN           ( UART_IF_FSM_0_OEN ),
        .WRITE         ( WRITE_net_0 ),
        .READ          ( READ_net_0 ),
        .RAM_WEN       ( UART_IF_FSM_0_RAM_WEN ),
        .RAM_REN       ( UART_IF_FSM_0_RAM_REN ),
        .DATA_OUT      ( UART_IF_FSM_0_DATA_OUT ),
        .WRITE_ADDRESS ( WRITE_ADDRESS_net_0 ),
        .READ_ADDRESS  ( READ_ADDRESS_net_0 ),
        .DATA_INPUT    ( DATA_INPUT_net_0 ),
        .RAM_WADDR     ( UART_IF_FSM_0_RAM_WADDR ),
        .RAM_WD        ( UART_IF_FSM_0_RAM_WD ),
        .RAM_RADDR     ( UART_IF_FSM_0_RAM_RADDR ),
        .WLEN          ( WLEN_net_0 ),
        .RLEN          ( RLEN_net_0 ) 
        );


endmodule
