//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Mar 30 10:15:22 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    DEVRST_N,
    MDDR_DQS_TMATCH_0_IN,
    RX,
    // Outputs
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    TX,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         MDDR_DQS_TMATCH_0_IN;
input         RX;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        TX;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          DEVRST_N;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [63:0] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0;
wire          MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0;
wire          MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0;
wire          MDDR_Demo_top_0_AXI_RBUSY;
wire          MDDR_Demo_top_0_AXI_WBUSY;
wire          MDDR_Demo_top_0_BREADY;
wire          MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK;
wire          MDDR_Demo_top_0_INIT_DONE;
wire          MDDR_Demo_top_0_RREADY;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          RX;
wire          TX_net_0;
wire   [63:0] UART_IF_0_DATA_INPUT;
wire          UART_IF_0_READ;
wire   [31:0] UART_IF_0_READ_ADDRESS;
wire   [3:0]  UART_IF_0_RLEN;
wire   [3:0]  UART_IF_0_WLEN;
wire          UART_IF_0_WRITE;
wire   [31:0] UART_IF_0_WRITE_ADDRESS;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          TX_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MDDR_DQS_TMATCH_0_OUT_net_1 = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT       = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1            = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                  = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1              = MDDR_CLK_net_0;
assign MDDR_CLK                    = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1            = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                  = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1              = MDDR_CKE_net_0;
assign MDDR_CKE                    = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1             = MDDR_CS_N_net_0;
assign MDDR_CS_N                   = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1              = MDDR_ODT_net_0;
assign MDDR_ODT                    = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1            = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                  = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1          = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1             = MDDR_WE_N_net_0;
assign MDDR_WE_N                   = MDDR_WE_N_net_1;
assign TX_net_1                    = TX_net_0;
assign TX                          = TX_net_1;
assign MDDR_ADDR_net_1             = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]             = MDDR_ADDR_net_1;
assign MDDR_BA_net_1               = MDDR_BA_net_0;
assign MDDR_BA[2:0]                = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MDDR_Demo_top
MDDR_Demo_top MDDR_Demo_top_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN       ( MDDR_DQS_TMATCH_0_IN ),
        .DEVRST_N                   ( DEVRST_N ),
        .read_start                 ( UART_IF_0_READ ),
        .write_start                ( UART_IF_0_WRITE ),
        .RLEN                       ( UART_IF_0_RLEN ),
        .WLEN                       ( UART_IF_0_WLEN ),
        .ARADDR_int                 ( UART_IF_0_READ_ADDRESS ),
        .AWADDR_int                 ( UART_IF_0_WRITE_ADDRESS ),
        .WDATA_int_input            ( UART_IF_0_DATA_INPUT ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT      ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N                 ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                   ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N                 ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                   ( MDDR_CKE_net_0 ),
        .MDDR_CS_N                  ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                   ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N                 ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N               ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N                  ( MDDR_WE_N_net_0 ),
        .HPMS_DDR_FIC_SUBSYSTEM_CLK ( MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .INIT_DONE                  ( MDDR_Demo_top_0_INIT_DONE ),
        .AXI_RBUSY                  ( MDDR_Demo_top_0_AXI_RBUSY ),
        .AXI_WBUSY                  ( MDDR_Demo_top_0_AXI_WBUSY ),
        .AMBA_MASTER_0_RLAST_M0     ( MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 ),
        .AMBA_MASTER_0_RVALID_M0    ( MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 ),
        .RREADY                     ( MDDR_Demo_top_0_RREADY ),
        .BREADY                     ( MDDR_Demo_top_0_BREADY ),
        .MDDR_ADDR                  ( MDDR_ADDR_net_0 ),
        .MDDR_BA                    ( MDDR_BA_net_0 ),
        .AMBA_MASTER_0_RDATA_M0     ( MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0 ),
        // Inouts
        .MDDR_DM_RDQS               ( MDDR_DM_RDQS ),
        .MDDR_DQ                    ( MDDR_DQ ),
        .MDDR_DQS                   ( MDDR_DQS ) 
        );

//--------UART_IF
UART_IF UART_IF_0(
        // Inputs
        .CLK           ( MDDR_Demo_top_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .RESET_N       ( MDDR_Demo_top_0_INIT_DONE ),
        .AXI_WBUSY     ( MDDR_Demo_top_0_AXI_WBUSY ),
        .AXI_RBUSY     ( MDDR_Demo_top_0_AXI_RBUSY ),
        .RX            ( RX ),
        .RREADY        ( MDDR_Demo_top_0_RREADY ),
        .RLAST         ( MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 ),
        .RVALID        ( MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 ),
        .BREADY        ( MDDR_Demo_top_0_BREADY ),
        .DATA_OUTPUT   ( MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0 ),
        // Outputs
        .READ          ( UART_IF_0_READ ),
        .WRITE         ( UART_IF_0_WRITE ),
        .TX            ( TX_net_0 ),
        .WRITE_ADDRESS ( UART_IF_0_WRITE_ADDRESS ),
        .READ_ADDRESS  ( UART_IF_0_READ_ADDRESS ),
        .DATA_INPUT    ( UART_IF_0_DATA_INPUT ),
        .WLEN          ( UART_IF_0_WLEN ),
        .RLEN          ( UART_IF_0_RLEN ) 
        );


endmodule
