`timescale 1 ns/100 ps
// Version: v12.6 12.900.20.24


module UART_IF_TPSRAM_0_TPSRAM(
       WD,
       RD,
       WADDR,
       RADDR,
       WEN,
       REN,
       CLK
    );
input  [63:0] WD;
output [7:0] RD;
input  [7:0] WADDR;
input  [10:0] RADDR;
input  WEN;
input  REN;
input  CLK;

    wire VCC, GND, ADLIB_VCC;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign ADLIB_VCC = VCC_power_net1;
    
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C2 (.A_DOUT({nc0, nc1, nc2, nc3, 
        nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, 
        nc15, RD[5], RD[4]}), .B_DOUT({nc16, nc17, nc18, nc19, nc20, 
        nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, 
        nc31, nc32, nc33}), .BUSY(), .A_CLK(CLK), .A_DOUT_CLK(VCC), 
        .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({REN, VCC, VCC}), 
        .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND}), .A_ADDR({GND, GND, RADDR[10], RADDR[9], 
        RADDR[8], RADDR[7], RADDR[6], RADDR[5], RADDR[4], RADDR[3], 
        RADDR[2], RADDR[1], RADDR[0], GND}), .A_WEN({GND, GND}), 
        .B_CLK(CLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), .B_DOUT_EN(VCC), 
        .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(
        VCC), .B_DIN({GND, WD[61], WD[60], WD[53], WD[52], WD[45], 
        WD[44], WD[37], WD[36], GND, WD[29], WD[28], WD[21], WD[20], 
        WD[13], WD[12], WD[5], WD[4]}), .B_ADDR({GND, GND, WADDR[7], 
        WADDR[6], WADDR[5], WADDR[4], WADDR[3], WADDR[2], WADDR[1], 
        WADDR[0], GND, GND, GND, GND}), .B_WEN({VCC, VCC}), .A_EN(VCC), 
        .A_DOUT_LAT(VCC), .A_WIDTH({GND, GND, VCC}), .A_WMODE(GND), 
        .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({VCC, GND, GND}), 
        .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C3 (.A_DOUT({nc34, nc35, nc36, 
        nc37, nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, nc46, 
        nc47, nc48, nc49, RD[7], RD[6]}), .B_DOUT({nc50, nc51, nc52, 
        nc53, nc54, nc55, nc56, nc57, nc58, nc59, nc60, nc61, nc62, 
        nc63, nc64, nc65, nc66, nc67}), .BUSY(), .A_CLK(CLK), 
        .A_DOUT_CLK(VCC), .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({REN, 
        VCC, VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .A_ADDR({GND, GND, RADDR[10], 
        RADDR[9], RADDR[8], RADDR[7], RADDR[6], RADDR[5], RADDR[4], 
        RADDR[3], RADDR[2], RADDR[1], RADDR[0], GND}), .A_WEN({GND, 
        GND}), .B_CLK(CLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), 
        .B_DOUT_EN(VCC), .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), 
        .B_DOUT_SRST_N(VCC), .B_DIN({GND, WD[63], WD[62], WD[55], 
        WD[54], WD[47], WD[46], WD[39], WD[38], GND, WD[31], WD[30], 
        WD[23], WD[22], WD[15], WD[14], WD[7], WD[6]}), .B_ADDR({GND, 
        GND, WADDR[7], WADDR[6], WADDR[5], WADDR[4], WADDR[3], 
        WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND}), .B_WEN({
        VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(VCC), .A_WIDTH({GND, GND, 
        VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({
        VCC, GND, GND}), .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C0 (.A_DOUT({nc68, nc69, nc70, 
        nc71, nc72, nc73, nc74, nc75, nc76, nc77, nc78, nc79, nc80, 
        nc81, nc82, nc83, RD[1], RD[0]}), .B_DOUT({nc84, nc85, nc86, 
        nc87, nc88, nc89, nc90, nc91, nc92, nc93, nc94, nc95, nc96, 
        nc97, nc98, nc99, nc100, nc101}), .BUSY(), .A_CLK(CLK), 
        .A_DOUT_CLK(VCC), .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({REN, 
        VCC, VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .A_ADDR({GND, GND, RADDR[10], 
        RADDR[9], RADDR[8], RADDR[7], RADDR[6], RADDR[5], RADDR[4], 
        RADDR[3], RADDR[2], RADDR[1], RADDR[0], GND}), .A_WEN({GND, 
        GND}), .B_CLK(CLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), 
        .B_DOUT_EN(VCC), .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), 
        .B_DOUT_SRST_N(VCC), .B_DIN({GND, WD[57], WD[56], WD[49], 
        WD[48], WD[41], WD[40], WD[33], WD[32], GND, WD[25], WD[24], 
        WD[17], WD[16], WD[9], WD[8], WD[1], WD[0]}), .B_ADDR({GND, 
        GND, WADDR[7], WADDR[6], WADDR[5], WADDR[4], WADDR[3], 
        WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND}), .B_WEN({
        VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(VCC), .A_WIDTH({GND, GND, 
        VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({
        VCC, GND, GND}), .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C1 (.A_DOUT({nc102, nc103, nc104, 
        nc105, nc106, nc107, nc108, nc109, nc110, nc111, nc112, nc113, 
        nc114, nc115, nc116, nc117, RD[3], RD[2]}), .B_DOUT({nc118, 
        nc119, nc120, nc121, nc122, nc123, nc124, nc125, nc126, nc127, 
        nc128, nc129, nc130, nc131, nc132, nc133, nc134, nc135}), 
        .BUSY(), .A_CLK(CLK), .A_DOUT_CLK(VCC), .A_ARST_N(VCC), 
        .A_DOUT_EN(VCC), .A_BLK({REN, VCC, VCC}), .A_DOUT_ARST_N(VCC), 
        .A_DOUT_SRST_N(VCC), .A_DIN({GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .A_ADDR({GND, GND, RADDR[10], RADDR[9], RADDR[8], RADDR[7], 
        RADDR[6], RADDR[5], RADDR[4], RADDR[3], RADDR[2], RADDR[1], 
        RADDR[0], GND}), .A_WEN({GND, GND}), .B_CLK(CLK), .B_DOUT_CLK(
        VCC), .B_ARST_N(VCC), .B_DOUT_EN(VCC), .B_BLK({WEN, VCC, VCC}), 
        .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .B_DIN({GND, WD[59], 
        WD[58], WD[51], WD[50], WD[43], WD[42], WD[35], WD[34], GND, 
        WD[27], WD[26], WD[19], WD[18], WD[11], WD[10], WD[3], WD[2]}), 
        .B_ADDR({GND, GND, WADDR[7], WADDR[6], WADDR[5], WADDR[4], 
        WADDR[3], WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND}), 
        .B_WEN({VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(VCC), .A_WIDTH({
        GND, GND, VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(VCC), 
        .B_WIDTH({VCC, GND, GND}), .B_WMODE(GND), .SII_LOCK(GND));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
