 // AXI_testbench.v
//////////////////////////////////////////////////////////////////////
`timescale 1ps /1fs


`include "dram.v"


module AXI_testbench(

RBUSY,
WBUSY,
WLEN,
RLEN,
READ,
WRITE,
READ_ADDRESS,
WRITE_ADDRESS,
DATA_IN,
RDATA_input,
RDATA,
RVALID,
RREADY,
CLK
  


);

parameter SYSCLK_PERIOD = 6250; // 160MHz

reg SYSCLK;
reg NSYSRESET;
input wire	   RBUSY;
input wire 	   WBUSY;
input wire     RREADY;
input wire     RVALID;
input wire [63:0] RDATA_input;
input wire CLK;

//// AXI -IF signals/////
output reg  [3:0] WLEN,RLEN;
output reg        READ;
output reg        WRITE;
output reg  [31:0] READ_ADDRESS;
output reg  [31:0] WRITE_ADDRESS;
output reg  [63:0] DATA_IN;
output reg  [63:0] RDATA;


always@(posedge CLK or negedge NSYSRESET)
begin
    if(NSYSRESET == 1'b0)
    begin
    RDATA <= 64'b0;
    end
    else
    begin
        if(RVALID && RREADY)
        RDATA <=  RDATA_input;
        else
        RDATA <=  RDATA;
    end    
end

initial
begin
    NSYSRESET = 1'b0;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
	   Unclocked;
end

task Unclocked;
    begin
// 1-beat burst////////////////////////////////////////////////////////////
//// write
	# (SYSCLK_PERIOD*140000);     //waiting to complete 875us
    WLEN <= 4'b0000;
	wait (WBUSY == 1'b0);	
    WRITE  <= 1'b1;
	WRITE_ADDRESS  <= 32'h00000000; 
    DATA_IN  <= 64'h1234567800000011;
    #(SYSCLK_PERIOD*2);
	WRITE  <= 1'b0;
////read
	# (SYSCLK_PERIOD*100);
    RLEN <= 4'b0000;
	wait (RBUSY == 1'b0);	
    READ  <= 1'b1;
    READ_ADDRESS  <= 32'h00;
    # (SYSCLK_PERIOD*2);
    READ  <= 1'b0;

// 16-beat burst/////////////////////////////////////////////////////////
//write
	# (SYSCLK_PERIOD*100);  
     WLEN <= 4'b1111; 
	wait (WBUSY == 1'b0);	
    WRITE  <= 1'b1;
	WRITE_ADDRESS  <= 32'h00000060; 
    DATA_IN  <= 64'h1234567800000031;
    # (SYSCLK_PERIOD*2);
	 WRITE  <= 1'b0;
	

//read
	# (SYSCLK_PERIOD*500);
    RLEN <= 4'b1111;
	wait (RBUSY == 1'b0);	
    READ  <= 1'b1;
    READ_ADDRESS  <= 32'h60;
    # (SYSCLK_PERIOD*2);
    READ  <= 1'b0;
    end

  endtask


endmodule

