| Project Settings |
|---|
| Project Name | PCIe_Demo_syn | Implementation Name | synthesis |
| Top Module | PCIe_Demo | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
449 |
555 |
0 |
- |
00m:07s |
- |
29-Aug-17
3:41:57 PM |
| (premap) | Complete |
111 |
23 |
0 |
0m:04s |
0m:05s |
206MB |
29-Aug-17
3:42:05 PM |
| (fpga_mapper) | Complete |
243 |
222 |
0 |
0m:13s |
0m:14s |
226MB |
29-Aug-17
3:42:19 PM |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 29-Aug-17
3:41:59 PM |
| Area Summary |
|---|
| |
| Carry Cells | 224 |
Sequential Cells | 1352 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 16 |
| Global Clock Buffers | 9 |
RAM1K18
(v_ram) | 17 |
| RAM64x18
(v_ram) | 2 |
LUTs
(total_luts) | 2641 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| CLK0 | 100.0 MHz | NA | NA |
| PCIe_Demo_sb_0/CCC_0/GL0 | 50.0 MHz | 78.4 MHz | 7.240 |
| PCIe_Demo_sb_0/CCC_0/GL3 | 125.0 MHz | 357.7 MHz | 5.204 |
| PCIe_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 431.2 MHz | 17.681 |
| PCIe_Demo_sb_0/PCIe_Demo_sb_HPMS_0/CLK_CONFIG_APB | 25.0 MHz | 100.3 MHz | 15.015 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 2 |
| |
|