@W: CG775 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG775 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:43|Found Component PCIe_Demo_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":148:14:148:28|Object sramahb_ack_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HWDATA_d[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HTRANS_d[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HBURST_d[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HSEL_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HREADYIN_d. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":364:35:364:44|Object writeAddr0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":365:35:365:44|Object writeAddr1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":366:35:366:44|Object writeAddr2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":367:35:367:44|Object writeAddr3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":368:35:368:44|Object writeAddr4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":369:35:369:44|Object writeAddr5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":370:35:370:44|Object writeAddr6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":371:35:371:44|Object writeAddr7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":372:35:372:44|Object writeAddr8 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":373:35:373:44|Object writeAddr9 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":374:35:374:45|Object writeAddr10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":375:35:375:45|Object writeAddr11 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":376:35:376:45|Object writeAddr12 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":377:35:377:45|Object writeAddr13 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":378:35:378:45|Object writeAddr14 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":379:35:379:45|Object writeAddr15 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":380:35:380:45|Object writeAddr16 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":381:35:381:45|Object writeAddr17 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":382:35:382:45|Object writeAddr18 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":383:35:383:45|Object writeAddr19 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":384:35:384:45|Object writeAddr20 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":385:35:385:45|Object writeAddr21 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":386:35:386:45|Object writeAddr22 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":387:35:387:45|Object writeAddr23 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":388:35:388:45|Object writeAddr24 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":389:35:389:45|Object writeAddr25 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":390:35:390:45|Object writeAddr26 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":391:35:391:45|Object writeAddr27 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":392:35:392:45|Object writeAddr28 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":393:35:393:45|Object writeAddr29 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":394:35:394:45|Object writeAddr30 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":395:35:395:45|Object writeAddr31 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":396:35:396:45|Object writeAddr32 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":397:35:397:45|Object writeAddr33 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":398:35:398:45|Object writeAddr34 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":399:35:399:45|Object writeAddr35 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":400:35:400:45|Object writeAddr36 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":401:35:401:45|Object writeAddr37 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":402:35:402:45|Object writeAddr38 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":403:35:403:45|Object writeAddr39 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":404:35:404:45|Object writeAddr40 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":405:35:405:45|Object writeAddr41 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":406:35:406:45|Object writeAddr42 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":407:35:407:45|Object writeAddr43 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":408:35:408:45|Object writeAddr44 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":409:35:409:45|Object writeAddr45 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":410:35:410:45|Object writeAddr46 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":411:35:411:45|Object writeAddr47 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":412:35:412:45|Object writeAddr48 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":413:35:413:45|Object writeAddr49 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":414:35:414:45|Object writeAddr50 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":415:35:415:45|Object writeAddr51 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":416:35:416:45|Object writeAddr52 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":417:35:417:45|Object writeAddr53 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":418:35:418:45|Object writeAddr54 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":419:35:419:45|Object writeAddr55 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":420:35:420:45|Object writeAddr56 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":421:35:421:45|Object writeAddr57 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":422:35:422:45|Object writeAddr58 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":423:35:423:45|Object writeAddr59 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":424:35:424:45|Object writeAddr60 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":425:35:425:45|Object writeAddr61 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":426:35:426:45|Object writeAddr62 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":427:35:427:45|Object writeAddr63 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":428:35:428:45|Object writeAddr64 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":429:35:429:45|Object writeAddr65 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":430:35:430:45|Object writeAddr66 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":431:35:431:45|Object writeAddr67 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":432:35:432:45|Object writeAddr68 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":434:35:434:43|Object readAddr0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":435:35:435:43|Object readAddr1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":436:35:436:43|Object readAddr2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":437:35:437:43|Object readAddr3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":438:35:438:43|Object readAddr4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":439:35:439:43|Object readAddr5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":440:35:440:43|Object readAddr6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":441:35:441:43|Object readAddr7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":442:35:442:43|Object readAddr8 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":443:35:443:43|Object readAddr9 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":444:35:444:44|Object readAddr10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":445:35:445:44|Object readAddr11 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":446:35:446:44|Object readAddr12 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":447:35:447:44|Object readAddr13 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":448:35:448:44|Object readAddr14 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":449:35:449:44|Object readAddr15 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":450:35:450:44|Object readAddr16 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":451:35:451:44|Object readAddr17 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":452:35:452:44|Object readAddr18 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":453:35:453:44|Object readAddr19 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":454:35:454:44|Object readAddr20 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":455:35:455:44|Object readAddr21 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":456:35:456:44|Object readAddr22 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":457:35:457:44|Object readAddr23 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":458:35:458:44|Object readAddr24 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":459:35:459:44|Object readAddr25 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":460:35:460:44|Object readAddr26 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":461:35:461:44|Object readAddr27 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":462:35:462:44|Object readAddr28 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":463:35:463:44|Object readAddr29 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":464:35:464:44|Object readAddr30 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":465:35:465:44|Object readAddr31 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":466:35:466:44|Object readAddr32 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":467:35:467:44|Object readAddr33 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":468:35:468:44|Object readAddr34 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":469:35:469:44|Object readAddr35 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":470:35:470:44|Object readAddr36 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":471:35:471:44|Object readAddr37 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":472:35:472:44|Object readAddr38 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":473:35:473:44|Object readAddr39 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":474:35:474:44|Object readAddr40 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":475:35:475:44|Object readAddr41 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":476:35:476:44|Object readAddr42 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":477:35:477:44|Object readAddr43 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":478:35:478:44|Object readAddr44 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":479:35:479:44|Object readAddr45 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":480:35:480:44|Object readAddr46 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":481:35:481:44|Object readAddr47 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":482:35:482:44|Object readAddr48 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":483:35:483:44|Object readAddr49 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":484:35:484:44|Object readAddr50 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":485:35:485:44|Object readAddr51 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":486:35:486:44|Object readAddr52 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":487:35:487:44|Object readAddr53 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":488:35:488:44|Object readAddr54 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":489:35:489:44|Object readAddr55 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":490:35:490:44|Object readAddr56 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":491:35:491:44|Object readAddr57 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":492:35:492:44|Object readAddr58 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":493:35:493:44|Object readAddr59 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":494:35:494:44|Object readAddr60 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":495:35:495:44|Object readAddr61 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":496:35:496:44|Object readAddr62 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":497:35:497:44|Object readAddr63 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":498:35:498:44|Object readAddr64 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":499:35:499:44|Object readAddr65 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":500:35:500:44|Object readAddr66 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":501:35:501:44|Object readAddr67 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":502:35:502:44|Object readAddr68 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9909:10:9909:16|Removing instance block17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9889:9:9889:15|Removing instance block18 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9868:10:9868:16|Removing instance block19 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9848:9:9848:15|Removing instance block20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9827:9:9827:15|Removing instance block21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9807:9:9807:15|Removing instance block22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9786:9:9786:15|Removing instance block23 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9765:9:9765:15|Removing instance block24 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9744:9:9744:15|Removing instance block25 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9724:9:9724:15|Removing instance block26 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9704:9:9704:15|Removing instance block27 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9683:9:9683:15|Removing instance block28 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9662:9:9662:15|Removing instance block29 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9640:9:9640:15|Removing instance block30 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9619:9:9619:15|Removing instance block31 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9599:9:9599:15|Removing instance block32 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9578:9:9578:15|Removing instance block33 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9558:9:9558:15|Removing instance block34 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9538:9:9538:15|Removing instance block35 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9517:10:9517:16|Removing instance block36 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9497:9:9497:15|Removing instance block37 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9477:9:9477:15|Removing instance block38 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9456:9:9456:15|Removing instance block39 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9435:9:9435:15|Removing instance block40 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9415:9:9415:15|Removing instance block41 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9394:9:9394:15|Removing instance block42 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9373:9:9373:15|Removing instance block43 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9352:9:9352:15|Removing instance block44 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9331:9:9331:15|Removing instance block45 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9310:9:9310:15|Removing instance block46 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9289:9:9289:15|Removing instance block47 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9268:9:9268:15|Removing instance block48 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9247:9:9247:15|Removing instance block49 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9226:9:9226:15|Removing instance block50 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9205:9:9205:15|Removing instance block51 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9184:9:9184:15|Removing instance block52 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9163:9:9163:15|Removing instance block53 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9142:9:9142:15|Removing instance block54 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9121:9:9121:15|Removing instance block55 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9100:9:9100:15|Removing instance block56 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9079:9:9079:15|Removing instance block57 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9058:9:9058:15|Removing instance block58 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9037:9:9037:15|Removing instance block59 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9016:9:9016:15|Removing instance block60 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8995:9:8995:15|Removing instance block61 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8974:9:8974:15|Removing instance block62 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8953:9:8953:15|Removing instance block63 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8933:9:8933:15|Removing instance block64 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8913:9:8913:15|Removing instance block65 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8893:9:8893:15|Removing instance block66 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8872:9:8872:15|Removing instance block67 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8851:9:8851:15|Removing instance block68 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":586:4:586:9|Pruning unused register ckRdAddr[15:9]. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":103:31:103:49|Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":104:31:104:51|Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":111:31:111:42|Removing wire u_BUSY_all_0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":112:31:112:42|Removing wire u_BUSY_all_1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":113:31:113:42|Removing wire u_BUSY_all_2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":114:31:114:42|Removing wire u_BUSY_all_3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":116:31:116:42|Removing wire l_BUSY_all_1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":117:31:117:42|Removing wire l_BUSY_all_2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":118:31:118:42|Removing wire l_BUSY_all_3, as there is no assignment to it.
@W: CG775 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v":8:0:8:12|Found Component COREAHBTOAPB3 in library COREAHBTOAPB3_LIB
@W: CG775 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v":13:0:13:7|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v":1495:0:1495:8|Removing wire CAPB3IlOI, as there is no assignment to it.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[8].APB_32.edge_both[8]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[8].APB_32.edge_neg[8]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[8].APB_32.edge_pos[8]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_both[7]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_neg[7]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_pos[7]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_both[6]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_neg[6]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_pos[6]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_both[5]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_neg[5]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_pos[5]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_both[4]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_neg[4]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_pos[4]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_both[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_neg[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_pos[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_both[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_neg[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_pos[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_both[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_neg[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_pos[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_both[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_neg[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_pos[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[0].APB_32.INTR_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[1].APB_32.INTR_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[2].APB_32.INTR_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[3].APB_32.INTR_reg[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[4].APB_32.INTR_reg[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[5].APB_32.INTR_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[6].APB_32.INTR_reg[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[7].APB_32.INTR_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[8].APB_32.INTR_reg[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.INTR_reg[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.INTR_reg[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.INTR_reg[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.INTR_reg[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[4].APB_32.INTR_reg[4]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[5].APB_32.INTR_reg[5]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[6].APB_32.INTR_reg[6]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[7].APB_32.INTR_reg[7]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[8].APB_32.INTR_reg[8]. Make sure that there are no unused intermediate registers.
@W: CG775 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":30:7:30:49|Found Component PCIe_Demo_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":789:3:789:8|Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":592:3:592:8|Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":522:3:522:8|Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers.
@W: CL207 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":719:3:719:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":418:30:418:40|Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":436:30:436:43|Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":437:30:437:43|Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":447:30:447:39|Object memwr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":470:30:470:44|Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":472:30:472:44|Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":512:30:512:50|Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":555:30:555:41|Removing wire cfwr_req_int, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":557:30:557:39|Removing wire cfwr_req_c, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":563:30:563:39|Removing wire cfdata_w_o, as there is no assignment to it.
@W: CL168 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2927:16:2927:29|Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2980:3:2980:8|Pruning unused register FF_exit. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2962:3:2962:8|Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2949:3:2949:8|Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2939:3:2939:8|Pruning unused register FF_entry. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2770:3:2770:8|Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1906:3:1906:8|Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1731:3:1731:8|Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1582:3:1582:8|Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1015:3:1015:8|Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers.
@W: CL271 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL113 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL207 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2786:3:2786:8|All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL207 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1594:3:1594:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL250 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":236:21:236:36|Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":237:21:237:36|Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":245:21:245:31|Removing wire fmhaddr_lat, as there is no assignment to it.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":952:3:952:8|Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":934:6:934:11|Pruning unused register pop_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":868:5:868:10|Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":732:3:732:8|Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":639:2:639:7|Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":627:2:627:7|Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":259:29:259:41|Removing wire cfburst_len_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":265:29:265:42|Removing wire ustatus_resp_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":266:29:266:35|Removing wire ubusy_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":267:29:267:38|Removing wire udata_en_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":268:29:268:41|Removing wire udata_valid_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":269:29:269:37|Removing wire udata_r_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":275:29:275:41|Removing wire uclatchpord_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":281:29:281:45|Removing wire uccrypto_opmode_o, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":304:29:304:40|Removing wire cudata_wen_o, as there is no assignment to it.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Optimizing register bit SERV_CMDBYTE_REQ[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\hdl\Serial_Num.v":66:0:66:5|Pruning register bits 7 to 1 of SERV_CMDBYTE_REQ[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb_HPMS\PCIe_Demo_sb_HPMS.v":51:14:51:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb\FABOSC_0\PCIe_Demo_sb_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb\FABOSC_0\PCIe_Demo_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb\FABOSC_0\PCIe_Demo_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb\FABOSC_0\PCIe_Demo_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo_sb\FABOSC_0\PCIe_Demo_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bit 31 of prdata[31:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bits 25 to 0 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning unused register fmhburst_d1[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_wr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Optimizing register bit cfrd_asyncevent_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning unused register resp_srcreg_addr_d1[30]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Pruning unused register cfrd_asyncevent_o. Make sure that there are no unused intermediate registers.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v":372:29:372:42|*Output cutrans_done_o has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\CoreGPIO_0\rtl\vlog\core\coregpio.v":182:26:182:31|Input port bits 31 to 9 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v":40:0:40:5|Input port bit 0 of HTRANS[1:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":69:28:69:32|Input port bits 31 to 20 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":64:26:64:34|Input port bits 15 to 14 of writeAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":65:26:65:33|Input port bits 15 to 14 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":65:26:65:33|Input port bits 8 to 0 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":78:29:78:40|Input port bits 19 to 18 of ahbsram_addr[19:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL156 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\work\PCIe_Demo\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":118:31:118:42|*Input l_BUSY_all_3 to expression [or] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 3 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 1 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 3 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 1 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 5 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bit 3 of SDATAREADY[16:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 1 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 5 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bit 3 of SHRESP[16:0] is unused
@W: CL246 :"C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 1 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.

