#--  Synopsys, Inc.
#--  Version L-2016.09M-2
#--  Project file C:\Users\athuldeep.n\Desktop\PHASE_1_WRK\dg0532\LiberoProject\PCIE_Demo\synthesis\run_options.txt
#--  Written on Tue Aug 29 15:41:50 2017


#project files
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/hdl/Debounce.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/CoreGPIO_0/rtl/vlog/core/coregpio.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/SERDES_IF_0/PCIe_Demo_SERDES_IF_0_SERDES_IF_syn.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/SERDES_IF_0/PCIe_Demo_SERDES_IF_0_SERDES_IF.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo_sb/CCC_0/PCIe_Demo_sb_CCC_0_FCCC.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo_sb/FABOSC_0/PCIe_Demo_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo_sb_HPMS/PCIe_Demo_sb_HPMS_syn.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo_sb_HPMS/PCIe_Demo_sb_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo_sb/PCIe_Demo_sb.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/hdl/Serial_Num.v"
add_file -verilog -lib COREAHBLSRAM_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/COREAHBLSRAM_0/rtl/vlog/core/AHBLSramIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/COREAHBLSRAM_0/rtl/vlog/core/lsram_2048to139264x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/COREAHBLSRAM_0/rtl/vlog/core/usram_128to9216x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/COREAHBLSRAM_0/rtl/vlog/core/SramCtrlIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/COREAHBLSRAM_0/rtl/vlog/core/CoreAHBLSRAM.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core_obfuscated/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core_obfuscated/coreapb3.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_AHBLMasterIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_CmdDec.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_FSMCtrl.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/Actel/DirectCore/CORESYSSERVICES/3.1.101/rtl/vlog/core/CoreSysServices_UserIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/CORESYSSERVICES_0/rtl/vlog/core/CoreSysServices.v"
add_file -verilog "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/component/work/PCIe_Demo/PCIe_Demo.v"
add_file -fpga_constraint "C:/Users/athuldeep.n/Desktop/PHASE_1_WRK/dg0532/LiberoProject/PCIE_Demo/designer/PCIe_Demo/synthesis.fdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "PCIe_Demo"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./PCIe_Demo.edn"
impl -active "synthesis"
