| Project Settings |
|---|
| Project Name | Top_syn | Implementation Name | synthesis |
| Top Module | Top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
322 |
331 |
0 |
- |
00m:06s |
- |
3/24/2017
7:49:51 PM |
| (premap) | Complete |
62 |
27 |
0 |
0m:03s |
0m:03s |
180MB |
3/24/2017
7:49:55 PM |
| (fpga_mapper) | Complete |
115 |
148 |
0 |
0m:14s |
0m:14s |
233MB |
3/24/2017
7:50:10 PM |
| Multi-srs Generator |
Complete | | | | | | | 3/24/2017
7:49:52 PM |
| Area Summary |
|---|
| |
| Carry Cells | 220 |
Sequential Cells | 916 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 10 |
| Global Clock Buffers | 3 |
RAM64x18
(v_ram) | 10 |
| LUTs
(total_luts) | 2508 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| my_hpms_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 92.5 MHz | -0.810 |
| my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 1 |
| |
|