library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_ACMTABLE is
    generic(
        TESTMODE        : integer := 0
    );
    port(
        ACMADDR         : in     vl_logic_vector(7 downto 0);
        ACMDATA         : out    vl_logic_vector(7 downto 0);
        ACMDO           : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of TESTMODE : constant is 1;
end UART_top_COREABC_0_ACMTABLE;
