library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_COREABC is
    generic(
        FAMILY          : integer := 0;
        APB_AWIDTH      : integer := 10;
        APB_DWIDTH      : integer := 8;
        APB_SDEPTH      : integer := 4;
        ICWIDTH         : integer := 8;
        ZRWIDTH         : integer := 8;
        IFWIDTH         : integer := 4;
        IIWIDTH         : integer := 4;
        IOWIDTH         : integer := 8;
        STWIDTH         : integer := 4;
        EN_RAM          : integer := 1;
        EN_AND          : integer := 1;
        EN_XOR          : integer := 1;
        EN_OR           : integer := 1;
        EN_ADD          : integer := 1;
        EN_INC          : integer := 1;
        EN_SHL          : integer := 1;
        EN_SHR          : integer := 1;
        EN_CALL         : integer := 1;
        EN_PUSH         : integer := 1;
        EN_MULT         : integer := 0;
        EN_ACM          : integer := 1;
        EN_DATAM        : integer := 1;
        EN_INT          : integer := 1;
        EN_IOREAD       : integer := 1;
        EN_IOWRT        : integer := 1;
        EN_ALURAM       : integer := 1;
        EN_INDIRECT     : integer := 1;
        ISRADDR         : integer := 1;
        DEBUG           : integer := 1;
        INSMODE         : integer := 0;
        INITWIDTH       : integer := 8;
        TESTMODE        : integer := 0;
        ACT_CALIBRATIONDATA: integer := 1;
        IMEM_APB_ACCESS : integer := 2;
        UNIQ_STRING_LENGTH: integer := 10;
        MAX_NVMDWIDTH   : integer := 32;
        CYCLE0          : vl_logic_vector(1 downto 0) := (Hi0, Hi0);
        CYCLE1          : vl_logic_vector(1 downto 0) := (Hi0, Hi1);
        CYCLE2          : vl_logic_vector(1 downto 0) := (Hi1, Hi0);
        CYCLE3          : vl_logic_vector(1 downto 0) := (Hi1, Hi1)
    );
    port(
        PCLK            : in     vl_logic;
        NSYSRESET       : in     vl_logic;
        PRESETN         : out    vl_logic;
        PENABLE_M       : out    vl_logic;
        PWRITE_M        : out    vl_logic;
        PSEL_M          : out    vl_logic;
        PADDR_M         : out    vl_logic_vector(19 downto 0);
        PWDATA_M        : out    vl_logic_vector;
        PRDATA_M        : in     vl_logic_vector;
        PREADY_M        : in     vl_logic;
        PSLVERR_M       : in     vl_logic;
        IO_IN           : in     vl_logic_vector;
        IO_OUT          : out    vl_logic_vector;
        INTREQ          : in     vl_logic;
        INTACT          : out    vl_logic;
        INITDATVAL      : in     vl_logic;
        INITDONE        : in     vl_logic;
        INITADDR        : in     vl_logic_vector;
        INITDATA        : in     vl_logic_vector(8 downto 0);
        PSEL_S          : in     vl_logic;
        PENABLE_S       : in     vl_logic;
        PWRITE_S        : in     vl_logic;
        PADDR_S         : in     vl_logic_vector;
        PWDATA_S        : in     vl_logic_vector;
        PRDATA_S        : out    vl_logic_vector;
        PSLVERR_S       : out    vl_logic;
        PREADY_S        : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FAMILY : constant is 1;
    attribute mti_svvh_generic_type of APB_AWIDTH : constant is 1;
    attribute mti_svvh_generic_type of APB_DWIDTH : constant is 1;
    attribute mti_svvh_generic_type of APB_SDEPTH : constant is 1;
    attribute mti_svvh_generic_type of ICWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ZRWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IFWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IIWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IOWIDTH : constant is 1;
    attribute mti_svvh_generic_type of STWIDTH : constant is 1;
    attribute mti_svvh_generic_type of EN_RAM : constant is 1;
    attribute mti_svvh_generic_type of EN_AND : constant is 1;
    attribute mti_svvh_generic_type of EN_XOR : constant is 1;
    attribute mti_svvh_generic_type of EN_OR : constant is 1;
    attribute mti_svvh_generic_type of EN_ADD : constant is 1;
    attribute mti_svvh_generic_type of EN_INC : constant is 1;
    attribute mti_svvh_generic_type of EN_SHL : constant is 1;
    attribute mti_svvh_generic_type of EN_SHR : constant is 1;
    attribute mti_svvh_generic_type of EN_CALL : constant is 1;
    attribute mti_svvh_generic_type of EN_PUSH : constant is 1;
    attribute mti_svvh_generic_type of EN_MULT : constant is 1;
    attribute mti_svvh_generic_type of EN_ACM : constant is 1;
    attribute mti_svvh_generic_type of EN_DATAM : constant is 1;
    attribute mti_svvh_generic_type of EN_INT : constant is 1;
    attribute mti_svvh_generic_type of EN_IOREAD : constant is 1;
    attribute mti_svvh_generic_type of EN_IOWRT : constant is 1;
    attribute mti_svvh_generic_type of EN_ALURAM : constant is 1;
    attribute mti_svvh_generic_type of EN_INDIRECT : constant is 1;
    attribute mti_svvh_generic_type of ISRADDR : constant is 1;
    attribute mti_svvh_generic_type of DEBUG : constant is 1;
    attribute mti_svvh_generic_type of INSMODE : constant is 1;
    attribute mti_svvh_generic_type of INITWIDTH : constant is 1;
    attribute mti_svvh_generic_type of TESTMODE : constant is 1;
    attribute mti_svvh_generic_type of ACT_CALIBRATIONDATA : constant is 1;
    attribute mti_svvh_generic_type of IMEM_APB_ACCESS : constant is 1;
    attribute mti_svvh_generic_type of UNIQ_STRING_LENGTH : constant is 1;
    attribute mti_svvh_generic_type of MAX_NVMDWIDTH : constant is 1;
    attribute mti_svvh_generic_type of CYCLE0 : constant is 2;
    attribute mti_svvh_generic_type of CYCLE1 : constant is 2;
    attribute mti_svvh_generic_type of CYCLE2 : constant is 2;
    attribute mti_svvh_generic_type of CYCLE3 : constant is 2;
end UART_top_COREABC_0_COREABC;
