library verilog;
use verilog.vl_types.all;
entity COREAHBLITE_MASTERSTAGE is
    generic(
        MEMSPACE        : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
        HADDR_SHG_CFG   : vl_logic_vector(0 downto 0) := (others => Hi1);
        SC              : vl_logic_vector(15 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        M_AHBSLOTENABLE : vl_logic_vector(16 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1)
    );
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        HADDR           : in     vl_logic_vector(31 downto 0);
        HMASTLOCK       : in     vl_logic;
        HSIZE           : in     vl_logic_vector(2 downto 0);
        HTRANS          : in     vl_logic;
        HWRITE          : in     vl_logic;
        HRESP           : out    vl_logic;
        HRDATA          : out    vl_logic_vector(31 downto 0);
        HREADY_M        : out    vl_logic;
        REMAP           : in     vl_logic;
        SADDRREADY      : in     vl_logic_vector(16 downto 0);
        SDATAREADY      : in     vl_logic_vector(16 downto 0);
        SHRESP          : in     vl_logic_vector(16 downto 0);
        GATEDHADDR      : out    vl_logic_vector(31 downto 0);
        GATEDHMASTLOCK  : out    vl_logic;
        GATEDHSIZE      : out    vl_logic_vector(2 downto 0);
        GATEDHTRANS     : out    vl_logic;
        GATEDHWRITE     : out    vl_logic;
        SADDRSEL        : out    vl_logic_vector(16 downto 0);
        SDATASEL        : out    vl_logic_vector(16 downto 0);
        PREVDATASLAVEREADY: out    vl_logic;
        HRDATA_S0       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S0    : in     vl_logic;
        HRDATA_S1       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S1    : in     vl_logic;
        HRDATA_S2       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S2    : in     vl_logic;
        HRDATA_S3       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S3    : in     vl_logic;
        HRDATA_S4       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S4    : in     vl_logic;
        HRDATA_S5       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S5    : in     vl_logic;
        HRDATA_S6       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S6    : in     vl_logic;
        HRDATA_S7       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S7    : in     vl_logic;
        HRDATA_S8       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S8    : in     vl_logic;
        HRDATA_S9       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S9    : in     vl_logic;
        HRDATA_S10      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S10   : in     vl_logic;
        HRDATA_S11      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S11   : in     vl_logic;
        HRDATA_S12      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S12   : in     vl_logic;
        HRDATA_S13      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S13   : in     vl_logic;
        HRDATA_S14      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S14   : in     vl_logic;
        HRDATA_S15      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S15   : in     vl_logic;
        HRDATA_S16      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S16   : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MEMSPACE : constant is 2;
    attribute mti_svvh_generic_type of HADDR_SHG_CFG : constant is 2;
    attribute mti_svvh_generic_type of SC : constant is 2;
    attribute mti_svvh_generic_type of M_AHBSLOTENABLE : constant is 2;
end COREAHBLITE_MASTERSTAGE;
