library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_fifo_ctrl_256 is
    generic(
        FIFO_DEPTH      : integer := 16;
        FIFO_BITS       : integer := 4;
        FIFO_WIDTH      : integer := 8
    );
    port(
        clock           : in     vl_logic;
        reset_n         : in     vl_logic;
        data_in         : in     vl_logic_vector;
        read_n          : in     vl_logic;
        write_n         : in     vl_logic;
        LEVEL           : in     vl_logic_vector(7 downto 0);
        data_out        : out    vl_logic_vector;
        full            : out    vl_logic;
        empty           : out    vl_logic;
        half            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
    attribute mti_svvh_generic_type of FIFO_BITS : constant is 1;
    attribute mti_svvh_generic_type of FIFO_WIDTH : constant is 1;
end UART_top_CoreUARTapb_0_fifo_ctrl_256;
