library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_INSTRUCTRAM is
    generic(
        AWIDTH          : integer := 7;
        DWIDTH          : integer := 16;
        SWIDTH          : integer := 1;
        ICWIDTH         : integer := 7;
        ICDEPTH         : integer := 128;
        IWWIDTH         : integer := 30;
        INITWIDTH       : integer := 7;
        TESTMODE        : integer := 0;
        IMEM_APB_ACCESS : integer := 2;
        UNIQ_STRING_LENGTH: integer := 10
    );
    port(
        CLK             : in     vl_logic;
        RSTN            : in     vl_logic;
        INITDATVAL      : in     vl_logic;
        INITDONE        : in     vl_logic;
        INITADDR        : in     vl_logic_vector;
        INITDATA        : in     vl_logic_vector(8 downto 0);
        ADDRESS         : in     vl_logic_vector;
        INSTRUCTION     : out    vl_logic_vector;
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PADDR           : in     vl_logic_vector;
        PWDATA          : in     vl_logic_vector;
        PRDATA          : out    vl_logic_vector;
        PSLVERR         : out    vl_logic;
        PREADY          : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of AWIDTH : constant is 1;
    attribute mti_svvh_generic_type of DWIDTH : constant is 1;
    attribute mti_svvh_generic_type of SWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ICWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ICDEPTH : constant is 1;
    attribute mti_svvh_generic_type of IWWIDTH : constant is 1;
    attribute mti_svvh_generic_type of INITWIDTH : constant is 1;
    attribute mti_svvh_generic_type of TESTMODE : constant is 1;
    attribute mti_svvh_generic_type of IMEM_APB_ACCESS : constant is 1;
    attribute mti_svvh_generic_type of UNIQ_STRING_LENGTH : constant is 1;
end UART_top_COREABC_0_INSTRUCTRAM;
