library verilog;
use verilog.vl_types.all;
entity COREAHBLITE_SLAVESTAGE is
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        HREADYOUT       : in     vl_logic;
        HRESP           : in     vl_logic;
        HSEL            : out    vl_logic;
        HADDR           : out    vl_logic_vector(31 downto 0);
        HSIZE           : out    vl_logic_vector(2 downto 0);
        HTRANS          : out    vl_logic;
        HWRITE          : out    vl_logic;
        HWDATA          : out    vl_logic_vector(31 downto 0);
        HREADY_S        : out    vl_logic;
        HMASTLOCK       : out    vl_logic;
        MADDRSEL        : in     vl_logic_vector(1 downto 0);
        MDATASEL        : in     vl_logic_vector(1 downto 0);
        MPREVDATASLAVEREADY: in     vl_logic_vector(1 downto 0);
        MADDRREADY      : out    vl_logic_vector(1 downto 0);
        MDATAREADY      : out    vl_logic_vector(1 downto 0);
        MHRESP          : out    vl_logic_vector(1 downto 0);
        M0GATEDHADDR    : in     vl_logic_vector(31 downto 0);
        M0GATEDHMASTLOCK: in     vl_logic;
        M0GATEDHSIZE    : in     vl_logic_vector(2 downto 0);
        M0GATEDHTRANS   : in     vl_logic;
        M0GATEDHWRITE   : in     vl_logic;
        M1GATEDHADDR    : in     vl_logic_vector(31 downto 0);
        M1GATEDHMASTLOCK: in     vl_logic;
        M1GATEDHSIZE    : in     vl_logic_vector(2 downto 0);
        M1GATEDHTRANS   : in     vl_logic;
        M1GATEDHWRITE   : in     vl_logic;
        HWDATA_M0       : in     vl_logic_vector(31 downto 0);
        HWDATA_M1       : in     vl_logic_vector(31 downto 0)
    );
end COREAHBLITE_SLAVESTAGE;
