library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_fifo_256x8 is
    generic(
        LEVEL           : vl_logic_vector(7 downto 0) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
    );
    port(
        DO              : out    vl_logic_vector(7 downto 0);
        RCLOCK          : in     vl_logic;
        WCLOCK          : in     vl_logic;
        DI              : in     vl_logic_vector(7 downto 0);
        WRB             : in     vl_logic;
        RDB             : in     vl_logic;
        RESET           : in     vl_logic;
        FULL            : out    vl_logic;
        EMPTY           : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of LEVEL : constant is 2;
end UART_top_CoreUARTapb_0_fifo_256x8;
