library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_INSTRUCTNVM is
    generic(
        MAX_NVMDWIDTH   : integer := 32;
        AWIDTH          : integer := 8;
        DWIDTH          : integer := 8;
        SWIDTH          : integer := 1;
        ICWIDTH         : integer := 8;
        ICDEPTH         : integer := 256;
        IWWIDTH         : integer := 58;
        ACT_CALIBRATIONDATA: integer := 1;
        IMEM_APB_ACCESS : integer := 2;
        UNIQ_STRING_LENGTH: integer := 10
    );
    port(
        CLK             : in     vl_logic;
        RSTN            : in     vl_logic;
        START           : in     vl_logic;
        STALL           : out    vl_logic;
        ADDRESS         : in     vl_logic_vector;
        INSTRUCTION     : out    vl_logic_vector;
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PADDR           : in     vl_logic_vector;
        PWDATA          : in     vl_logic_vector;
        PRDATA          : out    vl_logic_vector;
        PSLVERR         : out    vl_logic;
        PREADY          : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MAX_NVMDWIDTH : constant is 1;
    attribute mti_svvh_generic_type of AWIDTH : constant is 1;
    attribute mti_svvh_generic_type of DWIDTH : constant is 1;
    attribute mti_svvh_generic_type of SWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ICWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ICDEPTH : constant is 1;
    attribute mti_svvh_generic_type of IWWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ACT_CALIBRATIONDATA : constant is 1;
    attribute mti_svvh_generic_type of IMEM_APB_ACCESS : constant is 1;
    attribute mti_svvh_generic_type of UNIQ_STRING_LENGTH : constant is 1;
end UART_top_COREABC_0_INSTRUCTNVM;
