library verilog;
use verilog.vl_types.all;
entity my_sysservice_state is
    port(
        RESETn          : in     vl_logic;
        CLK             : in     vl_logic;
        START           : in     vl_logic;
        SELF_TEST_SERVICE: in     vl_logic;
        INSTANTIATE_SERVICE: in     vl_logic;
        GENERATE_SERVICE: in     vl_logic;
        SERV_BUSY       : in     vl_logic;
        SERV_DATA_WRDY  : in     vl_logic;
        SERV_DATA_W     : out    vl_logic_vector(31 downto 0);
        SERV_DATA_WVALID: out    vl_logic;
        SERV_DATA_RVALID: in     vl_logic;
        SERV_DATA_R     : in     vl_logic_vector(31 downto 0);
        SERV_ENABLE_REQ : out    vl_logic;
        SERV_CMDBYTE_REQ: out    vl_logic_vector(7 downto 0);
        SERV_STATUS_RESP: in     vl_logic_vector(7 downto 0);
        SERV_STATUS_VALID: in     vl_logic;
        SERV_NRBG_LENGTH: out    vl_logic_vector(7 downto 0);
        SERV_NRBG_HANDLE: out    vl_logic_vector(7 downto 0);
        SERV_NRBG_ADDLENGTH: out    vl_logic_vector(7 downto 0);
        SERV_NRBG_PRREQ : out    vl_logic_vector(7 downto 0);
        NRBG_DATA       : out    vl_logic_vector(31 downto 0);
        NRBG_HANDLE     : out    vl_logic_vector(7 downto 0);
        NRBG_SVC_DONE   : out    vl_logic;
        fsm             : out    vl_logic_vector(3 downto 0)
    );
end my_sysservice_state;
