library verilog;
use verilog.vl_types.all;
entity syssvc_blk is
    port(
        CLK             : in     vl_logic;
        COMM_BLK_INT    : in     vl_logic;
        GENERATE_SERVICE: in     vl_logic;
        HRDATA          : in     vl_logic_vector(31 downto 0);
        HREADY          : in     vl_logic;
        HRESP           : in     vl_logic;
        INSTANTIATE_SERVICE: in     vl_logic;
        RESETn          : in     vl_logic;
        SELF_TEST_SERVICE: in     vl_logic;
        START           : in     vl_logic;
        HADDR           : out    vl_logic_vector(31 downto 0);
        HBURST          : out    vl_logic_vector(2 downto 0);
        HSIZE           : out    vl_logic_vector(2 downto 0);
        HTRANS          : out    vl_logic_vector(1 downto 0);
        HWDATA          : out    vl_logic_vector(31 downto 0);
        HWRITE          : out    vl_logic;
        NRBG_DATA       : out    vl_logic_vector(31 downto 0);
        NRBG_HANDLE     : out    vl_logic_vector(7 downto 0);
        NRBG_SVC_DONE   : out    vl_logic;
        fsm             : out    vl_logic_vector(3 downto 0)
    );
end syssvc_blk;
