library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_Rx_async is
    generic(
        RX_FIFO         : integer := 0;
        receive_states_rx_idle: integer := 0;
        receive_states_rx_data_bits: integer := 1;
        receive_states_rx_stop_bit: integer := 2
    );
    port(
        clk             : in     vl_logic;
        baud_clock      : in     vl_logic;
        reset_n         : in     vl_logic;
        bit8            : in     vl_logic;
        parity_en       : in     vl_logic;
        odd_n_even      : in     vl_logic;
        read_rx_byte    : in     vl_logic;
        clear_parity    : in     vl_logic;
        rx              : in     vl_logic;
        overflow        : out    vl_logic;
        parity_err      : out    vl_logic;
        clear_parity_en : out    vl_logic;
        receive_full    : out    vl_logic;
        rx_byte         : out    vl_logic_vector(7 downto 0);
        fifo_write      : out    vl_logic;
        framing_error   : out    vl_logic;
        clear_framing_error: in     vl_logic;
        clear_framing_error_en: out    vl_logic;
        stop_strobe     : out    vl_logic;
        rx_idle         : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of RX_FIFO : constant is 1;
    attribute mti_svvh_generic_type of receive_states_rx_idle : constant is 1;
    attribute mti_svvh_generic_type of receive_states_rx_data_bits : constant is 1;
    attribute mti_svvh_generic_type of receive_states_rx_stop_bit : constant is 1;
end UART_top_CoreUARTapb_0_Rx_async;
