library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_Tx_async is
    generic(
        TX_FIFO         : integer := 0;
        tx_idle         : integer := 0;
        tx_load         : integer := 1;
        start_bit       : integer := 2;
        tx_data_bits    : integer := 3;
        parity_bit      : integer := 4;
        tx_stop_bit     : integer := 5;
        delay_state     : integer := 6
    );
    port(
        clk             : in     vl_logic;
        xmit_pulse      : in     vl_logic;
        reset_n         : in     vl_logic;
        rst_tx_empty    : in     vl_logic;
        tx_hold_reg     : in     vl_logic_vector(7 downto 0);
        tx_dout_reg     : in     vl_logic_vector(7 downto 0);
        fifo_empty      : in     vl_logic;
        fifo_full       : in     vl_logic;
        bit8            : in     vl_logic;
        parity_en       : in     vl_logic;
        odd_n_even      : in     vl_logic;
        txrdy           : out    vl_logic;
        tx              : out    vl_logic;
        fifo_read_tx    : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of TX_FIFO : constant is 1;
    attribute mti_svvh_generic_type of tx_idle : constant is 1;
    attribute mti_svvh_generic_type of tx_load : constant is 1;
    attribute mti_svvh_generic_type of start_bit : constant is 1;
    attribute mti_svvh_generic_type of tx_data_bits : constant is 1;
    attribute mti_svvh_generic_type of parity_bit : constant is 1;
    attribute mti_svvh_generic_type of tx_stop_bit : constant is 1;
    attribute mti_svvh_generic_type of delay_state : constant is 1;
end UART_top_CoreUARTapb_0_Tx_async;
