library verilog;
use verilog.vl_types.all;
entity CoreAPB3 is
    generic(
        APB_DWIDTH      : vl_logic_vector(5 downto 0) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
        IADDR_OPTION    : integer := 0;
        APBSLOT0ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT1ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT2ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT3ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT4ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT5ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT6ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT7ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT8ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT9ENABLE  : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT10ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT11ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT12ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT13ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT14ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        APBSLOT15ENABLE : vl_logic_vector(0 downto 0) := (others => Hi1);
        SC_0            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_1            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_2            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_3            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_4            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_5            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_6            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_7            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_8            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_9            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_10           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_11           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_12           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_13           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_14           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_15           : vl_logic_vector(0 downto 0) := (others => Hi0);
        MADDR_BITS      : vl_logic_vector(5 downto 0) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
        UPR_NIBBLE_POSN : vl_logic_vector(3 downto 0) := (Hi0, Hi1, Hi1, Hi1)
    );
    port(
        IADDR           : in     vl_logic_vector(31 downto 0);
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        PADDR           : in     vl_logic_vector(31 downto 0);
        PWRITE          : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PADDRS          : out    vl_logic_vector(31 downto 0);
        PWRITES         : out    vl_logic;
        PENABLES        : out    vl_logic;
        PWDATAS         : out    vl_logic_vector(31 downto 0);
        PSELS0          : out    vl_logic;
        PSELS1          : out    vl_logic;
        PSELS2          : out    vl_logic;
        PSELS3          : out    vl_logic;
        PSELS4          : out    vl_logic;
        PSELS5          : out    vl_logic;
        PSELS6          : out    vl_logic;
        PSELS7          : out    vl_logic;
        PSELS8          : out    vl_logic;
        PSELS9          : out    vl_logic;
        PSELS10         : out    vl_logic;
        PSELS11         : out    vl_logic;
        PSELS12         : out    vl_logic;
        PSELS13         : out    vl_logic;
        PSELS14         : out    vl_logic;
        PSELS15         : out    vl_logic;
        PSELS16         : out    vl_logic;
        PRDATAS0        : in     vl_logic_vector(31 downto 0);
        PRDATAS1        : in     vl_logic_vector(31 downto 0);
        PRDATAS2        : in     vl_logic_vector(31 downto 0);
        PRDATAS3        : in     vl_logic_vector(31 downto 0);
        PRDATAS4        : in     vl_logic_vector(31 downto 0);
        PRDATAS5        : in     vl_logic_vector(31 downto 0);
        PRDATAS6        : in     vl_logic_vector(31 downto 0);
        PRDATAS7        : in     vl_logic_vector(31 downto 0);
        PRDATAS8        : in     vl_logic_vector(31 downto 0);
        PRDATAS9        : in     vl_logic_vector(31 downto 0);
        PRDATAS10       : in     vl_logic_vector(31 downto 0);
        PRDATAS11       : in     vl_logic_vector(31 downto 0);
        PRDATAS12       : in     vl_logic_vector(31 downto 0);
        PRDATAS13       : in     vl_logic_vector(31 downto 0);
        PRDATAS14       : in     vl_logic_vector(31 downto 0);
        PRDATAS15       : in     vl_logic_vector(31 downto 0);
        PRDATAS16       : in     vl_logic_vector(31 downto 0);
        PREADYS0        : in     vl_logic;
        PREADYS1        : in     vl_logic;
        PREADYS2        : in     vl_logic;
        PREADYS3        : in     vl_logic;
        PREADYS4        : in     vl_logic;
        PREADYS5        : in     vl_logic;
        PREADYS6        : in     vl_logic;
        PREADYS7        : in     vl_logic;
        PREADYS8        : in     vl_logic;
        PREADYS9        : in     vl_logic;
        PREADYS10       : in     vl_logic;
        PREADYS11       : in     vl_logic;
        PREADYS12       : in     vl_logic;
        PREADYS13       : in     vl_logic;
        PREADYS14       : in     vl_logic;
        PREADYS15       : in     vl_logic;
        PREADYS16       : in     vl_logic;
        PSLVERRS0       : in     vl_logic;
        PSLVERRS1       : in     vl_logic;
        PSLVERRS2       : in     vl_logic;
        PSLVERRS3       : in     vl_logic;
        PSLVERRS4       : in     vl_logic;
        PSLVERRS5       : in     vl_logic;
        PSLVERRS6       : in     vl_logic;
        PSLVERRS7       : in     vl_logic;
        PSLVERRS8       : in     vl_logic;
        PSLVERRS9       : in     vl_logic;
        PSLVERRS10      : in     vl_logic;
        PSLVERRS11      : in     vl_logic;
        PSLVERRS12      : in     vl_logic;
        PSLVERRS13      : in     vl_logic;
        PSLVERRS14      : in     vl_logic;
        PSLVERRS15      : in     vl_logic;
        PSLVERRS16      : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of APB_DWIDTH : constant is 2;
    attribute mti_svvh_generic_type of IADDR_OPTION : constant is 1;
    attribute mti_svvh_generic_type of APBSLOT0ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT1ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT2ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT3ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT4ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT5ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT6ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT7ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT8ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT9ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT10ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT11ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT12ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT13ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT14ENABLE : constant is 2;
    attribute mti_svvh_generic_type of APBSLOT15ENABLE : constant is 2;
    attribute mti_svvh_generic_type of SC_0 : constant is 2;
    attribute mti_svvh_generic_type of SC_1 : constant is 2;
    attribute mti_svvh_generic_type of SC_2 : constant is 2;
    attribute mti_svvh_generic_type of SC_3 : constant is 2;
    attribute mti_svvh_generic_type of SC_4 : constant is 2;
    attribute mti_svvh_generic_type of SC_5 : constant is 2;
    attribute mti_svvh_generic_type of SC_6 : constant is 2;
    attribute mti_svvh_generic_type of SC_7 : constant is 2;
    attribute mti_svvh_generic_type of SC_8 : constant is 2;
    attribute mti_svvh_generic_type of SC_9 : constant is 2;
    attribute mti_svvh_generic_type of SC_10 : constant is 2;
    attribute mti_svvh_generic_type of SC_11 : constant is 2;
    attribute mti_svvh_generic_type of SC_12 : constant is 2;
    attribute mti_svvh_generic_type of SC_13 : constant is 2;
    attribute mti_svvh_generic_type of SC_14 : constant is 2;
    attribute mti_svvh_generic_type of SC_15 : constant is 2;
    attribute mti_svvh_generic_type of MADDR_BITS : constant is 2;
    attribute mti_svvh_generic_type of UPR_NIBBLE_POSN : constant is 2;
end CoreAPB3;
