`timescale 1 ns/100 ps
// Version: v11.8 11.8.0.26


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_075(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module counter28(
       cntout_c,
       my_hpms_top_0_HPMS_READY,
       my_hpms_top_0_FIC32_0_CLK
    );
output [27:24] cntout_c;
input  my_hpms_top_0_HPMS_READY;
input  my_hpms_top_0_FIC32_0_CLK;

    wire \cnt[0]_net_1 , \cnt_s[0] , VCC_net_1, GND_net_1, 
        \cnt[1]_net_1 , \cnt_s[1] , \cnt[2]_net_1 , \cnt_s[2] , 
        \cnt[3]_net_1 , \cnt_s[3] , \cnt[4]_net_1 , \cnt_s[4] , 
        \cnt[5]_net_1 , \cnt_s[5] , \cnt[6]_net_1 , \cnt_s[6] , 
        \cnt[7]_net_1 , \cnt_s[7] , \cnt[8]_net_1 , \cnt_s[8] , 
        \cnt[9]_net_1 , \cnt_s[9] , \cnt[10]_net_1 , \cnt_s[10] , 
        \cnt[11]_net_1 , \cnt_s[11] , \cnt[12]_net_1 , \cnt_s[12] , 
        \cnt[13]_net_1 , \cnt_s[13] , \cnt[14]_net_1 , \cnt_s[14] , 
        \cnt[15]_net_1 , \cnt_s[15] , \cnt[16]_net_1 , \cnt_s[16] , 
        \cnt[17]_net_1 , \cnt_s[17] , \cnt[18]_net_1 , \cnt_s[18] , 
        \cnt[19]_net_1 , \cnt_s[19] , \cnt[20]_net_1 , \cnt_s[20] , 
        \cnt[21]_net_1 , \cnt_s[21] , \cnt[22]_net_1 , \cnt_s[22] , 
        \cnt[23]_net_1 , \cnt_s[23] , \cnt_s[24] , \cnt_s[25] , 
        \cnt_s[26] , \cnt_s[27]_net_1 , cnt_s_809_FCO, 
        \cnt_cry[1]_net_1 , \cnt_cry[2]_net_1 , \cnt_cry[3]_net_1 , 
        \cnt_cry[4]_net_1 , \cnt_cry[5]_net_1 , \cnt_cry[6]_net_1 , 
        \cnt_cry[7]_net_1 , \cnt_cry[8]_net_1 , \cnt_cry[9]_net_1 , 
        \cnt_cry[10]_net_1 , \cnt_cry[11]_net_1 , \cnt_cry[12]_net_1 , 
        \cnt_cry[13]_net_1 , \cnt_cry[14]_net_1 , \cnt_cry[15]_net_1 , 
        \cnt_cry[16]_net_1 , \cnt_cry[17]_net_1 , \cnt_cry[18]_net_1 , 
        \cnt_cry[19]_net_1 , \cnt_cry[20]_net_1 , \cnt_cry[21]_net_1 , 
        \cnt_cry[22]_net_1 , \cnt_cry[23]_net_1 , \cnt_cry[24]_net_1 , 
        \cnt_cry[25]_net_1 , \cnt_cry[26]_net_1 ;
    
    SLE \cnt[19]  (.D(\cnt_s[19] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[19]_net_1 ));
    SLE \cnt[27]  (.D(\cnt_s[27]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(my_hpms_top_0_HPMS_READY), .SD(GND_net_1)
        , .LAT(GND_net_1), .Q(cntout_c[27]));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[16]  (.A(VCC_net_1), .B(
        \cnt[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[15]_net_1 ), .S(\cnt_s[16] ), .Y(), .FCO(
        \cnt_cry[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[4]  (.A(VCC_net_1), .B(
        \cnt[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[3]_net_1 ), .S(\cnt_s[4] ), .Y(), .FCO(
        \cnt_cry[4]_net_1 ));
    SLE \cnt[2]  (.D(\cnt_s[2] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[2]_net_1 ));
    SLE \cnt[8]  (.D(\cnt_s[8] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[8]_net_1 ));
    SLE \cnt[26]  (.D(\cnt_s[26] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cntout_c[26]));
    SLE \cnt[1]  (.D(\cnt_s[1] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[1]_net_1 ));
    SLE \cnt[11]  (.D(\cnt_s[11] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[11]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[26]  (.A(VCC_net_1), .B(
        cntout_c[26]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[25]_net_1 ), .S(\cnt_s[26] ), .Y(), .FCO(
        \cnt_cry[26]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[6]  (.A(VCC_net_1), .B(
        \cnt[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[5]_net_1 ), .S(\cnt_s[6] ), .Y(), .FCO(
        \cnt_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[9]  (.A(VCC_net_1), .B(
        \cnt[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[8]_net_1 ), .S(\cnt_s[9] ), .Y(), .FCO(
        \cnt_cry[9]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[2]  (.A(VCC_net_1), .B(
        \cnt[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[1]_net_1 ), .S(\cnt_s[2] ), .Y(), .FCO(
        \cnt_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[19]  (.A(VCC_net_1), .B(
        \cnt[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[18]_net_1 ), .S(\cnt_s[19] ), .Y(), .FCO(
        \cnt_cry[19]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[18]  (.A(VCC_net_1), .B(
        \cnt[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[17]_net_1 ), .S(\cnt_s[18] ), .Y(), .FCO(
        \cnt_cry[18]_net_1 ));
    SLE \cnt[17]  (.D(\cnt_s[17] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[17]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[11]  (.A(VCC_net_1), .B(
        \cnt[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[10]_net_1 ), .S(\cnt_s[11] ), .Y(), .FCO(
        \cnt_cry[11]_net_1 ));
    SLE \cnt[16]  (.D(\cnt_s[16] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[15]  (.A(VCC_net_1), .B(
        \cnt[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[14]_net_1 ), .S(\cnt_s[15] ), .Y(), .FCO(
        \cnt_cry[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[21]  (.A(VCC_net_1), .B(
        \cnt[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[20]_net_1 ), .S(\cnt_s[21] ), .Y(), .FCO(
        \cnt_cry[21]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[10]  (.A(VCC_net_1), .B(
        \cnt[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[9]_net_1 ), .S(\cnt_s[10] ), .Y(), .FCO(
        \cnt_cry[10]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[25]  (.A(VCC_net_1), .B(
        cntout_c[25]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[24]_net_1 ), .S(\cnt_s[25] ), .Y(), .FCO(
        \cnt_cry[25]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[20]  (.A(VCC_net_1), .B(
        \cnt[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[19]_net_1 ), .S(\cnt_s[20] ), .Y(), .FCO(
        \cnt_cry[20]_net_1 ));
    SLE \cnt[6]  (.D(\cnt_s[6] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[6]_net_1 ));
    SLE \cnt[4]  (.D(\cnt_s[4] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[4]_net_1 ));
    SLE \cnt[9]  (.D(\cnt_s[9] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[9]_net_1 ));
    CFG1 #( .INIT(2'h1) )  \cnt_RNO[0]  (.A(\cnt[0]_net_1 ), .Y(
        \cnt_s[0] ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[3]  (.A(VCC_net_1), .B(
        \cnt[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[2]_net_1 ), .S(\cnt_s[3] ), .Y(), .FCO(
        \cnt_cry[3]_net_1 ));
    SLE \cnt[0]  (.D(\cnt_s[0] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[0]_net_1 ));
    GND GND (.Y(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[13]  (.A(VCC_net_1), .B(
        \cnt[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[12]_net_1 ), .S(\cnt_s[13] ), .Y(), .FCO(
        \cnt_cry[13]_net_1 ));
    SLE \cnt[23]  (.D(\cnt_s[23] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[23]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[23]  (.A(VCC_net_1), .B(
        \cnt[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[22]_net_1 ), .S(\cnt_s[23] ), .Y(), .FCO(
        \cnt_cry[23]_net_1 ));
    SLE \cnt[20]  (.D(\cnt_s[20] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[20]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[8]  (.A(VCC_net_1), .B(
        \cnt[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[7]_net_1 ), .S(\cnt_s[8] ), .Y(), .FCO(
        \cnt_cry[8]_net_1 ));
    SLE \cnt[13]  (.D(\cnt_s[13] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[13]_net_1 ));
    SLE \cnt[18]  (.D(\cnt_s[18] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[18]_net_1 ));
    SLE \cnt[7]  (.D(\cnt_s[7] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[7]_net_1 ));
    SLE \cnt[10]  (.D(\cnt_s[10] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[14]  (.A(VCC_net_1), .B(
        \cnt[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[13]_net_1 ), .S(\cnt_s[14] ), .Y(), .FCO(
        \cnt_cry[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[24]  (.A(VCC_net_1), .B(
        cntout_c[24]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[23]_net_1 ), .S(\cnt_s[24] ), .Y(), .FCO(
        \cnt_cry[24]_net_1 ));
    SLE \cnt[3]  (.D(\cnt_s[3] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[17]  (.A(VCC_net_1), .B(
        \cnt[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[16]_net_1 ), .S(\cnt_s[17] ), .Y(), .FCO(
        \cnt_cry[17]_net_1 ));
    SLE \cnt[25]  (.D(\cnt_s[25] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cntout_c[25]));
    ARI1 #( .INIT(20'h4AA00) )  cnt_s_809 (.A(VCC_net_1), .B(
        \cnt[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), 
        .S(), .Y(), .FCO(cnt_s_809_FCO));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_s[27]  (.A(VCC_net_1), .B(
        cntout_c[27]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[26]_net_1 ), .S(\cnt_s[27]_net_1 ), .Y(), .FCO());
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[5]  (.A(VCC_net_1), .B(
        \cnt[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[4]_net_1 ), .S(\cnt_s[5] ), .Y(), .FCO(
        \cnt_cry[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[12]  (.A(VCC_net_1), .B(
        \cnt[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[11]_net_1 ), .S(\cnt_s[12] ), .Y(), .FCO(
        \cnt_cry[12]_net_1 ));
    SLE \cnt[22]  (.D(\cnt_s[22] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[22]_net_1 ));
    SLE \cnt[15]  (.D(\cnt_s[15] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[22]  (.A(VCC_net_1), .B(
        \cnt[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[21]_net_1 ), .S(\cnt_s[22] ), .Y(), .FCO(
        \cnt_cry[22]_net_1 ));
    SLE \cnt[24]  (.D(\cnt_s[24] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cntout_c[24]));
    SLE \cnt[5]  (.D(\cnt_s[5] ), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[5]_net_1 ));
    SLE \cnt[12]  (.D(\cnt_s[12] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[1]  (.A(VCC_net_1), .B(
        \cnt[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        cnt_s_809_FCO), .S(\cnt_s[1] ), .Y(), .FCO(\cnt_cry[1]_net_1 ));
    SLE \cnt[14]  (.D(\cnt_s[14] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \cnt_cry[7]  (.A(VCC_net_1), .B(
        \cnt[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \cnt_cry[6]_net_1 ), .S(\cnt_s[7] ), .Y(), .FCO(
        \cnt_cry[7]_net_1 ));
    SLE \cnt[21]  (.D(\cnt_s[21] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        my_hpms_top_0_HPMS_READY), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cnt[21]_net_1 ));
    
endmodule


module COREAPB3_MUXPTOB3(
       PRDATA_0_iv_0_0_0_2,
       PRDATA_0_iv_0_0_0_0,
       PRDATA_0_iv_0_0_0_3,
       APB_register_blk_0_PRDATA_12,
       APB_register_blk_0_PRDATA_2,
       APB_register_blk_0_PRDATA_0,
       APB_register_blk_0_PRDATA_3,
       iPRDATA_2,
       iPRDATA_0,
       iPRDATA_3,
       N_180,
       iPRDATA_0_sqmuxa,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave1_PSELx
    );
output PRDATA_0_iv_0_0_0_2;
output PRDATA_0_iv_0_0_0_0;
output PRDATA_0_iv_0_0_0_3;
input  APB_register_blk_0_PRDATA_12;
input  APB_register_blk_0_PRDATA_2;
input  APB_register_blk_0_PRDATA_0;
input  APB_register_blk_0_PRDATA_3;
input  iPRDATA_2;
input  iPRDATA_0;
input  iPRDATA_3;
output N_180;
output iPRDATA_0_sqmuxa;
input  CoreAPB3_0_APBmslave0_PSELx;
input  CoreAPB3_0_APBmslave1_PSELx;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hE2C0) )  \PRDATA_0_iv_0_0_0[3]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_3), .D(APB_register_blk_0_PRDATA_3), .Y(
        PRDATA_0_iv_0_0_0_3));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hE2C0) )  \PRDATA_0_iv_0_0_0[2]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_2), .D(APB_register_blk_0_PRDATA_2), .Y(
        PRDATA_0_iv_0_0_0_2));
    CFG4 #( .INIT(16'hE2C0) )  \PRDATA_0_iv_0_0_0[0]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_0), .D(APB_register_blk_0_PRDATA_0), .Y(
        PRDATA_0_iv_0_0_0_0));
    CFG3 #( .INIT(8'h08) )  \PRDATA_0_iv_0_0_a2[12]  (.A(
        APB_register_blk_0_PRDATA_12), .B(CoreAPB3_0_APBmslave0_PSELx), 
        .C(CoreAPB3_0_APBmslave1_PSELx), .Y(N_180));
    CFG2 #( .INIT(4'h4) )  iPRDATA_0_sqmuxa_0_a2_1_a2_0 (.A(
        CoreAPB3_0_APBmslave1_PSELx), .B(CoreAPB3_0_APBmslave0_PSELx), 
        .Y(iPRDATA_0_sqmuxa));
    
endmodule


module CoreAPB3_Z11(
       iPRDATA_2,
       iPRDATA_0,
       iPRDATA_3,
       APB_register_blk_0_PRDATA_12,
       APB_register_blk_0_PRDATA_2,
       APB_register_blk_0_PRDATA_0,
       APB_register_blk_0_PRDATA_3,
       PRDATA_0_iv_0_0_0_2,
       PRDATA_0_iv_0_0_0_0,
       PRDATA_0_iv_0_0_0_3,
       CoreAPB3_0_APBmslave1_PSELx,
       CoreAPB3_0_APBmslave0_PSELx,
       iPRDATA_0_sqmuxa,
       N_180
    );
input  iPRDATA_2;
input  iPRDATA_0;
input  iPRDATA_3;
input  APB_register_blk_0_PRDATA_12;
input  APB_register_blk_0_PRDATA_2;
input  APB_register_blk_0_PRDATA_0;
input  APB_register_blk_0_PRDATA_3;
output PRDATA_0_iv_0_0_0_2;
output PRDATA_0_iv_0_0_0_0;
output PRDATA_0_iv_0_0_0_3;
input  CoreAPB3_0_APBmslave1_PSELx;
input  CoreAPB3_0_APBmslave0_PSELx;
output iPRDATA_0_sqmuxa;
output N_180;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAPB3_MUXPTOB3 u_mux_p_to_b3 (.PRDATA_0_iv_0_0_0_2(
        PRDATA_0_iv_0_0_0_2), .PRDATA_0_iv_0_0_0_0(PRDATA_0_iv_0_0_0_0)
        , .PRDATA_0_iv_0_0_0_3(PRDATA_0_iv_0_0_0_3), 
        .APB_register_blk_0_PRDATA_12(APB_register_blk_0_PRDATA_12), 
        .APB_register_blk_0_PRDATA_2(APB_register_blk_0_PRDATA_2), 
        .APB_register_blk_0_PRDATA_0(APB_register_blk_0_PRDATA_0), 
        .APB_register_blk_0_PRDATA_3(APB_register_blk_0_PRDATA_3), 
        .iPRDATA_2(iPRDATA_2), .iPRDATA_0(iPRDATA_0), .iPRDATA_3(
        iPRDATA_3), .N_180(N_180), .iPRDATA_0_sqmuxa(iPRDATA_0_sqmuxa), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .CoreAPB3_0_APBmslave1_PSELx(CoreAPB3_0_APBmslave1_PSELx));
    GND GND (.Y(GND_net_1));
    
endmodule


module UART_top_COREABC_0_INSTRUCTIONS_Z10(
       INSTR_CMD,
       SMADDR,
       SMADDR_i,
       COREABC_0_APB3master_PADDR_0,
       doins_0_dreg_RNIJ2TF_0,
       COREABC_0_APB3master_PADDR_i_0,
       un1_ICYCLE_6_i,
       DOJMP,
       N_123_i,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave1_PSELx,
       m3_1,
       doins_adflt,
       doins_adflt_reto,
       doins_adflt_i_reto,
       doins_adflt_i,
       m10,
       G_622,
       N_7108_reto,
       N_7107_reto,
       N_7102_reto,
       N_7101_reto,
       N_7100_reto,
       N_7123_reto,
       N_7119_reto,
       N_7115_reto,
       N_7112_reto,
       N_7111_reto,
       N_7110_reto,
       N_7109_reto,
       N_7130_reto,
       N_7129_reto,
       N_7128_reto,
       N_7127_reto,
       N_7126_reto,
       N_7125_reto,
       my_hpms_top_0_FIC32_0_CLK,
       N_7124_reto
    );
output [2:0] INSTR_CMD;
input  [10:9] SMADDR;
input  [8:0] SMADDR_i;
output COREABC_0_APB3master_PADDR_0;
output doins_0_dreg_RNIJ2TF_0;
output COREABC_0_APB3master_PADDR_i_0;
output un1_ICYCLE_6_i;
input  DOJMP;
input  N_123_i;
output CoreAPB3_0_APBmslave0_PSELx;
output CoreAPB3_0_APBmslave1_PSELx;
input  m3_1;
output doins_adflt;
input  doins_adflt_reto;
input  doins_adflt_i_reto;
output doins_adflt_i;
output m10;
input  G_622;
output N_7108_reto;
output N_7107_reto;
output N_7102_reto;
output N_7101_reto;
output N_7100_reto;
output N_7123_reto;
output N_7119_reto;
output N_7115_reto;
output N_7112_reto;
output N_7111_reto;
output N_7110_reto;
output N_7109_reto;
output N_7130_reto;
output N_7129_reto;
output N_7128_reto;
output N_7127_reto;
output N_7126_reto;
output N_7125_reto;
input  my_hpms_top_0_FIC32_0_CLK;
output N_7124_reto;

    wire VCC_net_1, m315, GND_net_1, m344, m375, m406, m426_4, m445, 
        i7_mux_0, N_498_mux, m221, m229, N_499_mux, m232, m245, 
        N_500_mux, m285, N_7097_reto, N_44_i, N_7098_reto, N_86_i, 
        N_7099_reto, N_113_i, m135, m157, N_497_mux, N_7103_reto, m190, 
        m200_ns, m206_ns, m313_4_1_0_wmux_0_Y, m313_2, N_459_mux, 
        m313_4_1_0_0_y0, m313_4_1_0_0_co0, m305_0_0_wmux_0_Y, i2_mux, 
        N_2_i_i, m358_0_0_y0, m358_0_0_co0, m19, m188_0_0_wmux_0_Y, 
        N_14773_i, m186, m188_0_0_y0, m188_0_0_co0, N_185_i, m78, 
        m121_0_0_wmux_0_Y, m13, m34, m121_0_0_y0, m121_0_0_co0, m21, 
        m23, m381_0_0_wmux_0_Y, N_7_i, m93, m381_0_0_y0, m381_0_0_co0, 
        N_47_i, m402_0_0_wmux_0_Y, N_401_i, m297, m402_0_0_y0, 
        m402_0_0_co0, N_265_i, m436_0_0_wmux_0_Y, m279, m436_0_0_y0, 
        m436_0_0_co0, m179, N_277_i, m305_0_0_y0, m305_0_0_co0, 
        N_303_i, m50_0_0_wmux_0_Y, m9, m48, m50_0_0_y0, m50_0_0_co0, 
        N_4_i, m44, m183_0_0_wmux_0_Y, N_182_i, m127, m183_0_0_y0, 
        m183_0_0_co0, N_14774_i, N_146_i_0, m389_0_0_wmux_0_Y, N_386_i, 
        m387, m389_0_0_y0, m389_0_0_co0, N_98_i, m149_0_0_wmux_0_Y, 
        N_148_i, m72, m149_0_0_y0, m149_0_0_co0, m56_ns, m139_3, m80, 
        m139_4, m113, m116_1, m339_0, N_340_i, m145_0, m29, m335_2, 
        m361_bm_1, m361_ns_1, m361_ns, m351, m404_ns_1, m404_ns, 
        m404_am_1, m397, m83, m74_ns, N_86_i_1_0, m110, m104_ns, 
        N_113_i_1_0, m87, N_44_i_1_0, m16_ns, m33_ns, m41, m406_1_1, 
        m376_ns, m243, m241_ns, m245_1_1, m235_ns, m155, m157_1_1, 
        m133, m129_ns, m135_1_1, m116_4, m373, m375_1_1, m348, 
        m190_1_1, m175_ns, m301, m315_1_1, m290, m73_0, m104_bm_1, 
        m104_bm, m71, m101, m268, m283_4, m285_1_1, m256_4, m330, 
        m342_4, m344_1_1, m318_ns, m391, m394, m167, m168_1_1, m168, 
        m59, m164_1_0, m168_1_0_1, m91, m160, m83_1, m83_2, m155_1, 
        m150, m153, m83_1_0, m76, m443_1_1, m443, m441_ns, m24, m367_4, 
        m371, m373_1_1, m110_2, m110_1, m243_1, m209_1_0, m207, m209_2, 
        i7_mux, m126, N_460_mux, m330_1_2, m328, m330_1_1, m301_1_2, 
        m299, m294, m38, m268_1_2, m266, m268_1_1, m16_am_1_0, m16_am, 
        m4, N_2_i, m16_bm_1, m16_bm_1_0, m16_bm, m12, m159, m162, 
        N_386_i_1_0, m95_1, m95_2, m95, m180, m387_1_0, m41_1_2, m92, 
        m371_1_2, m299_1_2, m266_0, m328_1_0, m326, m433, m445_1_1, 
        N_496_mux, m142, m256_3, m274_1_1, m274_1, m283_4_1_1, m274_4, 
        m283_2, m342_4_1_1, m342_2, m335_4, m366, m367_4_1, m367_4_1_0, 
        m363, m426_2, m426_4_1_1, i6_mux_1, m441_ns_1, m249_ns_1, 
        i5_mux_6, m11_0, m68, m30, m452_ns_1, i8_mux, m421_ns_1_0, 
        m421_ns_1, m74_bm, m74_am, m104_am, m129_bm, m129_am, m200_bm, 
        m200_am, m241_bm, m241_am, m33_bm, m33_am, m206_bm, m206_am, 
        m235_bm, m235_am, m175_bm, m175_am, m376_bm, m376_am, m56_bm, 
        m56_am, m318_bm, m318_am, m428_3, m428_1, i5_mux_4, N_11_i, 
        m428_2, m400, m123, m428_0, i4_mux_1, N_467_mux, m335_3, 
        m335_1, m60, m335_0, m308, m310, m277, N_281_i_0, m274_3, 
        m274_2, m256_1, m256_0, m136, m139_2, m47, m116_3, N_48_i, 
        m116_2, m63_3, m63_1, m63_4, m63_2, m63_0, N_5_i, m204_e_0, 
        m193, m261_e, m212_e, m204_e, m264, N_477_mux, m27, m266_1, 
        m107, m22, N_478_mux, m407, m286, m124, m67, m346, i5_mux_0, 
        m217, m131, m110_0, m110_3, m128, m240, m133_0, m73, m220;
    
    CFG4 #( .INIT(16'hFFF8) )  \doins_0_57_0_.m74_bm  (.A(SMADDR_i[0]), 
        .B(m72), .C(m73), .D(m73_0), .Y(m74_bm));
    CFG2 #( .INIT(4'h8) )  doins_6dflt (.A(N_7103_reto), .B(
        doins_adflt_reto), .Y(COREABC_0_APB3master_PADDR_0));
    CFG4 #( .INIT(16'h0400) )  \doins_0_57_0_.m318_bm  (.A(SMADDR_i[1])
        , .B(N_2_i), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m318_bm));
    CFG4 #( .INIT(16'h9180) )  \doins_0_57_0_.m217  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m34), .D(m21), .Y(m217));
    CFG2 #( .INIT(4'h1) )  \doins_0_57_0_.m212_e  (.A(SMADDR_i[1]), .B(
        SMADDR_i[5]), .Y(m212_e));
    CFG2 #( .INIT(4'h2) )  \doins_0_57_0_.m198_e  (.A(SMADDR_i[0]), .B(
        SMADDR_i[6]), .Y(m204_e_0));
    CFG4 #( .INIT(16'hFFEC) )  \doins_0_57_0_.m129_bm  (.A(m127), .B(
        m73_0), .C(SMADDR_i[0]), .D(m128), .Y(m129_bm));
    CFG3 #( .INIT(8'h35) )  \doins_0_57_0_.m283_4_1_1  (.A(m283_2), .B(
        m38), .C(SMADDR_i[0]), .Y(m283_4_1_1));
    CFG4 #( .INIT(16'hA143) )  \doins_0_57_0_.N_281_i  (.A(SMADDR_i[4])
        , .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(
        N_281_i_0));
    CFG4 #( .INIT(16'h3F44) )  \doins_0_57_0_.N_86_i  (.A(m83), .B(
        SMADDR_i[8]), .C(m74_ns), .D(N_86_i_1_0), .Y(N_86_i));
    CFG4 #( .INIT(16'hB1F5) )  \doins_0_57_0_.m441_ns  (.A(SMADDR_i[5])
        , .B(SMADDR_i[1]), .C(m441_ns_1), .D(m13), .Y(m441_ns));
    CFG4 #( .INIT(16'h1D0C) )  \doins_0_57_0_.m328_1  (.A(SMADDR_i[2]), 
        .B(SMADDR_i[1]), .C(m326), .D(N_2_i), .Y(m328_1_0));
    CFG3 #( .INIT(8'hA1) )  \doins_0_57_0_.m335_2  (.A(SMADDR_i[1]), 
        .B(m19), .C(SMADDR_i[2]), .Y(m335_2));
    CFG4 #( .INIT(16'h30AF) )  \doins_0_57_0_.m375  (.A(m373), .B(
        m361_ns), .C(SMADDR_i[8]), .D(m375_1_1), .Y(m375));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m315_1_1  (.A(
        SMADDR_i[6]), .B(m290), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        m315_1_1));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m200_ns  (.A(SMADDR_i[8]), 
        .B(m200_bm), .C(m200_am), .Y(m200_ns));
    SLE \doins_0_dreg[31]  (.D(m426_4), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7128_reto));
    SLE \doins_0_dreg[32]  (.D(m445), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7129_reto));
    CFG4 #( .INIT(16'h5776) )  \doins_0_57_0_.m48  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m48));
    CFG4 #( .INIT(16'h0080) )  \doins_0_57_0_.m266_1  (.A(SMADDR_i[1]), 
        .B(m19), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m266_0));
    SLE \doins_0_dreg[10]  (.D(m200_ns), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7107_reto));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m63_1  (.A(m59), .B(m63_0), 
        .C(SMADDR_i[1]), .Y(m63_1));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m104_ns  (.A(SMADDR_i[6]), 
        .B(m104_bm), .C(m104_am), .Y(m104_ns));
    CFG3 #( .INIT(8'hE2) )  \doins_0_57_0_.m104_am  (.A(m95), .B(
        SMADDR_i[0]), .C(N_98_i), .Y(m104_am));
    CFG4 #( .INIT(16'h5140) )  \doins_0_57_0_.m167  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m142), .D(N_2_i), .Y(m167));
    CFG3 #( .INIT(8'h47) )  \doins_0_57_0_.m445_1_1  (.A(SMADDR_i[7]), 
        .B(SMADDR_i[8]), .C(N_496_mux), .Y(m445_1_1));
    SLE \doins_0_dreg[1]  (.D(N_86_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7098_reto));
    CFG4 #( .INIT(16'h7250) )  \doins_0_57_0_.m433  (.A(SMADDR_i[6]), 
        .B(m193), .C(N_467_mux), .D(i5_mux_4), .Y(m433));
    CFG4 #( .INIT(16'h7255) )  \doins_0_57_0_.m371_1_2  (.A(
        SMADDR_i[1]), .B(N_2_i), .C(SMADDR_i[3]), .D(SMADDR_i[5]), .Y(
        m371_1_2));
    SLE \doins_0_dreg[3]  (.D(m135), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7100_reto));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m241_ns  (.A(SMADDR_i[6]), 
        .B(m241_bm), .C(m241_am), .Y(m241_ns));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m406_1_1  (.A(
        SMADDR_i[6]), .B(m376_ns), .C(SMADDR_i[7]), .D(SMADDR_i[8]), 
        .Y(m406_1_1));
    CFG3 #( .INIT(8'h02) )  \doins_0_57_0_.m29  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m29));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m170  (.A(SMADDR_i[7]), .B(
        SMADDR_i[8]), .C(m168), .Y(N_497_mux));
    CFG4 #( .INIT(16'h1D0C) )  \doins_0_57_0_.m443_1_1  (.A(
        SMADDR_i[5]), .B(SMADDR_i[6]), .C(m441_ns), .D(m24), .Y(
        m443_1_1));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m249_ns_1  (.A(SMADDR_i[1]), 
        .B(m11_0), .C(SMADDR_i[5]), .Y(m249_ns_1));
    CFG4 #( .INIT(16'hAC00) )  \doins_0_57_0_.m220  (.A(m131), .B(m217)
        , .C(SMADDR_i[7]), .D(m204_e_0), .Y(m220));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m216  (.A(SMADDR_i[6]), .B(
        i7_mux), .C(SMADDR_i[8]), .Y(N_498_mux));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m436_0_0_wmux_0  (.A(
        m436_0_0_y0), .B(SMADDR_i[5]), .C(m279), .D(N_2_i_i), .FCI(
        m436_0_0_co0), .S(), .Y(m436_0_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h0080) )  \doins_0_57_0_.m78  (.A(SMADDR_i[1]), 
        .B(m10), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m78));
    CFG4 #( .INIT(16'h1555) )  \doins_0_57_0_.m124  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m124));
    CFG4 #( .INIT(16'h3276) )  \doins_0_57_0_.N_386_i_1_0  (.A(
        SMADDR_i[5]), .B(SMADDR_i[1]), .C(m12), .D(N_2_i), .Y(
        N_386_i_1_0));
    CFG4 #( .INIT(16'hEFEE) )  \doins_0_57_0_.m155  (.A(m83_1), .B(
        m83_2), .C(SMADDR_i[6]), .D(m155_1), .Y(m155));
    CFG4 #( .INIT(16'hCA33) )  \doins_0_57_0_.m426_4  (.A(m426_2), .B(
        m426_4_1_1), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(m426_4));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m402_0_0_wmux_0  (.A(
        m402_0_0_y0), .B(SMADDR_i[5]), .C(N_401_i), .D(m297), .FCI(
        m402_0_0_co0), .S(), .Y(m402_0_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h2A08) )  \doins_0_57_0_.m97  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m47), .D(N_2_i), .Y(N_98_i));
    CFG4 #( .INIT(16'hD9C8) )  \doins_0_57_0_.m342_2  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m326), .D(N_340_i), .Y(m342_2));
    CFG4 #( .INIT(16'hA00C) )  \doins_0_57_0_.m452_ns  (.A(m68), .B(
        m30), .C(SMADDR_i[8]), .D(m452_ns_1), .Y(i8_mux));
    SLE \doins_0_dreg[30]  (.D(m406), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7127_reto));
    CFG4 #( .INIT(16'h9810) )  \doins_0_57_0_.m417  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[0]), .C(m124), .D(m400), .Y(i4_mux_1));
    CFG2 #( .INIT(4'hE) )  doins_0dflt (.A(doins_adflt_i_reto), .B(
        N_7097_reto), .Y(INSTR_CMD[0]));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m366  (.A(SMADDR_i[3]), .B(
        SMADDR_i[2]), .C(SMADDR_i[1]), .Y(m366));
    CFG3 #( .INIT(8'h10) )  \doins_0_57_0_.m23  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m23));
    CFG4 #( .INIT(16'h0D6A) )  \doins_0_57_0_.m394  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m394));
    CFG4 #( .INIT(16'h00C4) )  \doins_0_57_0_.m76  (.A(SMADDR_i[1]), 
        .B(m10), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m76));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m63_4  (.A(SMADDR_i[5]), .B(
        m63_3), .C(m63_1), .Y(m63_4));
    CFG3 #( .INIT(8'h04) )  \doins_0_57_0_.m34  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m34));
    CFG2 #( .INIT(4'hE) )  doins_adflt_i_0 (.A(SMADDR[9]), .B(
        SMADDR[10]), .Y(doins_adflt_i));
    CFG3 #( .INIT(8'hCA) )  \doins_0_57_0_.m116_1  (.A(N_4_i), .B(m113)
        , .C(SMADDR_i[5]), .Y(m116_1));
    CFG4 #( .INIT(16'h0444) )  \doins_0_57_0_.m110_2  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[6]), .C(m107), .D(SMADDR_i[5]), .Y(m110_1));
    CFG3 #( .INIT(8'h51) )  \doins_0_57_0_.m274_1_1  (.A(SMADDR_i[1]), 
        .B(m12), .C(SMADDR_i[2]), .Y(m274_1_1));
    CFG3 #( .INIT(8'h1B) )  \doins_0_57_0_.m164_1_0  (.A(SMADDR_i[1]), 
        .B(m159), .C(m162), .Y(m164_1_0));
    CFG3 #( .INIT(8'h08) )  \doins_0_57_0_.m204_e  (.A(SMADDR_i[1]), 
        .B(m204_e_0), .C(SMADDR_i[5]), .Y(m204_e));
    CFG4 #( .INIT(16'h688A) )  \doins_0_57_0_.m101  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m101));
    CFG4 #( .INIT(16'h8000) )  \doins_0_57_0_.m3  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(N_4_i));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m376_ns  (.A(SMADDR_i[0]), 
        .B(m376_bm), .C(m376_am), .Y(m376_ns));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m139_2  (.A(SMADDR_i[1]), 
        .B(m9), .C(SMADDR_i[5]), .Y(m139_2));
    CFG4 #( .INIT(16'h0001) )  \doins_0_57_0_.m68  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m68));
    CFG4 #( .INIT(16'hA0DD) )  \doins_0_57_0_.m274_1  (.A(SMADDR_i[2]), 
        .B(m10), .C(N_2_i), .D(m274_1_1), .Y(m274_1));
    CFG2 #( .INIT(4'h6) )  \doins_0_57_0_.N_303_i  (.A(m12), .B(
        SMADDR_i[2]), .Y(N_303_i));
    CFG4 #( .INIT(16'h5773) )  \doins_0_57_0_.m56_bm  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m56_bm));
    CFG2 #( .INIT(4'h6) )  \doins_0_57_0_.m193  (.A(SMADDR_i[5]), .B(
        SMADDR_i[0]), .Y(m193));
    GND GND (.Y(GND_net_1));
    SLE \doins_0_dreg[28]  (.D(m344), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7125_reto));
    CFG2 #( .INIT(4'h4) )  \doins_0_57_0_.m19  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(m19));
    SLE \doins_0_dreg[26]  (.D(m285), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7123_reto));
    CFG4 #( .INIT(16'h5B03) )  \doins_0_57_0_.m391  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m391));
    CFG4 #( .INIT(16'h1B5F) )  \doins_0_57_0_.m56_am  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[2]), .C(m21), .D(m19), .Y(m56_am));
    CFG3 #( .INIT(8'h2F) )  \doins_0_57_0_.m342_4_1_1  (.A(SMADDR_i[0])
        , .B(m38), .C(SMADDR_i[6]), .Y(m342_4_1_1));
    CFG4 #( .INIT(16'h75FD) )  \doins_0_57_0_.m235_bm  (.A(SMADDR_i[5])
        , .B(SMADDR_i[1]), .C(m47), .D(N_2_i), .Y(m235_bm));
    CFG4 #( .INIT(16'hD9C8) )  \doins_0_57_0_.m145_0  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m142), .D(m19), .Y(m145_0));
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m221  (.A(m220), .B(
        SMADDR_i[8]), .Y(m221));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m149_0_0_wmux  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(m56_ns), .D(N_146_i_0), .FCI(
        VCC_net_1), .S(), .Y(m149_0_0_y0), .FCO(m149_0_0_co0));
    CFG3 #( .INIT(8'hBA) )  \doins_0_57_0_.m104_bm  (.A(m73_0), .B(
        SMADDR_i[5]), .C(m104_bm_1), .Y(m104_bm));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m274_2  (.A(SMADDR_i[1]), 
        .B(m11_0), .C(SMADDR_i[2]), .Y(m274_2));
    CFG4 #( .INIT(16'hFFFE) )  \doins_0_57_0_.m133  (.A(m110_3), .B(
        m110_2), .C(m110_1), .D(m133_0), .Y(m133));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m116_2  (.A(SMADDR_i[1]), 
        .B(m9), .C(SMADDR_i[5]), .Y(m116_2));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m157_1_1  (.A(
        SMADDR_i[6]), .B(m139_4), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        m157_1_1));
    CFG3 #( .INIT(8'h08) )  \doins_0_57_0_.m13  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m13));
    CFG4 #( .INIT(16'h57DF) )  \doins_0_57_0_.m175_bm  (.A(SMADDR_i[5])
        , .B(SMADDR_i[1]), .C(m21), .D(N_2_i), .Y(m175_bm));
    CFG4 #( .INIT(16'hD9C8) )  \doins_0_57_0_.m426_2  (.A(SMADDR_i[7]), 
        .B(SMADDR_i[6]), .C(i4_mux_1), .D(N_467_mux), .Y(m426_2));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m381_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(N_47_i), .D(m19), .FCI(
        VCC_net_1), .S(), .Y(m381_0_0_y0), .FCO(m381_0_0_co0));
    CFG4 #( .INIT(16'h1B0A) )  \doins_0_57_0_.m283_4  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[0]), .C(m283_4_1_1), .D(m274_4), .Y(m283_4));
    CFG2 #( .INIT(4'h1) )  \doins_0_57_0_.m363  (.A(SMADDR_i[2]), .B(
        SMADDR_i[4]), .Y(m363));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m95_2  (.A(SMADDR_i[1]), .B(
        m92), .C(SMADDR_i[5]), .Y(m95_1));
    CFG4 #( .INIT(16'hFFF4) )  \doins_0_57_0_.m83  (.A(SMADDR_i[6]), 
        .B(m83_1_0), .C(m83_1), .D(m83_2), .Y(m83));
    CFG3 #( .INIT(8'h76) )  \doins_0_57_0_.m297  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m297));
    CFG4 #( .INIT(16'h0346) )  \doins_0_57_0_.m286  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m286));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m50_0_0_wmux_0  (.A(
        m50_0_0_y0), .B(SMADDR_i[0]), .C(m9), .D(m48), .FCI(
        m50_0_0_co0), .S(), .Y(m50_0_0_wmux_0_Y), .FCO());
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m56_ns  (.A(SMADDR_i[5]), 
        .B(m56_bm), .C(m56_am), .Y(m56_ns));
    CFG2 #( .INIT(4'h7) )  \doins_0_57_0_.N_2_i_i  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .Y(N_2_i_i));
    CFG4 #( .INIT(16'h8000) )  \doins_0_57_0_.m411  (.A(SMADDR_i[7]), 
        .B(SMADDR_i[6]), .C(m261_e), .D(m407), .Y(N_496_mux));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m381_0_0_wmux_0  (.A(
        m381_0_0_y0), .B(SMADDR_i[5]), .C(N_7_i), .D(m93), .FCI(
        m381_0_0_co0), .S(), .Y(m381_0_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h3210) )  \doins_0_57_0_.m33_bm  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m27), .D(m30), .Y(m33_bm));
    SLE \doins_0_dreg[29]  (.D(m375), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7126_reto));
    CFG3 #( .INIT(8'h1B) )  \doins_0_57_0_.m129_am  (.A(SMADDR_i[0]), 
        .B(N_98_i), .C(m121_0_0_wmux_0_Y), .Y(m129_am));
    CFG4 #( .INIT(16'hC05F) )  \doins_0_57_0_.N_113_i  (.A(m110), .B(
        m104_ns), .C(SMADDR_i[8]), .D(N_113_i_1_0), .Y(N_113_i));
    CFG2 #( .INIT(4'h1) )  doins_adflt_inst_1 (.A(SMADDR[9]), .B(
        SMADDR[10]), .Y(doins_adflt));
    CFG4 #( .INIT(16'hA921) )  \doins_0_57_0_.m268  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[0]), .C(m268_1_2), .D(m266), .Y(m268));
    CFG2 #( .INIT(4'h2) )  \doins_0_57_0_.m261_e  (.A(SMADDR_i[5]), .B(
        SMADDR_i[0]), .Y(m261_e));
    CFG3 #( .INIT(8'hA8) )  \doins_0_57_0_.m47_i  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(N_48_i));
    CFG3 #( .INIT(8'hFE) )  \doins_0_57_0_.m266  (.A(m266_0), .B(
        m266_1), .C(m95_2), .Y(m266));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m251  (.A(SMADDR_i[7]), .B(
        SMADDR_i[8]), .C(i5_mux_6), .Y(N_500_mux));
    CFG3 #( .INIT(8'h10) )  \doins_0_57_0_.m73_0  (.A(SMADDR_i[0]), .B(
        SMADDR_i[5]), .C(m67), .Y(m73));
    CFG4 #( .INIT(16'h5410) )  \doins_0_57_0_.m33_am  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m22), .D(m24), .Y(m33_am));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m74_ns  (.A(SMADDR_i[6]), 
        .B(m74_bm), .C(m74_am), .Y(m74_ns));
    SLE \doins_0_dreg[0]  (.D(N_44_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7097_reto));
    CFG4 #( .INIT(16'h1733) )  \doins_0_57_0_.m452_ns_1  (.A(
        SMADDR_i[6]), .B(SMADDR_i[8]), .C(SMADDR_i[5]), .D(SMADDR_i[0])
        , .Y(m452_ns_1));
    CFG3 #( .INIT(8'h2E) )  \doins_0_57_0_.m243_1_0  (.A(m76), .B(
        SMADDR_i[0]), .C(m153), .Y(m243_1));
    CFG4 #( .INIT(16'h5D4C) )  \doins_0_57_0_.m41_1_2  (.A(SMADDR_i[5])
        , .B(SMADDR_i[0]), .C(N_4_i), .D(m34), .Y(m41_1_2));
    CFG4 #( .INIT(16'h88F3) )  \doins_0_57_0_.m361_ns  (.A(m361_bm_1), 
        .B(SMADDR_i[6]), .C(i2_mux), .D(m361_ns_1), .Y(m361_ns));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m389_0_0_wmux  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(m381_0_0_wmux_0_Y), .D(
        N_98_i), .FCI(VCC_net_1), .S(), .Y(m389_0_0_y0), .FCO(
        m389_0_0_co0));
    CFG3 #( .INIT(8'h18) )  \doins_0_57_0_.m92  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m92));
    CFG4 #( .INIT(16'h51D9) )  \doins_0_57_0_.N_44_i_1_0  (.A(
        SMADDR_i[7]), .B(SMADDR_i[8]), .C(m33_ns), .D(m41), .Y(
        N_44_i_1_0));
    CFG4 #( .INIT(16'h0040) )  \doins_0_57_0_.m355  (.A(SMADDR_i[1]), 
        .B(m19), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(N_460_mux));
    CFG4 #( .INIT(16'h0080) )  \doins_0_57_0_.m200_am  (.A(SMADDR_i[6])
        , .B(SMADDR_i[7]), .C(i5_mux_0), .D(m193), .Y(m200_am));
    VCC VCC (.Y(VCC_net_1));
    SLE \doins_0_dreg[2]  (.D(N_113_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7099_reto));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m129_ns  (.A(SMADDR_i[6]), 
        .B(m129_bm), .C(m129_am), .Y(m129_ns));
    CFG4 #( .INIT(16'h0888) )  \doins_0_57_0_.m107  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m107));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m116_4  (.A(SMADDR_i[0]), 
        .B(m116_3), .C(m116_1), .Y(m116_4));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m289  (.A(SMADDR_i[1]), .B(
        m21), .C(SMADDR_i[5]), .Y(N_459_mux));
    CFG4 #( .INIT(16'h1101) )  \doins_0_57_0_.m110_0  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[6]), .C(m68), .D(SMADDR_i[5]), .Y(m110_3));
    CFG3 #( .INIT(8'hB8) )  \doins_0_57_0_.m175_ns  (.A(m175_bm), .B(
        SMADDR_i[0]), .C(m175_am), .Y(m175_ns));
    CFG4 #( .INIT(16'h4000) )  \doins_0_57_0_.m27  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m27));
    CFG4 #( .INIT(16'h0800) )  \doins_0_57_0_.m9  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m9));
    CFG3 #( .INIT(8'h51) )  \doins_0_57_0_.m162  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m162));
    CFG4 #( .INIT(16'h0F20) )  \doins_0_57_0_.N_113_i_1_0  (.A(
        SMADDR_i[6]), .B(m87), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        N_113_i_1_0));
    CFG4 #( .INIT(16'hC0AF) )  \doins_0_57_0_.m445  (.A(m443), .B(m433)
        , .C(SMADDR_i[8]), .D(m445_1_1), .Y(m445));
    CFG4 #( .INIT(16'h0080) )  \doins_0_57_0_.m206_am  (.A(SMADDR_i[6])
        , .B(SMADDR_i[7]), .C(i5_mux_0), .D(m193), .Y(m206_am));
    ARI1 #( .INIT(20'h05F88) )  \doins_0_57_0_.m305_0_0_wmux_0  (.A(
        m305_0_0_y0), .B(SMADDR_i[5]), .C(N_277_i), .D(SMADDR_i[3]), 
        .FCI(m305_0_0_co0), .S(), .Y(m305_0_0_wmux_0_Y), .FCO());
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m186  (.A(m21), .B(
        SMADDR_i[5]), .Y(m186));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m206_bm  (.A(SMADDR_i[7]), 
        .B(m11_0), .C(m204_e), .Y(m206_bm));
    CFG4 #( .INIT(16'h1105) )  \doins_0_57_0_.m150  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m150));
    CFG4 #( .INIT(16'h8000) )  \doins_0_57_0_.m110_3  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[6]), .C(m107), .D(SMADDR_i[5]), .Y(m110_2));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m274_4  (.A(SMADDR_i[5]), 
        .B(m274_3), .C(m274_1), .Y(m274_4));
    CFG4 #( .INIT(16'h8000) )  \doins_0_57_0_.m232  (.A(SMADDR_i[7]), 
        .B(SMADDR_i[8]), .C(m11_0), .D(m204_e), .Y(m232));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m305_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(N_303_i), .D(m13), .FCI(
        VCC_net_1), .S(), .Y(m305_0_0_y0), .FCO(m305_0_0_co0));
    CFG4 #( .INIT(16'h54DC) )  \doins_0_57_0_.m299_1_2  (.A(
        SMADDR_i[2]), .B(SMADDR_i[5]), .C(m12), .D(m19), .Y(m299_1_2));
    CFG3 #( .INIT(8'h1D) )  \doins_0_57_0_.m421_ns_1_0  (.A(m162), .B(
        SMADDR_i[1]), .C(m363), .Y(m421_ns_1_0));
    CFG4 #( .INIT(16'hD5F7) )  \doins_0_57_0_.m97_i  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m47), .D(N_2_i), .Y(N_14774_i));
    CFG4 #( .INIT(16'hFFF4) )  \doins_0_57_0_.m95  (.A(SMADDR_i[5]), 
        .B(m91), .C(m95_1), .D(m95_2), .Y(m95));
    CFG4 #( .INIT(16'hF3F1) )  \doins_0_57_0_.N_44_i  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[8]), .C(N_44_i_1_0), .D(m16_ns), .Y(N_44_i));
    CFG2 #( .INIT(4'h1) )  \doins_0_57_0_.m10  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(m10));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m121_0_0_wmux_0  (.A(
        m121_0_0_y0), .B(SMADDR_i[5]), .C(m13), .D(m34), .FCI(
        m121_0_0_co0), .S(), .Y(m121_0_0_wmux_0_Y), .FCO());
    CFG3 #( .INIT(8'h6A) )  \doins_0_57_0_.m179  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m179));
    CFG3 #( .INIT(8'h1B) )  \doins_0_57_0_.m16_bm  (.A(SMADDR_i[5]), 
        .B(m16_bm_1), .C(m16_bm_1_0), .Y(m16_bm));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m149_0_0_wmux_0  (.A(
        m149_0_0_y0), .B(SMADDR_i[6]), .C(N_148_i), .D(m72), .FCI(
        m149_0_0_co0), .S(), .Y(m149_0_0_wmux_0_Y), .FCO());
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m313_4_1_0_0_wmux  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(m305_0_0_wmux_0_Y), .D(G_622)
        , .FCI(VCC_net_1), .S(), .Y(m313_4_1_0_0_y0), .FCO(
        m313_4_1_0_0_co0));
    CFG4 #( .INIT(16'hBE36) )  \doins_0_57_0_.m301  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[6]), .C(m301_1_2), .D(m299), .Y(m301));
    CFG3 #( .INIT(8'h57) )  \doins_0_57_0_.m47  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m47));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m16_bm_1  (.A(SMADDR_i[1]), 
        .B(N_2_i), .C(SMADDR_i[2]), .Y(m16_bm_1));
    CFG4 #( .INIT(16'h4800) )  \doins_0_57_0_.m80  (.A(SMADDR_i[1]), 
        .B(N_2_i), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m80));
    CFG4 #( .INIT(16'hF971) )  \doins_0_57_0_.m16_am  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[5]), .C(m16_am_1_0), .D(N_7_i), .Y(m16_am));
    CFG4 #( .INIT(16'h038B) )  \doins_0_57_0_.m387  (.A(SMADDR_i[2]), 
        .B(SMADDR_i[5]), .C(m180), .D(m387_1_0), .Y(m387));
    CFG2 #( .INIT(4'hE) )  \doins_0_57_0_.N_182_i  (.A(m180), .B(
        SMADDR_i[5]), .Y(N_182_i));
    CFG3 #( .INIT(8'h1B) )  \doins_0_57_0_.m404_am_1  (.A(SMADDR_i[5]), 
        .B(m391), .C(m394), .Y(m404_am_1));
    CFG4 #( .INIT(16'hEC2C) )  \doins_0_57_0_.m274_3  (.A(m12), .B(
        m274_2), .C(SMADDR_i[1]), .D(m4), .Y(m274_3));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m256_4  (.A(SMADDR_i[0]), 
        .B(m256_3), .C(m256_1), .Y(m256_4));
    CFG2 #( .INIT(4'hD) )  \doins_0_57_0_.N_185_i  (.A(m10), .B(
        SMADDR_i[5]), .Y(N_185_i));
    CFG4 #( .INIT(16'h0240) )  \doins_0_57_0_.m330_1_0  (.A(
        SMADDR_i[4]), .B(SMADDR_i[6]), .C(m330_1_1), .D(SMADDR_i[5]), 
        .Y(m330_1_2));
    CFG4 #( .INIT(16'hEB63) )  \doins_0_57_0_.m299  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[5]), .C(m299_1_2), .D(m297), .Y(m299));
    CFG4 #( .INIT(16'h4EE4) )  \doins_0_57_0_.m308  (.A(SMADDR_i[1]), 
        .B(m4), .C(SMADDR_i[4]), .D(SMADDR_i[2]), .Y(m308));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m168  (.A(SMADDR_i[6]), .B(
        m167), .C(m168_1_1), .Y(m168));
    CFG4 #( .INIT(16'hCF77) )  \doins_0_57_0_.m371  (.A(SMADDR_i[2]), 
        .B(SMADDR_i[5]), .C(m92), .D(m371_1_2), .Y(m371));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m285_1_1  (.A(
        SMADDR_i[6]), .B(m256_4), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        m285_1_1));
    CFG4 #( .INIT(16'h5410) )  \doins_0_57_0_.m207  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[5]), .C(m21), .D(m13), .Y(m207));
    CFG3 #( .INIT(8'h2A) )  \doins_0_dreg_RNI3D6L_0[6]  (.A(m3_1), .B(
        doins_adflt_reto), .C(N_7103_reto), .Y(
        CoreAPB3_0_APBmslave0_PSELx));
    CFG4 #( .INIT(16'h3B7F) )  \doins_0_57_0_.m87  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(N_2_i), .D(m48), .Y(m87));
    CFG4 #( .INIT(16'h45CC) )  \doins_0_57_0_.m361_ns_1  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(m351), .D(SMADDR_i[5]), .Y(
        m361_ns_1));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m335_0  (.A(SMADDR_i[1]), 
        .B(m142), .C(SMADDR_i[2]), .Y(m335_0));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m188_0_0_wmux  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(N_185_i), .D(m78), .FCI(
        VCC_net_1), .S(), .Y(m188_0_0_y0), .FCO(m188_0_0_co0));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m183_0_0_wmux_0  (.A(
        m183_0_0_y0), .B(SMADDR_i[6]), .C(N_182_i), .D(m127), .FCI(
        m183_0_0_co0), .S(), .Y(m183_0_0_wmux_0_Y), .FCO());
    CFG2 #( .INIT(4'hE) )  doins_2dflt (.A(doins_adflt_i_reto), .B(
        N_7099_reto), .Y(INSTR_CMD[2]));
    CFG3 #( .INIT(8'h1C) )  \doins_0_57_0_.m60  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m60));
    CFG4 #( .INIT(16'hF838) )  \doins_0_57_0_.m139_3  (.A(m136), .B(
        SMADDR_i[5]), .C(m139_2), .D(m47), .Y(m139_3));
    CFG4 #( .INIT(16'h50CF) )  \doins_0_57_0_.m315  (.A(m301), .B(
        m313_4_1_0_wmux_0_Y), .C(SMADDR_i[8]), .D(m315_1_1), .Y(m315));
    SLE \doins_0_dreg[21]  (.D(m245), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREABC_0_APB3master_PADDR_i_0));
    SLE \doins_0_dreg[22]  (.D(N_500_mux), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7119_reto));
    SLE \doins_0_dreg[27]  (.D(m315), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7124_reto));
    CFG4 #( .INIT(16'h225F) )  \doins_0_57_0_.m168_1_1  (.A(
        SMADDR_i[0]), .B(m59), .C(m164_1_0), .D(m168_1_0_1), .Y(
        m168_1_1));
    CFG3 #( .INIT(8'h56) )  \doins_0_57_0_.m136  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m136));
    CFG4 #( .INIT(16'hDC98) )  \doins_0_57_0_.m339_0  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[2]), .C(m12), .D(N_5_i), .Y(m339_0));
    CFG4 #( .INIT(16'h4D41) )  \doins_0_57_0_.m277  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m277));
    CFG4 #( .INIT(16'h0400) )  \doins_0_57_0_.m38  (.A(SMADDR_i[1]), 
        .B(N_2_i), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m38));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m256_0  (.A(SMADDR_i[1]), 
        .B(N_4_i), .C(SMADDR_i[5]), .Y(m256_0));
    CFG4 #( .INIT(16'h5410) )  \doins_0_57_0_.m397  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m123), .D(m10), .Y(m397));
    CFG4 #( .INIT(16'h193B) )  \doins_0_57_0_.m367_4_1  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(m366), .D(m363), .Y(m367_4_1)
        );
    CFG4 #( .INIT(16'h4301) )  \doins_0_57_0_.m310  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m310));
    CFG4 #( .INIT(16'h28AA) )  \doins_0_57_0_.m67  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m67));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m63_2  (.A(SMADDR_i[1]), .B(
        m60), .C(SMADDR_i[2]), .Y(m63_2));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m188_0_0_wmux_0  (.A(
        m188_0_0_y0), .B(SMADDR_i[6]), .C(N_14773_i), .D(m186), .FCI(
        m188_0_0_co0), .S(), .Y(m188_0_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h0F20) )  \doins_0_57_0_.m190_1_1  (.A(
        SMADDR_i[6]), .B(m175_ns), .C(SMADDR_i[7]), .D(SMADDR_i[8]), 
        .Y(m190_1_1));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m436_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(SMADDR_i[4]), .D(m179), .FCI(
        VCC_net_1), .S(), .Y(m436_0_0_y0), .FCO(m436_0_0_co0));
    CFG4 #( .INIT(16'h5342) )  \doins_0_57_0_.m443  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[0]), .C(m443_1_1), .D(m436_0_0_wmux_0_Y), .Y(m443));
    CFG4 #( .INIT(16'h4800) )  \doins_0_57_0_.m376_am  (.A(SMADDR_i[1])
        , .B(N_2_i), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m376_am));
    CFG4 #( .INIT(16'hFFFE) )  \doins_0_57_0_.m110  (.A(m110_1), .B(
        m110_0), .C(m110_3), .D(m110_2), .Y(m110));
    CFG4 #( .INIT(16'hF838) )  \doins_0_57_0_.m335_1  (.A(N_11_i), .B(
        SMADDR_i[1]), .C(m335_0), .D(m4), .Y(m335_1));
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m225  (.A(m204_e), .B(m23), 
        .Y(N_477_mux));
    SLE \doins_0_dreg[14]  (.D(m229), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7111_reto));
    CFG4 #( .INIT(16'h4E00) )  \doins_0_57_0_.m376_bm  (.A(SMADDR_i[1])
        , .B(m136), .C(SMADDR_i[4]), .D(SMADDR_i[5]), .Y(m376_bm));
    CFG4 #( .INIT(16'h0CBB) )  \doins_0_57_0_.m135  (.A(m133), .B(
        SMADDR_i[8]), .C(m129_ns), .D(m135_1_1), .Y(m135));
    CFG3 #( .INIT(8'hA1) )  \doins_0_57_0_.N_47_i  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[2]), .C(SMADDR_i[3]), .Y(N_47_i));
    CFG3 #( .INIT(8'h2F) )  \doins_0_57_0_.m373_1_0  (.A(SMADDR_i[0]), 
        .B(m186), .C(SMADDR_i[6]), .Y(m373_1_1));
    CFG4 #( .INIT(16'h0AF3) )  \doins_0_57_0_.m373  (.A(m367_4), .B(
        m371), .C(SMADDR_i[0]), .D(m373_1_1), .Y(m373));
    CFG3 #( .INIT(8'h80) )  \doins_0_dreg_RNI3D6L[6]  (.A(m3_1), .B(
        doins_adflt_reto), .C(N_7103_reto), .Y(
        CoreAPB3_0_APBmslave1_PSELx));
    CFG3 #( .INIT(8'h1D) )  \doins_0_57_0_.m235_am  (.A(N_4_i), .B(
        SMADDR_i[5]), .C(m48), .Y(m235_am));
    CFG4 #( .INIT(16'h4CC9) )  \doins_0_57_0_.m91  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m91));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m335_4  (.A(SMADDR_i[5]), 
        .B(m335_3), .C(m335_1), .Y(m335_4));
    CFG4 #( .INIT(16'h6420) )  \doins_0_57_0_.m249_ns  (.A(SMADDR_i[6])
        , .B(SMADDR_i[0]), .C(m249_ns_1), .D(m121_0_0_wmux_0_Y), .Y(
        i5_mux_6));
    CFG4 #( .INIT(16'h0480) )  \doins_0_57_0_.m22  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m22));
    CFG4 #( .INIT(16'hEA40) )  \doins_0_57_0_.m290  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m286), .D(N_459_mux), .Y(m290));
    CFG4 #( .INIT(16'h3FA0) )  \doins_0_57_0_.m245  (.A(m243), .B(
        m241_ns), .C(SMADDR_i[8]), .D(m245_1_1), .Y(m245));
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m453  (.A(i8_mux), .B(
        SMADDR_i[7]), .Y(i7_mux_0));
    CFG3 #( .INIT(8'hE2) )  \doins_0_57_0_.m407  (.A(m19), .B(
        SMADDR_i[1]), .C(m93), .Y(m407));
    CFG2 #( .INIT(4'h1) )  \doins_0_57_0_.m127  (.A(m126), .B(
        SMADDR_i[5]), .Y(m127));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m121_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(m21), .D(m23), .FCI(
        VCC_net_1), .S(), .Y(m121_0_0_y0), .FCO(m121_0_0_co0));
    CFG4 #( .INIT(16'h4073) )  \doins_0_57_0_.m426_4_1_1  (.A(
        SMADDR_i[0]), .B(SMADDR_i[8]), .C(i6_mux_1), .D(N_496_mux), .Y(
        m426_4_1_1));
    CFG2 #( .INIT(4'hE) )  doins_1dflt (.A(doins_adflt_i_reto), .B(
        N_7098_reto), .Y(INSTR_CMD[1]));
    SLE \doins_0_dreg[13]  (.D(m221), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7110_reto));
    CFG2 #( .INIT(4'hE) )  \doins_0_57_0_.N_148_i  (.A(m67), .B(
        SMADDR_i[5]), .Y(N_148_i));
    CFG4 #( .INIT(16'h0004) )  \doins_0_57_0_.m24  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m24));
    CFG3 #( .INIT(8'h40) )  \doins_0_57_0_.m83_2  (.A(SMADDR_i[0]), .B(
        m80), .C(SMADDR_i[6]), .Y(m83_1));
    CFG4 #( .INIT(16'h0E5E) )  \doins_0_57_0_.m367_4  (.A(SMADDR_i[1]), 
        .B(m366), .C(m367_4_1), .D(m367_4_1_0), .Y(m367_4));
    CFG4 #( .INIT(16'h00A8) )  \doins_0_57_0_.m318_am  (.A(SMADDR_i[5])
        , .B(SMADDR_i[1]), .C(SMADDR_i[3]), .D(SMADDR_i[4]), .Y(
        m318_am));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m344_1_1  (.A(
        SMADDR_i[6]), .B(m318_ns), .C(SMADDR_i[7]), .D(SMADDR_i[8]), 
        .Y(m344_1_1));
    CFG3 #( .INIT(8'h27) )  \doins_0_57_0_.m387_1_0  (.A(SMADDR_i[1]), 
        .B(m10), .C(m19), .Y(m387_1_0));
    CFG4 #( .INIT(16'h7520) )  \doins_0_57_0_.m256_3  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[1]), .C(m142), .D(m9), .Y(m256_3));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m63_0  (.A(SMADDR_i[1]), .B(
        m59), .C(SMADDR_i[2]), .Y(m63_0));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m428_0  (.A(SMADDR_i[1]), 
        .B(m162), .C(SMADDR_i[2]), .Y(m428_0));
    SLE \doins_0_dreg[18]  (.D(m232), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7115_reto));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m313_4_1_0_wmux_0  (.A(
        m313_4_1_0_0_y0), .B(SMADDR_i[6]), .C(m313_2), .D(N_459_mux), 
        .FCI(m313_4_1_0_0_co0), .S(), .Y(m313_4_1_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h7323) )  \doins_0_57_0_.m441_ns_1  (.A(
        SMADDR_i[4]), .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2])
        , .Y(m441_ns_1));
    CFG3 #( .INIT(8'hB8) )  \doins_0_57_0_.m318_ns  (.A(m318_bm), .B(
        SMADDR_i[0]), .C(m318_am), .Y(m318_ns));
    CFG3 #( .INIT(8'h08) )  \doins_0_57_0_.m110_1  (.A(SMADDR_i[0]), 
        .B(m78), .C(SMADDR_i[6]), .Y(m110_0));
    CFG4 #( .INIT(16'hA0CF) )  \doins_0_57_0_.m344  (.A(m330), .B(
        m342_4), .C(SMADDR_i[8]), .D(m344_1_1), .Y(m344));
    CFG4 #( .INIT(16'h0880) )  \doins_0_57_0_.m44  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m44));
    CFG4 #( .INIT(16'hFFF8) )  \doins_0_57_0_.m241_bm  (.A(m127), .B(
        SMADDR_i[0]), .C(m73_0), .D(m240), .Y(m241_bm));
    CFG3 #( .INIT(8'h15) )  \doins_0_57_0_.m123  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m123));
    CFG3 #( .INIT(8'h10) )  \doins_0_57_0_.m266_2  (.A(SMADDR_i[1]), 
        .B(m264), .C(SMADDR_i[5]), .Y(m266_1));
    CFG4 #( .INIT(16'hF838) )  \doins_0_57_0_.m116_3  (.A(N_48_i), .B(
        SMADDR_i[5]), .C(m116_2), .D(m21), .Y(m116_3));
    CFG3 #( .INIT(8'h0E) )  \doins_0_57_0_.m326  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m326));
    CFG2 #( .INIT(4'h2) )  \doins_0_57_0_.m12  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(m12));
    SLE \doins_0_dreg[33]  (.D(i7_mux_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7130_reto));
    CFG3 #( .INIT(8'h7E) )  \doins_0_57_0_.m400  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m400));
    CFG4 #( .INIT(16'hFFA4) )  \doins_0_57_0_.m209  (.A(m209_1_0), .B(
        m207), .C(SMADDR_i[7]), .D(m209_2), .Y(i7_mux));
    CFG2 #( .INIT(4'h6) )  \doins_0_57_0_.m4  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(m4));
    CFG4 #( .INIT(16'hC0BB) )  \doins_0_57_0_.m157  (.A(m155), .B(
        SMADDR_i[8]), .C(m149_0_0_wmux_0_Y), .D(m157_1_1), .Y(m157));
    CFG2 #( .INIT(4'h1) )  \doins_0_57_0_.m72  (.A(m71), .B(
        SMADDR_i[5]), .Y(m72));
    CFG3 #( .INIT(8'h1D) )  \doins_0_57_0_.m367_4_1_0  (.A(N_2_i), .B(
        SMADDR_i[2]), .C(m19), .Y(m367_4_1_0));
    CFG3 #( .INIT(8'hB8) )  \doins_0_57_0_.m235_ns  (.A(m235_bm), .B(
        SMADDR_i[0]), .C(m235_am), .Y(m235_ns));
    SLE \doins_0_dreg[15]  (.D(N_499_mux), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7112_reto));
    CFG4 #( .INIT(16'h4555) )  \doins_0_dreg_RNI4D7L1[4]  (.A(N_123_i), 
        .B(INSTR_CMD[1]), .C(N_7101_reto), .D(DOJMP), .Y(
        un1_ICYCLE_6_i));
    CFG4 #( .INIT(16'h163A) )  \doins_0_57_0_.m330_1_1  (.A(
        SMADDR_i[4]), .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2])
        , .Y(m330_1_1));
    CFG4 #( .INIT(16'hE2C0) )  \doins_0_57_0_.m139_4  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[0]), .C(m139_3), .D(m80), .Y(m139_4));
    ARI1 #( .INIT(20'h05F88) )  \doins_0_57_0_.m358_0_0_wmux_0  (.A(
        m358_0_0_y0), .B(SMADDR_i[2]), .C(N_2_i_i), .D(SMADDR_i[4]), 
        .FCI(m358_0_0_co0), .S(), .Y(i2_mux), .FCO());
    CFG4 #( .INIT(16'h6E7F) )  \doins_0_57_0_.m16_bm_1_0  (.A(
        SMADDR_i[2]), .B(SMADDR_i[1]), .C(m12), .D(m10), .Y(m16_bm_1_0)
        );
    CFG4 #( .INIT(16'hF858) )  \doins_0_57_0_.m404_ns  (.A(SMADDR_i[6])
        , .B(N_14773_i), .C(m404_ns_1), .D(m402_0_0_wmux_0_Y), .Y(
        m404_ns));
    CFG4 #( .INIT(16'h4156) )  \doins_0_57_0_.m346  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m346));
    CFG4 #( .INIT(16'hE000) )  \doins_0_57_0_.m414  (.A(SMADDR_i[2]), 
        .B(SMADDR_i[1]), .C(m261_e), .D(N_2_i), .Y(N_467_mux));
    CFG4 #( .INIT(16'h68AA) )  \doins_0_57_0_.m180  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m180));
    CFG3 #( .INIT(8'h43) )  \doins_0_57_0_.m159  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m159));
    CFG4 #( .INIT(16'h2ECC) )  \doins_0_57_0_.m256_1  (.A(m13), .B(
        m256_0), .C(SMADDR_i[4]), .D(SMADDR_i[5]), .Y(m256_1));
    CFG4 #( .INIT(16'h45CD) )  \doins_0_57_0_.m16_am_1_0  (.A(
        SMADDR_i[2]), .B(SMADDR_i[1]), .C(m4), .D(N_2_i), .Y(
        m16_am_1_0));
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m1  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(N_2_i));
    CFG3 #( .INIT(8'hCE) )  \doins_0_57_0_.m328  (.A(SMADDR_i[5]), .B(
        m266_0), .C(m328_1_0), .Y(m328));
    CFG3 #( .INIT(8'h67) )  \doins_0_57_0_.m279  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m279));
    CFG3 #( .INIT(8'h4E) )  \doins_0_57_0_.m74_am  (.A(SMADDR_i[0]), 
        .B(m56_ns), .C(m63_4), .Y(m74_am));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m227  (.A(m204_e_0), .B(
        m212_e), .C(m34), .Y(N_478_mux));
    CFG4 #( .INIT(16'h193B) )  \doins_0_57_0_.m421_ns_1  (.A(
        SMADDR_i[5]), .B(SMADDR_i[6]), .C(m48), .D(m30), .Y(m421_ns_1));
    CFG4 #( .INIT(16'h0F20) )  \doins_0_57_0_.m245_1_1  (.A(
        SMADDR_i[6]), .B(m235_ns), .C(SMADDR_i[7]), .D(SMADDR_i[8]), 
        .Y(m245_1_1));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m231  (.A(SMADDR_i[7]), .B(
        SMADDR_i[8]), .C(N_478_mux), .Y(N_499_mux));
    CFG4 #( .INIT(16'h00C8) )  \doins_0_57_0_.m153  (.A(SMADDR_i[1]), 
        .B(m10), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m153));
    CFG4 #( .INIT(16'hA280) )  \doins_0_57_0_.m348  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[0]), .C(m21), .D(m346), .Y(m348));
    CFG4 #( .INIT(16'h8000) )  \doins_0_57_0_.m209_3  (.A(SMADDR_i[7]), 
        .B(SMADDR_i[0]), .C(m212_e), .D(m34), .Y(m209_2));
    CFG4 #( .INIT(16'h4533) )  \doins_0_57_0_.m160  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m160));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m50_0_0_wmux  (.A(
        SMADDR_i[5]), .B(SMADDR_i[0]), .C(N_4_i), .D(m44), .FCI(
        VCC_net_1), .S(), .Y(m50_0_0_y0), .FCO(m50_0_0_co0));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m358_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[2]), .C(SMADDR_i[4]), .D(m19), .FCI(
        VCC_net_1), .S(), .Y(m358_0_0_y0), .FCO(m358_0_0_co0));
    CFG3 #( .INIT(8'h27) )  \doins_0_57_0_.m351  (.A(SMADDR_i[1]), .B(
        N_7_i), .C(m21), .Y(m351));
    CFG4 #( .INIT(16'h3881) )  \doins_0_57_0_.m268_1_1  (.A(
        SMADDR_i[4]), .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2])
        , .Y(m268_1_1));
    CFG2 #( .INIT(4'h9) )  \doins_0_57_0_.N_5_i  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(N_5_i));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m428_4  (.A(SMADDR_i[0]), 
        .B(m428_3), .C(m428_1), .Y(i5_mux_4));
    CFG3 #( .INIT(8'h47) )  \doins_0_57_0_.m241_am  (.A(m63_4), .B(
        SMADDR_i[0]), .C(N_98_i), .Y(m241_am));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m428_1  (.A(m123), .B(
        m428_0), .C(SMADDR_i[1]), .Y(m428_1));
    CFG4 #( .INIT(16'h24CC) )  \doins_0_57_0_.m59  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m59));
    CFG3 #( .INIT(8'h81) )  \doins_0_57_0_.m400_i  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[2]), .C(SMADDR_i[3]), .Y(N_401_i));
    ARI1 #( .INIT(20'h0F588) )  \doins_0_57_0_.m389_0_0_wmux_0  (.A(
        m389_0_0_y0), .B(SMADDR_i[6]), .C(N_386_i), .D(m387), .FCI(
        m389_0_0_co0), .S(), .Y(m389_0_0_wmux_0_Y), .FCO());
    CFG4 #( .INIT(16'h10BA) )  \doins_0_57_0_.m155_1_0  (.A(
        SMADDR_i[0]), .B(SMADDR_i[5]), .C(m150), .D(m153), .Y(m155_1));
    CFG4 #( .INIT(16'hF838) )  \doins_0_57_0_.m63_3  (.A(m12), .B(
        SMADDR_i[1]), .C(m63_2), .D(m10), .Y(m63_3));
    CFG3 #( .INIT(8'h4E) )  \doins_0_57_0_.m83_1_0  (.A(SMADDR_i[0]), 
        .B(m76), .C(m78), .Y(m83_1_0));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m375_1_1  (.A(
        SMADDR_i[6]), .B(m348), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        m375_1_1));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.m135_1_1  (.A(
        SMADDR_i[6]), .B(m116_4), .C(SMADDR_i[7]), .D(SMADDR_i[8]), .Y(
        m135_1_1));
    CFG4 #( .INIT(16'h13D3) )  \doins_0_57_0_.N_146_i  (.A(m93), .B(
        m145_0), .C(SMADDR_i[5]), .D(m29), .Y(N_146_i_0));
    CFG2 #( .INIT(4'h8) )  \doins_0_57_0_.m6  (.A(SMADDR_i[2]), .B(
        SMADDR_i[4]), .Y(N_7_i));
    CFG4 #( .INIT(16'h2075) )  \doins_0_57_0_.m301_1_2  (.A(
        SMADDR_i[6]), .B(SMADDR_i[5]), .C(m294), .D(m38), .Y(m301_1_2));
    CFG4 #( .INIT(16'h3FA0) )  \doins_0_57_0_.m190  (.A(
        m188_0_0_wmux_0_Y), .B(m183_0_0_wmux_0_Y), .C(SMADDR_i[8]), .D(
        m190_1_1), .Y(m190));
    CFG2 #( .INIT(4'hE) )  \doins_0_57_0_.N_11_i  (.A(SMADDR_i[4]), .B(
        SMADDR_i[3]), .Y(N_11_i));
    CFG3 #( .INIT(8'hE4) )  \doins_0_57_0_.m428_2  (.A(SMADDR_i[1]), 
        .B(m400), .C(SMADDR_i[2]), .Y(m428_2));
    CFG4 #( .INIT(16'h1151) )  \doins_0_57_0_.m209_1_0  (.A(
        SMADDR_i[0]), .B(SMADDR_i[7]), .C(m24), .D(SMADDR_i[5]), .Y(
        m209_1_0));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m16_ns  (.A(SMADDR_i[0]), 
        .B(m16_bm), .C(m16_am), .Y(m16_ns));
    CFG3 #( .INIT(8'h01) )  \doins_0_57_0_.m128_0  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m124), .Y(m128));
    CFG4 #( .INIT(16'hB830) )  \doins_0_57_0_.m330  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[0]), .C(m330_1_2), .D(m328), .Y(m330));
    CFG3 #( .INIT(8'h10) )  \doins_0_57_0_.m240_0  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m180), .Y(m240));
    CFG3 #( .INIT(8'hC5) )  \doins_0_57_0_.N_277_i  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[2]), .C(SMADDR_i[3]), .Y(N_277_i));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m200_bm  (.A(m131), .B(
        SMADDR_i[7]), .C(m204_e_0), .Y(m200_bm));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m402_0_0_wmux  (.A(
        SMADDR_i[1]), .B(SMADDR_i[5]), .C(m21), .D(N_265_i), .FCI(
        VCC_net_1), .S(), .Y(m402_0_0_y0), .FCO(m402_0_0_co0));
    CFG3 #( .INIT(8'h20) )  \doins_0_57_0_.m21  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m21));
    CFG4 #( .INIT(16'hDC98) )  \doins_0_57_0_.m283_2  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(m277), .D(N_281_i_0), .Y(m283_2));
    CFG4 #( .INIT(16'h0020) )  \doins_0_57_0_.m30  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m30));
    CFG3 #( .INIT(8'h58) )  \doins_0_57_0_.m264  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m264));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m83_3  (.A(SMADDR_i[6]), .B(
        SMADDR_i[0]), .C(N_14773_i), .Y(m83_2));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m33_ns  (.A(SMADDR_i[6]), 
        .B(m33_bm), .C(m33_am), .Y(m33_ns));
    CFG4 #( .INIT(16'hC0AF) )  \doins_0_57_0_.m406  (.A(m404_ns), .B(
        m389_0_0_wmux_0_Y), .C(SMADDR_i[8]), .D(m406_1_1), .Y(m406));
    CFG3 #( .INIT(8'h14) )  \doins_0_57_0_.m93  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m93));
    SLE \doins_0_dreg[4]  (.D(m157), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7101_reto));
    CFG3 #( .INIT(8'h01) )  \doins_0_dreg_RNIJ2TF[3]  (.A(N_7101_reto), 
        .B(INSTR_CMD[1]), .C(N_7100_reto), .Y(doins_0_dreg_RNIJ2TF_0));
    CFG3 #( .INIT(8'h27) )  \doins_0_57_0_.m361_bm_1  (.A(SMADDR_i[0]), 
        .B(m126), .C(N_460_mux), .Y(m361_bm_1));
    CFG3 #( .INIT(8'hAC) )  \doins_0_57_0_.m335_3  (.A(m60), .B(m335_2)
        , .C(SMADDR_i[1]), .Y(m335_3));
    CFG4 #( .INIT(16'h1373) )  \doins_0_57_0_.m268_1_0  (.A(
        SMADDR_i[4]), .B(SMADDR_i[6]), .C(m268_1_1), .D(SMADDR_i[5]), 
        .Y(m268_1_2));
    CFG4 #( .INIT(16'h4044) )  \doins_0_57_0_.m103_1  (.A(SMADDR_i[0]), 
        .B(SMADDR_i[5]), .C(SMADDR_i[1]), .D(m11_0), .Y(m73_0));
    CFG4 #( .INIT(16'hC5E7) )  \doins_0_57_0_.m41  (.A(SMADDR_i[6]), 
        .B(SMADDR_i[0]), .C(m41_1_2), .D(m38), .Y(m41));
    CFG3 #( .INIT(8'hA7) )  \doins_0_57_0_.N_265_i  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[2]), .C(SMADDR_i[3]), .Y(N_265_i));
    CFG4 #( .INIT(16'h1454) )  \doins_0_57_0_.m294  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m294));
    CFG4 #( .INIT(16'h5476) )  \doins_0_57_0_.m168_1_0_1  (.A(
        SMADDR_i[5]), .B(SMADDR_i[0]), .C(m91), .D(m160), .Y(
        m168_1_0_1));
    CFG4 #( .INIT(16'h2367) )  \doins_0_57_0_.m404_ns_1  (.A(
        SMADDR_i[6]), .B(SMADDR_i[0]), .C(m404_am_1), .D(m397), .Y(
        m404_ns_1));
    CFG4 #( .INIT(16'hA03F) )  \doins_0_57_0_.N_340_i  (.A(SMADDR_i[3])
        , .B(SMADDR_i[4]), .C(SMADDR_i[1]), .D(m339_0), .Y(N_340_i));
    CFG4 #( .INIT(16'h2ECC) )  \doins_0_57_0_.m428_3  (.A(N_11_i), .B(
        m428_2), .C(SMADDR_i[3]), .D(SMADDR_i[1]), .Y(m428_3));
    CFG4 #( .INIT(16'hBA98) )  \doins_0_57_0_.m313_2  (.A(SMADDR_i[5]), 
        .B(SMADDR_i[0]), .C(m308), .D(m310), .Y(m313_2));
    CFG4 #( .INIT(16'hFCFD) )  \doins_0_57_0_.m243  (.A(SMADDR_i[6]), 
        .B(m110_2), .C(m110_1), .D(m243_1), .Y(m243));
    CFG4 #( .INIT(16'h7430) )  \doins_0_57_0_.m191  (.A(SMADDR_i[1]), 
        .B(SMADDR_i[0]), .C(N_4_i), .D(m13), .Y(i5_mux_0));
    CFG3 #( .INIT(8'hE2) )  \doins_0_57_0_.m113  (.A(N_4_i), .B(
        SMADDR_i[5]), .C(m48), .Y(m113));
    CFG3 #( .INIT(8'h01) )  \doins_0_57_0_.m11  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m11_0));
    ARI1 #( .INIT(20'h0FA44) )  \doins_0_57_0_.m183_0_0_wmux  (.A(
        SMADDR_i[0]), .B(SMADDR_i[6]), .C(N_14774_i), .D(N_146_i_0), 
        .FCI(VCC_net_1), .S(), .Y(m183_0_0_y0), .FCO(m183_0_0_co0));
    CFG4 #( .INIT(16'h9DCC) )  \doins_0_57_0_.N_386_i  (.A(SMADDR_i[2])
        , .B(SMADDR_i[5]), .C(m10), .D(N_386_i_1_0), .Y(N_386_i));
    SLE \doins_0_dreg[6]  (.D(m190), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7103_reto));
    SLE \doins_0_dreg[5]  (.D(N_497_mux), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7102_reto));
    CFG4 #( .INIT(16'h4022) )  \doins_0_57_0_.m71  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m71));
    CFG3 #( .INIT(8'h28) )  \doins_0_57_0_.m142  (.A(SMADDR_i[4]), .B(
        SMADDR_i[2]), .C(SMADDR_i[3]), .Y(m142));
    CFG4 #( .INIT(16'hA820) )  \doins_0_57_0_.m229  (.A(SMADDR_i[8]), 
        .B(SMADDR_i[7]), .C(N_477_mux), .D(N_478_mux), .Y(m229));
    CFG3 #( .INIT(8'hD8) )  \doins_0_57_0_.m206_ns  (.A(SMADDR_i[8]), 
        .B(m206_bm), .C(m206_am), .Y(m206_ns));
    CFG2 #( .INIT(4'h7) )  \doins_0_57_0_.m81  (.A(N_2_i), .B(
        SMADDR_i[5]), .Y(N_14773_i));
    CFG4 #( .INIT(16'h54AA) )  \doins_0_57_0_.m421_ns  (.A(SMADDR_i[6])
        , .B(SMADDR_i[5]), .C(m421_ns_1_0), .D(m421_ns_1), .Y(i6_mux_1)
        );
    CFG4 #( .INIT(16'h7654) )  \doins_0_57_0_.m342_4  (.A(m342_4_1_1), 
        .B(SMADDR_i[0]), .C(m342_2), .D(m335_4), .Y(m342_4));
    CFG4 #( .INIT(16'hB1FF) )  \doins_0_57_0_.m175_am  (.A(SMADDR_i[1])
        , .B(m136), .C(SMADDR_i[4]), .D(SMADDR_i[5]), .Y(m175_am));
    CFG4 #( .INIT(16'h0F7F) )  \doins_0_57_0_.N_86_i_1_0  (.A(
        SMADDR_i[6]), .B(m50_0_0_wmux_0_Y), .C(SMADDR_i[7]), .D(
        SMADDR_i[8]), .Y(N_86_i_1_0));
    CFG3 #( .INIT(8'h08) )  \doins_0_57_0_.m133_1  (.A(SMADDR_i[0]), 
        .B(m131), .C(SMADDR_i[6]), .Y(m133_0));
    CFG4 #( .INIT(16'h0048) )  \doins_0_57_0_.m131  (.A(SMADDR_i[1]), 
        .B(m10), .C(SMADDR_i[2]), .D(SMADDR_i[5]), .Y(m131));
    CFG4 #( .INIT(16'h4002) )  \doins_0_57_0_.m126  (.A(SMADDR_i[4]), 
        .B(SMADDR_i[3]), .C(SMADDR_i[1]), .D(SMADDR_i[2]), .Y(m126));
    CFG4 #( .INIT(16'h88F3) )  \doins_0_57_0_.m285  (.A(m268), .B(
        SMADDR_i[8]), .C(m283_4), .D(m285_1_1), .Y(m285));
    CFG3 #( .INIT(8'h80) )  \doins_0_57_0_.m266_3  (.A(SMADDR_i[1]), 
        .B(m93), .C(SMADDR_i[5]), .Y(m95_2));
    CFG3 #( .INIT(8'h2E) )  \doins_0_57_0_.m104_bm_1  (.A(m71), .B(
        SMADDR_i[0]), .C(m101), .Y(m104_bm_1));
    SLE \doins_0_dreg[11]  (.D(m206_ns), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7108_reto));
    SLE \doins_0_dreg[12]  (.D(N_498_mux), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(N_7109_reto));
    
endmodule


module UART_top_COREABC_0_RAM256X16(
       RAMRDATA,
       RAMADDR,
       RAMWDATA,
       RD_2_reto,
       RDX_reto,
       RAM_RAM_0_2_RNI9AJE1_0,
       RAM_RAM_0_2_RNIBCJE1_0,
       RAM_RAM_0_2_RNIR37F1_0,
       REN_reto_rep2,
       REN_reto_rep1,
       un4_RD_reto,
       my_hpms_top_0_FIC32_0_CLK,
       REN_reto,
       STBRAM
    );
output [10:0] RAMRDATA;
input  [7:0] RAMADDR;
input  [15:0] RAMWDATA;
output [15:11] RD_2_reto;
output [15:11] RDX_reto;
output RAM_RAM_0_2_RNI9AJE1_0;
output RAM_RAM_0_2_RNIBCJE1_0;
output RAM_RAM_0_2_RNIR37F1_0;
output REN_reto_rep2;
output REN_reto_rep1;
output un4_RD_reto;
input  my_hpms_top_0_FIC32_0_CLK;
output REN_reto;
input  STBRAM;

    wire STBRAM_i_rep2, STBRAM_i_rep1, STBRAM_i_fast, STBRAM_i, 
        VCC_net_1, GND_net_1, \RDX_reto[3] , \RD_2_reto[3] , 
        \RDX_reto[4] , \RD_2_reto[4] , \RDX_reto[5] , \RD_2_reto[5] , 
        \RDX_reto[6] , \RD_2_reto[6] , \RDX_reto[7] , \RD_2_reto[7] , 
        \RDX_reto[8] , \RD_2_reto[8] , \RDX_reto[9] , \RD_2_reto[9] , 
        \RDX_reto[10] , \RD_2_reto[10] , \WD_reto[4] , \WD_reto[5] , 
        \WD_reto[6] , \WD_reto[7] , \WD_reto[8] , \WD_reto[9] , 
        \WD_reto[10] , \WD_reto[11] , \WD_reto[12] , \WD_reto[13] , 
        \WD_reto[14] , \WD_reto[15] , \RDX_reto[0] , \RD_2_reto[0] , 
        \RDX_reto[1] , \RD_2_reto[1] , \RDX_reto[2] , \RD_2_reto[2] , 
        \WD_reto[0] , \WD_reto[1] , \WD_reto[2] , \WD_reto[3] , 
        REN_reto_fast, \RAM_reto[0] , \RAM_reto[1] , \RAM_reto[2] , 
        \RAM_reto[3] , \RAM_reto[4] , \RAM_reto[5] , \RAM_reto[6] , 
        \RAM_reto[7] , \RAM_reto[8] , \RAM_reto[9] , \RAM_reto[10] , 
        \RAM_reto[11] , \RAM_reto[12] , \RAM_reto[13] , \RAM_reto[14] , 
        \RAM_reto[15] , \RD_0_1[10] , \RD_0_1[9] , \RD_0_1[8] , 
        \RD_0_sx[0] , \RD_0_1[7] , \RD_0_1[6] , \RD_0_1[5] , 
        \RD_0_1[4] , \RD_0_1[3] , \RD_0_1[2] , \RD_0_1[1] ;
    
    SLE \RD_ret[1]  (.D(\RD_2_reto[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[1] ));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_0_RNIRTIE1 (.A(\RD_0_1[2] ), 
        .B(\RAM_reto[2] ), .C(\WD_reto[2] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[2]));
    SLE \RD_ret[15]  (.D(RD_2_reto[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDX_reto[15]));
    SLE \RD_ret_17[4]  (.D(RAMWDATA[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[4] ));
    SLE \RD_ret_17[12]  (.D(RAMWDATA[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[12] ));
    SLE \RD_ret_17[7]  (.D(RAMWDATA[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[7] ));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_0_RNIPRIE1 (.A(\RD_0_1[1] ), 
        .B(\RAM_reto[1] ), .C(\WD_reto[1] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[1]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[6]  (.A(\RAM_reto[6] ), .B(
        \WD_reto[6] ), .C(un4_RD_reto), .Y(\RD_2_reto[6] ));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[5]  (.A(\RAM_reto[5] ), .B(
        \WD_reto[5] ), .C(un4_RD_reto), .Y(\RD_2_reto[5] ));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIP6F61[2]  (.A(\RDX_reto[2] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[2] ));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_1_RNI46JE1 (.A(\RD_0_1[6] ), 
        .B(\RAM_reto[6] ), .C(\WD_reto[6] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[6]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[9]  (.A(\RAM_reto[9] ), .B(
        \WD_reto[9] ), .C(un4_RD_reto), .Y(\RD_2_reto[9] ));
    CFG4 #( .INIT(16'h058D) )  \RD_ret_RNI48S51[0]  (.A(REN_reto_rep2), 
        .B(un4_RD_reto), .C(\RDX_reto[0] ), .D(\WD_reto[0] ), .Y(
        \RD_0_sx[0] ));
    RAM64x18 RAM_RAM_0_3 (.A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, nc6, 
        nc7, nc8, nc9, nc10, nc11, nc12, nc13, \RAM_reto[15] , 
        \RAM_reto[14] , \RAM_reto[13] , \RAM_reto[12] }), .B_DOUT({
        nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23, 
        nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[15], RAMWDATA[14], 
        RAMWDATA[13], RAMWDATA[12]}), .C_WEN(STBRAM), .C_BLK({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(
        GND_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(
        GND_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .SII_LOCK(GND_net_1));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[2]  (.A(\RAM_reto[2] ), .B(
        \WD_reto[2] ), .C(un4_RD_reto), .Y(\RD_2_reto[2] ));
    SLE RD_ret_32_fast (.D(STBRAM_i_fast), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(REN_reto_fast));
    RAM64x18 RAM_RAM_0_0 (.A_DOUT({nc32, nc33, nc34, nc35, nc36, nc37, 
        nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, \RAM_reto[3] , 
        \RAM_reto[2] , \RAM_reto[1] , \RAM_reto[0] }), .B_DOUT({nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[3], RAMWDATA[2], 
        RAMWDATA[1], RAMWDATA[0]}), .C_WEN(STBRAM), .C_BLK({VCC_net_1, 
        VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(GND_net_1), 
        .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(GND_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .SII_LOCK(GND_net_1));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[0]  (.A(\RAM_reto[0] ), .B(
        \WD_reto[0] ), .C(un4_RD_reto), .Y(\RD_2_reto[0] ));
    SLE \RD_ret[14]  (.D(RD_2_reto[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDX_reto[14]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[3]  (.A(\RAM_reto[3] ), .B(
        \WD_reto[3] ), .C(un4_RD_reto), .Y(\RD_2_reto[3] ));
    SLE \RD_ret_17[2]  (.D(RAMWDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[2] ));
    SLE \RD_ret[9]  (.D(\RD_2_reto[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[9] ));
    SLE \RD_ret[3]  (.D(\RD_2_reto[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[3] ));
    SLE \RD_ret_17[3]  (.D(RAMWDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[3] ));
    SLE \RD_ret[12]  (.D(RD_2_reto[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDX_reto[12]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[4]  (.A(\RAM_reto[4] ), .B(
        \WD_reto[4] ), .C(un4_RD_reto), .Y(\RD_2_reto[4] ));
    VCC VCC (.Y(VCC_net_1));
    SLE RD_ret_32_rep2 (.D(STBRAM_i_rep2), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(REN_reto_rep2));
    CFG3 #( .INIT(8'hCA) )  RAM_RAM_0_2_RNIU0MM (.A(\RAM_reto[11] ), 
        .B(\WD_reto[11] ), .C(un4_RD_reto), .Y(RD_2_reto[11]));
    SLE \RD_ret[7]  (.D(\RD_2_reto[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[7] ));
    RAM64x18 RAM_RAM_0_2 (.A_DOUT({nc64, nc65, nc66, nc67, nc68, nc69, 
        nc70, nc71, nc72, nc73, nc74, nc75, nc76, nc77, \RAM_reto[11] , 
        \RAM_reto[10] , \RAM_reto[9] , \RAM_reto[8] }), .B_DOUT({nc78, 
        nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88, 
        nc89, nc90, nc91, nc92, nc93, nc94, nc95}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[11], RAMWDATA[10], 
        RAMWDATA[9], RAMWDATA[8]}), .C_WEN(STBRAM), .C_BLK({VCC_net_1, 
        VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(GND_net_1), 
        .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(GND_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .SII_LOCK(GND_net_1));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_1_RNI68JE1 (.A(\RD_0_1[7] ), 
        .B(\RAM_reto[7] ), .C(\WD_reto[7] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[7]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[7]  (.A(\RAM_reto[7] ), .B(
        \WD_reto[7] ), .C(un4_RD_reto), .Y(\RD_2_reto[7] ));
    SLE \RD_ret[4]  (.D(\RD_2_reto[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[4] ));
    CFG3 #( .INIT(8'hCA) )  RAM_RAM_0_3_RNI24MM (.A(\RAM_reto[14] ), 
        .B(\WD_reto[14] ), .C(un4_RD_reto), .Y(RD_2_reto[14]));
    SLE \RD_ret[10]  (.D(\RD_2_reto[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[10] ));
    SLE \RD_ret_17[11]  (.D(RAMWDATA[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[11] ));
    CFG4 #( .INIT(16'h27AA) )  RAM_RAM_0_2_RNIBCJE1_0_inst_1 (.A(
        \RD_0_1[9] ), .B(\RAM_reto[9] ), .C(\WD_reto[9] ), .D(
        REN_reto_rep1), .Y(RAM_RAM_0_2_RNIBCJE1_0));
    RAM64x18 RAM_RAM_0_1 (.A_DOUT({nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103, nc104, nc105, nc106, nc107, nc108, nc109, 
        \RAM_reto[7] , \RAM_reto[6] , \RAM_reto[5] , \RAM_reto[4] }), 
        .B_DOUT({nc110, nc111, nc112, nc113, nc114, nc115, nc116, 
        nc117, nc118, nc119, nc120, nc121, nc122, nc123, nc124, nc125, 
        nc126, nc127}), .BUSY(), .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK)
        , .A_DOUT_CLK(VCC_net_1), .A_ADDR_SRST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_ADDR_ARST_N(VCC_net_1), 
        .A_DOUT_ARST_N(VCC_net_1), .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(
        VCC_net_1), .A_BLK({VCC_net_1, VCC_net_1}), .A_ADDR({
        RAMADDR[7], RAMADDR[6], RAMADDR[5], RAMADDR[4], RAMADDR[3], 
        RAMADDR[2], RAMADDR[1], RAMADDR[0], GND_net_1, GND_net_1}), 
        .B_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[7], RAMWDATA[6], 
        RAMWDATA[5], RAMWDATA[4]}), .C_WEN(STBRAM), .C_BLK({VCC_net_1, 
        VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(GND_net_1), 
        .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(GND_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, VCC_net_1, 
        GND_net_1}), .SII_LOCK(GND_net_1));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIQ7F61[3]  (.A(\RDX_reto[3] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[3] ));
    SLE \RD_ret_17[15]  (.D(RAMWDATA[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[15] ));
    SLE \RD_ret_17[13]  (.D(RAMWDATA[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[13] ));
    CFG3 #( .INIT(8'hCA) )  RAM_RAM_0_3_RNI02MM (.A(\RAM_reto[12] ), 
        .B(\WD_reto[12] ), .C(un4_RD_reto), .Y(RD_2_reto[12]));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[8]  (.A(\RAM_reto[8] ), .B(
        \WD_reto[8] ), .C(un4_RD_reto), .Y(\RD_2_reto[8] ));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNI8M731[10]  (.A(\RDX_reto[10] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[10] ));
    SLE \RD_ret[11]  (.D(RD_2_reto[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDX_reto[11]));
    SLE \RD_ret_17[14]  (.D(RAMWDATA[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[14] ));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_0_RNITVIE1 (.A(\RD_0_1[3] ), 
        .B(\RAM_reto[3] ), .C(\WD_reto[3] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[3]));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[10]  (.A(\RAM_reto[10] ), .B(
        \WD_reto[10] ), .C(un4_RD_reto), .Y(\RD_2_reto[10] ));
    CFG1 #( .INIT(2'h1) )  RD_ret_32_fast_RNO (.A(STBRAM), .Y(
        STBRAM_i_fast));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIO5F61[1]  (.A(\RDX_reto[1] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[1] ));
    SLE \RD_ret[0]  (.D(\RD_2_reto[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[0] ));
    SLE RD_ret_32 (.D(STBRAM_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(REN_reto));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIVCF61[8]  (.A(\RDX_reto[8] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[8] ));
    CFG1 #( .INIT(2'h1) )  RD_ret_32_rep1_RNO (.A(STBRAM), .Y(
        STBRAM_i_rep1));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_2_RNIBCJE1 (.A(\RD_0_1[9] ), 
        .B(\RAM_reto[9] ), .C(\WD_reto[9] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[9]));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_1_RNI02JE1 (.A(\RD_0_1[4] ), 
        .B(\RAM_reto[4] ), .C(\WD_reto[4] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[4]));
    CFG1 #( .INIT(2'h1) )  RD_ret_32_RNO (.A(STBRAM), .Y(STBRAM_i));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_2_RNIR37F1 (.A(\RD_0_1[10] ), 
        .B(\RAM_reto[10] ), .C(\WD_reto[10] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[10]));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNITAF61[6]  (.A(\RDX_reto[6] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[6] ));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIS9F61[5]  (.A(\RDX_reto[5] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[5] ));
    SLE RD_ret_32_rep1 (.D(STBRAM_i_rep1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(REN_reto_rep1));
    CFG3 #( .INIT(8'hCA) )  RAM_RAM_0_3_RNI35MM (.A(\RAM_reto[15] ), 
        .B(\WD_reto[15] ), .C(un4_RD_reto), .Y(RD_2_reto[15]));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_1_RNI24JE1 (.A(\RD_0_1[5] ), 
        .B(\RAM_reto[5] ), .C(\WD_reto[5] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[5]));
    SLE \RD_ret_17[9]  (.D(RAMWDATA[9]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[9] ));
    SLE \RD_ret_17[1]  (.D(RAMWDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[1] ));
    CFG3 #( .INIT(8'hCA) )  \RD_ret_RNO[1]  (.A(\RAM_reto[1] ), .B(
        \WD_reto[1] ), .C(un4_RD_reto), .Y(\RD_2_reto[1] ));
    CFG4 #( .INIT(16'h27AA) )  RAM_RAM_0_2_RNI9AJE1_0_inst_1 (.A(
        \RD_0_1[8] ), .B(\RAM_reto[8] ), .C(\WD_reto[8] ), .D(
        REN_reto_rep1), .Y(RAM_RAM_0_2_RNI9AJE1_0));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIR8F61[4]  (.A(\RDX_reto[4] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[4] ));
    SLE \RD_ret_17[6]  (.D(RAMWDATA[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[6] ));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNIUBF61[7]  (.A(\RDX_reto[7] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[7] ));
    SLE \RD_ret_17[8]  (.D(RAMWDATA[8]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[8] ));
    CFG3 #( .INIT(8'hCA) )  RAM_RAM_0_3_RNI13MM (.A(\RAM_reto[13] ), 
        .B(\WD_reto[13] ), .C(un4_RD_reto), .Y(RD_2_reto[13]));
    SLE RD_ret_33 (.D(STBRAM), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(un4_RD_reto));
    SLE \RD_ret[2]  (.D(\RD_2_reto[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[2] ));
    CFG4 #( .INIT(16'h27AA) )  RAM_RAM_0_2_RNIR37F1_0_inst_1 (.A(
        \RD_0_1[10] ), .B(\RAM_reto[10] ), .C(\WD_reto[10] ), .D(
        REN_reto_rep1), .Y(RAM_RAM_0_2_RNIR37F1_0));
    CFG4 #( .INIT(16'h00FB) )  RAM_RAM_0_0_RNIR3DR1 (.A(un4_RD_reto), 
        .B(REN_reto_rep2), .C(\RAM_reto[0] ), .D(\RD_0_sx[0] ), .Y(
        RAMRDATA[0]));
    SLE \RD_ret[8]  (.D(\RD_2_reto[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[8] ));
    SLE \RD_ret_17[5]  (.D(RAMWDATA[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[5] ));
    CFG1 #( .INIT(2'h1) )  RD_ret_32_rep2_RNO (.A(STBRAM), .Y(
        STBRAM_i_rep2));
    SLE \RD_ret[6]  (.D(\RD_2_reto[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[6] ));
    CFG3 #( .INIT(8'h1D) )  \RD_ret_RNI0EF61[9]  (.A(\RDX_reto[9] ), 
        .B(REN_reto_fast), .C(un4_RD_reto), .Y(\RD_0_1[9] ));
    SLE \RD_ret_17[0]  (.D(RAMWDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[0] ));
    CFG4 #( .INIT(16'hD855) )  RAM_RAM_0_2_RNI9AJE1 (.A(\RD_0_1[8] ), 
        .B(\RAM_reto[8] ), .C(\WD_reto[8] ), .D(REN_reto_rep1), .Y(
        RAMRDATA[8]));
    SLE \RD_ret_17[10]  (.D(RAMWDATA[10]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\WD_reto[10] ));
    SLE \RD_ret[5]  (.D(\RD_2_reto[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\RDX_reto[5] ));
    SLE \RD_ret[13]  (.D(RD_2_reto[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDX_reto[13]));
    
endmodule


module UART_top_COREABC_0_RAM256X16_0(
       RAMWDATA,
       RAMADDR,
       COREABC_0_APB3master_PWDATA,
       RD_2_reto,
       RDY_reto,
       un4_RD_reto,
       STBRAM,
       N_130_i,
       REN_reto,
       my_hpms_top_0_FIC32_0_CLK
    );
input  [31:16] RAMWDATA;
input  [7:0] RAMADDR;
input  [31:16] COREABC_0_APB3master_PWDATA;
output [15:0] RD_2_reto;
output [15:0] RDY_reto;
input  un4_RD_reto;
input  STBRAM;
input  N_130_i;
input  REN_reto;
input  my_hpms_top_0_FIC32_0_CLK;

    wire VCC_net_1, GND_net_1, \WD_reto[16] , \WD_reto[31] , 
        \WD_reto[30] , \WD_reto[29] , \WD_reto[28] , \WD_reto[27] , 
        \WD_reto[26] , \WD_reto[25] , \WD_reto[24] , \WD_reto[23] , 
        \WD_reto[22] , \WD_reto[21] , \WD_reto[20] , \WD_reto[19] , 
        \WD_reto[18] , \WD_reto[17] , \RAM_reto[0] , \RAM_reto[1] , 
        \RAM_reto[2] , \RAM_reto[3] , \RAM_reto[4] , \RAM_reto[5] , 
        \RAM_reto[6] , \RAM_reto[7] , \RAM_reto[8] , \RAM_reto[9] , 
        \RAM_reto[10] , \RAM_reto[11] , \RAM_reto[12] , \RAM_reto[13] , 
        \RAM_reto[14] , \RAM_reto[15] ;
    
    SLE \RD_ret[1]  (.D(RD_2_reto[1]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[1]));
    SLE \RD_ret[15]  (.D(RD_2_reto[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[15]));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNIJ2UL[15]  (.A(\WD_reto[31] ), 
        .B(un4_RD_reto), .C(\RAM_reto[15] ), .Y(RD_2_reto[15]));
    SLE \RD_ret_17[4]  (.D(COREABC_0_APB3master_PWDATA[20]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[20] ));
    SLE \RD_ret_17[12]  (.D(COREABC_0_APB3master_PWDATA[28]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[28] ));
    SLE \RD_ret_17[7]  (.D(COREABC_0_APB3master_PWDATA[23]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[23] ));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_1_RNI2K3Q (.A(\WD_reto[23] ), .B(
        un4_RD_reto), .C(\RAM_reto[7] ), .Y(RD_2_reto[7]));
    RAM64x18 RAM_RAM_0_3 (.A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, nc6, 
        nc7, nc8, nc9, nc10, nc11, nc12, nc13, \RAM_reto[15] , 
        \RAM_reto[14] , \RAM_reto[13] , \RAM_reto[12] }), .B_DOUT({
        nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23, 
        nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[31], RAMWDATA[30], 
        RAMWDATA[29], RAMWDATA[28]}), .C_WEN(STBRAM), .C_BLK({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(
        GND_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(
        GND_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .SII_LOCK(GND_net_1));
    RAM64x18 RAM_RAM_0_0 (.A_DOUT({nc32, nc33, nc34, nc35, nc36, nc37, 
        nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, \RAM_reto[3] , 
        \RAM_reto[2] , \RAM_reto[1] , \RAM_reto[0] }), .B_DOUT({nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[19], RAMWDATA[18], 
        RAMWDATA[17], RAMWDATA[16]}), .C_WEN(STBRAM), .C_BLK({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(
        GND_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(
        GND_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .SII_LOCK(GND_net_1));
    SLE \RD_ret[14]  (.D(RD_2_reto[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[14]));
    SLE \RD_ret_17[2]  (.D(COREABC_0_APB3master_PWDATA[18]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[18] ));
    SLE \RD_ret[9]  (.D(RD_2_reto[9]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[9]));
    SLE \RD_ret[3]  (.D(RD_2_reto[3]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[3]));
    SLE \RD_ret_17[3]  (.D(COREABC_0_APB3master_PWDATA[19]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[19] ));
    SLE \RD_ret[12]  (.D(RD_2_reto[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[12]));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_2_RNI5M3Q (.A(\WD_reto[25] ), .B(
        un4_RD_reto), .C(\RAM_reto[9] ), .Y(RD_2_reto[9]));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNIGVTL[12]  (.A(\WD_reto[28] ), 
        .B(un4_RD_reto), .C(\RAM_reto[12] ), .Y(RD_2_reto[12]));
    SLE \RD_ret[7]  (.D(RD_2_reto[7]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[7]));
    RAM64x18 RAM_RAM_0_2 (.A_DOUT({nc64, nc65, nc66, nc67, nc68, nc69, 
        nc70, nc71, nc72, nc73, nc74, nc75, nc76, nc77, \RAM_reto[11] , 
        \RAM_reto[10] , \RAM_reto[9] , \RAM_reto[8] }), .B_DOUT({nc78, 
        nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88, 
        nc89, nc90, nc91, nc92, nc93, nc94, nc95}), .BUSY(), 
        .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ADDR_SRST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), 
        .A_ADDR_ARST_N(VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), 
        .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        VCC_net_1, VCC_net_1}), .A_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .B_ADDR_CLK(
        my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[27], RAMWDATA[26], 
        RAMWDATA[25], RAMWDATA[24]}), .C_WEN(STBRAM), .C_BLK({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(
        GND_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(
        GND_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .SII_LOCK(GND_net_1));
    SLE \RD_ret[4]  (.D(RD_2_reto[4]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[4]));
    SLE \RD_ret[10]  (.D(RD_2_reto[10]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[10]));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_0_RNISE3Q (.A(\WD_reto[18] ), .B(
        un4_RD_reto), .C(\RAM_reto[2] ), .Y(RD_2_reto[2]));
    SLE \RD_ret_17[11]  (.D(COREABC_0_APB3master_PWDATA[27]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[27] ));
    RAM64x18 RAM_RAM_0_1 (.A_DOUT({nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103, nc104, nc105, nc106, nc107, nc108, nc109, 
        \RAM_reto[7] , \RAM_reto[6] , \RAM_reto[5] , \RAM_reto[4] }), 
        .B_DOUT({nc110, nc111, nc112, nc113, nc114, nc115, nc116, 
        nc117, nc118, nc119, nc120, nc121, nc122, nc123, nc124, nc125, 
        nc126, nc127}), .BUSY(), .A_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK)
        , .A_DOUT_CLK(VCC_net_1), .A_ADDR_SRST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_ADDR_ARST_N(VCC_net_1), 
        .A_DOUT_ARST_N(VCC_net_1), .A_ADDR_EN(VCC_net_1), .A_DOUT_EN(
        VCC_net_1), .A_BLK({VCC_net_1, VCC_net_1}), .A_ADDR({
        RAMADDR[7], RAMADDR[6], RAMADDR[5], RAMADDR[4], RAMADDR[3], 
        RAMADDR[2], RAMADDR[1], RAMADDR[0], GND_net_1, GND_net_1}), 
        .B_ADDR_CLK(my_hpms_top_0_FIC32_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), 
        .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(VCC_net_1), 
        .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        VCC_net_1, VCC_net_1}), .B_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({RAMADDR[7], RAMADDR[6], 
        RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], RAMADDR[1], 
        RAMADDR[0], GND_net_1, GND_net_1}), .C_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, RAMWDATA[23], RAMWDATA[22], 
        RAMWDATA[21], RAMWDATA[20]}), .C_WEN(STBRAM), .C_BLK({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_ADDR_LAT(
        GND_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .B_EN(GND_net_1), .B_ADDR_LAT(
        GND_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .C_EN(VCC_net_1), .C_WIDTH({GND_net_1, 
        VCC_net_1, GND_net_1}), .SII_LOCK(GND_net_1));
    SLE \RD_ret_17[15]  (.D(COREABC_0_APB3master_PWDATA[31]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[31] ));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_1_RNIVG3Q (.A(\WD_reto[20] ), .B(
        un4_RD_reto), .C(\RAM_reto[4] ), .Y(RD_2_reto[4]));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_1_RNI0I3Q (.A(\WD_reto[21] ), .B(
        un4_RD_reto), .C(\RAM_reto[5] ), .Y(RD_2_reto[5]));
    SLE \RD_ret_17[13]  (.D(COREABC_0_APB3master_PWDATA[29]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[29] ));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNIEUTL[11]  (.A(\WD_reto[27] ), 
        .B(un4_RD_reto), .C(\RAM_reto[11] ), .Y(RD_2_reto[11]));
    SLE \RD_ret[11]  (.D(RD_2_reto[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[11]));
    SLE \RD_ret_17[14]  (.D(COREABC_0_APB3master_PWDATA[30]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[30] ));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNIDTTL[10]  (.A(\WD_reto[26] ), 
        .B(un4_RD_reto), .C(\RAM_reto[10] ), .Y(RD_2_reto[10]));
    SLE \RD_ret[0]  (.D(RD_2_reto[0]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[0]));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_0_RNITF3Q (.A(\WD_reto[19] ), .B(
        un4_RD_reto), .C(\RAM_reto[3] ), .Y(RD_2_reto[3]));
    SLE \RD_ret_17[9]  (.D(COREABC_0_APB3master_PWDATA[25]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[25] ));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_0_RNIRD3Q (.A(\WD_reto[17] ), .B(
        un4_RD_reto), .C(\RAM_reto[1] ), .Y(RD_2_reto[1]));
    SLE \RD_ret_17[1]  (.D(COREABC_0_APB3master_PWDATA[17]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[17] ));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_1_RNI1J3Q (.A(\WD_reto[22] ), .B(
        un4_RD_reto), .C(\RAM_reto[6] ), .Y(RD_2_reto[6]));
    SLE \RD_ret_17[6]  (.D(COREABC_0_APB3master_PWDATA[22]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[22] ));
    SLE \RD_ret_17[8]  (.D(COREABC_0_APB3master_PWDATA[24]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[24] ));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_2_RNI4L3Q (.A(\WD_reto[24] ), .B(
        un4_RD_reto), .C(\RAM_reto[8] ), .Y(RD_2_reto[8]));
    SLE \RD_ret[2]  (.D(RD_2_reto[2]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[2]));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNII1UL[14]  (.A(\WD_reto[30] ), 
        .B(un4_RD_reto), .C(\RAM_reto[14] ), .Y(RD_2_reto[14]));
    CFG3 #( .INIT(8'hB8) )  \RD_ret_17_RNIH0UL[13]  (.A(\WD_reto[29] ), 
        .B(un4_RD_reto), .C(\RAM_reto[13] ), .Y(RD_2_reto[13]));
    CFG3 #( .INIT(8'hB8) )  RAM_RAM_0_0_RNIQC3Q (.A(\WD_reto[16] ), .B(
        un4_RD_reto), .C(\RAM_reto[0] ), .Y(RD_2_reto[0]));
    SLE \RD_ret[8]  (.D(RD_2_reto[8]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[8]));
    SLE \RD_ret_17[5]  (.D(COREABC_0_APB3master_PWDATA[21]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[21] ));
    SLE \RD_ret[6]  (.D(RD_2_reto[6]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[6]));
    SLE \RD_ret_17[0]  (.D(COREABC_0_APB3master_PWDATA[16]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[16] ));
    SLE \RD_ret_17[10]  (.D(COREABC_0_APB3master_PWDATA[26]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(N_130_i), .SD(GND_net_1), .LAT(GND_net_1)
        , .Q(\WD_reto[26] ));
    SLE \RD_ret[5]  (.D(RD_2_reto[5]), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(REN_reto), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(RDY_reto[5]));
    SLE \RD_ret[13]  (.D(RD_2_reto[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(REN_reto), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RDY_reto[13]));
    
endmodule


module UART_top_COREABC_0_RAMBLOCKS_32s_24s(
       RDY_reto,
       RD_2_reto_0,
       RD_2_reto,
       COREABC_0_APB3master_PWDATA,
       RAMWDATA,
       RDX_reto,
       RAMADDR,
       RAMRDATA,
       N_130_i,
       STBRAM,
       my_hpms_top_0_FIC32_0_CLK,
       REN_reto_rep1,
       REN_reto_rep2,
       RAM_RAM_0_2_RNIR37F1_0,
       RAM_RAM_0_2_RNIBCJE1_0,
       RAM_RAM_0_2_RNI9AJE1_0
    );
output [15:0] RDY_reto;
output [15:11] RD_2_reto_0;
output [15:0] RD_2_reto;
input  [31:16] COREABC_0_APB3master_PWDATA;
input  [31:0] RAMWDATA;
output [15:11] RDX_reto;
input  [7:0] RAMADDR;
output [10:0] RAMRDATA;
input  N_130_i;
input  STBRAM;
input  my_hpms_top_0_FIC32_0_CLK;
output REN_reto_rep1;
output REN_reto_rep2;
output RAM_RAM_0_2_RNIR37F1_0;
output RAM_RAM_0_2_RNIBCJE1_0;
output RAM_RAM_0_2_RNI9AJE1_0;

    wire un4_RD_reto, REN_reto, GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    UART_top_COREABC_0_RAM256X16 \UG3.UR_xhdl12  (.RAMRDATA({
        RAMRDATA[10], RAMRDATA[9], RAMRDATA[8], RAMRDATA[7], 
        RAMRDATA[6], RAMRDATA[5], RAMRDATA[4], RAMRDATA[3], 
        RAMRDATA[2], RAMRDATA[1], RAMRDATA[0]}), .RAMADDR({RAMADDR[7], 
        RAMADDR[6], RAMADDR[5], RAMADDR[4], RAMADDR[3], RAMADDR[2], 
        RAMADDR[1], RAMADDR[0]}), .RAMWDATA({RAMWDATA[15], 
        RAMWDATA[14], RAMWDATA[13], RAMWDATA[12], RAMWDATA[11], 
        RAMWDATA[10], RAMWDATA[9], RAMWDATA[8], RAMWDATA[7], 
        RAMWDATA[6], RAMWDATA[5], RAMWDATA[4], RAMWDATA[3], 
        RAMWDATA[2], RAMWDATA[1], RAMWDATA[0]}), .RD_2_reto({
        RD_2_reto[15], RD_2_reto[14], RD_2_reto[13], RD_2_reto[12], 
        RD_2_reto[11]}), .RDX_reto({RDX_reto[15], RDX_reto[14], 
        RDX_reto[13], RDX_reto[12], RDX_reto[11]}), 
        .RAM_RAM_0_2_RNI9AJE1_0(RAM_RAM_0_2_RNI9AJE1_0), 
        .RAM_RAM_0_2_RNIBCJE1_0(RAM_RAM_0_2_RNIBCJE1_0), 
        .RAM_RAM_0_2_RNIR37F1_0(RAM_RAM_0_2_RNIR37F1_0), 
        .REN_reto_rep2(REN_reto_rep2), .REN_reto_rep1(REN_reto_rep1), 
        .un4_RD_reto(un4_RD_reto), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .REN_reto(REN_reto), .STBRAM(
        STBRAM));
    GND GND (.Y(GND_net_1));
    UART_top_COREABC_0_RAM256X16_0 \UG3.UR32.UR0  (.RAMWDATA({
        RAMWDATA[31], RAMWDATA[30], RAMWDATA[29], RAMWDATA[28], 
        RAMWDATA[27], RAMWDATA[26], RAMWDATA[25], RAMWDATA[24], 
        RAMWDATA[23], RAMWDATA[22], RAMWDATA[21], RAMWDATA[20], 
        RAMWDATA[19], RAMWDATA[18], RAMWDATA[17], RAMWDATA[16]}), 
        .RAMADDR({RAMADDR[7], RAMADDR[6], RAMADDR[5], RAMADDR[4], 
        RAMADDR[3], RAMADDR[2], RAMADDR[1], RAMADDR[0]}), 
        .COREABC_0_APB3master_PWDATA({COREABC_0_APB3master_PWDATA[31], 
        COREABC_0_APB3master_PWDATA[30], 
        COREABC_0_APB3master_PWDATA[29], 
        COREABC_0_APB3master_PWDATA[28], 
        COREABC_0_APB3master_PWDATA[27], 
        COREABC_0_APB3master_PWDATA[26], 
        COREABC_0_APB3master_PWDATA[25], 
        COREABC_0_APB3master_PWDATA[24], 
        COREABC_0_APB3master_PWDATA[23], 
        COREABC_0_APB3master_PWDATA[22], 
        COREABC_0_APB3master_PWDATA[21], 
        COREABC_0_APB3master_PWDATA[20], 
        COREABC_0_APB3master_PWDATA[19], 
        COREABC_0_APB3master_PWDATA[18], 
        COREABC_0_APB3master_PWDATA[17], 
        COREABC_0_APB3master_PWDATA[16]}), .RD_2_reto({RD_2_reto_0[15], 
        RD_2_reto_0[14], RD_2_reto_0[13], RD_2_reto_0[12], 
        RD_2_reto_0[11], RD_2_reto[10], RD_2_reto[9], RD_2_reto[8], 
        RD_2_reto[7], RD_2_reto[6], RD_2_reto[5], RD_2_reto[4], 
        RD_2_reto[3], RD_2_reto[2], RD_2_reto[1], RD_2_reto[0]}), 
        .RDY_reto({RDY_reto[15], RDY_reto[14], RDY_reto[13], 
        RDY_reto[12], RDY_reto[11], RDY_reto[10], RDY_reto[9], 
        RDY_reto[8], RDY_reto[7], RDY_reto[6], RDY_reto[5], 
        RDY_reto[4], RDY_reto[3], RDY_reto[2], RDY_reto[1], 
        RDY_reto[0]}), .un4_RD_reto(un4_RD_reto), .STBRAM(STBRAM), 
        .N_130_i(N_130_i), .REN_reto(REN_reto), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK));
    
endmodule


module UART_top_COREABC_0_COREABC_Z9(
       COREABC_0_APB3master_PWDATA,
       COREABC_0_APB3master_PADDR_i_0,
       iPRDATA_5,
       iPRDATA_4,
       iPRDATA_3,
       iPRDATA_0,
       iPRDATA_6,
       APB_register_blk_0_PRDATA_5,
       APB_register_blk_0_PRDATA_3,
       APB_register_blk_0_PRDATA_0,
       APB_register_blk_0_PRDATA_13,
       APB_register_blk_0_PRDATA_10,
       APB_register_blk_0_PRDATA_9,
       APB_register_blk_0_PRDATA_8,
       APB_register_blk_0_PRDATA_7,
       PRDATA_0_iv_0_0_0_3,
       PRDATA_0_iv_0_0_0_2,
       PRDATA_0_iv_0_0_0_0,
       SMADDR_i_4,
       SMADDR_i_1,
       SMADDR_i_0,
       N_7119_reto,
       G_622,
       m10,
       N_180,
       APB_register_blk_0_PREADY,
       iPRDATA_0_sqmuxa,
       COREABC_0_APB3master_PWRITE,
       N_7112_reto,
       CoreAPB3_0_APBmslave1_PSELx,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreUARTapb_0_TXRDY,
       CoreUARTapb_0_RXRDY,
       syssvc_blk_0_NRBG_SVC_DONE,
       N_7107_reto,
       N_7108_reto,
       N_7109_reto,
       N_7110_reto,
       N_7111_reto,
       N_7115_reto,
       RSTSYNC1,
       my_hpms_top_0_HPMS_READY,
       COREABC_0_APB3master_PENABLE,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
output [7:0] COREABC_0_APB3master_PWDATA;
output COREABC_0_APB3master_PADDR_i_0;
input  iPRDATA_5;
input  iPRDATA_4;
input  iPRDATA_3;
input  iPRDATA_0;
input  iPRDATA_6;
input  APB_register_blk_0_PRDATA_5;
input  APB_register_blk_0_PRDATA_3;
input  APB_register_blk_0_PRDATA_0;
input  APB_register_blk_0_PRDATA_13;
input  APB_register_blk_0_PRDATA_10;
input  APB_register_blk_0_PRDATA_9;
input  APB_register_blk_0_PRDATA_8;
input  APB_register_blk_0_PRDATA_7;
input  PRDATA_0_iv_0_0_0_3;
input  PRDATA_0_iv_0_0_0_2;
input  PRDATA_0_iv_0_0_0_0;
output SMADDR_i_4;
output SMADDR_i_1;
output SMADDR_i_0;
output N_7119_reto;
input  G_622;
output m10;
input  N_180;
input  APB_register_blk_0_PREADY;
input  iPRDATA_0_sqmuxa;
output COREABC_0_APB3master_PWRITE;
output N_7112_reto;
output CoreAPB3_0_APBmslave1_PSELx;
output CoreAPB3_0_APBmslave0_PSELx;
input  CoreUARTapb_0_TXRDY;
input  CoreUARTapb_0_RXRDY;
input  syssvc_blk_0_NRBG_SVC_DONE;
output N_7107_reto;
output N_7108_reto;
output N_7109_reto;
output N_7110_reto;
output N_7111_reto;
output N_7115_reto;
input  RSTSYNC1;
input  my_hpms_top_0_HPMS_READY;
output COREABC_0_APB3master_PENABLE;
input  my_hpms_top_0_FIC32_0_CLK;
output COREABC_0_PRESETN;

    wire RSTSYNC2, N_130, N_130_i, \SMADDR[9]_net_1 , GND_net_1, N_100, 
        un1_ICYCLE_6_i, VCC_net_1, \SMADDR[10]_net_1 , N_102, 
        \STKPTR[0]_net_1 , un1_STKPTR_cry_0_Y, \STKPTR[1]_net_1 , 
        \STKPTR_12[1]_net_1 , \STKPTR[2]_net_1 , \STKPTR_12[2]_net_1 , 
        \STKPTR[3]_net_1 , \STKPTR_12[3]_net_1 , \STKPTR[4]_net_1 , 
        \STKPTR_12[4]_net_1 , \STKPTR[5]_net_1 , \STKPTR_12[5]_net_1 , 
        \STKPTR[6]_net_1 , \STKPTR_12[6]_net_1 , \STKPTR[7]_net_1 , 
        \STKPTR_12[7]_net_1 , \ACCUMULATOR[23]_net_1 , 
        \ACCUM_NEXT[23]_net_1 , ACCUMULATOR4_net_1, 
        \ACCUMULATOR[24]_net_1 , \ACCUM_NEXT[24]_net_1 , 
        \ACCUMULATOR[25]_net_1 , \ACCUM_NEXT[25]_net_1 , 
        \ACCUMULATOR[26]_net_1 , \ACCUM_NEXT[26]_net_1 , 
        \ACCUMULATOR[27]_net_1 , \ACCUM_NEXT[27]_net_1 , 
        \ACCUMULATOR[28]_net_1 , \ACCUM_NEXT[28]_net_1 , 
        \ACCUMULATOR[29]_net_1 , \ACCUM_NEXT[29]_net_1 , 
        \ACCUMULATOR[30]_net_1 , \ACCUM_NEXT[30]_net_1 , 
        \ACCUMULATOR[31]_net_1 , \ACCUM_NEXT[31]_net_1 , 
        \ACCUMULATOR[8]_net_1 , \ACCUM_NEXT[8]_net_1 , 
        \ACCUMULATOR[9]_net_1 , \ACCUM_NEXT[9]_net_1 , 
        \ACCUMULATOR[10]_net_1 , \ACCUM_NEXT[10]_net_1 , 
        \ACCUMULATOR[11]_net_1 , \ACCUM_NEXT[11]_net_1 , 
        \ACCUMULATOR[12]_net_1 , \ACCUM_NEXT[12]_net_1 , 
        \ACCUMULATOR[13]_net_1 , \ACCUM_NEXT[13]_net_1 , 
        \ACCUMULATOR[14]_net_1 , \ACCUM_NEXT[14]_net_1 , 
        \ACCUMULATOR[15]_net_1 , \ACCUM_NEXT[15]_net_1 , 
        \ACCUMULATOR[16]_net_1 , \ACCUM_NEXT[16]_net_1 , 
        \ACCUMULATOR[17]_net_1 , \ACCUM_NEXT[17]_net_1 , 
        \ACCUMULATOR[18]_net_1 , \ACCUM_NEXT[18]_net_1 , 
        \ACCUMULATOR[19]_net_1 , \ACCUM_NEXT[19]_net_1 , 
        \ACCUMULATOR[20]_net_1 , \ACCUM_NEXT[20]_net_1 , 
        \ACCUMULATOR[21]_net_1 , \ACCUM_NEXT[21]_net_1 , 
        \ACCUMULATOR[22]_net_1 , \ACCUM_NEXT[22]_net_1 , 
        \ACCUMULATOR[0]_net_1 , \ACCUM_NEXT[0]_net_1 , 
        \ACCUMULATOR[1]_net_1 , \ACCUM_NEXT[1]_net_1 , 
        \ACCUMULATOR[2]_net_1 , \ACCUM_NEXT[2]_net_1 , 
        \ACCUMULATOR[3]_net_1 , \ACCUM_NEXT[3]_net_1 , 
        \ACCUMULATOR[4]_net_1 , \ACCUM_NEXT[4]_net_1 , 
        \ACCUMULATOR[5]_net_1 , \ACCUM_NEXT[5]_net_1 , 
        \ACCUMULATOR[6]_net_1 , \ACCUM_NEXT[6]_net_1 , 
        \ACCUMULATOR[7]_net_1 , \ACCUM_NEXT[7]_net_1 , 
        STD_ACCUM_ZERO_net_1, \tmp_4[0] , STBFLAG_net_1, 
        STD_ACCUM_NEG_net_1, DOJMP_net_1, DOJMP_55_net_1, 
        \ICYCLE[1]_net_1 , N_87_i, \ICYCLE[0]_net_1 , N_909_i, 
        ICYCLE_1_sqmuxa, m3_1, PSELI_5, STBACCUM_net_1, STBACCUM_4, 
        STBFLAG_5, STBRAM_net_1, STBRAM_6, \SMADDR_i[8] , N_98_i, 
        \SMADDR_i[7] , N_96_i, \SMADDR_i[6] , N_94_i, N_92_i, 
        \SMADDR_i[4] , N_799_i, \SMADDR_i[3] , N_814_i, N_829_i, 
        N_679_i, \SMADDR_i[0] , N_694_i, doins_adflt_i_reto, 
        doins_adflt_i, doins_adflt_reto, doins_adflt, 
        ACCUM_NEXT_m5_0_cry_0, \ACCUM_IN_RNIG5JV_Y[0] , 
        \ACCUM_IN[0]_net_1 , \MSEL[2] , ACCUM_NEXT_m5_0_cry_1, 
        \ACCUM_IN_RNI2D6V1_S[1] , \ACCUM_IN[1]_net_1 , 
        ACCUM_NEXT_m5_0_cry_2, \ACCUM_IN_RNIMMPU2_S[2] , 
        \ACCUM_IN[2]_net_1 , ACCUM_NEXT_m5_0_cry_3, 
        \ACCUM_IN_RNIC2DU3_S[3] , \ACCUM_IN[3]_net_1 , 
        ACCUM_NEXT_m5_0_cry_4, \ACCUM_IN_RNI4G0U4_S[4] , 
        \ACCUM_IN[4]_net_1 , ACCUM_NEXT_m5_0_cry_5, 
        \ACCUM_IN_RNIUVJT5_S[5] , \ACCUM_IN[5]_net_1 , 
        ACCUM_NEXT_m5_0_cry_6, \ACCUM_IN_RNIQH7T6_S[6] , 
        \ACCUM_IN[6]_net_1 , ACCUM_NEXT_m5_0_cry_7, 
        \ACCUM_IN_RNIO5RS7_S[7] , \ACCUM_IN[7]_net_1 , 
        ACCUM_NEXT_m5_0_cry_8, \ACCUM_IN_RNI3J5VA_S[7] , 
        \ACCUM_IN_RNIPGLJ[8]_net_1 , ACCUM_NEXT_m5_0_axb_8, 
        ACCUM_NEXT_m5_0_cry_9, \ACCUM_IN_RNII4G1E_S[9] , 
        \ACCUM_IN_RNIQHLJ[9]_net_1 , ACCUM_NEXT_m5_0_axb_9, 
        ACCUM_NEXT_m5_0_cry_10, \ALUOUT_4_0_m2_RNIT231H_S[10] , 
        \ALUOUT_4_0_m2_RNIUQDI[10] , ACCUM_NEXT_m5_0_axb_10, 
        ACCUM_NEXT_m5_0_cry_11, \ACCUM_IN_RNIHKP6I_S[11] , 
        \ACCUM_IN[11]_net_1 , ACCUM_NEXT_m5_0_cry_12, 
        \ACCUM_IN_RNI78GCJ_S[12] , \ACCUM_IN[12]_net_1 , 
        ACCUM_NEXT_m5_0_cry_13, \ACCUM_IN_RNIVT6IK_S[13] , 
        \ACCUM_IN[13]_net_1 , ACCUM_NEXT_m5_0_cry_14, 
        \ACCUM_IN_RNIPLTNL_S[14] , \ACCUM_IN[14]_net_1 , 
        ACCUM_NEXT_m5_0_cry_15, \ACCUM_IN_RNILFKTM_S[15] , 
        \ACCUM_IN[15]_net_1 , ACCUM_NEXT_m5_0_cry_16, 
        \ACCUM_IN_RNIJBB3O_S[16] , \ACCUM_IN[16]_net_1 , 
        ACCUM_NEXT_m5_0_cry_17, \ACCUM_IN_RNIJ929P_S[17] , 
        \ACCUM_IN[17]_net_1 , ACCUM_NEXT_m5_0_cry_18, 
        \ACCUM_IN_RNIL9PEQ_S[18] , \ACCUM_IN[18]_net_1 , 
        ACCUM_NEXT_m5_0_cry_19, \ACCUM_IN_RNIPBGKR_S[19] , 
        \ACCUM_IN[19]_net_1 , ACCUM_NEXT_m5_0_cry_20, 
        \ACCUM_IN_RNIDV8QS_S[20] , \ACCUM_IN[20]_net_1 , 
        ACCUM_NEXT_m5_0_cry_21, \ACCUM_IN_RNI3L10U_S[21] , 
        \ACCUM_IN[21]_net_1 , ACCUM_NEXT_m5_0_cry_22, 
        \ACCUM_IN_RNIRCQ5V_S[22] , \ACCUM_IN[22]_net_1 , 
        ACCUM_NEXT_m5_0_cry_23, \ACCUM_IN_RNIL6JRV_S[23] , 
        \ACCUM_IN[23]_net_1 , ACCUM_NEXT_m5_0_cry_24, 
        \ACCUM_IN_RNIH2CH01_S[24] , \ACCUM_IN[24]_net_1 , 
        ACCUM_NEXT_m5_0_cry_25, \ACCUM_IN_RNIF05711_S[25] , 
        \ACCUM_IN[25]_net_1 , ACCUM_NEXT_m5_0_cry_26, 
        \ACCUM_IN_RNIF0US11_S[26] , \ACCUM_IN[26]_net_1 , 
        ACCUM_NEXT_m5_0_cry_27, \ACCUM_IN_RNIH2NI21_S[27] , 
        \ACCUM_IN[27]_net_1 , ACCUM_NEXT_m5_0_cry_28, 
        \ACCUM_IN_RNIL6G831_S[28] , \ACCUM_IN[28]_net_1 , 
        ACCUM_NEXT_m5_0_cry_29, \ACCUM_IN_RNIRC9U31_S[29] , 
        \ACCUM_IN[29]_net_1 , \ACCUM_NEXT_RNO_S[31] , 
        \ACCUM_IN[31]_net_1 , ACCUM_NEXT_m5_0_cry_30, 
        \ACCUM_IN_RNIH44K41_S[30] , \ACCUM_IN[30]_net_1 , 
        un1_STKPTR_cry_0_net_1, N_111_1, N_126, N_7101_reto, 
        un1_STKPTR_cry_1_net_1, un1_STKPTR_cry_1_S, 
        un1_STKPTR_cry_2_net_1, un1_STKPTR_cry_2_S, 
        un1_STKPTR_cry_3_net_1, un1_STKPTR_cry_3_S, 
        un1_STKPTR_cry_4_net_1, un1_STKPTR_cry_4_S, 
        un1_STKPTR_cry_5_net_1, un1_STKPTR_cry_5_S, un1_STKPTR_s_7_S, 
        un1_STKPTR_cry_6_net_1, un1_STKPTR_cry_6_S, 
        un1_SMADDR_cry_0_net_1, un1_SMADDR_cry_1_net_1, 
        un1_SMADDR_cry_1_S, un1_SMADDR_cry_2_net_1, un1_SMADDR_cry_2_S, 
        un1_SMADDR_cry_3_net_1, un1_SMADDR_cry_3_S, 
        un1_SMADDR_cry_4_net_1, un1_SMADDR_cry_4_S, 
        un1_SMADDR_cry_5_net_1, un1_SMADDR_cry_5_S, 
        un1_SMADDR_cry_6_net_1, un1_SMADDR_cry_6_S, 
        un1_SMADDR_cry_7_net_1, un1_SMADDR_cry_7_S, 
        un1_SMADDR_cry_8_net_1, un1_SMADDR_cry_8_S, un1_SMADDR_s_10_S, 
        un1_SMADDR_cry_9_net_1, un1_SMADDR_cry_9_S, 
        un1_STKPTRP1_s_1_812_FCO, un1_STKPTRP1_cry_1_net_1, 
        un1_STKPTRP1_cry_1_S, un1_STKPTRP1_cry_2_net_1, 
        un1_STKPTRP1_cry_2_S, un1_STKPTRP1_cry_3_net_1, 
        un1_STKPTRP1_cry_3_S, un1_STKPTRP1_cry_4_net_1, 
        un1_STKPTRP1_cry_4_S, un1_STKPTRP1_cry_5_net_1, 
        un1_STKPTRP1_cry_5_S, un1_STKPTRP1_s_7_S, 
        un1_STKPTRP1_cry_6_net_1, un1_STKPTRP1_cry_6_S, 
        \ACCUM_IN[8]_net_1 , \ACCUM_IN[9]_net_1 , N_81, 
        \to_logic_9_i_o2_sx[0]_net_1 , \RAMRDATA[1] , N_7124_reto, 
        \INSTR_CMD[1] , RAM_RAM_0_2_RNIR37F1_0, N_915, 
        RAM_RAM_0_2_RNIBCJE1_0, RAM_RAM_0_2_RNI9AJE1_0, 
        \ACCUM_NEXT_1[23] , ALUOUT_6_sqmuxa, ACCUM_NEXT_sm5, 
        \doins_0_dreg_RNIJ2TF[3] , \ACCUM_NEXT_m4[23]_net_1 , 
        \ACCUM_NEXT_1[22] , \ACCUM_NEXT_m4[22]_net_1 , 
        \ACCUM_NEXT_1_0[17]_net_1 , \ACCUM_NEXT_m4[17]_net_1 , 
        \ACCUM_NEXT_1[27] , \ACCUM_NEXT_m4[27]_net_1 , 
        \ACCUM_NEXT_1_0[18]_net_1 , \ACCUM_NEXT_m4[18]_net_1 , 
        ALUOUT_1_sqmuxa_net_1, \MSEL[0] , 
        \ACCUM_NEXT_m4_1_0[21]_net_1 , \ACCUM_NEXT_m4_1_0[24]_net_1 , 
        \ACCUM_NEXT_m4_1_0[25]_net_1 , \ACCUM_NEXT_m4_1_0[28]_net_1 , 
        \ACCUM_NEXT_m4_1_0[30]_net_1 , \ACCUM_NEXT_m4_1_0[29]_net_1 , 
        \ACCUM_NEXT_m4_1_0[26]_net_1 , \ACCUM_NEXT_m0[15]_net_1 , 
        ACCUM_NEXT_sm0, \ACCUM_NEXT_m4_1_0[15]_net_1 , 
        \ACCUM_NEXT_1_sx[15]_net_1 , \ACCUM_NEXT_1[15]_net_1 , 
        \ACCUM_NEXT_m0[16]_net_1 , \ACCUM_NEXT_m4_1_0[16]_net_1 , 
        \ACCUM_NEXT_1_sx[16]_net_1 , \ACCUM_NEXT_1[16]_net_1 , 
        \ACCUM_NEXT_m0[19]_net_1 , \ACCUM_NEXT_m4_1_0[19]_net_1 , 
        \ACCUM_NEXT_1_sx[19]_net_1 , \ACCUM_NEXT_1[19]_net_1 , 
        \ACCUM_NEXT_m0[20]_net_1 , \ACCUM_NEXT_m4_1_0[20]_net_1 , 
        \ACCUM_NEXT_1_sx[20]_net_1 , \ACCUM_NEXT_1[20]_net_1 , 
        \ACCUM_NEXT_m0[21]_net_1 , \ACCUM_NEXT_1_sx[21]_net_1 , 
        \ACCUM_NEXT_1[21]_net_1 , \ACCUM_NEXT_m0[24]_net_1 , 
        \ACCUM_NEXT_1_sx[24]_net_1 , \ACCUM_NEXT_1[24]_net_1 , 
        \ACCUM_NEXT_m0[25]_net_1 , \ACCUM_NEXT_1_sx[25]_net_1 , 
        \ACCUM_NEXT_1[25]_net_1 , \ACCUM_NEXT_m0[30]_net_1 , 
        \ACCUM_NEXT_1_sx[30]_net_1 , \ACCUM_NEXT_1[30]_net_1 , 
        \ACCUM_NEXT_m0[29]_net_1 , \ACCUM_NEXT_1_sx[29]_net_1 , 
        \ACCUM_NEXT_1[29]_net_1 , \ACCUM_NEXT_m0[28]_net_1 , 
        \ACCUM_NEXT_1_sx[28]_net_1 , \ACCUM_NEXT_1[28]_net_1 , 
        \ACCUM_NEXT_m0[26]_net_1 , \ACCUM_NEXT_1_sx[26]_net_1 , 
        \ACCUM_NEXT_1[26]_net_1 , N_7102_reto, \INSTR_CMD[2] , 
        \INSTR_CMD[0] , \ACCUM_NEXT_1[1]_net_1 , 
        \ACCUM_NEXT_m5_4_1_0[1] , \ACCUM_NEXT_m6[1] , 
        \ACCUM_NEXT_1[2]_net_1 , \ACCUM_NEXT_m5_4_1_0[2] , 
        \ACCUM_NEXT_m6[2]_net_1 , \ACCUM_NEXT_1[3]_net_1 , 
        \ACCUM_NEXT_m5_4_1_0[3] , \ACCUM_NEXT_m6[3]_net_1 , 
        \ACCUM_NEXT_1[4]_net_1 , \ACCUM_NEXT_m5_4_1_0[4] , 
        \ACCUM_NEXT_m6[4] , \ACCUM_NEXT_1[8]_net_1 , 
        \ACCUM_NEXT_m5_4_1_0[8] , \ACCUM_NEXT_m6[8]_net_1 , 
        \ACCUM_NEXT_1[9]_net_1 , \ACCUM_NEXT_m5_4_1_0[9] , 
        \ACCUM_NEXT_m6[9]_net_1 , \ACCUM_NEXT_1[10]_net_1 , 
        \ACCUM_NEXT_m5_4_1_0[10] , \ACCUM_NEXT_m6[10]_net_1 , 
        \ACCUM_NEXT_1[11]_net_1 , \ACCUM_NEXT_m5_4_1_0[11] , 
        \ACCUM_NEXT_m6[11]_net_1 , \ACCUM_NEXT_1[12]_net_1 , 
        \ACCUM_NEXT_m5_4_1_0[12] , \ACCUM_NEXT_m6[12]_net_1 , 
        ACCUM_NEXT_1, ACCUM_NEXT_5, ACCUM_NEXT_9, ACCUM_NEXT_13, 
        ACCUM_NEXT_25, ACCUM_NEXT_29, ACCUM_NEXT_33, ACCUM_NEXT_41, 
        ACCUM_NEXT_45, ACCUM_NEXT_57, ACCUM_NEXT_61, ACCUM_NEXT_65, 
        \ACCUM_NEXT_1[31]_net_1 , \ACCUM_NEXT_m4[31]_net_1 , 
        \RAMRDATA[8] , N_98_i_1, SMADDR_20_iv_3_212_i_m2_i_m2_2, 
        SMADDR_20_iv_2_229_i_m2_i_m2_1, 
        SMADDR_20_iv_2_229_i_m2_i_m2_2_net_1, \RAMRDATA[4] , N_799_i_1, 
        \RAMRDATA[3] , N_814_i_1, \RAMRDATA[2] , N_829_i_1, N_679_i_1, 
        N_694_i_1, \RAMRDATA[0] , \ACCUM_NEXT_m6_1_0[3]_net_1 , 
        ICYCLE22, \ACCUM_NEXT_m6_1_0[2]_net_1 , 
        \ACCUM_NEXT_m6_1_0[0]_net_1 , \ACCUM_NEXT_m6[0]_net_1 , 
        \ACCUM_NEXT_m0[18]_net_1 , \ACCUM_NEXT_m4_1_0[18]_net_1 , 
        \ACCUM_NEXT_m1[18]_net_1 , \ACCUM_NEXT_m1[19]_net_1 , 
        \ACCUM_NEXT_m0[17]_net_1 , \ACCUM_NEXT_m4_1_0[17]_net_1 , 
        \ACCUM_NEXT_m1[17]_net_1 , \ACCUM_NEXT_m0[31]_net_1 , 
        \ACCUM_NEXT_m4_1_1[31]_net_1 , \ACCUM_NEXT_m1[15]_net_1 , 
        \ACCUM_NEXT_m0[23]_net_1 , \ACCUM_NEXT_m4_1_0[23]_net_1 , 
        \ACCUM_NEXT_m1[23]_net_1 , \ACCUM_NEXT_m0[22]_net_1 , 
        \ACCUM_NEXT_m4_1_0[22]_net_1 , \ACCUM_NEXT_m1[22]_net_1 , 
        \ACCUM_NEXT_m1[16]_net_1 , \ACCUM_NEXT_m0[27]_net_1 , 
        \ACCUM_NEXT_m4_1_0[27]_net_1 , \ACCUM_NEXT_m1[27]_net_1 , 
        \ACCUM_NEXT_m1[20]_net_1 , \ACCUM_NEXT_m5_4_1_0[0] , 
        \ACCUM_NEXT_m5_4_1[0] , \ACCUM_NEXT_m5[0] , 
        \ACCUM_NEXT_m1[0]_net_1 , \ACCUM_NEXT_m0[0] , \ALUOUT_3[0] , 
        \ACCUM_NEXT_m0[1]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[1] , 
        \ACCUM_NEXT_m0[2]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[2] , 
        \ACCUM_NEXT_m0[3]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[3] , 
        \ACCUM_NEXT_m0[4]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[4] , 
        \ACCUM_NEXT_m0[5]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[5] , 
        \ACCUM_NEXT_m5_4_1_0[5] , \ACCUM_NEXT_m5[5] , 
        \ACCUM_NEXT_m0[6]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[6] , 
        \ACCUM_NEXT_m5_4_1_0[6] , \ACCUM_NEXT_m5[6] , 
        \ACCUM_NEXT_m0[7]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[7] , 
        \ACCUM_NEXT_m5_4_1_0[7] , \ACCUM_NEXT_m5[7] , 
        \ACCUM_NEXT_m0[8]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[8] , 
        \ACCUM_NEXT_m0[9]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[9] , 
        \ACCUM_NEXT_m0[10]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[10] , 
        \ACCUM_NEXT_m0[11]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[11] , 
        \ACCUM_NEXT_m0[12]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[12] , 
        \ACCUM_NEXT_m0[13]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[13] , 
        \ACCUM_NEXT_m5_4_1_0[13] , \ACCUM_NEXT_m5[13] , 
        \ACCUM_NEXT_m0[14]_net_1 , \ACCUM_NEXT_m5_4_1_0_0[14] , 
        \ACCUM_NEXT_m5_4_1_0[14] , \ACCUM_NEXT_m5[14] , 
        \ACCUM_NEXT_m6_ns_1[6]_net_1 , \ACCUM_NEXT_m6[6] , 
        \ACCUM_NEXT_m6_ns_1[5]_net_1 , \ACCUM_NEXT_m6[5] , 
        \ACCUM_NEXT_m6_ns_1[4]_net_1 , \ACCUM_NEXT_m6_ns_1[1]_net_1 , 
        \ACCUM_NEXT_m0_bm[0]_net_1 , \ACCUM_NEXT_m0_am[0]_net_1 , 
        \MSEL[1] , SHIFTMSB, N_7100_reto, STBFLAG_5_u_0_a2_0_0_net_1, 
        N_78, STBRAM_6_1, un5_flagvalue, N_7125_reto, N_7130_reto, 
        flagvalue_1, PSELI11_net_1, N_121, flagvalue, N_88, N_123_i, 
        \COREABC_0_APB3master_PADDR[16] , N_83, un1_ICYCLE_8_0_0_net_1, 
        STBACCUM_4_u_0_a2_1_net_1, N_7123_reto, N_7127_reto, 
        flagvalue_3, \ACCUM_NEXT_m3[7]_net_1 , 
        \ACCUM_NEXT_m3[8]_net_1 , \ACCUM_NEXT_m3[9]_net_1 , 
        \ACCUM_NEXT_m3[10]_net_1 , \ACCUM_NEXT_m3[11]_net_1 , 
        \ACCUM_NEXT_m3[14]_net_1 , STBACCUM_4_sqmuxa, 
        \COREABC_0_APB3master_PWDATA[30] , 
        \COREABC_0_APB3master_PWDATA[29] , 
        \COREABC_0_APB3master_PWDATA[28] , 
        \COREABC_0_APB3master_PWDATA[27] , 
        \COREABC_0_APB3master_PWDATA[26] , 
        \COREABC_0_APB3master_PWDATA[25] , 
        \COREABC_0_APB3master_PWDATA[24] , 
        \COREABC_0_APB3master_PWDATA[23] , 
        \COREABC_0_APB3master_PWDATA[22] , 
        \COREABC_0_APB3master_PWDATA[21] , 
        \COREABC_0_APB3master_PWDATA[20] , 
        \COREABC_0_APB3master_PWDATA[19] , 
        \COREABC_0_APB3master_PWDATA[18] , 
        \COREABC_0_APB3master_PWDATA[17] , 
        \COREABC_0_APB3master_PWDATA[16] , 
        \COREABC_0_APB3master_PWDATA[31] , N_104, N_117, \RAMRDATA[6] , 
        \RAMRDATA[5] , N_125, N_7129_reto, \RD_2_reto[15] , 
        \RDX_reto[15] , REN_reto_rep1, \RD_2_reto[14] , \RDX_reto[14] , 
        REN_reto_rep2, \RD_2_reto[13] , \RDX_reto[13] , 
        \RD_2_reto[12] , \RDX_reto[12] , \RD_2_reto[11] , 
        \RDX_reto[11] , \RAMRDATA[10] , \RAMRDATA[9] , 
        \RD_2_reto_0[14] , \RDY_reto[14] , \RD_2_reto_0[13] , 
        \RDY_reto[13] , \RD_2_reto_0[12] , \RDY_reto[12] , 
        \RD_2_reto_0[11] , \RDY_reto[11] , \RD_2_reto[10] , 
        \RDY_reto[10] , \RD_2_reto[9] , \RDY_reto[9] , \RD_2_reto[8] , 
        \RDY_reto[8] , \RD_2_reto[7] , \RDY_reto[7] , \RD_2_reto[6] , 
        \RDY_reto[6] , \RD_2_reto[5] , \RDY_reto[5] , \RD_2_reto[4] , 
        \RDY_reto[4] , \RD_2_reto[3] , \RDY_reto[3] , \RD_2_reto[2] , 
        \RDY_reto[2] , \RD_2_reto[1] , \RDY_reto[1] , \RD_2_reto[0] , 
        \RDY_reto[0] , \RD_2_reto_0[15] , \RDY_reto[15] , N_7128_reto, 
        N_7126_reto, \RAMWDATA[15]_net_1 , \RAMWDATA[13]_net_1 , 
        \RAMWDATA[12]_net_1 , \RAMWDATA[11]_net_1 , 
        \RAMWDATA[14]_net_1 , \RAMADDR[7]_net_1 , 
        \ACCUM_NEXT_m6[14]_net_1 , \ACCUM_NEXT_m6[13]_net_1 , 
        \ACCUM_NEXT_m6[7]_net_1 , \RAMWDATA[16]_net_1 , 
        \RAMWDATA[25]_net_1 , \RAMWDATA[29]_net_1 , 
        \RAMWDATA[24]_net_1 , \RAMWDATA[22]_net_1 , 
        \RAMWDATA[23]_net_1 , \RAMWDATA[21]_net_1 , 
        \RAMWDATA[20]_net_1 , \RAMWDATA[19]_net_1 , 
        \RAMWDATA[18]_net_1 , \RAMWDATA[17]_net_1 , 
        \RAMWDATA[31]_net_1 , \RAMRDATA[7] , \RAMWDATA[28]_net_1 , 
        \RAMWDATA[30]_net_1 , \RAMWDATA[27]_net_1 , 
        \RAMWDATA[26]_net_1 , N_910, \RAMWDATA[10]_net_1 , 
        \RAMADDR[1]_net_1 , \RAMADDR[2]_net_1 , \RAMADDR[3]_net_1 , 
        \RAMADDR[4]_net_1 , \RAMADDR[5]_net_1 , \RAMADDR[6]_net_1 , 
        \RAMWDATA[8]_net_1 , \RAMWDATA[9]_net_1 , \RAMADDR[0]_net_1 , 
        \RAMWDATA[5]_net_1 , \RAMWDATA[0]_net_1 , \RAMWDATA[7]_net_1 , 
        \RAMWDATA[2]_net_1 , \RAMWDATA[3]_net_1 , \RAMWDATA[1]_net_1 , 
        \RAMWDATA[6]_net_1 , \RAMWDATA[4]_net_1 , \tmp_4_12[0] , 
        \tmp_4_16[0] , \tmp_4_23[0] , \tmp_4_27[0] , \tmp_4_21[0] , 
        \tmp_4_20[0] , \tmp_4_19[0] , \tmp_4_18[0] , \tmp_4_17[0] , 
        \tmp_4_28[0] ;
    
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_4 (.A(VCC_net_1), .B(
        \SMADDR_i[4] ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_3_net_1), .S(un1_SMADDR_cry_4_S), .Y(), .FCO(
        un1_SMADDR_cry_4_net_1));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[21]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[22]_net_1 ), .Y(ACCUM_NEXT_57));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[11]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[11] ), .C(\ACCUM_NEXT_m6[11]_net_1 ), .Y(
        \ACCUM_NEXT_1[11]_net_1 ));
    SLE STBACCUM (.D(STBACCUM_4), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(STBACCUM_net_1)
        );
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[2]  (.A(N_7125_reto), .B(
        \ACCUMULATOR[2]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[2]));
    CFG4 #( .INIT(16'hE444) )  \ACCUM_NEXT_m6[10]  (.A(ICYCLE22), .B(
        \ACCUM_NEXT_m3[10]_net_1 ), .C(APB_register_blk_0_PRDATA_9), 
        .D(iPRDATA_0_sqmuxa), .Y(\ACCUM_NEXT_m6[10]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[29]  (.A(\RD_2_reto_0[13] ), 
        .B(N_915), .C(\RDY_reto[13] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[29]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[7]  (.A(un1_STKPTRP1_s_7_S), .B(
        N_910), .C(un1_STKPTR_s_7_S), .Y(\STKPTR_12[7]_net_1 ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[22]  (.A(
        \ACCUM_IN[22]_net_1 ), .B(\ACCUMULATOR[22]_net_1 ), .C(
        \ACCUM_NEXT_m1[22]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[22]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_18[0]  (.A(
        \ACCUM_NEXT[30]_net_1 ), .B(\ACCUM_NEXT[20]_net_1 ), .C(
        \ACCUM_NEXT[25]_net_1 ), .D(\ACCUM_NEXT[21]_net_1 ), .Y(
        \tmp_4_18[0] ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[16]  (.A(
        \ACCUM_IN[16]_net_1 ), .B(\ACCUMULATOR[15]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[16]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[28]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[28]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[28]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[19]  (.A(\RD_2_reto[3] ), .B(
        N_915), .C(\RDY_reto[3] ), .D(REN_reto_rep1), .Y(
        \ACCUM_IN[19]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[25]  (.A(ACCUM_NEXT_9), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[25]_net_1 ), .D(
        \ACCUM_IN_RNIF05711_S[25] ), .Y(\ACCUM_NEXT[25]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[31]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[31] ), .Y(\RAMWDATA[31]_net_1 ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[15]  (.A(
        \ACCUM_IN[15]_net_1 ), .B(\ACCUMULATOR[15]_net_1 ), .C(
        \ACCUM_NEXT_m1[15]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[15]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[3]  (.A(un1_STKPTRP1_cry_3_S), 
        .B(N_910), .C(un1_STKPTR_cry_3_S), .Y(\STKPTR_12[3]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[24]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[24]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[24]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[7]  (.A(N_130), .B(
        un1_SMADDR_cry_7_S), .C(COREABC_0_APB3master_PWDATA[7]), .Y(
        \RAMWDATA[7]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_RNO_1[6]  (.A(
        \ACCUM_IN[6]_net_1 ), .B(\ACCUMULATOR[6]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[6] ));
    CFG4 #( .INIT(16'h44FE) )  \ACCUM_NEXT_m4[27]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[27]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_0[27]_net_1 ), .Y(\ACCUM_NEXT_m4[27]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_RNO_1[14]  (.A(
        \ACCUM_IN[14]_net_1 ), .B(\ACCUMULATOR[14]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[14] ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[15]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[15]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[15]_net_1 ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[16]  (.A(
        \ACCUM_IN[16]_net_1 ), .B(\ACCUMULATOR[16]_net_1 ), .C(
        \ACCUM_NEXT_m1[16]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[16]_net_1 ));
    CFG3 #( .INIT(8'hD5) )  \ACCUM_NEXT[17]  (.A(
        \ACCUM_NEXT_1_0[17]_net_1 ), .B(\ACCUMULATOR[18]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .Y(\ACCUM_NEXT[17]_net_1 ));
    SLE \ACCUMULATOR[11]  (.D(\ACCUM_NEXT[11]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[11]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[27]  (.A(N_83), .B(
        \ACCUMULATOR[27]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[27] )
        );
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_23[0]  (.A(
        \ACCUM_NEXT[4]_net_1 ), .B(\ACCUM_NEXT[3]_net_1 ), .C(
        \ACCUM_NEXT[2]_net_1 ), .D(\ACCUM_NEXT[1]_net_1 ), .Y(
        \tmp_4_23[0] ));
    CFG3 #( .INIT(8'h27) )  \SMADDR_RNO_0[3]  (.A(DOJMP_net_1), .B(
        N_7110_reto), .C(un1_SMADDR_cry_3_S), .Y(N_814_i_1));
    CFG3 #( .INIT(8'hD1) )  \ACCUM_NEXT_RNO[13]  (.A(
        \ACCUM_NEXT_m5_4_1_0[13] ), .B(\doins_0_dreg_RNIJ2TF[3] ), .C(
        \ACCUM_IN_RNIVT6IK_S[13] ), .Y(\ACCUM_NEXT_m5[13] ));
    SLE \ACCUMULATOR[20]  (.D(\ACCUM_NEXT[20]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[20]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_RNO_0[6]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[6]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[6] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[6] ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIMMPU2[2]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[2]_net_1 ), .C(\ACCUMULATOR[2]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_1), .S(
        \ACCUM_IN_RNIMMPU2_S[2] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_2));
    SLE \ACCUMULATOR[7]  (.D(\ACCUM_NEXT[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[7]_net_1 ));
    CFG4 #( .INIT(16'h6800) )  STBFLAG_5_u_0_a2 (.A(N_7102_reto), .B(
        N_7100_reto), .C(N_7101_reto), .D(STBACCUM_4_sqmuxa), .Y(N_117)
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[25]  (.A(
        \ACCUM_IN[25]_net_1 ), .B(\ACCUMULATOR[24]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[25]_net_1 ));
    CFG4 #( .INIT(16'hF10B) )  \ACCUM_NEXT_1_RNO[11]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[11]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\ACCUM_NEXT_m5_4_1_0_0[11] ), .Y(
        \ACCUM_NEXT_m5_4_1_0[11] ));
    SLE \SMADDR[9]  (.D(N_100), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR[9]_net_1 ));
    CFG4 #( .INIT(16'hB888) )  \RAMWDATA[10]  (.A(un1_SMADDR_s_10_S), 
        .B(N_130), .C(\ACCUMULATOR[10]_net_1 ), .D(N_83), .Y(
        \RAMWDATA[10]_net_1 ));
    CFG4 #( .INIT(16'hF10B) )  \ACCUM_NEXT_RNO_0[13]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[13]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\ACCUM_NEXT_m5_4_1_0_0[13] ), .Y(
        \ACCUM_NEXT_m5_4_1_0[13] ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[10]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[10]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[10] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[10] ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[31]  (.A(ALUOUT_6_sqmuxa), 
        .B(SHIFTMSB), .Y(ACCUM_NEXT_65));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[27]  (.A(
        \ACCUM_IN[27]_net_1 ), .B(\ACCUMULATOR[27]_net_1 ), .C(
        \ACCUM_NEXT_m1[27]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[27]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[19]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[19]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[19]_net_1 ));
    CFG2 #( .INIT(4'h2) )  \ACCUM_NEXT_1[31]  (.A(
        \ACCUM_NEXT_m4[31]_net_1 ), .B(ACCUM_NEXT_sm5), .Y(
        \ACCUM_NEXT_1[31]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[26]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[26] ), .Y(\RAMWDATA[26]_net_1 ));
    CFG4 #( .INIT(16'hA9AA) )  \ACCUMULATOR_RNILVKE2[9]  (.A(
        \ACCUMULATOR[9]_net_1 ), .B(RAM_RAM_0_2_RNIBCJE1_0), .C(N_915), 
        .D(\MSEL[2] ), .Y(ACCUM_NEXT_m5_0_axb_9));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[29]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[29] ), .Y(\RAMWDATA[29]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[22]  (.A(\RD_2_reto[6] ), .B(
        N_915), .C(\RDY_reto[6] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[22]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_s_7 (.A(VCC_net_1), .B(
        \STKPTR[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_6_net_1), .S(un1_STKPTRP1_s_7_S), .Y(), .FCO()
        );
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[3]  (.A(N_7126_reto), .B(
        \ACCUMULATOR[3]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[3]));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[13]  (.A(
        \ACCUM_IN[13]_net_1 ), .B(\ACCUMULATOR[12]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[13]_net_1 ));
    CFG2 #( .INIT(4'hB) )  \to_logic_9_i_o2[0]  (.A(
        \to_logic_9_i_o2_sx[0]_net_1 ), .B(\INSTR_CMD[1] ), .Y(N_915));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[2]  (.A(\ACCUM_IN[2]_net_1 )
        , .B(\ACCUMULATOR[1]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[2]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[30]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[30]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[30]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIF05711[25]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[25]_net_1 ), .C(\ACCUMULATOR[25]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_24), .S(
        \ACCUM_IN_RNIF05711_S[25] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_25)
        );
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[21]  (.A(ACCUM_NEXT_57), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[21]_net_1 ), .D(
        \ACCUM_IN_RNI3L10U_S[21] ), .Y(\ACCUM_NEXT[21]_net_1 ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[3]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[3]_net_1 ), .D(
        \ACCUM_IN_RNIC2DU3_S[3] ), .Y(\ACCUM_NEXT[3]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIL9PEQ[18]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[18]_net_1 ), .C(\ACCUMULATOR[18]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_17), .S(
        \ACCUM_IN_RNIL9PEQ_S[18] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_18));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[12]  (.A(\RD_2_reto[12] ), .B(
        N_915), .C(\RDX_reto[12] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[12]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \SMADDR_RNO_0[1]  (.A(DOJMP_net_1), .B(
        un1_SMADDR_cry_1_S), .C(N_7108_reto), .Y(N_679_i_1));
    CFG4 #( .INIT(16'hB888) )  \RAMWDATA[9]  (.A(un1_SMADDR_cry_9_S), 
        .B(N_130), .C(\ACCUMULATOR[9]_net_1 ), .D(N_83), .Y(
        \RAMWDATA[9]_net_1 ));
    CFG4 #( .INIT(16'hE444) )  \ACCUM_NEXT_m6[8]  (.A(ICYCLE22), .B(
        \ACCUM_NEXT_m3[8]_net_1 ), .C(APB_register_blk_0_PRDATA_7), .D(
        iPRDATA_0_sqmuxa), .Y(\ACCUM_NEXT_m6[8]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[8]  (.A(
        \ACCUM_IN[8]_net_1 ), .B(\ACCUMULATOR[8]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[8] ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[4]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[4]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[4] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[4] ));
    CFG3 #( .INIT(8'h27) )  \SMADDR_RNO_0[2]  (.A(DOJMP_net_1), .B(
        N_7109_reto), .C(un1_SMADDR_cry_2_S), .Y(N_829_i_1));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[5]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[5] ), .C(\ACCUM_NEXT_m6[5] ), .Y(
        \ACCUM_NEXT[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[19]  (.A(N_83), .B(
        \ACCUMULATOR[19]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[19] )
        );
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[20]  (.A(
        \ACCUMULATOR[20]_net_1 ), .B(\ACCUM_IN[20]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[20]_net_1 ));
    SLE \STKPTR[6]  (.D(\STKPTR_12[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[6]_net_1 ));
    CFG4 #( .INIT(16'h5CCC) )  \SMADDR_RNO[3]  (.A(\RAMRDATA[3] ), .B(
        N_814_i_1), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(N_814_i));
    SLE \STKPTR[5]  (.D(\STKPTR_12[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[5]_net_1 ));
    CFG4 #( .INIT(16'hF8F0) )  ACCUMULATOR4 (.A(N_7100_reto), .B(
        N_7101_reto), .C(STBACCUM_net_1), .D(
        COREABC_0_APB3master_PENABLE), .Y(ACCUMULATOR4_net_1));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[11]  (.A(
        \ACCUM_IN[11]_net_1 ), .B(\ACCUMULATOR[10]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[11]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[8]  (.A(ALUOUT_6_sqmuxa), .B(
        \ACCUMULATOR[9]_net_1 ), .Y(\ACCUM_NEXT_m3[8]_net_1 ));
    CFG4 #( .INIT(16'h002F) )  \ACCUM_NEXT_1[20]  (.A(
        \ACCUM_NEXT_m0[20]_net_1 ), .B(ACCUM_NEXT_sm0), .C(
        \ACCUM_NEXT_m4_1_0[20]_net_1 ), .D(\ACCUM_NEXT_1_sx[20]_net_1 )
        , .Y(\ACCUM_NEXT_1[20]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIUVJT5[5]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[5]_net_1 ), .C(\ACCUMULATOR[5]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_4), .S(
        \ACCUM_IN_RNIUVJT5_S[5] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_5));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_0 (.A(VCC_net_1), .B(
        \SMADDR_i[0] ), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), 
        .S(), .Y(), .FCO(un1_SMADDR_cry_0_net_1));
    CFG4 #( .INIT(16'hFF08) )  STBFLAG_5_u_0 (.A(STBRAM_6_1), .B(
        STBFLAG_5_u_0_a2_0_0_net_1), .C(STBACCUM_4_sqmuxa), .D(N_117), 
        .Y(STBFLAG_5));
    CFG4 #( .INIT(16'hD850) )  SMADDR_20_iv_7_144_i_m2_i_m2 (.A(
        DOJMP_net_1), .B(\INSTR_CMD[1] ), .C(un1_SMADDR_s_10_S), .D(
        \RAMRDATA[10] ), .Y(N_102));
    CFG4 #( .INIT(16'h44FE) )  \ACCUM_NEXT_m4[23]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[23]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_0[23]_net_1 ), .Y(\ACCUM_NEXT_m4[23]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_21[0]  (.A(
        \ACCUM_NEXT[14]_net_1 ), .B(\ACCUM_NEXT[13]_net_1 ), .C(
        \ACCUM_NEXT[31]_net_1 ), .D(\ACCUM_NEXT[22]_net_1 ), .Y(
        \tmp_4_21[0] ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[8]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[8]_net_1 ), .D(
        \ACCUM_IN_RNI3J5VA_S[7] ), .Y(\ACCUM_NEXT[8]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIRC9U31[29]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[29]_net_1 ), .C(\ACCUMULATOR[29]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_28), .S(
        \ACCUM_IN_RNIRC9U31_S[29] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_29)
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[9]  (.A(\ACCUM_IN[9]_net_1 )
        , .B(\ACCUMULATOR[8]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[9]_net_1 ));
    CFG3 #( .INIT(8'h10) )  ICYCLE_1_sqmuxa_0_a3_0_a2 (.A(
        \ICYCLE[0]_net_1 ), .B(PSELI11_net_1), .C(\ICYCLE[1]_net_1 ), 
        .Y(ICYCLE_1_sqmuxa));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[9]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[9]_net_1 ), .D(
        \ACCUM_IN_RNII4G1E_S[9] ), .Y(\ACCUM_NEXT[9]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[24]  (.A(
        \ACCUM_IN[24]_net_1 ), .B(\ACCUMULATOR[23]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[24]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNI4G0U4[4]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[4]_net_1 ), .C(\ACCUMULATOR[4]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_3), .S(
        \ACCUM_IN_RNI4G0U4_S[4] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_4));
    SLE \SMADDR[5]  (.D(N_92_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        SMADDR_i_4));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_m4_1_1[31]  (.A(
        \ACCUM_IN[31]_net_1 ), .B(\ACCUMULATOR[31]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_1[31]_net_1 ));
    SLE \ACCUMULATOR[2]  (.D(\ACCUM_NEXT[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[2]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_17[0]  (.A(
        \ACCUM_NEXT[26]_net_1 ), .B(\ACCUM_NEXT[16]_net_1 ), .C(
        \ACCUM_NEXT[15]_net_1 ), .D(\ACCUM_NEXT[8]_net_1 ), .Y(
        \tmp_4_17[0] ));
    CFG3 #( .INIT(8'h80) )  SMADDR_20_iv_3_212_i_m2_i_m2_3 (.A(
        \RAMRDATA[6] ), .B(DOJMP_net_1), .C(\INSTR_CMD[1] ), .Y(
        SMADDR_20_iv_3_212_i_m2_i_m2_2));
    CFG4 #( .INIT(16'hB888) )  \RAMWDATA[8]  (.A(un1_SMADDR_cry_8_S), 
        .B(N_130), .C(\ACCUMULATOR[8]_net_1 ), .D(N_83), .Y(
        \RAMWDATA[8]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[20]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[20] ), .Y(\RAMWDATA[20]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[18]  (.A(N_83), .B(
        \ACCUMULATOR[18]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[18] )
        );
    CFG4 #( .INIT(16'h23EF) )  \ACCUM_NEXT_1_0[22]  (.A(ACCUM_NEXT_sm5)
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_m4[22]_net_1 ), 
        .D(\ACCUM_IN_RNIRCQ5V_S[22] ), .Y(\ACCUM_NEXT_1[22] ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[24]  (.A(ACCUM_NEXT_33), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[24]_net_1 ), .D(
        \ACCUM_IN_RNIH2CH01_S[24] ), .Y(\ACCUM_NEXT[24]_net_1 ));
    CFG4 #( .INIT(16'hB3B1) )  \ACCUM_NEXT_m6[3]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUM_NEXT_m6_1_0[3]_net_1 ), .C(\ACCUMULATOR[4]_net_1 ), 
        .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[3]_net_1 ));
    CFG2 #( .INIT(4'h7) )  un1_PWRITE_M_i_0 (.A(N_7101_reto), .B(
        N_7100_reto), .Y(COREABC_0_APB3master_PWRITE));
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[7]  (.A(N_7130_reto), .B(
        \ACCUMULATOR[7]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[7]));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[9]  (.A(ALUOUT_6_sqmuxa), .B(
        \ACCUMULATOR[10]_net_1 ), .Y(\ACCUM_NEXT_m3[9]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[3]  (.A(N_915), .B(N_7126_reto), 
        .C(\RAMRDATA[3] ), .Y(\ACCUM_IN[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[22]  (.A(N_83), .B(
        \ACCUMULATOR[22]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[22] )
        );
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[29]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[29]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[29]_net_1 ), .D(\ACCUM_NEXT_1_sx[29]_net_1 )
        , .Y(\ACCUM_NEXT_1[29]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[18]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[18] ), .Y(\RAMWDATA[18]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[16]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[17]_net_1 ), .Y(ACCUM_NEXT_29));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[10]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[10] ), .C(\ACCUM_NEXT_m6[10]_net_1 ), .Y(
        \ACCUM_NEXT_1[10]_net_1 ));
    SLE \ACCUMULATOR[23]  (.D(\ACCUM_NEXT[23]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[23]_net_1 ));
    CFG3 #( .INIT(8'hD5) )  \ACCUM_NEXT[18]  (.A(
        \ACCUM_NEXT_1_0[18]_net_1 ), .B(\ACCUMULATOR[19]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .Y(\ACCUM_NEXT[18]_net_1 ));
    GND GND (.Y(GND_net_1));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIH2CH01[24]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[24]_net_1 ), .C(\ACCUMULATOR[24]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_23), .S(
        \ACCUM_IN_RNIH2CH01_S[24] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_24)
        );
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_6 (.A(\STKPTR[6]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_5_net_1), .S(un1_STKPTR_cry_6_S), .Y(), .FCO(
        un1_STKPTR_cry_6_net_1));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIJBB3O[16]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[16]_net_1 ), .C(\ACCUMULATOR[16]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_15), .S(
        \ACCUM_IN_RNIJBB3O_S[16] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_16));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[20]  (.A(ACCUM_NEXT_25), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[20]_net_1 ), .D(
        \ACCUM_IN_RNIDV8QS_S[20] ), .Y(\ACCUM_NEXT[20]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[23]  (.A(N_83), .B(
        \ACCUMULATOR[23]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[23] )
        );
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[4]  (.A(N_130), .B(
        un1_SMADDR_cry_4_S), .C(COREABC_0_APB3master_PWDATA[4]), .Y(
        \RAMWDATA[4]_net_1 ));
    CFG4 #( .INIT(16'h23EF) )  \ACCUM_NEXT_1_0[23]  (.A(ACCUM_NEXT_sm5)
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_m4[23]_net_1 ), 
        .D(\ACCUM_IN_RNIL6JRV_S[23] ), .Y(\ACCUM_NEXT_1[23] ));
    CFG3 #( .INIT(8'h08) )  \RAMWDATA[12]  (.A(\ACCUMULATOR[12]_net_1 )
        , .B(N_83), .C(N_130), .Y(\RAMWDATA[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[7]  (.A(ALUOUT_6_sqmuxa), .B(
        \ACCUMULATOR[8]_net_1 ), .Y(\ACCUM_NEXT_m3[7]_net_1 ));
    SLE \STKPTR[2]  (.D(\STKPTR_12[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[2]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[8]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[8] ), .C(\ACCUM_NEXT_m6[8]_net_1 ), .Y(
        \ACCUM_NEXT_1[8]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[0]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[0] ), .C(\ACCUM_NEXT_m6[0]_net_1 ), .Y(
        \ACCUM_NEXT[0]_net_1 ));
    CFG4 #( .INIT(16'hF10B) )  \ACCUM_NEXT_RNO_0[14]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[14]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\ACCUM_NEXT_m5_4_1_0_0[14] ), .Y(
        \ACCUM_NEXT_m5_4_1_0[14] ));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_4 (.A(\STKPTR[4]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_3_net_1), .S(un1_STKPTR_cry_4_S), .Y(), .FCO(
        un1_STKPTR_cry_4_net_1));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[29]  (.A(ACCUM_NEXT_45), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[29]_net_1 ), .D(
        \ACCUM_IN_RNIRC9U31_S[29] ), .Y(\ACCUM_NEXT[29]_net_1 ));
    CFG4 #( .INIT(16'h002F) )  \ACCUM_NEXT_1[19]  (.A(
        \ACCUM_NEXT_m0[19]_net_1 ), .B(ACCUM_NEXT_sm0), .C(
        \ACCUM_NEXT_m4_1_0[19]_net_1 ), .D(\ACCUM_NEXT_1_sx[19]_net_1 )
        , .Y(\ACCUM_NEXT_1[19]_net_1 ));
    SLE \ACCUMULATOR[10]  (.D(\ACCUM_NEXT[10]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[10]_net_1 ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[17]  (.A(
        \ACCUM_IN[17]_net_1 ), .B(\ACCUMULATOR[17]_net_1 ), .C(
        \ACCUM_NEXT_m1[17]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[17]_net_1 ));
    CFG3 #( .INIT(8'hD5) )  \ACCUM_NEXT[23]  (.A(\ACCUM_NEXT_1[23] ), 
        .B(\ACCUMULATOR[24]_net_1 ), .C(ALUOUT_6_sqmuxa), .Y(
        \ACCUM_NEXT[23]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIL6G831[28]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[28]_net_1 ), .C(\ACCUMULATOR[28]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_27), .S(
        \ACCUM_IN_RNIL6G831_S[28] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_28)
        );
    ARI1 #( .INIT(20'h544BB) )  \ACCUM_IN_RNIG5JV[0]  (.A(
        \ACCUMULATOR[0]_net_1 ), .B(\ACCUM_IN[0]_net_1 ), .C(\MSEL[2] )
        , .D(GND_net_1), .FCI(GND_net_1), .S(), .Y(
        \ACCUM_IN_RNIG5JV_Y[0] ), .FCO(ACCUM_NEXT_m5_0_cry_0));
    CFG4 #( .INIT(16'hEA40) )  \ACCUM_NEXT_m6[13]  (.A(ICYCLE22), .B(
        ALUOUT_6_sqmuxa), .C(\ACCUMULATOR[14]_net_1 ), .D(N_180), .Y(
        \ACCUM_NEXT_m6[13]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[26]  (.A(ACCUM_NEXT_1), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[26]_net_1 ), .D(
        \ACCUM_IN_RNIF0US11_S[26] ), .Y(\ACCUM_NEXT[26]_net_1 ));
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[30]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[30]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[30]_net_1 ), .D(\ACCUM_NEXT_1_sx[30]_net_1 )
        , .Y(\ACCUM_NEXT_1[30]_net_1 ));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[27]  (.A(
        \ACCUMULATOR[27]_net_1 ), .B(\ACCUM_IN[27]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[27]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[4]  (.A(un1_STKPTRP1_cry_4_S), .B(
        N_104), .C(N_7111_reto), .Y(\RAMADDR[4]_net_1 ));
    UART_top_COREABC_0_INSTRUCTIONS_Z10 \UROM.UROM  (.INSTR_CMD({
        \INSTR_CMD[2] , \INSTR_CMD[1] , \INSTR_CMD[0] }), .SMADDR({
        \SMADDR[10]_net_1 , \SMADDR[9]_net_1 }), .SMADDR_i({
        \SMADDR_i[8] , \SMADDR_i[7] , \SMADDR_i[6] , SMADDR_i_4, 
        \SMADDR_i[4] , \SMADDR_i[3] , SMADDR_i_1, SMADDR_i_0, 
        \SMADDR_i[0] }), .COREABC_0_APB3master_PADDR_0(
        \COREABC_0_APB3master_PADDR[16] ), .doins_0_dreg_RNIJ2TF_0(
        \doins_0_dreg_RNIJ2TF[3] ), .COREABC_0_APB3master_PADDR_i_0(
        COREABC_0_APB3master_PADDR_i_0), .un1_ICYCLE_6_i(
        un1_ICYCLE_6_i), .DOJMP(DOJMP_net_1), .N_123_i(N_123_i), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .CoreAPB3_0_APBmslave1_PSELx(CoreAPB3_0_APBmslave1_PSELx), 
        .m3_1(m3_1), .doins_adflt(doins_adflt), .doins_adflt_reto(
        doins_adflt_reto), .doins_adflt_i_reto(doins_adflt_i_reto), 
        .doins_adflt_i(doins_adflt_i), .m10(m10), .G_622(G_622), 
        .N_7108_reto(N_7108_reto), .N_7107_reto(N_7107_reto), 
        .N_7102_reto(N_7102_reto), .N_7101_reto(N_7101_reto), 
        .N_7100_reto(N_7100_reto), .N_7123_reto(N_7123_reto), 
        .N_7119_reto(N_7119_reto), .N_7115_reto(N_7115_reto), 
        .N_7112_reto(N_7112_reto), .N_7111_reto(N_7111_reto), 
        .N_7110_reto(N_7110_reto), .N_7109_reto(N_7109_reto), 
        .N_7130_reto(N_7130_reto), .N_7129_reto(N_7129_reto), 
        .N_7128_reto(N_7128_reto), .N_7127_reto(N_7127_reto), 
        .N_7126_reto(N_7126_reto), .N_7125_reto(N_7125_reto), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .N_7124_reto(N_7124_reto));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIH2NI21[27]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[27]_net_1 ), .C(\ACCUMULATOR[27]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_26), .S(
        \ACCUM_IN_RNIH2NI21_S[27] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_27)
        );
    CFG3 #( .INIT(8'hD1) )  \ACCUM_NEXT_RNO[6]  (.A(
        \ACCUM_NEXT_m5_4_1_0[6] ), .B(\doins_0_dreg_RNIJ2TF[3] ), .C(
        \ACCUM_IN_RNIQH7T6_S[6] ), .Y(\ACCUM_NEXT_m5[6] ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[17]  (.A(N_83), .B(
        \ACCUMULATOR[17]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[17] )
        );
    SLE PENABLEI (.D(ICYCLE_1_sqmuxa), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREABC_0_APB3master_PENABLE));
    CFG3 #( .INIT(8'h04) )  \ICYCLE_ns_1_0_.m5_i_a2_0  (.A(N_78), .B(
        \ICYCLE[0]_net_1 ), .C(\INSTR_CMD[0] ), .Y(N_121));
    CFG3 #( .INIT(8'h3B) )  ACCUM_NEXT_m2s2 (.A(N_915), .B(\MSEL[2] ), 
        .C(N_7100_reto), .Y(ACCUM_NEXT_sm0));
    CFG2 #( .INIT(4'h4) )  \xhdl_31.ALUOUT_4_0_m2[10]  (.A(N_915), .B(
        \RAMRDATA[10] ), .Y(N_81));
    SLE \ACCUMULATOR[25]  (.D(\ACCUM_NEXT[25]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[25]_net_1 ));
    CFG2 #( .INIT(4'h1) )  STBFLAG_5_u_0_a2_0_0 (.A(\INSTR_CMD[1] ), 
        .B(\INSTR_CMD[2] ), .Y(STBFLAG_5_u_0_a2_0_0_net_1));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[15]  (.A(
        \ACCUMULATOR[15]_net_1 ), .B(\ACCUM_IN[15]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[15]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \SMADDR_RNO_0[8]  (.A(DOJMP_net_1), .B(
        un1_SMADDR_cry_8_S), .C(N_7115_reto), .Y(N_98_i_1));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[31]  (.A(N_83), .B(
        \ACCUMULATOR[31]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[31] )
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[5]  (.A(\ACCUM_IN[5]_net_1 )
        , .B(\ACCUMULATOR[4]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[5]_net_1 ));
    CFG4 #( .INIT(16'hE200) )  \xhdl_31.ALUOUT_3[0]  (.A(\RAMRDATA[0] )
        , .B(N_915), .C(N_7123_reto), .D(\ACCUMULATOR[0]_net_1 ), .Y(
        \ALUOUT_3[0] ));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_7 (.A(VCC_net_1), .B(
        \SMADDR_i[7] ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_6_net_1), .S(un1_SMADDR_cry_7_S), .Y(), .FCO(
        un1_SMADDR_cry_7_net_1));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[28]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[28] ), .Y(\RAMWDATA[28]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[6]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[6] ), .C(\ACCUM_NEXT_m6[6] ), .Y(
        \ACCUM_NEXT[6]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[26]  (.A(N_83), .B(
        \ACCUMULATOR[26]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[26] )
        );
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[21]  (.A(
        \ACCUM_IN[21]_net_1 ), .B(\ACCUMULATOR[21]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[21]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[28]  (.A(\RD_2_reto_0[12] ), 
        .B(N_915), .C(\RDY_reto[12] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[28]_net_1 ));
    CFG4 #( .INIT(16'hE444) )  \ACCUM_NEXT_m6[11]  (.A(ICYCLE22), .B(
        \ACCUM_NEXT_m3[11]_net_1 ), .C(APB_register_blk_0_PRDATA_10), 
        .D(iPRDATA_0_sqmuxa), .Y(\ACCUM_NEXT_m6[11]_net_1 ));
    CFG4 #( .INIT(16'hB3B1) )  \ACCUM_NEXT_m6[0]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUM_NEXT_m6_1_0[0]_net_1 ), .C(\ACCUMULATOR[1]_net_1 ), 
        .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[0]_net_1 ));
    SLE \ACCUMULATOR[8]  (.D(\ACCUM_NEXT[8]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[8]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[12]  (.A(
        \ACCUM_IN[12]_net_1 ), .B(\ACCUMULATOR[11]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[12]_net_1 ));
    SLE \SMADDR[4]  (.D(N_799_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[4] ));
    CFG2 #( .INIT(4'hD) )  \ICYCLE_ns_1_0_.m5_i_o2_0  (.A(
        \INSTR_CMD[1] ), .B(\INSTR_CMD[2] ), .Y(N_78));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[25]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[26]_net_1 ), .Y(ACCUM_NEXT_9));
    ARI1 #( .INIT(20'h5CCAA) )  \ACCUM_IN_RNII4G1E[9]  (.A(VCC_net_1), 
        .B(\ACCUM_IN_RNIQHLJ[9]_net_1 ), .C(ACCUM_NEXT_m5_0_axb_9), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_8), .S(
        \ACCUM_IN_RNII4G1E_S[9] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_9));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_2 (.A(VCC_net_1), .B(
        \STKPTR[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_1_net_1), .S(un1_STKPTRP1_cry_2_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_2_net_1));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[18]  (.A(\RD_2_reto[2] ), .B(
        N_915), .C(\RDY_reto[2] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[18]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[6]  (.A(N_130), .B(
        un1_SMADDR_cry_6_S), .C(COREABC_0_APB3master_PWDATA[6]), .Y(
        \RAMWDATA[6]_net_1 ));
    SLE STD_ACCUM_ZERO (.D(\tmp_4[0] ), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(STBFLAG_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        STD_ACCUM_ZERO_net_1));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[1]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[1]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[1] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[1] ));
    SLE \ACCUMULATOR[26]  (.D(\ACCUM_NEXT[26]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[26]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[22]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[22] ), .Y(\RAMWDATA[22]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[30]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[30] ), .Y(\RAMWDATA[30]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[2]  (.A(
        \ACCUM_IN[2]_net_1 ), .B(\ACCUMULATOR[2]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[2] ));
    CFG4 #( .INIT(16'h0031) )  \SMADDR_RNO[5]  (.A(un1_SMADDR_cry_5_S), 
        .B(SMADDR_20_iv_2_229_i_m2_i_m2_2_net_1), .C(DOJMP_net_1), .D(
        SMADDR_20_iv_2_229_i_m2_i_m2_1), .Y(N_92_i));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[31]  (.A(\RD_2_reto_0[15] ), 
        .B(N_915), .C(\RDY_reto[15] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[31]_net_1 ));
    ARI1 #( .INIT(20'h5CCAA) )  \xhdl_31.ALUOUT_4_0_m2_RNIT231H[10]  (
        .A(VCC_net_1), .B(\ALUOUT_4_0_m2_RNIUQDI[10] ), .C(
        ACCUM_NEXT_m5_0_axb_10), .D(GND_net_1), .FCI(
        ACCUM_NEXT_m5_0_cry_9), .S(\ALUOUT_4_0_m2_RNIT231H_S[10] ), .Y(
        ), .FCO(ACCUM_NEXT_m5_0_cry_10));
    SLE STBFLAG (.D(STBFLAG_5), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(STBFLAG_net_1));
    CFG4 #( .INIT(16'h5CCC) )  \SMADDR_RNO[4]  (.A(\RAMRDATA[4] ), .B(
        N_799_i_1), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(N_799_i));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[25]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[25]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[25]_net_1 ));
    CFG4 #( .INIT(16'hFF04) )  PSELI_5_0_0 (.A(\INSTR_CMD[0] ), .B(
        STBRAM_6_1), .C(N_78), .D(ICYCLE_1_sqmuxa), .Y(PSELI_5));
    SLE \ACCUMULATOR[3]  (.D(\ACCUM_NEXT[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[3]_net_1 ));
    SLE DOJMP (.D(DOJMP_55_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(DOJMP_net_1));
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[29]  (.A(
        \ACCUM_IN[29]_net_1 ), .B(\ACCUMULATOR[29]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[29]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h35) )  \ACCUM_NEXT_m6_1_0[2]  (.A(
        CoreUARTapb_0_RXRDY), .B(PRDATA_0_iv_0_0_0_2), .C(ICYCLE22), 
        .Y(\ACCUM_NEXT_m6_1_0[2]_net_1 ));
    CFG4 #( .INIT(16'h44FE) )  \ACCUM_NEXT_m4[22]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[22]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_0[22]_net_1 ), .Y(\ACCUM_NEXT_m4[22]_net_1 ));
    CFG4 #( .INIT(16'h5CCC) )  \SMADDR_RNO[2]  (.A(\RAMRDATA[2] ), .B(
        N_829_i_1), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(N_829_i));
    CFG4 #( .INIT(16'hB3B1) )  \ACCUM_NEXT_m6[2]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUM_NEXT_m6_1_0[2]_net_1 ), .C(\ACCUMULATOR[3]_net_1 ), 
        .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[2]_net_1 ));
    SLE \SMADDR[1]  (.D(N_679_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        SMADDR_i_0));
    CFG4 #( .INIT(16'hF858) )  SHIFTMSB_iv (.A(N_7124_reto), .B(
        \ACCUMULATOR[31]_net_1 ), .C(N_7123_reto), .D(
        \ACCUMULATOR[0]_net_1 ), .Y(SHIFTMSB));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[23]  (.A(
        \ACCUMULATOR[23]_net_1 ), .B(\ACCUM_IN[23]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[23]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[29]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[29]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[29]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIPBGKR[19]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[19]_net_1 ), .C(\ACCUMULATOR[19]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_18), .S(
        \ACCUM_IN_RNIPBGKR_S[19] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_19));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[5]  (.A(un1_STKPTRP1_cry_5_S), 
        .B(N_910), .C(un1_STKPTR_cry_5_S), .Y(\STKPTR_12[5]_net_1 ));
    CFG4 #( .INIT(16'h23EF) )  \ACCUM_NEXT_1_0[18]  (.A(ACCUM_NEXT_sm5)
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_m4[18]_net_1 ), 
        .D(\ACCUM_IN_RNIL9PEQ_S[18] ), .Y(\ACCUM_NEXT_1_0[18]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \ICYCLE_RNIHSIR[0]  (.A(\ICYCLE[0]_net_1 ), 
        .B(\ICYCLE[1]_net_1 ), .Y(N_123_i));
    SLE STD_ACCUM_NEG (.D(\ACCUM_NEXT[31]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(STBFLAG_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(STD_ACCUM_NEG_net_1));
    SLE \ACCUMULATOR[13]  (.D(\ACCUM_NEXT[13]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[13]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[14]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[15]_net_1 ), .Y(\ACCUM_NEXT_m3[14]_net_1 ));
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[24]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[24]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[24]_net_1 ), .D(\ACCUM_NEXT_1_sx[24]_net_1 )
        , .Y(\ACCUM_NEXT_1[24]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_1 (.A(VCC_net_1), .B(
        \STKPTR[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_s_1_812_FCO), .S(un1_STKPTRP1_cry_1_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_1_net_1));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIH44K41[30]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[30]_net_1 ), .C(\ACCUMULATOR[30]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_29), .S(
        \ACCUM_IN_RNIH44K41_S[30] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_30)
        );
    SLE \SMADDR[7]  (.D(N_96_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[7] ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[24]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[25]_net_1 ), .Y(ACCUM_NEXT_33));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[1]  (.A(
        \ACCUM_IN[1]_net_1 ), .B(\ACCUMULATOR[1]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[1] ));
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[25]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[25]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[25]_net_1 ), .D(\ACCUM_NEXT_1_sx[25]_net_1 )
        , .Y(\ACCUM_NEXT_1[25]_net_1 ));
    CFG4 #( .INIT(16'h44FE) )  \ACCUM_NEXT_m4[18]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[18]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_0[18]_net_1 ), .Y(\ACCUM_NEXT_m4[18]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[2]  (.A(N_915), .B(N_7125_reto), 
        .C(\RAMRDATA[2] ), .Y(\ACCUM_IN[2]_net_1 ));
    SLE \SMADDR[2]  (.D(N_829_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        SMADDR_i_1));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[2]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[2]_net_1 ), .D(
        \ACCUM_IN_RNIMMPU2_S[2] ), .Y(\ACCUM_NEXT[2]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNI78GCJ[12]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[12]_net_1 ), .C(\ACCUMULATOR[12]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_11), .S(
        \ACCUM_IN_RNI78GCJ_S[12] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_12));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_IN_RNIRUE31[7]  (.A(
        \ACCUM_IN[7]_net_1 ), .B(\ACCUMULATOR[7]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[7] ));
    SLE \UROM.INSTR_DATA_ret  (.D(doins_adflt), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(doins_adflt_reto));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[28]  (.A(
        \ACCUM_IN[28]_net_1 ), .B(\ACCUMULATOR[27]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[28]_net_1 ));
    CFG3 #( .INIT(8'hF2) )  STBACCUM_4_u_0 (.A(
        STBACCUM_4_u_0_a2_1_net_1), .B(STBACCUM_4_sqmuxa), .C(N_117), 
        .Y(STBACCUM_4));
    CFG4 #( .INIT(16'h8000) )  \to_logic_2.tmp_4_28[0]  (.A(
        \tmp_4_19[0] ), .B(\tmp_4_18[0] ), .C(\tmp_4_17[0] ), .D(
        \tmp_4_16[0] ), .Y(\tmp_4_28[0] ));
    CFG4 #( .INIT(16'h0800) )  un1_STBRAM_4_sqmuxa_3_i_a2_0 (.A(
        N_7102_reto), .B(N_7100_reto), .C(N_7101_reto), .D(
        STBACCUM_4_sqmuxa), .Y(N_125));
    SLE \STKPTR[3]  (.D(\STKPTR_12[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[3]_net_1 ));
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[28]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[28]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[28]_net_1 ), .D(\ACCUM_NEXT_1_sx[28]_net_1 )
        , .Y(\ACCUM_NEXT_1[28]_net_1 ));
    CFG4 #( .INIT(16'hFEEE) )  \xhdl_41.flagvalue_3  (.A(N_7123_reto), 
        .B(flagvalue_1), .C(CoreUARTapb_0_TXRDY), .D(N_7127_reto), .Y(
        flagvalue_3));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[21]  (.A(N_83), .B(
        \ACCUMULATOR[21]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[21] )
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[15]  (.A(
        \ACCUM_IN[15]_net_1 ), .B(\ACCUMULATOR[14]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[15]_net_1 ));
    SLE STBRAM (.D(STBRAM_6), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(STBRAM_net_1));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[23]  (.A(\RD_2_reto[7] ), .B(
        N_915), .C(\RDY_reto[7] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[23]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[9]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[9] ), .C(\ACCUM_NEXT_m6[9]_net_1 ), .Y(
        \ACCUM_NEXT_1[9]_net_1 ));
    SLE \ACCUMULATOR[24]  (.D(\ACCUM_NEXT[24]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[24]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[8]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[8]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[8] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[8] ));
    CFG4 #( .INIT(16'h002F) )  \ACCUM_NEXT_1[15]  (.A(
        \ACCUM_NEXT_m0[15]_net_1 ), .B(ACCUM_NEXT_sm0), .C(
        \ACCUM_NEXT_m4_1_0[15]_net_1 ), .D(\ACCUM_NEXT_1_sx[15]_net_1 )
        , .Y(\ACCUM_NEXT_1[15]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[2]  (.A(un1_STKPTRP1_cry_2_S), 
        .B(N_910), .C(un1_STKPTR_cry_2_S), .Y(\STKPTR_12[2]_net_1 ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[12]  (.A(ACCUM_NEXT_sm5), 
        .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[12]_net_1 ), 
        .D(\ACCUM_IN_RNI78GCJ_S[12] ), .Y(\ACCUM_NEXT[12]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[13]  (.A(\RD_2_reto[13] ), .B(
        N_915), .C(\RDX_reto[13] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[13]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PWDATA_M[1]  (.A(N_83), .B(N_7124_reto), 
        .C(\ACCUMULATOR[1]_net_1 ), .Y(COREABC_0_APB3master_PWDATA[1]));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[12]  (.A(
        \ACCUM_IN[12]_net_1 ), .B(\ACCUMULATOR[12]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[12] ));
    CFG4 #( .INIT(16'hE4F0) )  \ACCUM_IN[1]  (.A(
        \to_logic_9_i_o2_sx[0]_net_1 ), .B(\RAMRDATA[1] ), .C(
        N_7124_reto), .D(\INSTR_CMD[1] ), .Y(\ACCUM_IN[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[25]  (.A(N_83), .B(
        \ACCUMULATOR[25]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[25] )
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0_ns[0]  (.A(
        \ACCUM_NEXT_m0_bm[0]_net_1 ), .B(\ACCUM_NEXT_m0_am[0]_net_1 ), 
        .C(\MSEL[1] ), .Y(\ACCUM_NEXT_m0[0] ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[29]  (.A(
        \ACCUM_IN[29]_net_1 ), .B(\ACCUMULATOR[28]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[29]_net_1 ));
    CFG4 #( .INIT(16'h7350) )  \STBRAM_6.m10_0  (.A(\INSTR_CMD[1] ), 
        .B(N_7100_reto), .C(N_126), .D(N_111_1), .Y(STBRAM_6));
    SLE \ACCUMULATOR[15]  (.D(\ACCUM_NEXT[15]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[15]_net_1 ));
    CFG3 #( .INIT(8'h08) )  \RAMWDATA[14]  (.A(\ACCUMULATOR[14]_net_1 )
        , .B(N_83), .C(N_130), .Y(\RAMWDATA[14]_net_1 ));
    CFG4 #( .INIT(16'hEA40) )  \ACCUM_NEXT_m6[12]  (.A(ICYCLE22), .B(
        ALUOUT_6_sqmuxa), .C(\ACCUMULATOR[13]_net_1 ), .D(N_180), .Y(
        \ACCUM_NEXT_m6[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_5 (.A(VCC_net_1), .B(
        \STKPTR[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_4_net_1), .S(un1_STKPTRP1_cry_5_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_5_net_1));
    CFG4 #( .INIT(16'hA3AA) )  RAMADDR_1_sqmuxa_i_m2 (.A(
        \COREABC_0_APB3master_PADDR[16] ), .B(N_7102_reto), .C(N_78), 
        .D(\INSTR_CMD[0] ), .Y(N_104));
    CFG4 #( .INIT(16'h0073) )  \ICYCLE_ns_1_0_.N_909_i  (.A(
        \ICYCLE[0]_net_1 ), .B(\ICYCLE[1]_net_1 ), .C(PSELI11_net_1), 
        .D(N_121), .Y(N_909_i));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[11]  (.A(
        \ACCUM_IN[11]_net_1 ), .B(\ACCUMULATOR[11]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[11] ));
    SLE \STKPTR[1]  (.D(\STKPTR_12[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[1]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[30]  (.A(\RD_2_reto_0[14] ), 
        .B(N_915), .C(\RDY_reto[14] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[30]_net_1 ));
    CFG2 #( .INIT(4'h6) )  \ICYCLE_ns_1_0_.m6_i_x2  (.A(
        \ICYCLE[0]_net_1 ), .B(\ICYCLE[1]_net_1 ), .Y(N_87_i));
    CFG4 #( .INIT(16'h4EF4) )  \ACCUM_NEXT_m4[31]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[31]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_1[31]_net_1 ), .Y(\ACCUM_NEXT_m4[31]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[20]  (.A(
        \ACCUM_IN[20]_net_1 ), .B(\ACCUMULATOR[19]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[20]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[24]  (.A(\RD_2_reto[8] ), .B(
        N_915), .C(\RDY_reto[8] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[24]_net_1 ));
    CFG3 #( .INIT(8'h51) )  \URAM.ii72_i_a2  (.A(
        \COREABC_0_APB3master_PADDR[16] ), .B(\INSTR_CMD[0] ), .C(N_78)
        , .Y(N_130));
    CFG4 #( .INIT(16'h0020) )  ALUOUT_6_sqmuxa_0_a2 (.A(N_7102_reto), 
        .B(N_7100_reto), .C(N_7101_reto), .D(\INSTR_CMD[1] ), .Y(
        ALUOUT_6_sqmuxa));
    CFG4 #( .INIT(16'hFEEE) )  \xhdl_41.flagvalue  (.A(un5_flagvalue), 
        .B(flagvalue_3), .C(CoreUARTapb_0_RXRDY), .D(N_7129_reto), .Y(
        flagvalue));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[1]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[1]_net_1 ), .D(
        \ACCUM_IN_RNI2D6V1_S[1] ), .Y(\ACCUM_NEXT[1]_net_1 ));
    CFG3 #( .INIT(8'h08) )  \RAMWDATA[13]  (.A(\ACCUMULATOR[13]_net_1 )
        , .B(N_83), .C(N_130), .Y(\RAMWDATA[13]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIL6JRV[23]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[23]_net_1 ), .C(\ACCUMULATOR[23]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_22), .S(
        \ACCUM_IN_RNIL6JRV_S[23] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_23));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNI3L10U[21]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[21]_net_1 ), .C(\ACCUMULATOR[21]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_20), .S(
        \ACCUM_IN_RNI3L10U_S[21] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_21));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[14]  (.A(\RD_2_reto[14] ), .B(
        N_915), .C(\RDX_reto[14] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[14]_net_1 ));
    SLE \ACCUMULATOR[16]  (.D(\ACCUM_NEXT[16]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[16]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \xhdl_31.ALUOUT_4_0_m2_RNIUQDI[10]  (.A(
        N_81), .B(\MSEL[2] ), .Y(\ALUOUT_4_0_m2_RNIUQDI[10] ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_IN[0]  (.A(N_7123_reto), .B(
        \RAMRDATA[0] ), .C(N_915), .Y(\ACCUM_IN[0]_net_1 ));
    SLE \ACCUMULATOR[5]  (.D(\ACCUM_NEXT[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[5]_net_1 ));
    SLE \UROM.INSTR_DATA_ret_1  (.D(doins_adflt_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(doins_adflt_i_reto));
    CFG4 #( .INIT(16'h1D33) )  \ACCUM_NEXT_RNO_1[0]  (.A(\ALUOUT_3[0] )
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_IN_RNIG5JV_Y[0] ), 
        .D(ALUOUT_1_sqmuxa_net_1), .Y(\ACCUM_NEXT_m5_4_1[0] ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[30]  (.A(N_83), .B(
        \ACCUMULATOR[30]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[30] )
        );
    CFG2 #( .INIT(4'h4) )  \RAMADDR[7]  (.A(N_104), .B(
        un1_STKPTRP1_s_7_S), .Y(\RAMADDR[7]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[16]  (.A(N_83), .B(
        \ACCUMULATOR[16]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[16] )
        );
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[20]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[20]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[20]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[15]  (.A(ACCUM_NEXT_61), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[15]_net_1 ), .D(
        \ACCUM_IN_RNILFKTM_S[15] ), .Y(\ACCUM_NEXT[15]_net_1 ));
    SLE \SMADDR[6]  (.D(N_94_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[6] ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[19]  (.A(
        \ACCUM_IN[19]_net_1 ), .B(\ACCUMULATOR[19]_net_1 ), .C(
        \ACCUM_NEXT_m1[19]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[19]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[14]  (.A(
        \ACCUM_IN[14]_net_1 ), .B(\ACCUMULATOR[13]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[14]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[3]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[3]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[3] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[3] ));
    ARI1 #( .INIT(20'h43C1E) )  un1_STKPTR_s_7 (.A(N_7101_reto), .B(
        N_111_1), .C(N_126), .D(\STKPTR[7]_net_1 ), .FCI(
        un1_STKPTR_cry_6_net_1), .S(un1_STKPTR_s_7_S), .Y(), .FCO());
    CFG3 #( .INIT(8'hD1) )  \ACCUM_NEXT_RNO[5]  (.A(
        \ACCUM_NEXT_m5_4_1_0[5] ), .B(\doins_0_dreg_RNIJ2TF[3] ), .C(
        \ACCUM_IN_RNIUVJT5_S[5] ), .Y(\ACCUM_NEXT_m5[5] ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[21]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[21]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[21]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIJ929P[17]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[17]_net_1 ), .C(\ACCUMULATOR[17]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_16), .S(
        \ACCUM_IN_RNIJ929P_S[17] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_17));
    CFG3 #( .INIT(8'h08) )  \RAMWDATA[15]  (.A(\ACCUMULATOR[15]_net_1 )
        , .B(N_83), .C(N_130), .Y(\RAMWDATA[15]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[1]  (.A(N_130), .B(
        un1_SMADDR_cry_1_S), .C(COREABC_0_APB3master_PWDATA[1]), .Y(
        \RAMWDATA[1]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[2]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[2] ), .C(\ACCUM_NEXT_m6[2]_net_1 ), .Y(
        \ACCUM_NEXT_1[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_IN_RNIQHLJ[9]  (.A(
        \ACCUM_IN[9]_net_1 ), .B(\MSEL[2] ), .Y(
        \ACCUM_IN_RNIQHLJ[9]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[5]  (.A(N_915), .B(N_7128_reto), 
        .C(\RAMRDATA[5] ), .Y(\ACCUM_IN[5]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[12]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[12] ), .C(\ACCUM_NEXT_m6[12]_net_1 ), .Y(
        \ACCUM_NEXT_1[12]_net_1 ));
    CFG4 #( .INIT(16'hE444) )  \ACCUM_NEXT_m6[9]  (.A(ICYCLE22), .B(
        \ACCUM_NEXT_m3[9]_net_1 ), .C(APB_register_blk_0_PRDATA_8), .D(
        iPRDATA_0_sqmuxa), .Y(\ACCUM_NEXT_m6[9]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[9]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[9]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[9] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[9] ));
    SLE \ACCUMULATOR[31]  (.D(\ACCUM_NEXT[31]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[31]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[5]  (.A(un1_STKPTRP1_cry_5_S), .B(
        N_104), .C(N_7112_reto), .Y(\RAMADDR[5]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_5 (.A(VCC_net_1), .B(
        SMADDR_i_4), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_4_net_1), .S(un1_SMADDR_cry_5_S), .Y(), .FCO(
        un1_SMADDR_cry_5_net_1));
    CFG3 #( .INIT(8'h35) )  \ACCUM_NEXT_m6_1_0[3]  (.A(
        syssvc_blk_0_NRBG_SVC_DONE), .B(PRDATA_0_iv_0_0_0_3), .C(
        ICYCLE22), .Y(\ACCUM_NEXT_m6_1_0[3]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_RNO_0[5]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[5]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[5] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[5] ));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[7]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[7] ), .C(\ACCUM_NEXT_m6[7]_net_1 ), .Y(
        \ACCUM_NEXT[7]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[8]  (.A(\ACCUM_IN[8]_net_1 )
        , .B(\ACCUMULATOR[7]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[8]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[3]  (.A(
        \ACCUM_IN[3]_net_1 ), .B(\ACCUMULATOR[3]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[3] ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[10]  (.A(N_81), .B(
        \ACCUMULATOR[10]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m5_4_1_0_0[10] ));
    CFG3 #( .INIT(8'hD5) )  \ACCUM_NEXT[27]  (.A(\ACCUM_NEXT_1[27] ), 
        .B(\ACCUMULATOR[28]_net_1 ), .C(ALUOUT_6_sqmuxa), .Y(
        \ACCUM_NEXT[27]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  \to_logic_2.tmp_4_27[0]  (.A(
        \ACCUM_NEXT[5]_net_1 ), .B(\ACCUM_NEXT[6]_net_1 ), .C(
        \tmp_4_23[0] ), .D(\tmp_4_12[0] ), .Y(\tmp_4_27[0] ));
    CFG4 #( .INIT(16'hD850) )  SMADDR_20_iv_6_161_i_m2_i_m2 (.A(
        DOJMP_net_1), .B(\INSTR_CMD[1] ), .C(un1_SMADDR_cry_9_S), .D(
        \RAMRDATA[9] ), .Y(N_100));
    CFG4 #( .INIT(16'h8F80) )  \ACCUM_NEXT_m6[7]  (.A(iPRDATA_6), .B(
        CoreAPB3_0_APBmslave1_PSELx), .C(ICYCLE22), .D(
        \ACCUM_NEXT_m3[7]_net_1 ), .Y(\ACCUM_NEXT_m6[7]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[24]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[24] ), .Y(\RAMWDATA[24]_net_1 ));
    CFG3 #( .INIT(8'h53) )  \ACCUM_NEXT_RNO_0[0]  (.A(
        \ACCUM_NEXT_m1[0]_net_1 ), .B(\ACCUM_NEXT_m0[0] ), .C(
        ACCUM_NEXT_sm0), .Y(\ACCUM_NEXT_m5_4_1_0[0] ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[4]  (.A(
        \ACCUM_IN[4]_net_1 ), .B(\ACCUMULATOR[4]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[4] ));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[4]  (.A(N_915), .B(N_7127_reto), 
        .C(\RAMRDATA[4] ), .Y(\ACCUM_IN[4]_net_1 ));
    CFG3 #( .INIT(8'h8B) )  USE_ACC_1_i_m2 (.A(
        \COREABC_0_APB3master_PADDR[16] ), .B(\INSTR_CMD[0] ), .C(
        N_7100_reto), .Y(N_83));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIQH7T6[6]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[6]_net_1 ), .C(\ACCUMULATOR[6]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_5), .S(
        \ACCUM_IN_RNIQH7T6_S[6] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_6));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_3 (.A(\STKPTR[3]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_2_net_1), .S(un1_STKPTR_cry_3_S), .Y(), .FCO(
        un1_STKPTR_cry_3_net_1));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[22]  (.A(
        \ACCUMULATOR[22]_net_1 ), .B(\ACCUM_IN[22]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[22]_net_1 ));
    CFG2 #( .INIT(4'h2) )  ICYCLE_s1_0_a2_0_a2 (.A(\ICYCLE[0]_net_1 ), 
        .B(\ICYCLE[1]_net_1 ), .Y(STBRAM_6_1));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[0]  (.A(
        \ACCUMULATOR[0]_net_1 ), .B(\ACCUM_IN[0]_net_1 ), .C(\MSEL[0] )
        , .Y(\ACCUM_NEXT_m1[0]_net_1 ));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_0 (.A(\STKPTR[0]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(GND_net_1), .S(
        ), .Y(un1_STKPTR_cry_0_Y), .FCO(un1_STKPTR_cry_0_net_1));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIF0US11[26]  (.A(\MSEL[2] )
        , .B(\ACCUM_IN[26]_net_1 ), .C(\ACCUMULATOR[26]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_25), .S(
        \ACCUM_IN_RNIF0US11_S[26] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_26)
        );
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[28]  (.A(
        \ACCUM_IN[28]_net_1 ), .B(\ACCUMULATOR[28]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[28]_net_1 ));
    UART_top_COREABC_0_RAMBLOCKS_32s_24s \URAM.UR  (.RDY_reto({
        \RDY_reto[15] , \RDY_reto[14] , \RDY_reto[13] , \RDY_reto[12] , 
        \RDY_reto[11] , \RDY_reto[10] , \RDY_reto[9] , \RDY_reto[8] , 
        \RDY_reto[7] , \RDY_reto[6] , \RDY_reto[5] , \RDY_reto[4] , 
        \RDY_reto[3] , \RDY_reto[2] , \RDY_reto[1] , \RDY_reto[0] }), 
        .RD_2_reto_0({\RD_2_reto_0[15] , \RD_2_reto_0[14] , 
        \RD_2_reto_0[13] , \RD_2_reto_0[12] , \RD_2_reto_0[11] }), 
        .RD_2_reto({\RD_2_reto[15] , \RD_2_reto[14] , \RD_2_reto[13] , 
        \RD_2_reto[12] , \RD_2_reto[11] , \RD_2_reto[10] , 
        \RD_2_reto[9] , \RD_2_reto[8] , \RD_2_reto[7] , \RD_2_reto[6] , 
        \RD_2_reto[5] , \RD_2_reto[4] , \RD_2_reto[3] , \RD_2_reto[2] , 
        \RD_2_reto[1] , \RD_2_reto[0] }), .COREABC_0_APB3master_PWDATA({
        \COREABC_0_APB3master_PWDATA[31] , 
        \COREABC_0_APB3master_PWDATA[30] , 
        \COREABC_0_APB3master_PWDATA[29] , 
        \COREABC_0_APB3master_PWDATA[28] , 
        \COREABC_0_APB3master_PWDATA[27] , 
        \COREABC_0_APB3master_PWDATA[26] , 
        \COREABC_0_APB3master_PWDATA[25] , 
        \COREABC_0_APB3master_PWDATA[24] , 
        \COREABC_0_APB3master_PWDATA[23] , 
        \COREABC_0_APB3master_PWDATA[22] , 
        \COREABC_0_APB3master_PWDATA[21] , 
        \COREABC_0_APB3master_PWDATA[20] , 
        \COREABC_0_APB3master_PWDATA[19] , 
        \COREABC_0_APB3master_PWDATA[18] , 
        \COREABC_0_APB3master_PWDATA[17] , 
        \COREABC_0_APB3master_PWDATA[16] }), .RAMWDATA({
        \RAMWDATA[31]_net_1 , \RAMWDATA[30]_net_1 , 
        \RAMWDATA[29]_net_1 , \RAMWDATA[28]_net_1 , 
        \RAMWDATA[27]_net_1 , \RAMWDATA[26]_net_1 , 
        \RAMWDATA[25]_net_1 , \RAMWDATA[24]_net_1 , 
        \RAMWDATA[23]_net_1 , \RAMWDATA[22]_net_1 , 
        \RAMWDATA[21]_net_1 , \RAMWDATA[20]_net_1 , 
        \RAMWDATA[19]_net_1 , \RAMWDATA[18]_net_1 , 
        \RAMWDATA[17]_net_1 , \RAMWDATA[16]_net_1 , 
        \RAMWDATA[15]_net_1 , \RAMWDATA[14]_net_1 , 
        \RAMWDATA[13]_net_1 , \RAMWDATA[12]_net_1 , 
        \RAMWDATA[11]_net_1 , \RAMWDATA[10]_net_1 , 
        \RAMWDATA[9]_net_1 , \RAMWDATA[8]_net_1 , \RAMWDATA[7]_net_1 , 
        \RAMWDATA[6]_net_1 , \RAMWDATA[5]_net_1 , \RAMWDATA[4]_net_1 , 
        \RAMWDATA[3]_net_1 , \RAMWDATA[2]_net_1 , \RAMWDATA[1]_net_1 , 
        \RAMWDATA[0]_net_1 }), .RDX_reto({\RDX_reto[15] , 
        \RDX_reto[14] , \RDX_reto[13] , \RDX_reto[12] , \RDX_reto[11] })
        , .RAMADDR({\RAMADDR[7]_net_1 , \RAMADDR[6]_net_1 , 
        \RAMADDR[5]_net_1 , \RAMADDR[4]_net_1 , \RAMADDR[3]_net_1 , 
        \RAMADDR[2]_net_1 , \RAMADDR[1]_net_1 , \RAMADDR[0]_net_1 }), 
        .RAMRDATA({\RAMRDATA[10] , \RAMRDATA[9] , \RAMRDATA[8] , 
        \RAMRDATA[7] , \RAMRDATA[6] , \RAMRDATA[5] , \RAMRDATA[4] , 
        \RAMRDATA[3] , \RAMRDATA[2] , \RAMRDATA[1] , \RAMRDATA[0] }), 
        .N_130_i(N_130_i), .STBRAM(STBRAM_net_1), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .REN_reto_rep1(REN_reto_rep1), .REN_reto_rep2(REN_reto_rep2), 
        .RAM_RAM_0_2_RNIR37F1_0(RAM_RAM_0_2_RNIR37F1_0), 
        .RAM_RAM_0_2_RNIBCJE1_0(RAM_RAM_0_2_RNIBCJE1_0), 
        .RAM_RAM_0_2_RNI9AJE1_0(RAM_RAM_0_2_RNI9AJE1_0));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[5]  (.A(N_130), .B(
        un1_SMADDR_cry_5_S), .C(COREABC_0_APB3master_PWDATA[5]), .Y(
        \RAMWDATA[5]_net_1 ));
    SLE \ICYCLE[1]  (.D(N_87_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ICYCLE[1]_net_1 ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[11]  (.A(ACCUM_NEXT_sm5), 
        .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[11]_net_1 ), 
        .D(\ACCUM_IN_RNIHKP6I_S[11] ), .Y(\ACCUM_NEXT[11]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[21]  (.A(\RD_2_reto[5] ), .B(
        N_915), .C(\RDY_reto[5] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[21]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[23]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[23] ), .Y(\RAMWDATA[23]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIHKP6I[11]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[11]_net_1 ), .C(\ACCUMULATOR[11]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_10), .S(
        \ACCUM_IN_RNIHKP6I_S[11] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_11));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_6 (.A(VCC_net_1), .B(
        \SMADDR_i[6] ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_5_net_1), .S(un1_SMADDR_cry_6_S), .Y(), .FCO(
        un1_SMADDR_cry_6_net_1));
    CFG4 #( .INIT(16'h55C0) )  \ACCUM_NEXT_m6_ns[6]  (.A(
        \ACCUM_NEXT_m6_ns_1[6]_net_1 ), .B(\ACCUMULATOR[7]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[6] ));
    CFG3 #( .INIT(8'hD1) )  \ACCUM_NEXT_m0_RNIFSN8A[7]  (.A(
        \ACCUM_NEXT_m5_4_1_0[7] ), .B(\doins_0_dreg_RNIJ2TF[3] ), .C(
        \ACCUM_IN_RNIO5RS7_S[7] ), .Y(\ACCUM_NEXT_m5[7] ));
    CFG4 #( .INIT(16'hDAD0) )  \ACCUM_NEXT_m0_am[0]  (.A(N_7124_reto), 
        .B(\ACCUMULATOR[31]_net_1 ), .C(N_7123_reto), .D(
        \ACCUMULATOR[0]_net_1 ), .Y(\ACCUM_NEXT_m0_am[0]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[15]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[16]_net_1 ), .Y(ACCUM_NEXT_61));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_3 (.A(VCC_net_1), .B(
        \STKPTR[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_2_net_1), .S(un1_STKPTRP1_cry_3_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_3_net_1));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[3]  (.A(\ACCUM_IN[3]_net_1 )
        , .B(\ACCUMULATOR[2]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[3]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[11]  (.A(\RD_2_reto[11] ), .B(
        N_915), .C(\RDX_reto[11] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[11]_net_1 ));
    CFG4 #( .INIT(16'h44FE) )  \ACCUM_NEXT_m4[17]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[17]_net_1 ), .C(ALUOUT_1_sqmuxa_net_1), .D(
        \ACCUM_NEXT_m4_1_0[17]_net_1 ), .Y(\ACCUM_NEXT_m4[17]_net_1 ));
    CFG2 #( .INIT(4'h2) )  \ICYCLE22.ICYCLE22_0_a2_0_a2  (.A(
        \INSTR_CMD[1] ), .B(\INSTR_CMD[0] ), .Y(ICYCLE22));
    CFG4 #( .INIT(16'h1200) )  un1_ICYCLE_10_i_a2 (.A(\INSTR_CMD[1] ), 
        .B(N_88), .C(\INSTR_CMD[0] ), .D(STBRAM_6_1), .Y(N_126));
    SLE \ACCUMULATOR[27]  (.D(\ACCUM_NEXT[27]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[27]_net_1 ));
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[6]  (.A(N_7129_reto), .B(
        \ACCUMULATOR[6]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[6]));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[16]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[16]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[16]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIC2DU3[3]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[3]_net_1 ), .C(\ACCUMULATOR[3]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_2), .S(
        \ACCUM_IN_RNIC2DU3_S[3] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_3));
    CFG2 #( .INIT(4'h4) )  \ACCUM_IN[8]  (.A(N_915), .B(\RAMRDATA[8] ), 
        .Y(\ACCUM_IN[8]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[27]  (.A(
        \ACCUM_IN[27]_net_1 ), .B(\ACCUMULATOR[26]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[27]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIVT6IK[13]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[13]_net_1 ), .C(\ACCUMULATOR[13]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_12), .S(
        \ACCUM_IN_RNIVT6IK_S[13] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_13));
    SLE \ACCUMULATOR[14]  (.D(\ACCUM_NEXT[14]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[14]_net_1 ));
    CFG4 #( .INIT(16'hF8FF) )  \to_logic_9_i_o2_sx[0]  (.A(N_7102_reto)
        , .B(N_7101_reto), .C(\INSTR_CMD[2] ), .D(\INSTR_CMD[0] ), .Y(
        \to_logic_9_i_o2_sx[0]_net_1 ));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[18]  (.A(
        \ACCUMULATOR[18]_net_1 ), .B(\ACCUM_IN[18]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[18]_net_1 ));
    ARI1 #( .INIT(20'h5CCAA) )  \ACCUM_IN_RNI3J5VA[7]  (.A(VCC_net_1), 
        .B(\ACCUM_IN_RNIPGLJ[8]_net_1 ), .C(ACCUM_NEXT_m5_0_axb_8), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_7), .S(
        \ACCUM_IN_RNI3J5VA_S[7] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_8));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_1 (.A(\STKPTR[1]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_0_net_1), .S(un1_STKPTR_cry_1_S), .Y(), .FCO(
        un1_STKPTR_cry_1_net_1));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[25]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[25] ), .Y(\RAMWDATA[25]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[6]  (.A(un1_STKPTRP1_cry_6_S), .B(
        N_104), .C(N_7112_reto), .Y(\RAMADDR[6]_net_1 ));
    SLE \ACCUMULATOR[9]  (.D(\ACCUM_NEXT[9]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[9]_net_1 ));
    SLE \SMADDR[10]  (.D(N_102), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR[10]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[3]  (.A(un1_STKPTRP1_cry_3_S), .B(
        N_104), .C(N_7110_reto), .Y(\RAMADDR[3]_net_1 ));
    ARI1 #( .INIT(20'h46A00) )  \ACCUM_NEXT_RNO[31]  (.A(VCC_net_1), 
        .B(\ACCUMULATOR[31]_net_1 ), .C(\ACCUM_IN[31]_net_1 ), .D(
        \MSEL[2] ), .FCI(ACCUM_NEXT_m5_0_cry_30), .S(
        \ACCUM_NEXT_RNO_S[31] ), .Y(), .FCO());
    CFG4 #( .INIT(16'hF10B) )  \ACCUM_NEXT_1_RNO[12]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[12]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\ACCUM_NEXT_m5_4_1_0_0[12] ), .Y(
        \ACCUM_NEXT_m5_4_1_0[12] ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[28]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[29]_net_1 ), .Y(ACCUM_NEXT_5));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[20]  (.A(N_83), .B(
        \ACCUMULATOR[20]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[20] )
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[30]  (.A(
        \ACCUM_IN[30]_net_1 ), .B(\ACCUMULATOR[29]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[30]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[26]  (.A(
        \ACCUM_IN[26]_net_1 ), .B(\ACCUMULATOR[25]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[26]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[14]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[14] ), .C(\ACCUM_NEXT_m6[14]_net_1 ), .Y(
        \ACCUM_NEXT[14]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_RNO_1[5]  (.A(
        \ACCUM_IN[5]_net_1 ), .B(\ACCUMULATOR[5]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[5] ));
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[24]  (.A(
        \ACCUM_IN[24]_net_1 ), .B(\ACCUMULATOR[24]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[24]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_2 (.A(VCC_net_1), .B(
        SMADDR_i_1), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_1_net_1), .S(un1_SMADDR_cry_2_S), .Y(), .FCO(
        un1_SMADDR_cry_2_net_1));
    CFG3 #( .INIT(8'h47) )  \SMADDR_RNO_0[0]  (.A(N_7107_reto), .B(
        DOJMP_net_1), .C(\SMADDR_i[0] ), .Y(N_694_i_1));
    CFG4 #( .INIT(16'h1D3F) )  \ACCUM_NEXT_m6_ns_1[6]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_5), .D(APB_register_blk_0_PRDATA_5), .Y(
        \ACCUM_NEXT_m6_ns_1[6]_net_1 ));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[19]  (.A(
        \ACCUMULATOR[19]_net_1 ), .B(\ACCUM_IN[19]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[19]_net_1 ));
    SLE \STKPTR[4]  (.D(\STKPTR_12[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[4]_net_1 ));
    CFG4 #( .INIT(16'h5CCC) )  \SMADDR_RNO[1]  (.A(\RAMRDATA[1] ), .B(
        N_679_i_1), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(N_679_i));
    CFG3 #( .INIT(8'hF8) )  ACCUM_NEXTs2 (.A(N_915), .B(\INSTR_CMD[1] )
        , .C(ALUOUT_6_sqmuxa), .Y(ACCUM_NEXT_sm5));
    CFG4 #( .INIT(16'h1D3F) )  \ACCUM_NEXT_m6_ns_1[1]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_0), .D(APB_register_blk_0_PRDATA_0), .Y(
        \ACCUM_NEXT_m6_ns_1[1]_net_1 ));
    CFG4 #( .INIT(16'hE444) )  \ACCUM_NEXT_m6[14]  (.A(ICYCLE22), .B(
        \ACCUM_NEXT_m3[14]_net_1 ), .C(APB_register_blk_0_PRDATA_13), 
        .D(iPRDATA_0_sqmuxa), .Y(\ACCUM_NEXT_m6[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_4 (.A(VCC_net_1), .B(
        \STKPTR[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_3_net_1), .S(un1_STKPTRP1_cry_4_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_4_net_1));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[26]  (.A(\RD_2_reto[10] ), .B(
        N_915), .C(\RDY_reto[10] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[26]_net_1 ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[10]  (.A(ACCUM_NEXT_sm5), 
        .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[10]_net_1 ), 
        .D(\ALUOUT_4_0_m2_RNIT231H_S[10] ), .Y(\ACCUM_NEXT[10]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[29]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[30]_net_1 ), .Y(ACCUM_NEXT_45));
    SLE \ACCUMULATOR[0]  (.D(\ACCUM_NEXT[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[0]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_SMADDR_cry_9 (.A(VCC_net_1), .B(
        \SMADDR[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_8_net_1), .S(un1_SMADDR_cry_9_S), .Y(), .FCO(
        un1_SMADDR_cry_9_net_1));
    SLE \ACCUMULATOR[29]  (.D(\ACCUM_NEXT[29]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[29]_net_1 ));
    CFG4 #( .INIT(16'h5E1A) )  \ACCUM_NEXT[4]  (.A(ACCUM_NEXT_sm5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[4]_net_1 ), .D(
        \ACCUM_IN_RNI4G0U4_S[4] ), .Y(\ACCUM_NEXT[4]_net_1 ));
    SLE \ICYCLE[0]  (.D(N_909_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ICYCLE[0]_net_1 ));
    CFG4 #( .INIT(16'h55C0) )  \ACCUM_NEXT_m6_ns[1]  (.A(
        \ACCUM_NEXT_m6_ns_1[1]_net_1 ), .B(\ACCUMULATOR[2]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[1] ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[10]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[11]_net_1 ), .Y(\ACCUM_NEXT_m3[10]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[1]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[1] ), .C(\ACCUM_NEXT_m6[1] ), .Y(
        \ACCUM_NEXT_1[1]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[28]  (.A(ACCUM_NEXT_5), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[28]_net_1 ), .D(
        \ACCUM_IN_RNIL6G831_S[28] ), .Y(\ACCUM_NEXT[28]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[16]  (.A(\RD_2_reto[0] ), .B(
        N_915), .C(\RDY_reto[0] ), .D(REN_reto_rep1), .Y(
        \ACCUM_IN[16]_net_1 ));
    SLE \ACCUMULATOR[6]  (.D(\ACCUM_NEXT[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[6]_net_1 ));
    SLE \ACCUMULATOR[22]  (.D(\ACCUM_NEXT[22]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[22]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_s_1_812 (.A(VCC_net_1), 
        .B(\STKPTR[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(un1_STKPTRP1_s_1_812_FCO));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[1]  (.A(\ACCUM_IN[1]_net_1 )
        , .B(\ACCUMULATOR[0]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[20]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[21]_net_1 ), .Y(ACCUM_NEXT_25));
    CFG1 #( .INIT(2'h1) )  \URAM.ii72_i_a2_RNIFOPB  (.A(N_130), .Y(
        N_130_i));
    CFG4 #( .INIT(16'hBAAA) )  un1_STBRAM_4_sqmuxa_3_i (.A(N_125), .B(
        N_88), .C(STBRAM_6_1), .D(ICYCLE22), .Y(N_910));
    CFG4 #( .INIT(16'h0207) )  \to_logic_2.tmp_4_12[0]  (.A(
        ACCUM_NEXT_sm5), .B(\ACCUM_NEXT_m6[7]_net_1 ), .C(
        \ACCUM_NEXT[0]_net_1 ), .D(\ACCUM_NEXT_m5[7] ), .Y(
        \tmp_4_12[0] ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[24]  (.A(N_83), .B(
        \ACCUMULATOR[24]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[24] )
        );
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[4]  (.A(\ACCUM_IN[4]_net_1 )
        , .B(\ACCUMULATOR[3]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[4]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[19]  (.A(ACCUM_NEXT_41), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[19]_net_1 ), .D(
        \ACCUM_IN_RNIPBGKR_S[19] ), .Y(\ACCUM_NEXT[19]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0_bm[0]  (.A(N_7123_reto), .B(
        \RAMRDATA[0] ), .C(N_915), .Y(\ACCUM_NEXT_m0_bm[0]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[23]  (.A(
        \ACCUM_IN[23]_net_1 ), .B(\ACCUMULATOR[22]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[23]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIPLTNL[14]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[14]_net_1 ), .C(\ACCUMULATOR[14]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_13), .S(
        \ACCUM_IN_RNIPLTNL_S[14] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_14));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIO5RS7[7]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[7]_net_1 ), .C(\ACCUMULATOR[7]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_6), .S(
        \ACCUM_IN_RNIO5RS7_S[7] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_7));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_3 (.A(VCC_net_1), .B(
        \SMADDR_i[3] ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_2_net_1), .S(un1_SMADDR_cry_3_S), .Y(), .FCO(
        un1_SMADDR_cry_3_net_1));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[31]  (.A(ACCUM_NEXT_65), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[31]_net_1 ), .D(
        \ACCUM_NEXT_RNO_S[31] ), .Y(\ACCUM_NEXT[31]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[20]  (.A(\RD_2_reto[4] ), .B(
        N_915), .C(\RDY_reto[4] ), .D(REN_reto_rep1), .Y(
        \ACCUM_IN[20]_net_1 ));
    CFG4 #( .INIT(16'hA9AA) )  \ACCUMULATOR_RNID35D2[10]  (.A(
        \ACCUMULATOR[10]_net_1 ), .B(RAM_RAM_0_2_RNIR37F1_0), .C(N_915)
        , .D(\MSEL[2] ), .Y(ACCUM_NEXT_m5_0_axb_10));
    CFG3 #( .INIT(8'hAE) )  \xhdl_31.MSEL[2]  (.A(N_7102_reto), .B(
        \INSTR_CMD[0] ), .C(N_78), .Y(\MSEL[2] ));
    CFG3 #( .INIT(8'hE4) )  \ACCUM_NEXT[13]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5[13] ), .C(\ACCUM_NEXT_m6[13]_net_1 ), .Y(
        \ACCUM_NEXT[13]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIRCQ5V[22]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[22]_net_1 ), .C(\ACCUMULATOR[22]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_21), .S(
        \ACCUM_IN_RNIRCQ5V_S[22] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_22));
    SLE \ACCUMULATOR[30]  (.D(\ACCUM_NEXT[30]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[30]_net_1 ));
    CFG3 #( .INIT(8'h80) )  SMADDR_20_iv_2_229_i_m2_i_m2_3 (.A(
        \RAMRDATA[5] ), .B(DOJMP_net_1), .C(\INSTR_CMD[1] ), .Y(
        SMADDR_20_iv_2_229_i_m2_i_m2_2_net_1));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[16]  (.A(ACCUM_NEXT_29), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[16]_net_1 ), .D(
        \ACCUM_IN_RNIJBB3O_S[16] ), .Y(\ACCUM_NEXT[16]_net_1 ));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[20]  (.A(
        \ACCUM_IN[20]_net_1 ), .B(\ACCUMULATOR[20]_net_1 ), .C(
        \ACCUM_NEXT_m1[20]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[20]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \ACCUM_IN[9]  (.A(N_915), .B(\RAMRDATA[9] ), 
        .Y(\ACCUM_IN[9]_net_1 ));
    CFG4 #( .INIT(16'hA2FF) )  PSELI11 (.A(
        COREABC_0_APB3master_PENABLE), .B(iPRDATA_0_sqmuxa), .C(
        APB_register_blk_0_PREADY), .D(m3_1), .Y(PSELI11_net_1));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[18]  (.A(
        \ACCUM_IN[18]_net_1 ), .B(\ACCUMULATOR[18]_net_1 ), .C(
        \ACCUM_NEXT_m1[18]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[18]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[21]  (.A(
        \ACCUM_IN[21]_net_1 ), .B(\ACCUMULATOR[20]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[21]_net_1 ));
    CFG3 #( .INIT(8'hAE) )  \xhdl_31.MSEL[1]  (.A(N_7101_reto), .B(
        \INSTR_CMD[0] ), .C(N_78), .Y(\MSEL[1] ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[4]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[4] ), .C(\ACCUM_NEXT_m6[4] ), .Y(
        \ACCUM_NEXT_1[4]_net_1 ));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_5 (.A(\STKPTR[5]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_4_net_1), .S(un1_STKPTR_cry_5_S), .Y(), .FCO(
        un1_STKPTR_cry_5_net_1));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[17]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[17] ), .Y(\RAMWDATA[17]_net_1 ));
    CFG4 #( .INIT(16'hA9AA) )  \ACCUMULATOR_RNIISKE2[8]  (.A(
        \ACCUMULATOR[8]_net_1 ), .B(RAM_RAM_0_2_RNI9AJE1_0), .C(N_915), 
        .D(\MSEL[2] ), .Y(ACCUM_NEXT_m5_0_axb_8));
    CFG3 #( .INIT(8'h08) )  \RAMWDATA[11]  (.A(\ACCUMULATOR[11]_net_1 )
        , .B(N_83), .C(N_130), .Y(\RAMWDATA[11]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[18]  (.A(
        \ACCUM_IN[18]_net_1 ), .B(\ACCUMULATOR[17]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[18]_net_1 ));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_1_RNO_0[9]  (.A(
        \ACCUM_IN[9]_net_1 ), .B(\ACCUMULATOR[9]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[9] ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[27]  (.A(\RD_2_reto_0[11] ), 
        .B(N_915), .C(\RDY_reto[11] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[27]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[1]  (.A(un1_STKPTRP1_cry_1_S), 
        .B(N_910), .C(un1_STKPTR_cry_1_S), .Y(\STKPTR_12[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[30]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[31]_net_1 ), .Y(ACCUM_NEXT_13));
    SLE \genblk2.RSTSYNC2  (.D(RSTSYNC1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(RSTSYNC2));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_m0_RNI4KVR1[7]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[7]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[7] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[7] ));
    SLE \ACCUMULATOR[17]  (.D(\ACCUM_NEXT[17]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[17]_net_1 ));
    CFG4 #( .INIT(16'h3734) )  \ACCUM_NEXT_RNO[0]  (.A(
        \ACCUM_NEXT_m5_4_1_0[0] ), .B(\ACCUM_NEXT_m5_4_1[0] ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\ACCUM_IN_RNIG5JV_Y[0] ), .Y(
        \ACCUM_NEXT_m5[0] ));
    SLE \ACCUMULATOR[28]  (.D(\ACCUM_NEXT[28]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[28]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[17]  (.A(\RD_2_reto[1] ), .B(
        N_915), .C(\RDY_reto[1] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[17]_net_1 ));
    CFG4 #( .INIT(16'h2000) )  STBACCUM_4_sqmuxa_0_a3_0_a2 (.A(
        \INSTR_CMD[0] ), .B(\INSTR_CMD[2] ), .C(\INSTR_CMD[1] ), .D(
        STBRAM_6_1), .Y(STBACCUM_4_sqmuxa));
    SLE \SMADDR[3]  (.D(N_814_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[3] ));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[2]  (.A(N_130), .B(
        un1_SMADDR_cry_2_S), .C(COREABC_0_APB3master_PWDATA[2]), .Y(
        \RAMWDATA[2]_net_1 ));
    CFG3 #( .INIT(8'hD1) )  \ACCUM_NEXT_RNO[14]  (.A(
        \ACCUM_NEXT_m5_4_1_0[14] ), .B(\doins_0_dreg_RNIJ2TF[3] ), .C(
        \ACCUM_IN_RNIPLTNL_S[14] ), .Y(\ACCUM_NEXT_m5[14] ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[19]  (.A(
        \ACCUM_IN[19]_net_1 ), .B(\ACCUMULATOR[18]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[19]_net_1 ));
    CFG4 #( .INIT(16'h7555) )  un1_ICYCLE_8_0_0 (.A(\ICYCLE[0]_net_1 ), 
        .B(\ICYCLE[1]_net_1 ), .C(\INSTR_CMD[1] ), .D(\INSTR_CMD[0] ), 
        .Y(un1_ICYCLE_8_0_0_net_1));
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[30]  (.A(
        \ACCUM_IN[30]_net_1 ), .B(\ACCUMULATOR[30]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[30]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[25]  (.A(\RD_2_reto[9] ), .B(
        N_915), .C(\RDY_reto[9] ), .D(REN_reto_rep2), .Y(
        \ACCUM_IN[25]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \to_logic_2.tmp_4[0]  (.A(\tmp_4_20[0] )
        , .B(\tmp_4_21[0] ), .C(\tmp_4_28[0] ), .D(\tmp_4_27[0] ), .Y(
        \tmp_4[0] ));
    CFG4 #( .INIT(16'h0100) )  STBACCUM_4_u_0_a2_1 (.A(\INSTR_CMD[0] ), 
        .B(\INSTR_CMD[2] ), .C(\INSTR_CMD[1] ), .D(STBRAM_6_1), .Y(
        STBACCUM_4_u_0_a2_1_net_1));
    CFG4 #( .INIT(16'h1D3F) )  \ACCUM_NEXT_m6_ns_1[5]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_4), .D(APB_register_blk_0_PRDATA_3), .Y(
        \ACCUM_NEXT_m6_ns_1[5]_net_1 ));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[17]  (.A(
        \ACCUMULATOR[17]_net_1 ), .B(\ACCUM_IN[17]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[17]_net_1 ));
    CFG3 #( .INIT(8'h60) )  \STBRAM_6.m10_0_a2_1_0  (.A(N_7102_reto), 
        .B(N_7101_reto), .C(STBACCUM_4_sqmuxa), .Y(N_111_1));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[1]  (.A(un1_STKPTRP1_cry_1_S), .B(
        N_104), .C(N_7108_reto), .Y(\RAMADDR[1]_net_1 ));
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[26]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[26]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[26]_net_1 ), .D(\ACCUM_NEXT_1_sx[26]_net_1 )
        , .Y(\ACCUM_NEXT_1[26]_net_1 ));
    CFG4 #( .INIT(16'hFEBA) )  \ACCUM_NEXT[30]  (.A(ACCUM_NEXT_13), .B(
        \doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_1[30]_net_1 ), .D(
        \ACCUM_IN_RNIH44K41_S[30] ), .Y(\ACCUM_NEXT[30]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_STKPTRP1_cry_6 (.A(VCC_net_1), .B(
        \STKPTR[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_STKPTRP1_cry_5_net_1), .S(un1_STKPTRP1_cry_6_S), .Y(), 
        .FCO(un1_STKPTRP1_cry_6_net_1));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[7]  (.A(N_915), .B(N_7130_reto), 
        .C(\RAMRDATA[7] ), .Y(\ACCUM_IN[7]_net_1 ));
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[5]  (.A(N_7128_reto), .B(
        \ACCUMULATOR[5]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[5]));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[10]  (.A(N_81), .B(
        \ACCUMULATOR[9]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[10]_net_1 ));
    CFG4 #( .INIT(16'h2230) )  \ACCUM_IN[15]  (.A(\RD_2_reto[15] ), .B(
        N_915), .C(\RDX_reto[15] ), .D(REN_reto_rep1), .Y(
        \ACCUM_IN[15]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNIDV8QS[20]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[20]_net_1 ), .C(\ACCUMULATOR[20]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_19), .S(
        \ACCUM_IN_RNIDV8QS_S[20] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_20));
    SLE \STKPTR[0]  (.D(un1_STKPTR_cry_0_Y), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[0]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PWDATA_M[0]  (.A(N_83), .B(N_7123_reto), 
        .C(\ACCUMULATOR[0]_net_1 ), .Y(COREABC_0_APB3master_PWDATA[0]));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_19[0]  (.A(
        \ACCUM_NEXT[29]_net_1 ), .B(\ACCUM_NEXT[19]_net_1 ), .C(
        \ACCUM_NEXT[24]_net_1 ), .D(\ACCUM_NEXT[28]_net_1 ), .Y(
        \tmp_4_19[0] ));
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[25]  (.A(
        \ACCUM_IN[25]_net_1 ), .B(\ACCUMULATOR[25]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[25]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[7]  (.A(\ACCUM_IN[7]_net_1 )
        , .B(\ACCUMULATOR[6]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[7]_net_1 ));
    SLE \ACCUMULATOR[21]  (.D(\ACCUM_NEXT[21]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[21]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \xhdl_41.flagvalue_1  (.A(
        syssvc_blk_0_NRBG_SVC_DONE), .B(STD_ACCUM_NEG_net_1), .C(
        N_7125_reto), .D(N_7130_reto), .Y(flagvalue_1));
    CFG2 #( .INIT(4'h8) )  \ACCUM_IN_RNIPGLJ[8]  (.A(
        \ACCUM_IN[8]_net_1 ), .B(\MSEL[2] ), .Y(
        \ACCUM_IN_RNIPGLJ[8]_net_1 ));
    SLE PSELI (.D(PSELI_5), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(m3_1));
    CFG3 #( .INIT(8'h6E) )  \ACCUM_NEXT_m1[16]  (.A(
        \ACCUMULATOR[16]_net_1 ), .B(\ACCUM_IN[16]_net_1 ), .C(
        \MSEL[0] ), .Y(\ACCUM_NEXT_m1[16]_net_1 ));
    CFG4 #( .INIT(16'h7971) )  \ACCUM_NEXT_m4_1_0[26]  (.A(
        \ACCUM_IN[26]_net_1 ), .B(\ACCUMULATOR[26]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m4_1_0[26]_net_1 ));
    SLE \ACCUMULATOR[4]  (.D(\ACCUM_NEXT[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[4]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[27]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[27] ), .Y(\RAMWDATA[27]_net_1 ));
    CFG3 #( .INIT(8'h08) )  SMADDR_20_iv_2_229_i_m2_i_m2_2 (.A(
        N_7112_reto), .B(DOJMP_net_1), .C(\INSTR_CMD[1] ), .Y(
        SMADDR_20_iv_2_229_i_m2_i_m2_1));
    CFG4 #( .INIT(16'h55C0) )  \ACCUM_NEXT_m6_ns[5]  (.A(
        \ACCUM_NEXT_m6_ns_1[5]_net_1 ), .B(\ACCUMULATOR[6]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[5] ));
    SLE \ACCUMULATOR[1]  (.D(\ACCUM_NEXT[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[21]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[21] ), .Y(\RAMWDATA[21]_net_1 ));
    SLE \SMADDR[0]  (.D(N_694_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[0] ));
    CLKINT \genblk2.RSTSYNC2_RNII35A  (.A(RSTSYNC2), .Y(
        COREABC_0_PRESETN));
    CFG4 #( .INIT(16'h767E) )  \ACCUM_NEXT_RNO_1[13]  (.A(
        \ACCUM_IN[13]_net_1 ), .B(\ACCUMULATOR[13]_net_1 ), .C(
        ALUOUT_1_sqmuxa_net_1), .D(\MSEL[0] ), .Y(
        \ACCUM_NEXT_m5_4_1_0_0[13] ));
    SLE \ACCUMULATOR[19]  (.D(\ACCUM_NEXT[19]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[19]_net_1 ));
    CFG3 #( .INIT(8'hCA) )  \PWDATA_M[4]  (.A(N_7127_reto), .B(
        \ACCUMULATOR[4]_net_1 ), .C(N_83), .Y(
        COREABC_0_APB3master_PWDATA[4]));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_20[0]  (.A(
        \ACCUM_NEXT[27]_net_1 ), .B(\ACCUM_NEXT[23]_net_1 ), .C(
        \ACCUM_NEXT[18]_net_1 ), .D(\ACCUM_NEXT[17]_net_1 ), .Y(
        \tmp_4_20[0] ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[26]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[27]_net_1 ), .Y(ACCUM_NEXT_1));
    CFG4 #( .INIT(16'h002F) )  \ACCUM_NEXT_1[16]  (.A(
        \ACCUM_NEXT_m0[16]_net_1 ), .B(ACCUM_NEXT_sm0), .C(
        \ACCUM_NEXT_m4_1_0[16]_net_1 ), .D(\ACCUM_NEXT_1_sx[16]_net_1 )
        , .Y(\ACCUM_NEXT_1[16]_net_1 ));
    SLE \ACCUMULATOR[12]  (.D(\ACCUM_NEXT[12]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[12]_net_1 ));
    CFG4 #( .INIT(16'h5CCC) )  \SMADDR_RNO[8]  (.A(\RAMRDATA[8] ), .B(
        N_98_i_1), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(N_98_i));
    CFG3 #( .INIT(8'hE2) )  \RAMADDR[2]  (.A(un1_STKPTRP1_cry_2_S), .B(
        N_104), .C(N_7109_reto), .Y(\RAMADDR[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[29]  (.A(N_83), .B(
        \ACCUMULATOR[29]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[29] )
        );
    CFG4 #( .INIT(16'h27AF) )  \SMADDR_RNO[7]  (.A(DOJMP_net_1), .B(
        \INSTR_CMD[1] ), .C(un1_SMADDR_cry_7_S), .D(\RAMRDATA[7] ), .Y(
        N_96_i));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[6]  (.A(\ACCUM_IN[6]_net_1 )
        , .B(\ACCUMULATOR[5]_net_1 ), .C(\MSEL[1] ), .Y(
        \ACCUM_NEXT_m0[6]_net_1 ));
    CFG2 #( .INIT(4'hD) )  \xhdl_31.MSEL[0]  (.A(N_915), .B(
        N_7100_reto), .Y(\MSEL[0] ));
    CFG3 #( .INIT(8'hE2) )  \RAMWDATA[0]  (.A(
        COREABC_0_APB3master_PWDATA[0]), .B(N_130), .C(\SMADDR_i[0] ), 
        .Y(\RAMWDATA[0]_net_1 ));
    CFG3 #( .INIT(8'h7D) )  un1_ICYCLE_8_0_o2 (.A(\INSTR_CMD[2] ), .B(
        flagvalue), .C(N_7100_reto), .Y(N_88));
    CFG4 #( .INIT(16'h0031) )  \SMADDR_RNO[6]  (.A(un1_SMADDR_cry_6_S), 
        .B(SMADDR_20_iv_3_212_i_m2_i_m2_2), .C(DOJMP_net_1), .D(
        SMADDR_20_iv_2_229_i_m2_i_m2_1), .Y(N_94_i));
    CFG3 #( .INIT(8'hB1) )  \RAMADDR[0]  (.A(N_104), .B(
        \STKPTR[0]_net_1 ), .C(N_7107_reto), .Y(\RAMADDR[0]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \ACCUM_NEXT_1[3]  (.A(ACCUM_NEXT_sm5), .B(
        \ACCUM_NEXT_m5_4_1_0[3] ), .C(\ACCUM_NEXT_m6[3]_net_1 ), .Y(
        \ACCUM_NEXT_1[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_SMADDR_s_10 (.A(VCC_net_1), .B(
        \SMADDR[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_9_net_1), .S(un1_SMADDR_s_10_S), .Y(), .FCO());
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_1 (.A(VCC_net_1), .B(
        SMADDR_i_0), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_0_net_1), .S(un1_SMADDR_cry_1_S), .Y(), .FCO(
        un1_SMADDR_cry_1_net_1));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[6]  (.A(un1_STKPTRP1_cry_6_S), 
        .B(N_910), .C(un1_STKPTR_cry_6_S), .Y(\STKPTR_12[6]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \ACCUM_NEXT_1_sx[26]  (.A(
        ALUOUT_1_sqmuxa_net_1), .B(\ACCUM_NEXT_m0[26]_net_1 ), .C(
        ACCUM_NEXT_sm5), .D(ACCUM_NEXT_sm0), .Y(
        \ACCUM_NEXT_1_sx[26]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  un1_SMADDR_cry_8 (.A(VCC_net_1), .B(
        \SMADDR_i[8] ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_SMADDR_cry_7_net_1), .S(un1_SMADDR_cry_8_S), .Y(), .FCO(
        un1_SMADDR_cry_8_net_1));
    CFG3 #( .INIT(8'h35) )  \ACCUM_NEXT_m6_1_0[0]  (.A(
        CoreUARTapb_0_TXRDY), .B(PRDATA_0_iv_0_0_0_0), .C(ICYCLE22), 
        .Y(\ACCUM_NEXT_m6_1_0[0]_net_1 ));
    SLE \SMADDR[8]  (.D(N_98_i), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_ICYCLE_6_i), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SMADDR_i[8] ));
    CFG4 #( .INIT(16'h55C0) )  \ACCUM_NEXT_m6_ns[4]  (.A(
        \ACCUM_NEXT_m6_ns_1[4]_net_1 ), .B(\ACCUMULATOR[5]_net_1 ), .C(
        ALUOUT_6_sqmuxa), .D(ICYCLE22), .Y(\ACCUM_NEXT_m6[4] ));
    CFG4 #( .INIT(16'h23EF) )  \ACCUM_NEXT_1_0[17]  (.A(ACCUM_NEXT_sm5)
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_m4[17]_net_1 ), 
        .D(\ACCUM_IN_RNIJ929P_S[17] ), .Y(\ACCUM_NEXT_1_0[17]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \xhdl_41.xhdl_40_l1.un5_flagvalue  (.A(
        N_7124_reto), .B(STD_ACCUM_ZERO_net_1), .Y(un5_flagvalue));
    CFG3 #( .INIT(8'hD8) )  \RAMWDATA[3]  (.A(N_130), .B(
        un1_SMADDR_cry_3_S), .C(COREABC_0_APB3master_PWDATA[3]), .Y(
        \RAMWDATA[3]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[22]  (.A(
        \ACCUM_IN[22]_net_1 ), .B(\ACCUMULATOR[21]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[22]_net_1 ));
    CFG4 #( .INIT(16'h23EF) )  \ACCUM_NEXT_1_0[27]  (.A(ACCUM_NEXT_sm5)
        , .B(\doins_0_dreg_RNIJ2TF[3] ), .C(\ACCUM_NEXT_m4[27]_net_1 ), 
        .D(\ACCUM_IN_RNIH2NI21_S[27] ), .Y(\ACCUM_NEXT_1[27] ));
    SLE \STKPTR[7]  (.D(\STKPTR_12[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\STKPTR[7]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[31]  (.A(
        \ACCUM_IN[31]_net_1 ), .B(\ACCUMULATOR[30]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[31]_net_1 ));
    CFG4 #( .INIT(16'hF01B) )  \ACCUM_NEXT_1_RNO[2]  (.A(
        ACCUM_NEXT_sm0), .B(\ACCUM_NEXT_m0[2]_net_1 ), .C(
        \ACCUM_NEXT_m5_4_1_0_0[2] ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m5_4_1_0[2] ));
    CFG4 #( .INIT(16'h0001) )  \to_logic_2.tmp_4_16[0]  (.A(
        \ACCUM_NEXT[10]_net_1 ), .B(\ACCUM_NEXT[9]_net_1 ), .C(
        \ACCUM_NEXT[12]_net_1 ), .D(\ACCUM_NEXT[11]_net_1 ), .Y(
        \tmp_4_16[0] ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_M[28]  (.A(N_83), .B(
        \ACCUMULATOR[28]_net_1 ), .Y(\COREABC_0_APB3master_PWDATA[28] )
        );
    CFG4 #( .INIT(16'h004F) )  \ACCUM_NEXT_1[21]  (.A(ACCUM_NEXT_sm0), 
        .B(\ACCUM_NEXT_m0[21]_net_1 ), .C(
        \ACCUM_NEXT_m4_1_0[21]_net_1 ), .D(\ACCUM_NEXT_1_sx[21]_net_1 )
        , .Y(\ACCUM_NEXT_1[21]_net_1 ));
    CFG4 #( .INIT(16'h0103) )  ALUOUT_1_sqmuxa (.A(N_915), .B(
        \MSEL[2] ), .C(N_7101_reto), .D(\INSTR_CMD[1] ), .Y(
        ALUOUT_1_sqmuxa_net_1));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNI2D6V1[1]  (.A(
        \ACCUM_IN[1]_net_1 ), .B(\MSEL[2] ), .C(\ACCUMULATOR[1]_net_1 )
        , .D(GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_0), .S(
        \ACCUM_IN_RNI2D6V1_S[1] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_1));
    CFG3 #( .INIT(8'hD5) )  \ACCUM_NEXT[22]  (.A(\ACCUM_NEXT_1[22] ), 
        .B(\ACCUMULATOR[23]_net_1 ), .C(ALUOUT_6_sqmuxa), .Y(
        \ACCUM_NEXT[22]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \STKPTR_12[4]  (.A(un1_STKPTRP1_cry_4_S), 
        .B(N_910), .C(un1_STKPTR_cry_4_S), .Y(\STKPTR_12[4]_net_1 ));
    ARI1 #( .INIT(20'h566CC) )  \ACCUM_IN_RNILFKTM[15]  (.A(\MSEL[2] ), 
        .B(\ACCUM_IN[15]_net_1 ), .C(\ACCUMULATOR[15]_net_1 ), .D(
        GND_net_1), .FCI(ACCUM_NEXT_m5_0_cry_14), .S(
        \ACCUM_IN_RNILFKTM_S[15] ), .Y(), .FCO(ACCUM_NEXT_m5_0_cry_15));
    ARI1 #( .INIT(20'h531CE) )  un1_STKPTR_cry_2 (.A(\STKPTR[2]_net_1 )
        , .B(N_111_1), .C(N_126), .D(N_7101_reto), .FCI(
        un1_STKPTR_cry_1_net_1), .S(un1_STKPTR_cry_2_S), .Y(), .FCO(
        un1_STKPTR_cry_2_net_1));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[16]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[16] ), .Y(\RAMWDATA[16]_net_1 ));
    CFG4 #( .INIT(16'h3AAA) )  \SMADDR_RNO[0]  (.A(N_694_i_1), .B(
        \RAMRDATA[0] ), .C(DOJMP_net_1), .D(\INSTR_CMD[1] ), .Y(
        N_694_i));
    CFG4 #( .INIT(16'h770F) )  \ACCUM_NEXT_m4_1_0[23]  (.A(
        \ACCUM_IN[23]_net_1 ), .B(\ACCUMULATOR[23]_net_1 ), .C(
        \ACCUM_NEXT_m1[23]_net_1 ), .D(ALUOUT_1_sqmuxa_net_1), .Y(
        \ACCUM_NEXT_m4_1_0[23]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \ACCUM_IN[6]  (.A(N_915), .B(N_7129_reto), 
        .C(\RAMRDATA[6] ), .Y(\ACCUM_IN[6]_net_1 ));
    SLE \ACCUMULATOR[18]  (.D(\ACCUM_NEXT[18]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(ACCUMULATOR4_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ACCUMULATOR[18]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \RAMWDATA[19]  (.A(N_130), .B(
        \COREABC_0_APB3master_PWDATA[19] ), .Y(\RAMWDATA[19]_net_1 ));
    CFG4 #( .INIT(16'hC4C5) )  DOJMP_55 (.A(\ICYCLE[1]_net_1 ), .B(
        DOJMP_net_1), .C(un1_ICYCLE_8_0_0_net_1), .D(N_88), .Y(
        DOJMP_55_net_1));
    CFG4 #( .INIT(16'h1D3F) )  \ACCUM_NEXT_m6_ns_1[4]  (.A(
        CoreAPB3_0_APBmslave0_PSELx), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(iPRDATA_3), .D(APB_register_blk_0_PRDATA_3), .Y(
        \ACCUM_NEXT_m6_ns_1[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m3[11]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[12]_net_1 ), .Y(\ACCUM_NEXT_m3[11]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \SMADDR_RNO_0[4]  (.A(DOJMP_net_1), .B(
        un1_SMADDR_cry_4_S), .C(N_7111_reto), .Y(N_799_i_1));
    CFG2 #( .INIT(4'h8) )  \ACCUM_NEXT_m6[19]  (.A(ALUOUT_6_sqmuxa), 
        .B(\ACCUMULATOR[20]_net_1 ), .Y(ACCUM_NEXT_41));
    CFG3 #( .INIT(8'hAC) )  \ACCUM_NEXT_m0[17]  (.A(
        \ACCUM_IN[17]_net_1 ), .B(\ACCUMULATOR[16]_net_1 ), .C(
        \MSEL[1] ), .Y(\ACCUM_NEXT_m0[17]_net_1 ));
    
endmodule


module Nibble2Ascii(
       syssvc_blk_0_NRBG_HANDLE,
       reg0_16_0
    );
input  [7:5] syssvc_blk_0_NRBG_HANDLE;
output reg0_16_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h57) )  \un1_IsDecimal_1.CO3  (.A(
        syssvc_blk_0_NRBG_HANDLE[7]), .B(syssvc_blk_0_NRBG_HANDLE[6]), 
        .C(syssvc_blk_0_NRBG_HANDLE[5]), .Y(reg0_16_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module Nibble2Ascii_0(
       syssvc_blk_0_NRBG_HANDLE,
       reg0_16_0
    );
input  [3:1] syssvc_blk_0_NRBG_HANDLE;
output reg0_16_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h57) )  \un1_IsDecimal_1.CO3_0_o2  (.A(
        syssvc_blk_0_NRBG_HANDLE[3]), .B(syssvc_blk_0_NRBG_HANDLE[2]), 
        .C(syssvc_blk_0_NRBG_HANDLE[1]), .Y(reg0_16_0));
    
endmodule


module Binary2Ascii(
       syssvc_blk_0_NRBG_HANDLE,
       reg0_16_0,
       reg0_16_8
    );
input  [7:1] syssvc_blk_0_NRBG_HANDLE;
output reg0_16_0;
output reg0_16_8;

    wire GND_net_1, VCC_net_1;
    
    Nibble2Ascii MSB (.syssvc_blk_0_NRBG_HANDLE({
        syssvc_blk_0_NRBG_HANDLE[7], syssvc_blk_0_NRBG_HANDLE[6], 
        syssvc_blk_0_NRBG_HANDLE[5]}), .reg0_16_0(reg0_16_0));
    Nibble2Ascii_0 LSB (.syssvc_blk_0_NRBG_HANDLE({
        syssvc_blk_0_NRBG_HANDLE[3], syssvc_blk_0_NRBG_HANDLE[2], 
        syssvc_blk_0_NRBG_HANDLE[1]}), .reg0_16_0(reg0_16_8));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module Nibble2Ascii_5(
       syssvc_blk_0_NRBG_DATA,
       N_392
    );
input  [15:12] syssvc_blk_0_NRBG_DATA;
output N_392;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h3D33) )  \un9_ascii_1.SUM[1]  (.A(
        syssvc_blk_0_NRBG_DATA[14]), .B(syssvc_blk_0_NRBG_DATA[13]), 
        .C(syssvc_blk_0_NRBG_DATA[12]), .D(syssvc_blk_0_NRBG_DATA[15]), 
        .Y(N_392));
    
endmodule


module Nibble2Ascii_6(
       syssvc_blk_0_NRBG_DATA,
       N_514
    );
input  [11:8] syssvc_blk_0_NRBG_DATA;
output N_514;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h2220) )  \un9_ascii_1.CO0_i_a2  (.A(
        syssvc_blk_0_NRBG_DATA[11]), .B(syssvc_blk_0_NRBG_DATA[8]), .C(
        syssvc_blk_0_NRBG_DATA[10]), .D(syssvc_blk_0_NRBG_DATA[9]), .Y(
        N_514));
    
endmodule


module Binary2Ascii_2(
       syssvc_blk_0_NRBG_DATA,
       N_514,
       N_392
    );
input  [15:8] syssvc_blk_0_NRBG_DATA;
output N_514;
output N_392;

    wire GND_net_1, VCC_net_1;
    
    Nibble2Ascii_5 MSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[15], syssvc_blk_0_NRBG_DATA[14], 
        syssvc_blk_0_NRBG_DATA[13], syssvc_blk_0_NRBG_DATA[12]}), 
        .N_392(N_392));
    Nibble2Ascii_6 LSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[11], syssvc_blk_0_NRBG_DATA[10], 
        syssvc_blk_0_NRBG_DATA[9], syssvc_blk_0_NRBG_DATA[8]}), .N_514(
        N_514));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module Nibble2Ascii_2(
       syssvc_blk_0_NRBG_DATA,
       reg1_16_0
    );
input  [27:25] syssvc_blk_0_NRBG_DATA;
output reg1_16_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h57) )  \un1_IsDecimal_1.CO3_0_o2  (.A(
        syssvc_blk_0_NRBG_DATA[27]), .B(syssvc_blk_0_NRBG_DATA[26]), 
        .C(syssvc_blk_0_NRBG_DATA[25]), .Y(reg1_16_0));
    
endmodule


module Binary2Ascii_0(
       syssvc_blk_0_NRBG_DATA,
       reg1_16_0
    );
input  [27:25] syssvc_blk_0_NRBG_DATA;
output reg1_16_0;

    wire GND_net_1, VCC_net_1;
    
    Nibble2Ascii_2 LSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[27], syssvc_blk_0_NRBG_DATA[26], 
        syssvc_blk_0_NRBG_DATA[25]}), .reg1_16_0(reg1_16_0));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module Nibble2Ascii_7(
       reg2_16_0,
       syssvc_blk_0_NRBG_DATA_25,
       syssvc_blk_0_NRBG_DATA_27,
       syssvc_blk_0_NRBG_DATA_24,
       syssvc_blk_0_NRBG_DATA_26,
       syssvc_blk_0_NRBG_DATA_0,
       syssvc_blk_0_NRBG_DATA_3,
       syssvc_blk_0_NRBG_DATA_1,
       syssvc_blk_0_NRBG_DATA_2,
       syssvc_blk_0_NRBG_DATA_11,
       syssvc_blk_0_NRBG_DATA_10,
       syssvc_blk_0_NRBG_DATA_9,
       syssvc_blk_0_NRBG_DATA_19,
       syssvc_blk_0_NRBG_DATA_17,
       syssvc_blk_0_NRBG_DATA_18,
       reg3_16_0,
       reg4_16_0,
       N_416,
       N_588,
       N_187,
       PRDATA19,
       N_585,
       N_30_mux
    );
output reg2_16_0;
input  syssvc_blk_0_NRBG_DATA_25;
input  syssvc_blk_0_NRBG_DATA_27;
input  syssvc_blk_0_NRBG_DATA_24;
input  syssvc_blk_0_NRBG_DATA_26;
input  syssvc_blk_0_NRBG_DATA_0;
input  syssvc_blk_0_NRBG_DATA_3;
input  syssvc_blk_0_NRBG_DATA_1;
input  syssvc_blk_0_NRBG_DATA_2;
input  syssvc_blk_0_NRBG_DATA_11;
input  syssvc_blk_0_NRBG_DATA_10;
input  syssvc_blk_0_NRBG_DATA_9;
input  syssvc_blk_0_NRBG_DATA_19;
input  syssvc_blk_0_NRBG_DATA_17;
input  syssvc_blk_0_NRBG_DATA_18;
output reg3_16_0;
output reg4_16_0;
output N_416;
output N_588;
output N_187;
input  PRDATA19;
output N_585;
output N_30_mux;

    wire m17_am, m17_bm, GND_net_1, VCC_net_1;
    
    CFG4 #( .INIT(16'h3D33) )  \un9_ascii_1.SUM[1]  (.A(
        syssvc_blk_0_NRBG_DATA_2), .B(syssvc_blk_0_NRBG_DATA_1), .C(
        syssvc_blk_0_NRBG_DATA_0), .D(syssvc_blk_0_NRBG_DATA_3), .Y(
        N_416));
    CFG3 #( .INIT(8'h02) )  \un9_ascii_1.m8  (.A(
        syssvc_blk_0_NRBG_DATA_3), .B(syssvc_blk_0_NRBG_DATA_2), .C(
        syssvc_blk_0_NRBG_DATA_1), .Y(reg4_16_0));
    CFG3 #( .INIT(8'h57) )  \un9_ascii_1.m17_am  (.A(
        syssvc_blk_0_NRBG_DATA_11), .B(syssvc_blk_0_NRBG_DATA_10), .C(
        syssvc_blk_0_NRBG_DATA_9), .Y(m17_am));
    CFG3 #( .INIT(8'hE2) )  \un9_ascii_1.m17_ns  (.A(m17_am), .B(
        PRDATA19), .C(m17_bm), .Y(N_187));
    CFG4 #( .INIT(16'h0C08) )  \un9_ascii_1.m16  (.A(
        syssvc_blk_0_NRBG_DATA_25), .B(syssvc_blk_0_NRBG_DATA_27), .C(
        syssvc_blk_0_NRBG_DATA_24), .D(syssvc_blk_0_NRBG_DATA_26), .Y(
        N_30_mux));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h02) )  \un9_ascii_1.m9  (.A(
        syssvc_blk_0_NRBG_DATA_11), .B(syssvc_blk_0_NRBG_DATA_10), .C(
        syssvc_blk_0_NRBG_DATA_9), .Y(reg3_16_0));
    CFG3 #( .INIT(8'h57) )  \un9_ascii_1.m17_bm  (.A(
        syssvc_blk_0_NRBG_DATA_3), .B(syssvc_blk_0_NRBG_DATA_2), .C(
        syssvc_blk_0_NRBG_DATA_1), .Y(m17_bm));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h57) )  \un9_ascii_1.m14  (.A(
        syssvc_blk_0_NRBG_DATA_19), .B(syssvc_blk_0_NRBG_DATA_17), .C(
        syssvc_blk_0_NRBG_DATA_18), .Y(reg2_16_0));
    CFG4 #( .INIT(16'hFB00) )  \un9_ascii_1.m23  (.A(
        syssvc_blk_0_NRBG_DATA_0), .B(syssvc_blk_0_NRBG_DATA_3), .C(
        syssvc_blk_0_NRBG_DATA_1), .D(syssvc_blk_0_NRBG_DATA_2), .Y(
        N_585));
    CFG3 #( .INIT(8'h02) )  \un9_ascii_1.m26_e  (.A(
        syssvc_blk_0_NRBG_DATA_27), .B(syssvc_blk_0_NRBG_DATA_25), .C(
        syssvc_blk_0_NRBG_DATA_26), .Y(N_588));
    
endmodule


module Nibble2Ascii_8(
       syssvc_blk_0_NRBG_DATA,
       reg4_16_0,
       N_486
    );
input  [3:0] syssvc_blk_0_NRBG_DATA;
output reg4_16_0;
output N_486;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'h02FF) )  \un9_ascii_1.SUM_0_x2[2]  (.A(
        syssvc_blk_0_NRBG_DATA[3]), .B(syssvc_blk_0_NRBG_DATA[1]), .C(
        syssvc_blk_0_NRBG_DATA[0]), .D(syssvc_blk_0_NRBG_DATA[2]), .Y(
        N_486));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h57) )  \un1_IsDecimal_1.CO3_0_o2  (.A(
        syssvc_blk_0_NRBG_DATA[3]), .B(syssvc_blk_0_NRBG_DATA[1]), .C(
        syssvc_blk_0_NRBG_DATA[2]), .Y(reg4_16_0));
    
endmodule


module Binary2Ascii_3(
       syssvc_blk_0_NRBG_DATA_29,
       syssvc_blk_0_NRBG_DATA_31,
       syssvc_blk_0_NRBG_DATA_28,
       syssvc_blk_0_NRBG_DATA_30,
       syssvc_blk_0_NRBG_DATA_4,
       syssvc_blk_0_NRBG_DATA_7,
       syssvc_blk_0_NRBG_DATA_5,
       syssvc_blk_0_NRBG_DATA_6,
       syssvc_blk_0_NRBG_DATA_15,
       syssvc_blk_0_NRBG_DATA_14,
       syssvc_blk_0_NRBG_DATA_13,
       syssvc_blk_0_NRBG_DATA_23,
       syssvc_blk_0_NRBG_DATA_21,
       syssvc_blk_0_NRBG_DATA_22,
       syssvc_blk_0_NRBG_DATA_0,
       syssvc_blk_0_NRBG_DATA_1,
       syssvc_blk_0_NRBG_DATA_2,
       syssvc_blk_0_NRBG_DATA_3,
       reg4_16_0,
       reg4_16_9,
       reg3_16_0,
       reg2_16_0,
       N_486,
       N_30_mux,
       N_585,
       PRDATA19,
       N_187,
       N_588,
       N_416
    );
input  syssvc_blk_0_NRBG_DATA_29;
input  syssvc_blk_0_NRBG_DATA_31;
input  syssvc_blk_0_NRBG_DATA_28;
input  syssvc_blk_0_NRBG_DATA_30;
input  syssvc_blk_0_NRBG_DATA_4;
input  syssvc_blk_0_NRBG_DATA_7;
input  syssvc_blk_0_NRBG_DATA_5;
input  syssvc_blk_0_NRBG_DATA_6;
input  syssvc_blk_0_NRBG_DATA_15;
input  syssvc_blk_0_NRBG_DATA_14;
input  syssvc_blk_0_NRBG_DATA_13;
input  syssvc_blk_0_NRBG_DATA_23;
input  syssvc_blk_0_NRBG_DATA_21;
input  syssvc_blk_0_NRBG_DATA_22;
input  syssvc_blk_0_NRBG_DATA_0;
input  syssvc_blk_0_NRBG_DATA_1;
input  syssvc_blk_0_NRBG_DATA_2;
input  syssvc_blk_0_NRBG_DATA_3;
output reg4_16_0;
output reg4_16_9;
output reg3_16_0;
output reg2_16_0;
output N_486;
output N_30_mux;
output N_585;
input  PRDATA19;
output N_187;
output N_588;
output N_416;

    wire GND_net_1, VCC_net_1;
    
    Nibble2Ascii_7 MSB (.reg2_16_0(reg2_16_0), 
        .syssvc_blk_0_NRBG_DATA_25(syssvc_blk_0_NRBG_DATA_29), 
        .syssvc_blk_0_NRBG_DATA_27(syssvc_blk_0_NRBG_DATA_31), 
        .syssvc_blk_0_NRBG_DATA_24(syssvc_blk_0_NRBG_DATA_28), 
        .syssvc_blk_0_NRBG_DATA_26(syssvc_blk_0_NRBG_DATA_30), 
        .syssvc_blk_0_NRBG_DATA_0(syssvc_blk_0_NRBG_DATA_4), 
        .syssvc_blk_0_NRBG_DATA_3(syssvc_blk_0_NRBG_DATA_7), 
        .syssvc_blk_0_NRBG_DATA_1(syssvc_blk_0_NRBG_DATA_5), 
        .syssvc_blk_0_NRBG_DATA_2(syssvc_blk_0_NRBG_DATA_6), 
        .syssvc_blk_0_NRBG_DATA_11(syssvc_blk_0_NRBG_DATA_15), 
        .syssvc_blk_0_NRBG_DATA_10(syssvc_blk_0_NRBG_DATA_14), 
        .syssvc_blk_0_NRBG_DATA_9(syssvc_blk_0_NRBG_DATA_13), 
        .syssvc_blk_0_NRBG_DATA_19(syssvc_blk_0_NRBG_DATA_23), 
        .syssvc_blk_0_NRBG_DATA_17(syssvc_blk_0_NRBG_DATA_21), 
        .syssvc_blk_0_NRBG_DATA_18(syssvc_blk_0_NRBG_DATA_22), 
        .reg3_16_0(reg3_16_0), .reg4_16_0(reg4_16_0), .N_416(N_416), 
        .N_588(N_588), .N_187(N_187), .PRDATA19(PRDATA19), .N_585(
        N_585), .N_30_mux(N_30_mux));
    Nibble2Ascii_8 LSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA_3, syssvc_blk_0_NRBG_DATA_2, 
        syssvc_blk_0_NRBG_DATA_1, syssvc_blk_0_NRBG_DATA_0}), 
        .reg4_16_0(reg4_16_9), .N_486(N_486));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module Nibble2Ascii_3(
       syssvc_blk_0_NRBG_DATA,
       N_399
    );
input  [23:20] syssvc_blk_0_NRBG_DATA;
output N_399;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h333B) )  \un9_ascii_1.SUM[2]  (.A(
        syssvc_blk_0_NRBG_DATA[23]), .B(syssvc_blk_0_NRBG_DATA[22]), 
        .C(syssvc_blk_0_NRBG_DATA[20]), .D(syssvc_blk_0_NRBG_DATA[21]), 
        .Y(N_399));
    
endmodule


module Nibble2Ascii_4(
       syssvc_blk_0_NRBG_DATA,
       reg2_16_0
    );
input  [19:17] syssvc_blk_0_NRBG_DATA;
output reg2_16_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h57) )  \un1_IsDecimal_1.CO3_0_o2  (.A(
        syssvc_blk_0_NRBG_DATA[19]), .B(syssvc_blk_0_NRBG_DATA[18]), 
        .C(syssvc_blk_0_NRBG_DATA[17]), .Y(reg2_16_0));
    
endmodule


module Binary2Ascii_1(
       syssvc_blk_0_NRBG_DATA,
       reg2_16_0,
       N_399
    );
input  [23:17] syssvc_blk_0_NRBG_DATA;
output reg2_16_0;
output N_399;

    wire GND_net_1, VCC_net_1;
    
    Nibble2Ascii_3 MSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[23], syssvc_blk_0_NRBG_DATA[22], 
        syssvc_blk_0_NRBG_DATA[21], syssvc_blk_0_NRBG_DATA[20]}), 
        .N_399(N_399));
    Nibble2Ascii_4 LSB (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[19], syssvc_blk_0_NRBG_DATA[18], 
        syssvc_blk_0_NRBG_DATA[17]}), .reg2_16_0(reg2_16_0));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module APB_register_blk(
       syssvc_blk_0_NRBG_DATA,
       syssvc_blk_0_NRBG_HANDLE,
       COREABC_0_APB3master_PWDATA,
       APB_register_blk_0_PRDATA,
       COREABC_0_APB3master_PADDR_i_0,
       N_7112_reto,
       N_7107_reto,
       CoreAPB3_0_APBmslave0_PSELx,
       COREABC_0_APB3master_PENABLE,
       COREABC_0_APB3master_PWRITE,
       N_7108_reto,
       N_7115_reto,
       N_7109_reto,
       N_7110_reto,
       N_7119_reto,
       N_7111_reto,
       UART_top_0_INSTANTIATE_SERVICE,
       UART_top_0_SELF_TEST_SERVICE,
       UART_top_0_START_sysservice,
       APB_register_blk_0_PREADY,
       UART_top_0_GENERATE_SERVICE,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
input  [31:0] syssvc_blk_0_NRBG_DATA;
input  [7:0] syssvc_blk_0_NRBG_HANDLE;
input  [3:0] COREABC_0_APB3master_PWDATA;
output [14:0] APB_register_blk_0_PRDATA;
input  COREABC_0_APB3master_PADDR_i_0;
input  N_7112_reto;
input  N_7107_reto;
input  CoreAPB3_0_APBmslave0_PSELx;
input  COREABC_0_APB3master_PENABLE;
input  COREABC_0_APB3master_PWRITE;
input  N_7108_reto;
input  N_7115_reto;
input  N_7109_reto;
input  N_7110_reto;
input  N_7119_reto;
input  N_7111_reto;
output UART_top_0_INSTANTIATE_SERVICE;
output UART_top_0_SELF_TEST_SERVICE;
output UART_top_0_START_sysservice;
output APB_register_blk_0_PREADY;
output UART_top_0_GENERATE_SERVICE;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire VCC_net_1, N_537_i, N_221, GND_net_1, N_534_i, N_525_i, 
        N_465_i, N_150_mux_i, N_148_mux_i, N_147_mux_i, N_151_mux_i, 
        N_145_mux_i, N_144_mux_i, N_73_i, N_63_i, 
        GENERATE_SERVICE_0_sqmuxa, \fsm[1]_net_1 , N_79_i, 
        \fsm[0]_net_1 , \fsm_ns[0] , N_526, N_127_mux, \reg4_16[12] , 
        PRDATA18, PRDATA19, PRDATA_9_i_m2_net_1, m39_1_0, N_542, N_2_0, 
        N_499, N_496, \PRDATA_1_RNO_0[2]_net_1 , 
        \PRDATA_1_RNO_1[2]_net_1 , m15_e_0, \PRDATA_1_RNO_0[1]_net_1 , 
        \PRDATA_1_RNO_1[1]_net_1 , \PRDATA_1_RNO_0[3]_net_1 , 
        \PRDATA_1_RNO_1[3]_net_1 , N_539_i, m72_4_1, 
        \PRDATA_1_RNO_2[8]_net_1 , m101_am_1_1, N_585, N_537_i_1_0, 
        N_132_mux, N_486, N_63_i_1_0, N_514, N_60, N_534_i_1_0, m28_0, 
        N_531, N_525_i_1_1, N_523, N_145_mux_i_1, N_187, \reg2_16[4] , 
        PRDATA17, N_547, N_491, N_144_mux_i_1, m92, m94_bm_1, N_588, 
        PRDATA16, m59_0, m59, m59_1_0, N_8_0, 
        \PRDATA_9_i_m2_1[14]_net_1 , N_474, PRDATA15, \reg2_16[12] , 
        N_472, m39_0, m39, m21_1_1, \reg1_16[12] , \reg0_16[12] , 
        m67_1_1, N_540, \PRDATA_1_RNO_3[8]_net_1 , \reg0_16[4] , 
        \PRDATA_9_0_i_m2_ns_1[0]_net_1 , N_503, N_183, N_215, 
        \PRDATA_9_1_am[0]_net_1 , \PRDATA_9_1_bm[0]_net_1 , N_541, 
        N_30_mux, m99_0, \PRDATA_9_2_0_a2_0[11]_net_1 , 
        PRDATA19_0_a2_0_a2_1_net_1, PRDATA19_0_a2_0_3_net_1, 
        \PRDATA_9_2_i_0[9]_net_1 , \PRDATA_9_2_i_0[10]_net_1 , 
        GENERATE_SERVICE_0_sqmuxa_0_a2_0_a2_2_net_1, N_5_0, N_656, 
        N_9_0, N_6_0, m106, m99, m50_1, N_111, N_105, m106_0, m50_0, 
        m50, \reg4_16[3] , \reg3_16[3] , N_399, m99_1, N_416, N_392;
    
    Binary2Ascii u0 (.syssvc_blk_0_NRBG_HANDLE({
        syssvc_blk_0_NRBG_HANDLE[7], syssvc_blk_0_NRBG_HANDLE[6], 
        syssvc_blk_0_NRBG_HANDLE[5], nc0, syssvc_blk_0_NRBG_HANDLE[3], 
        syssvc_blk_0_NRBG_HANDLE[2], syssvc_blk_0_NRBG_HANDLE[1]}), 
        .reg0_16_0(\reg0_16[4] ), .reg0_16_8(\reg0_16[12] ));
    CFG4 #( .INIT(16'h0F99) )  \PRDATA_9_0_i_m2_ns[0]  (.A(
        syssvc_blk_0_NRBG_HANDLE[4]), .B(\reg0_16[4] ), .C(
        \PRDATA_9_0_i_m2_ns_1[0]_net_1 ), .D(PRDATA16), .Y(N_503));
    CFG4 #( .INIT(16'h70F0) )  \PRDATA_1_RNO_3[3]  (.A(\reg2_16[4] ), 
        .B(syssvc_blk_0_NRBG_DATA[23]), .C(N_547), .D(PRDATA17), .Y(
        m94_bm_1));
    SLE \PRDATA_1[6]  (.D(N_144_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[6]));
    CFG4 #( .INIT(16'h0200) )  \PRDATA_1_RNO_7[10]  (.A(
        syssvc_blk_0_NRBG_DATA[26]), .B(syssvc_blk_0_NRBG_DATA[25]), 
        .C(syssvc_blk_0_NRBG_DATA[24]), .D(syssvc_blk_0_NRBG_DATA[27]), 
        .Y(N_9_0));
    CFG3 #( .INIT(8'h10) )  \PRDATA_1_RNO_5[2]  (.A(
        syssvc_blk_0_NRBG_DATA[13]), .B(syssvc_blk_0_NRBG_DATA[12]), 
        .C(syssvc_blk_0_NRBG_DATA[15]), .Y(m101_am_1_1));
    CFG3 #( .INIT(8'h90) )  \PRDATA_1_RNO_4[1]  (.A(
        syssvc_blk_0_NRBG_DATA[29]), .B(N_30_mux), .C(PRDATA16), .Y(
        m106_0));
    CFG4 #( .INIT(16'hA900) )  \PRDATA_1_RNO_3[1]  (.A(
        syssvc_blk_0_NRBG_DATA[21]), .B(syssvc_blk_0_NRBG_DATA[20]), 
        .C(\reg2_16[4] ), .D(PRDATA17), .Y(N_105));
    CFG4 #( .INIT(16'h0600) )  \PRDATA_1_RNO_2[1]  (.A(N_496), .B(
        syssvc_blk_0_NRBG_HANDLE[5]), .C(PRDATA16), .D(PRDATA15), .Y(
        m106));
    SLE \PRDATA_1[3]  (.D(N_151_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[3]));
    CFG4 #( .INIT(16'h0F1B) )  \PRDATA_9_i_m2_1[14]  (.A(PRDATA15), .B(
        \reg2_16[12] ), .C(N_472), .D(PRDATA16), .Y(
        \PRDATA_9_i_m2_1[14]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \PRDATA_9_1_ns[0]  (.A(
        \PRDATA_9_1_am[0]_net_1 ), .B(PRDATA19), .C(
        \PRDATA_9_1_bm[0]_net_1 ), .Y(N_183));
    CFG4 #( .INIT(16'h0040) )  \PRDATA_1_RNO_2[10]  (.A(
        syssvc_blk_0_NRBG_DATA[8]), .B(syssvc_blk_0_NRBG_DATA[11]), .C(
        syssvc_blk_0_NRBG_DATA[10]), .D(syssvc_blk_0_NRBG_DATA[9]), .Y(
        N_526));
    CFG3 #( .INIT(8'h10) )  \fsm_ns_0_a2_0_a2[0]  (.A(\fsm[1]_net_1 ), 
        .B(\fsm[0]_net_1 ), .C(CoreAPB3_0_APBmslave0_PSELx), .Y(
        \fsm_ns[0] ));
    CFG3 #( .INIT(8'hAC) )  \PRDATA_1_RNO_1[1]  (.A(N_416), .B(N_392), 
        .C(PRDATA19), .Y(\PRDATA_1_RNO_1[1]_net_1 ));
    CFG4 #( .INIT(16'hFFAE) )  \PRDATA_1_RNO_0[1]  (.A(m106), .B(N_547)
        , .C(N_105), .D(m106_0), .Y(\PRDATA_1_RNO_0[1]_net_1 ));
    CFG4 #( .INIT(16'hC1F1) )  \PRDATA_1_RNO[8]  (.A(N_539_i), .B(
        PRDATA19), .C(m72_4_1), .D(\PRDATA_1_RNO_2[8]_net_1 ), .Y(
        N_73_i));
    CFG3 #( .INIT(8'h20) )  un1_fsm_1_i_a2 (.A(\fsm[0]_net_1 ), .B(
        COREABC_0_APB3master_PWRITE), .C(COREABC_0_APB3master_PENABLE), 
        .Y(N_221));
    CFG4 #( .INIT(16'h335F) )  \PRDATA_1_RNO_2[12]  (.A(\reg2_16[12] ), 
        .B(\reg0_16[12] ), .C(PRDATA17), .D(PRDATA15), .Y(m21_1_1));
    Binary2Ascii_2 u3 (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[15], syssvc_blk_0_NRBG_DATA[14], 
        syssvc_blk_0_NRBG_DATA[13], syssvc_blk_0_NRBG_DATA[12], 
        syssvc_blk_0_NRBG_DATA[11], syssvc_blk_0_NRBG_DATA[10], 
        syssvc_blk_0_NRBG_DATA[9], syssvc_blk_0_NRBG_DATA[8]}), .N_514(
        N_514), .N_392(N_392));
    CFG4 #( .INIT(16'h0E00) )  \PRDATA_1_RNO_7[9]  (.A(
        syssvc_blk_0_NRBG_DATA[26]), .B(syssvc_blk_0_NRBG_DATA[25]), 
        .C(syssvc_blk_0_NRBG_DATA[24]), .D(syssvc_blk_0_NRBG_DATA[27]), 
        .Y(N_8_0));
    CFG2 #( .INIT(4'h6) )  \PRDATA_1_RNO_5[9]  (.A(N_8_0), .B(
        syssvc_blk_0_NRBG_DATA[25]), .Y(m59_1_0));
    CFG3 #( .INIT(8'hFE) )  \PRDATA_1_RNO_1[10]  (.A(m50_1), .B(m50), 
        .C(m50_0), .Y(N_132_mux));
    SLE PREADY (.D(\fsm[1]_net_1 ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_79_i), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PREADY));
    CFG4 #( .INIT(16'h000D) )  \PRDATA_1_RNO_3[2]  (.A(PRDATA17), .B(
        N_399), .C(PRDATA16), .D(PRDATA15), .Y(m99_1));
    CFG3 #( .INIT(8'h53) )  \PRDATA_1_RNO[1]  (.A(
        \PRDATA_1_RNO_0[1]_net_1 ), .B(\PRDATA_1_RNO_1[1]_net_1 ), .C(
        m15_e_0), .Y(N_148_mux_i));
    SLE INSTANTIATE_SERVICE (.D(COREABC_0_APB3master_PWDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(GENERATE_SERVICE_0_sqmuxa), 
        .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(UART_top_0_INSTANTIATE_SERVICE)
        );
    CFG4 #( .INIT(16'h0E00) )  \PRDATA_1_RNO_6[9]  (.A(
        syssvc_blk_0_NRBG_HANDLE[2]), .B(syssvc_blk_0_NRBG_HANDLE[1]), 
        .C(syssvc_blk_0_NRBG_HANDLE[0]), .D(
        syssvc_blk_0_NRBG_HANDLE[3]), .Y(N_5_0));
    CFG3 #( .INIT(8'h3A) )  \PRDATA_1_RNO_1[12]  (.A(m21_1_1), .B(
        \reg1_16[12] ), .C(PRDATA16), .Y(N_523));
    VCC VCC (.Y(VCC_net_1));
    Binary2Ascii_0 u1 (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[27], syssvc_blk_0_NRBG_DATA[26], 
        syssvc_blk_0_NRBG_DATA[25]}), .reg1_16_0(\reg1_16[12] ));
    CFG4 #( .INIT(16'hCC50) )  PRDATA_9_i_m2 (.A(N_127_mux), .B(
        \reg4_16[12] ), .C(PRDATA18), .D(PRDATA19), .Y(
        PRDATA_9_i_m2_net_1));
    CFG4 #( .INIT(16'h0700) )  \PRDATA_1_RNO_2[3]  (.A(\reg0_16[4] ), 
        .B(syssvc_blk_0_NRBG_HANDLE[7]), .C(PRDATA16), .D(PRDATA15), 
        .Y(m92));
    CFG4 #( .INIT(16'h6500) )  \PRDATA_1_RNO_2[2]  (.A(
        syssvc_blk_0_NRBG_DATA[30]), .B(syssvc_blk_0_NRBG_DATA[29]), 
        .C(N_30_mux), .D(PRDATA16), .Y(m99_0));
    CFG3 #( .INIT(8'hE2) )  \PRDATA_1_RNO_3[8]  (.A(N_542), .B(
        PRDATA18), .C(PRDATA16), .Y(\PRDATA_1_RNO_3[8]_net_1 ));
    CFG2 #( .INIT(4'h1) )  PRDATA18_0_a2_1_a2_RNIU89I (.A(PRDATA18), 
        .B(PRDATA19), .Y(m15_e_0));
    SLE \PRDATA_1[11]  (.D(N_534_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[11]));
    CFG4 #( .INIT(16'h4000) )  PRDATA17_0_a2_0_a2 (.A(N_7109_reto), .B(
        N_7119_reto), .C(N_656), .D(N_7110_reto), .Y(PRDATA17));
    CFG4 #( .INIT(16'h0007) )  \PRDATA_1_RNO_4[11]  (.A(PRDATA17), .B(
        \PRDATA_9_2_0_a2_0[11]_net_1 ), .C(PRDATA16), .D(PRDATA15), .Y(
        m39));
    CFG4 #( .INIT(16'h0600) )  \PRDATA_1_RNO_3[11]  (.A(\reg0_16[12] ), 
        .B(syssvc_blk_0_NRBG_HANDLE[3]), .C(PRDATA16), .D(PRDATA15), 
        .Y(m39_0));
    CFG3 #( .INIT(8'h53) )  \PRDATA_1_RNO_1[3]  (.A(\reg4_16[3] ), .B(
        \reg3_16[3] ), .C(PRDATA19), .Y(\PRDATA_1_RNO_1[3]_net_1 ));
    CFG3 #( .INIT(8'hFE) )  \PRDATA_1_RNO_0[2]  (.A(m99_0), .B(m99_1), 
        .C(m99), .Y(\PRDATA_1_RNO_0[2]_net_1 ));
    CFG4 #( .INIT(16'h4ECC) )  \PRDATA_1_RNO[0]  (.A(N_547), .B(N_215), 
        .C(N_111), .D(m15_e_0), .Y(N_150_mux_i));
    SLE \PRDATA_1[8]  (.D(N_73_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[8]));
    CFG4 #( .INIT(16'h660F) )  \PRDATA_1_RNO_1[9]  (.A(N_514), .B(
        syssvc_blk_0_NRBG_DATA[9]), .C(N_60), .D(PRDATA18), .Y(
        N_63_i_1_0));
    CFG4 #( .INIT(16'h9F90) )  \PRDATA_1_RNO[11]  (.A(
        syssvc_blk_0_NRBG_DATA[3]), .B(\reg4_16[12] ), .C(PRDATA19), 
        .D(N_534_i_1_0), .Y(N_534_i));
    Binary2Ascii_3 u4 (.syssvc_blk_0_NRBG_DATA_29(
        syssvc_blk_0_NRBG_DATA[29]), .syssvc_blk_0_NRBG_DATA_31(
        syssvc_blk_0_NRBG_DATA[31]), .syssvc_blk_0_NRBG_DATA_28(
        syssvc_blk_0_NRBG_DATA[28]), .syssvc_blk_0_NRBG_DATA_30(
        syssvc_blk_0_NRBG_DATA[30]), .syssvc_blk_0_NRBG_DATA_4(
        syssvc_blk_0_NRBG_DATA[4]), .syssvc_blk_0_NRBG_DATA_7(
        syssvc_blk_0_NRBG_DATA[7]), .syssvc_blk_0_NRBG_DATA_5(
        syssvc_blk_0_NRBG_DATA[5]), .syssvc_blk_0_NRBG_DATA_6(
        syssvc_blk_0_NRBG_DATA[6]), .syssvc_blk_0_NRBG_DATA_15(
        syssvc_blk_0_NRBG_DATA[15]), .syssvc_blk_0_NRBG_DATA_14(
        syssvc_blk_0_NRBG_DATA[14]), .syssvc_blk_0_NRBG_DATA_13(
        syssvc_blk_0_NRBG_DATA[13]), .syssvc_blk_0_NRBG_DATA_23(
        syssvc_blk_0_NRBG_DATA[23]), .syssvc_blk_0_NRBG_DATA_21(
        syssvc_blk_0_NRBG_DATA[21]), .syssvc_blk_0_NRBG_DATA_22(
        syssvc_blk_0_NRBG_DATA[22]), .syssvc_blk_0_NRBG_DATA_0(
        syssvc_blk_0_NRBG_DATA[0]), .syssvc_blk_0_NRBG_DATA_1(
        syssvc_blk_0_NRBG_DATA[1]), .syssvc_blk_0_NRBG_DATA_2(
        syssvc_blk_0_NRBG_DATA[2]), .syssvc_blk_0_NRBG_DATA_3(
        syssvc_blk_0_NRBG_DATA[3]), .reg4_16_0(\reg4_16[3] ), 
        .reg4_16_9(\reg4_16[12] ), .reg3_16_0(\reg3_16[3] ), 
        .reg2_16_0(\reg2_16[4] ), .N_486(N_486), .N_30_mux(N_30_mux), 
        .N_585(N_585), .PRDATA19(PRDATA19), .N_187(N_187), .N_588(
        N_588), .N_416(N_416));
    CFG4 #( .INIT(16'h3D33) )  \PRDATA_9_2_i_0[9]  (.A(
        syssvc_blk_0_NRBG_DATA[18]), .B(syssvc_blk_0_NRBG_DATA[17]), 
        .C(syssvc_blk_0_NRBG_DATA[16]), .D(syssvc_blk_0_NRBG_DATA[19]), 
        .Y(\PRDATA_9_2_i_0[9]_net_1 ));
    CFG4 #( .INIT(16'h707F) )  \PRDATA_1_RNO_0[4]  (.A(\reg2_16[4] ), 
        .B(PRDATA17), .C(N_547), .D(N_491), .Y(N_145_mux_i_1));
    CFG4 #( .INIT(16'h5A53) )  \PRDATA_1_RNO[12]  (.A(N_525_i_1_1), .B(
        N_523), .C(PRDATA19), .D(PRDATA18), .Y(N_525_i));
    SLE \PRDATA_1[9]  (.D(N_63_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[9]));
    CFG4 #( .INIT(16'h0040) )  PRDATA15_0_a2_3_a2 (.A(N_7109_reto), .B(
        N_7119_reto), .C(N_656), .D(N_7110_reto), .Y(PRDATA15));
    SLE \fsm[0]  (.D(\fsm_ns[0] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm[0]_net_1 )
        );
    CFG3 #( .INIT(8'hE2) )  \PRDATA_9_3_ns[0]  (.A(N_183), .B(m15_e_0), 
        .C(N_503), .Y(N_215));
    CFG4 #( .INIT(16'h66F0) )  \PRDATA_1_RNO_5[8]  (.A(\reg0_16[12] ), 
        .B(syssvc_blk_0_NRBG_HANDLE[0]), .C(m67_1_1), .D(PRDATA15), .Y(
        N_540));
    CFG4 #( .INIT(16'h1000) )  PRDATA19_0_a2_0_a2 (.A(N_7107_reto), .B(
        N_7112_reto), .C(PRDATA19_0_a2_0_3_net_1), .D(
        PRDATA19_0_a2_0_a2_1_net_1), .Y(PRDATA19));
    CFG4 #( .INIT(16'h0D0F) )  \PRDATA_1_RNO[14]  (.A(m15_e_0), .B(
        PRDATA17), .C(N_474), .D(N_547), .Y(N_465_i));
    CFG4 #( .INIT(16'hDDF0) )  \PRDATA_9_0_i_o2[4]  (.A(
        syssvc_blk_0_NRBG_DATA[31]), .B(N_588), .C(\reg0_16[4] ), .D(
        PRDATA16), .Y(N_491));
    CFG4 #( .INIT(16'hFDFF) )  \PRDATA_9_0_i_o2_0[2]  (.A(
        syssvc_blk_0_NRBG_HANDLE[6]), .B(syssvc_blk_0_NRBG_HANDLE[4]), 
        .C(syssvc_blk_0_NRBG_HANDLE[5]), .D(
        syssvc_blk_0_NRBG_HANDLE[7]), .Y(N_499));
    CFG4 #( .INIT(16'hEE50) )  \PRDATA_1_RNO_2[8]  (.A(PRDATA18), .B(
        N_541), .C(N_540), .D(PRDATA16), .Y(\PRDATA_1_RNO_2[8]_net_1 ));
    SLE GENERATE_SERVICE (.D(COREABC_0_APB3master_PWDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(GENERATE_SERVICE_0_sqmuxa), 
        .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(UART_top_0_GENERATE_SERVICE));
    CFG3 #( .INIT(8'h02) )  PRDATA19_0_a2_0_3 (.A(
        COREABC_0_APB3master_PADDR_i_0), .B(N_7115_reto), .C(
        N_7108_reto), .Y(PRDATA19_0_a2_0_3_net_1));
    CFG3 #( .INIT(8'h02) )  \PRDATA_9_2_0_a2_0[11]  (.A(
        syssvc_blk_0_NRBG_DATA[19]), .B(syssvc_blk_0_NRBG_DATA[18]), 
        .C(syssvc_blk_0_NRBG_DATA[17]), .Y(
        \PRDATA_9_2_0_a2_0[11]_net_1 ));
    CFG4 #( .INIT(16'hFEEE) )  \PRDATA_1_RNO_2[11]  (.A(m39_0), .B(m39)
        , .C(m39_1_0), .D(PRDATA16), .Y(N_531));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h90) )  \PRDATA_1_RNO_5[10]  (.A(
        syssvc_blk_0_NRBG_DATA[26]), .B(N_9_0), .C(PRDATA16), .Y(m50_0)
        );
    SLE \PRDATA_1[0]  (.D(N_150_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[0]));
    CFG3 #( .INIT(8'hDC) )  \PRDATA_9_i_m2[14]  (.A(
        \PRDATA_9_i_m2_1[14]_net_1 ), .B(PRDATA_9_i_m2_net_1), .C(
        m15_e_0), .Y(N_474));
    CFG4 #( .INIT(16'hF3F7) )  \PRDATA_9_0_i_o2[1]  (.A(
        syssvc_blk_0_NRBG_HANDLE[6]), .B(syssvc_blk_0_NRBG_HANDLE[7]), 
        .C(syssvc_blk_0_NRBG_HANDLE[4]), .D(
        syssvc_blk_0_NRBG_HANDLE[5]), .Y(N_496));
    CFG4 #( .INIT(16'hEFEE) )  \PRDATA_1_RNO_2[9]  (.A(m59_0), .B(m59), 
        .C(m59_1_0), .D(PRDATA16), .Y(N_60));
    SLE \PRDATA_1[2]  (.D(N_147_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[2]));
    CFG3 #( .INIT(8'h8D) )  \PRDATA_1_RNO[6]  (.A(m15_e_0), .B(
        N_144_mux_i_1), .C(N_187), .Y(N_144_mux_i));
    SLE \PRDATA_1[14]  (.D(N_465_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[14]));
    CFG3 #( .INIT(8'hAC) )  \PRDATA_9_i_m2_2[14]  (.A(\reg1_16[12] ), 
        .B(\reg0_16[12] ), .C(PRDATA16), .Y(N_472));
    CFG3 #( .INIT(8'h2D) )  \PRDATA_9_0_i_m2_ns_1[0]  (.A(
        syssvc_blk_0_NRBG_DATA[31]), .B(N_588), .C(
        syssvc_blk_0_NRBG_DATA[28]), .Y(
        \PRDATA_9_0_i_m2_ns_1[0]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \PRDATA_1_RNO_1[11]  (.A(
        syssvc_blk_0_NRBG_DATA[10]), .B(syssvc_blk_0_NRBG_DATA[11]), 
        .Y(m28_0));
    CFG4 #( .INIT(16'hEFEE) )  \PRDATA_1_RNO_0[3]  (.A(m92), .B(
        m94_bm_1), .C(N_588), .D(PRDATA16), .Y(
        \PRDATA_1_RNO_0[3]_net_1 ));
    CFG4 #( .INIT(16'h335A) )  \PRDATA_1_RNO_0[10]  (.A(
        syssvc_blk_0_NRBG_DATA[10]), .B(N_486), .C(N_526), .D(PRDATA19)
        , .Y(N_537_i_1_0));
    SLE \PRDATA_1[1]  (.D(N_148_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[1]));
    CFG4 #( .INIT(16'h1000) )  GENERATE_SERVICE_0_sqmuxa_0_a2_0_a2 (.A(
        N_7110_reto), .B(N_7109_reto), .C(
        GENERATE_SERVICE_0_sqmuxa_0_a2_0_a2_2_net_1), .D(N_656), .Y(
        GENERATE_SERVICE_0_sqmuxa));
    CFG4 #( .INIT(16'h434F) )  \PRDATA_1_RNO_1[8]  (.A(N_542), .B(
        PRDATA19), .C(PRDATA18), .D(\PRDATA_1_RNO_3[8]_net_1 ), .Y(
        m72_4_1));
    SLE \PRDATA_1[10]  (.D(N_537_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[10]));
    CFG4 #( .INIT(16'hC393) )  m71 (.A(syssvc_blk_0_NRBG_DATA[2]), .B(
        syssvc_blk_0_NRBG_DATA[0]), .C(syssvc_blk_0_NRBG_DATA[3]), .D(
        syssvc_blk_0_NRBG_DATA[1]), .Y(N_542));
    CFG4 #( .INIT(16'h404F) )  \PRDATA_1_RNO_0[6]  (.A(\reg2_16[4] ), 
        .B(PRDATA17), .C(N_547), .D(N_491), .Y(N_144_mux_i_1));
    CFG3 #( .INIT(8'h53) )  \PRDATA_1_RNO[3]  (.A(
        \PRDATA_1_RNO_0[3]_net_1 ), .B(\PRDATA_1_RNO_1[3]_net_1 ), .C(
        m15_e_0), .Y(N_151_mux_i));
    CFG2 #( .INIT(4'h9) )  \PRDATA_1_RNO_0[8]  (.A(N_127_mux), .B(
        syssvc_blk_0_NRBG_DATA[8]), .Y(N_539_i));
    CFG3 #( .INIT(8'h1D) )  \PRDATA_1_RNO_0[12]  (.A(N_127_mux), .B(
        PRDATA19), .C(\reg4_16[12] ), .Y(N_525_i_1_1));
    SLE START_sysservice (.D(COREABC_0_APB3master_PWDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(GENERATE_SERVICE_0_sqmuxa), 
        .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(UART_top_0_START_sysservice));
    Binary2Ascii_1 u2 (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[23], syssvc_blk_0_NRBG_DATA[22], 
        syssvc_blk_0_NRBG_DATA[21], syssvc_blk_0_NRBG_DATA[20], 
        syssvc_blk_0_NRBG_DATA[19], syssvc_blk_0_NRBG_DATA[18], 
        syssvc_blk_0_NRBG_DATA[17]}), .reg2_16_0(\reg2_16[12] ), 
        .N_399(N_399));
    CFG4 #( .INIT(16'h1EF0) )  \PRDATA_9_1_bm[0]  (.A(
        syssvc_blk_0_NRBG_DATA[6]), .B(syssvc_blk_0_NRBG_DATA[5]), .C(
        syssvc_blk_0_NRBG_DATA[4]), .D(syssvc_blk_0_NRBG_DATA[7]), .Y(
        \PRDATA_9_1_bm[0]_net_1 ));
    CFG4 #( .INIT(16'h1EF0) )  \PRDATA_9_1_am[0]  (.A(
        syssvc_blk_0_NRBG_DATA[14]), .B(syssvc_blk_0_NRBG_DATA[13]), 
        .C(syssvc_blk_0_NRBG_DATA[12]), .D(syssvc_blk_0_NRBG_DATA[15]), 
        .Y(\PRDATA_9_1_am[0]_net_1 ));
    CFG3 #( .INIT(8'h6F) )  \PRDATA_1_RNO_6[8]  (.A(
        syssvc_blk_0_NRBG_DATA[16]), .B(\reg2_16[12] ), .C(PRDATA17), 
        .Y(m67_1_1));
    CFG4 #( .INIT(16'h0200) )  \PRDATA_1_RNO_6[10]  (.A(
        syssvc_blk_0_NRBG_HANDLE[2]), .B(syssvc_blk_0_NRBG_HANDLE[1]), 
        .C(syssvc_blk_0_NRBG_HANDLE[0]), .D(
        syssvc_blk_0_NRBG_HANDLE[3]), .Y(N_6_0));
    CFG4 #( .INIT(16'hAAA3) )  \PRDATA_1_RNO[10]  (.A(N_537_i_1_0), .B(
        N_132_mux), .C(PRDATA19), .D(PRDATA18), .Y(N_537_i));
    CFG4 #( .INIT(16'h6F60) )  \PRDATA_1_RNO[9]  (.A(
        syssvc_blk_0_NRBG_DATA[1]), .B(N_2_0), .C(PRDATA19), .D(
        N_63_i_1_0), .Y(N_63_i));
    CFG4 #( .INIT(16'h0008) )  PRDATA19_0_a2_0_a2_1 (.A(N_7111_reto), 
        .B(N_7119_reto), .C(N_7110_reto), .D(N_7109_reto), .Y(
        PRDATA19_0_a2_0_a2_1_net_1));
    CFG4 #( .INIT(16'h5755) )  \PRDATA_9_2_i_0[10]  (.A(
        syssvc_blk_0_NRBG_DATA[18]), .B(syssvc_blk_0_NRBG_DATA[17]), 
        .C(syssvc_blk_0_NRBG_DATA[16]), .D(syssvc_blk_0_NRBG_DATA[19]), 
        .Y(\PRDATA_9_2_i_0[10]_net_1 ));
    CFG3 #( .INIT(8'h72) )  \PRDATA_1_RNO[4]  (.A(m15_e_0), .B(
        N_145_mux_i_1), .C(N_187), .Y(N_145_mux_i));
    CFG4 #( .INIT(16'h0900) )  \PRDATA_1_RNO_3[9]  (.A(N_5_0), .B(
        syssvc_blk_0_NRBG_HANDLE[1]), .C(PRDATA16), .D(PRDATA15), .Y(
        m59_0));
    CFG4 #( .INIT(16'h0FDD) )  \PRDATA_1_RNO_1[2]  (.A(
        syssvc_blk_0_NRBG_DATA[14]), .B(m101_am_1_1), .C(N_585), .D(
        PRDATA19), .Y(\PRDATA_1_RNO_1[2]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  PRDATA18_0_a2_1_a2 (.A(N_7109_reto), .B(
        N_7119_reto), .C(N_656), .D(N_7110_reto), .Y(PRDATA18));
    CFG4 #( .INIT(16'h0100) )  PRDATA15_0_a2_3_a2_1 (.A(N_7107_reto), 
        .B(N_7112_reto), .C(N_7111_reto), .D(PRDATA19_0_a2_0_3_net_1), 
        .Y(N_656));
    CFG2 #( .INIT(4'h6) )  \PRDATA_1_RNO_4[8]  (.A(\reg1_16[12] ), .B(
        syssvc_blk_0_NRBG_DATA[24]), .Y(N_541));
    CFG4 #( .INIT(16'h4000) )  GENERATE_SERVICE_0_sqmuxa_0_a2_0_a2_2 (
        .A(N_7119_reto), .B(COREABC_0_APB3master_PENABLE), .C(
        \fsm[0]_net_1 ), .D(COREABC_0_APB3master_PWRITE), .Y(
        GENERATE_SERVICE_0_sqmuxa_0_a2_0_a2_2_net_1));
    CFG4 #( .INIT(16'h0600) )  \PRDATA_1_RNO_4[2]  (.A(N_499), .B(
        syssvc_blk_0_NRBG_HANDLE[6]), .C(PRDATA16), .D(PRDATA15), .Y(
        m99));
    CFG3 #( .INIT(8'hFE) )  PREADY_RNO (.A(\fsm[1]_net_1 ), .B(
        \fsm[0]_net_1 ), .C(CoreAPB3_0_APBmslave0_PSELx), .Y(N_79_i));
    CFG2 #( .INIT(4'h1) )  PRDATA15_0_a2_3_a2_RNIQIVB (.A(PRDATA16), 
        .B(PRDATA15), .Y(N_547));
    SLE \fsm[1]  (.D(\fsm[0]_net_1 ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm[1]_net_1 )
        );
    CFG4 #( .INIT(16'h000D) )  \PRDATA_1_RNO_4[9]  (.A(PRDATA17), .B(
        \PRDATA_9_2_i_0[9]_net_1 ), .C(PRDATA16), .D(PRDATA15), .Y(m59)
        );
    CFG3 #( .INIT(8'hFB) )  \PRDATA_1_RNO_5[11]  (.A(
        syssvc_blk_0_NRBG_DATA[26]), .B(syssvc_blk_0_NRBG_DATA[27]), 
        .C(syssvc_blk_0_NRBG_DATA[25]), .Y(m39_1_0));
    CFG3 #( .INIT(8'hA8) )  m11 (.A(syssvc_blk_0_NRBG_DATA[11]), .B(
        syssvc_blk_0_NRBG_DATA[10]), .C(syssvc_blk_0_NRBG_DATA[9]), .Y(
        N_127_mux));
    CFG3 #( .INIT(8'h6F) )  \PRDATA_1_RNO_0[0]  (.A(
        syssvc_blk_0_NRBG_DATA[20]), .B(\reg2_16[4] ), .C(PRDATA17), 
        .Y(N_111));
    CFG4 #( .INIT(16'h0080) )  PRDATA16_0_a2_0_a2 (.A(N_7109_reto), .B(
        N_7119_reto), .C(N_656), .D(N_7110_reto), .Y(PRDATA16));
    SLE \PRDATA_1[4]  (.D(N_145_mux_i), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[4]));
    SLE SELF_TEST_SERVICE (.D(COREABC_0_APB3master_PWDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(GENERATE_SERVICE_0_sqmuxa), 
        .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(UART_top_0_SELF_TEST_SERVICE));
    CFG4 #( .INIT(16'h3020) )  \PRDATA_1_RNO_0[9]  (.A(
        syssvc_blk_0_NRBG_DATA[2]), .B(syssvc_blk_0_NRBG_DATA[0]), .C(
        syssvc_blk_0_NRBG_DATA[3]), .D(syssvc_blk_0_NRBG_DATA[1]), .Y(
        N_2_0));
    CFG3 #( .INIT(8'h53) )  \PRDATA_1_RNO[2]  (.A(
        \PRDATA_1_RNO_0[2]_net_1 ), .B(\PRDATA_1_RNO_1[2]_net_1 ), .C(
        m15_e_0), .Y(N_147_mux_i));
    SLE \PRDATA_1[12]  (.D(N_525_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_221), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        APB_register_blk_0_PRDATA[12]));
    CFG4 #( .INIT(16'h0900) )  \PRDATA_1_RNO_4[10]  (.A(N_6_0), .B(
        syssvc_blk_0_NRBG_HANDLE[2]), .C(PRDATA16), .D(PRDATA15), .Y(
        m50));
    CFG4 #( .INIT(16'h000D) )  \PRDATA_1_RNO_3[10]  (.A(PRDATA17), .B(
        \PRDATA_9_2_i_0[10]_net_1 ), .C(PRDATA16), .D(PRDATA15), .Y(
        m50_1));
    CFG4 #( .INIT(16'h220F) )  \PRDATA_1_RNO_0[11]  (.A(m28_0), .B(
        syssvc_blk_0_NRBG_DATA[9]), .C(N_531), .D(PRDATA18), .Y(
        N_534_i_1_0));
    
endmodule


module UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(
       rx_byte,
       N_238,
       clear_parity_reg,
       un1_framing_error11_i_a2_0,
       N_7109_reto,
       N_7111_reto,
       N_7110_reto,
       RX_c,
       fifo_write,
       clear_parity_en,
       FRAMING_ERR,
       baud_clock,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
output [7:0] rx_byte;
input  N_238;
input  clear_parity_reg;
output un1_framing_error11_i_a2_0;
input  N_7109_reto;
input  N_7111_reto;
input  N_7110_reto;
input  RX_c;
output fifo_write;
output clear_parity_en;
output FRAMING_ERR;
input  baud_clock;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire \rx_bit_cnt[2]_net_1 , VCC_net_1, \rx_bit_cnt_4[2] , 
        GND_net_1, \rx_bit_cnt[3]_net_1 , \rx_bit_cnt_4[3] , 
        \receive_count[2]_net_1 , receive_count_88_net_1, 
        \receive_count[3]_net_1 , receive_count_89_net_1, 
        \rx_shift[0]_net_1 , rx_byte_1_sqmuxa, \rx_shift[1]_net_1 , 
        \rx_shift[2]_net_1 , \rx_shift[3]_net_1 , \rx_shift[4]_net_1 , 
        \rx_shift[5]_net_1 , \rx_shift[6]_net_1 , \rx_shift[7]_net_1 , 
        \samples[0]_net_1 , samples_72_net_1, \samples[1]_net_1 , 
        samples_73_net_1, \samples[2]_net_1 , samples_74_net_1, 
        \rx_bit_cnt[0]_net_1 , \rx_bit_cnt_4[0] , 
        \rx_bit_cnt[1]_net_1 , \rx_bit_cnt_4[1] , \rx_shift_11[0] , 
        un1_samples7_1_0_net_1, \rx_shift_11[1] , \rx_shift_11[2] , 
        \rx_shift_11[3] , \rx_shift_11[4] , \rx_shift_11[5] , 
        \rx_shift_11[6] , \rx_shift_11[7] , \receive_count[0]_net_1 , 
        receive_count_86_net_1, \receive_count[1]_net_1 , 
        receive_count_87_net_1, \rx_state[0]_net_1 , 
        \rx_state_RNO[0]_net_1 , framing_error_int_net_1, 
        framing_error_int_0_sqmuxa, framing_error_0_sqmuxa, 
        un1_framing_error11_i_0_net_1, \last_bit[0]_net_1 , 
        rx_state_0_sqmuxa, \rx_state[1]_net_1 , N_713_mux, 
        clear_parity_en_9, clear_parity_en_9_i, rx_bit_cnt_1_sqmuxa, 
        rx_bit_cnt_0_sqmuxa, rx_state_78_d, N_167, 
        rx_state_99_2_1_net_1, rx_state19, rx_state_99_2_net_1, 
        rx_state_99_3_net_1, i5_mux, N_23_mux, parity_err15, 
        rx_state19_NE_0, N_153, N_713, 
        framing_error_int_0_sqmuxa_0_a2_2_net_1, 
        \receive_count_3_i_a2_0_1[0] , N_24_mux, N_179, rx_filtered, 
        \receive_count_3_i_0[3] , N_152, CO1;
    
    CFG4 #( .INIT(16'h0800) )  rx_bit_cnt_1_sqmuxa_0_a2 (.A(
        \receive_count[2]_net_1 ), .B(\receive_count[3]_net_1 ), .C(
        N_153), .D(baud_clock), .Y(rx_bit_cnt_1_sqmuxa));
    CFG4 #( .INIT(16'h11F0) )  receive_count_89 (.A(N_167), .B(
        \receive_count_3_i_0[3] ), .C(\receive_count[3]_net_1 ), .D(
        baud_clock), .Y(receive_count_89_net_1));
    CFG3 #( .INIT(8'hFE) )  un1_framing_error11_i_0 (.A(
        clear_parity_reg), .B(framing_error_0_sqmuxa), .C(N_238), .Y(
        un1_framing_error11_i_0_net_1));
    SLE \samples[0]  (.D(samples_72_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\samples[0]_net_1 ));
    SLE \rx_shift[2]  (.D(\rx_shift_11[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[2]_net_1 ));
    CFG4 #( .INIT(16'hF8F0) )  \rcv_cnt.receive_count_3_i_o2[0]  (.A(
        \receive_count[2]_net_1 ), .B(\receive_count[1]_net_1 ), .C(
        N_167), .D(\receive_count_3_i_a2_0_1[0] ), .Y(N_152));
    CFG4 #( .INIT(16'h2226) )  receive_count_86 (.A(
        \receive_count[0]_net_1 ), .B(baud_clock), .C(
        rx_state_0_sqmuxa), .D(N_152), .Y(receive_count_86_net_1));
    CFG4 #( .INIT(16'h2000) )  rx_byte_1_sqmuxa_0_a2 (.A(
        \rx_state[0]_net_1 ), .B(\rx_state[1]_net_1 ), .C(rx_state19), 
        .D(baud_clock), .Y(rx_byte_1_sqmuxa));
    CFG4 #( .INIT(16'h0010) )  rx_state_99_2_1 (.A(
        \receive_count[1]_net_1 ), .B(\receive_count[0]_net_1 ), .C(
        \receive_count[3]_net_1 ), .D(\receive_count[2]_net_1 ), .Y(
        rx_state_99_2_1_net_1));
    CFG4 #( .INIT(16'hCCCE) )  un1_samples7_1_0 (.A(baud_clock), .B(
        rx_bit_cnt_1_sqmuxa), .C(\rx_state[1]_net_1 ), .D(
        \rx_state[0]_net_1 ), .Y(un1_samples7_1_0_net_1));
    SLE \rx_byte[0]  (.D(\rx_shift[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[0]));
    CFG4 #( .INIT(16'h0010) )  \rcv_cnt.receive_count_3_i_a2_0[3]  (.A(
        \receive_count[0]_net_1 ), .B(\receive_count[1]_net_1 ), .C(
        rx_state_78_d), .D(\receive_count[2]_net_1 ), .Y(N_179));
    SLE \receive_count[1]  (.D(receive_count_87_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\receive_count[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \rx_state_RNO_0[1]  (.A(baud_clock), .B(
        \rx_state[0]_net_1 ), .Y(N_713));
    SLE \rx_shift[7]  (.D(\rx_shift_11[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[7]_net_1 ));
    CFG4 #( .INIT(16'hBC8C) )  rx_state_99_3 (.A(i5_mux), .B(
        rx_state_99_2_net_1), .C(\rx_state[1]_net_1 ), .D(N_23_mux), 
        .Y(rx_state_99_3_net_1));
    CFG3 #( .INIT(8'hAC) )  samples_73 (.A(\samples[2]_net_1 ), .B(
        \samples[1]_net_1 ), .C(baud_clock), .Y(samples_73_net_1));
    CFG4 #( .INIT(16'h0200) )  framing_error_int_0_sqmuxa_0_a2_2 (.A(
        \receive_count[3]_net_1 ), .B(\receive_count[0]_net_1 ), .C(
        \rx_state[0]_net_1 ), .D(\rx_state[1]_net_1 ), .Y(
        framing_error_int_0_sqmuxa_0_a2_2_net_1));
    SLE \rx_shift[0]  (.D(\rx_shift_11[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[0]_net_1 ));
    CFG4 #( .INIT(16'h0021) )  \rcv_sm.rx_state19_NE_i  (.A(
        \rx_bit_cnt[0]_net_1 ), .B(rx_state19_NE_0), .C(
        \last_bit[0]_net_1 ), .D(\rx_bit_cnt[2]_net_1 ), .Y(rx_state19)
        );
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[0]  (.A(
        rx_state_78_d), .B(\rx_shift[1]_net_1 ), .Y(\rx_shift_11[0] ));
    SLE \receive_count[3]  (.D(receive_count_89_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\receive_count[3]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hDFFF) )  
        \receive_full_indicator.clear_parity_en_9_i_0  (.A(
        \rx_state[0]_net_1 ), .B(\rx_state[1]_net_1 ), .C(parity_err15)
        , .D(baud_clock), .Y(clear_parity_en_9_i));
    SLE fifo_write_inst_1 (.D(clear_parity_en_9_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(fifo_write));
    SLE \rx_byte[4]  (.D(\rx_shift[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[4]));
    SLE \rx_bit_cnt[2]  (.D(\rx_bit_cnt_4[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_bit_cnt[2]_net_1 ));
    CFG4 #( .INIT(16'h006C) )  \receive_shift.rx_bit_cnt_4[3]  (.A(
        \rx_bit_cnt[2]_net_1 ), .B(\rx_bit_cnt[3]_net_1 ), .C(CO1), .D(
        rx_bit_cnt_0_sqmuxa), .Y(\rx_bit_cnt_4[3] ));
    CFG2 #( .INIT(4'h8) )  rx_state_0_sqmuxa_0_a2 (.A(N_179), .B(
        \receive_count[3]_net_1 ), .Y(rx_state_0_sqmuxa));
    CFG3 #( .INIT(8'h10) )  rx_bit_cnt_0_sqmuxa_0_a2 (.A(
        \rx_state[0]_net_1 ), .B(\rx_state[1]_net_1 ), .C(baud_clock), 
        .Y(rx_bit_cnt_0_sqmuxa));
    SLE \rx_bit_cnt[1]  (.D(\rx_bit_cnt_4[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_bit_cnt[1]_net_1 ));
    CFG2 #( .INIT(4'h1) )  rx_state_s0_0_a2 (.A(\rx_state[0]_net_1 ), 
        .B(\rx_state[1]_net_1 ), .Y(rx_state_78_d));
    CFG4 #( .INIT(16'hF3F9) )  \rcv_cnt.receive_count_3_i_0[3]  (.A(
        \receive_count[2]_net_1 ), .B(\receive_count[3]_net_1 ), .C(
        N_179), .D(N_153), .Y(\receive_count_3_i_0[3] ));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[7]  (.A(
        rx_state_78_d), .B(rx_filtered), .Y(\rx_shift_11[7] ));
    SLE \samples[1]  (.D(samples_73_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\samples[1]_net_1 ));
    CFG4 #( .INIT(16'hEA62) )  \rx_state_RNO[1]  (.A(
        \rx_state[1]_net_1 ), .B(N_713), .C(rx_state19), .D(i5_mux), 
        .Y(N_713_mux));
    CFG4 #( .INIT(16'h2000) )  
        \receive_full_indicator.clear_parity_en_9  (.A(
        \rx_state[0]_net_1 ), .B(\rx_state[1]_net_1 ), .C(parity_err15)
        , .D(baud_clock), .Y(clear_parity_en_9));
    SLE \rx_byte[1]  (.D(\rx_shift[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[1]));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[2]  (.A(
        rx_state_78_d), .B(\rx_shift[3]_net_1 ), .Y(\rx_shift_11[2] ));
    SLE \receive_count[2]  (.D(receive_count_88_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\receive_count[2]_net_1 ));
    SLE clear_parity_en_1 (.D(clear_parity_en_9), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(clear_parity_en));
    CFG3 #( .INIT(8'h80) )  \un1_rx_bit_cnt_1.CO1  (.A(
        \rx_bit_cnt[0]_net_1 ), .B(rx_bit_cnt_1_sqmuxa), .C(
        \rx_bit_cnt[1]_net_1 ), .Y(CO1));
    SLE \rx_state[1]  (.D(N_713_mux), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rx_state[1]_net_1 ));
    SLE \rx_byte[6]  (.D(\rx_shift[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[6]));
    CFG4 #( .INIT(16'h06CC) )  receive_count_87 (.A(
        \receive_count[0]_net_1 ), .B(\receive_count[1]_net_1 ), .C(
        N_152), .D(baud_clock), .Y(receive_count_87_net_1));
    GND GND (.Y(GND_net_1));
    SLE \rx_shift[4]  (.D(\rx_shift_11[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[4]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[3]  (.A(
        rx_state_78_d), .B(\rx_shift[4]_net_1 ), .Y(\rx_shift_11[3] ));
    SLE \rx_byte[7]  (.D(\rx_shift[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[7]));
    CFG3 #( .INIT(8'hE8) )  rx_filtered_i_o2 (.A(\samples[1]_net_1 ), 
        .B(\samples[0]_net_1 ), .C(\samples[2]_net_1 ), .Y(rx_filtered)
        );
    CFG3 #( .INIT(8'h12) )  \receive_shift.rx_bit_cnt_4[2]  (.A(
        \rx_bit_cnt[2]_net_1 ), .B(rx_bit_cnt_0_sqmuxa), .C(CO1), .Y(
        \rx_bit_cnt_4[2] ));
    SLE \rx_byte[3]  (.D(\rx_shift[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[3]));
    CFG4 #( .INIT(16'h0200) )  \rx_state_ns_1_0_.m10  (.A(
        \receive_count[1]_net_1 ), .B(\receive_count[0]_net_1 ), .C(
        \receive_count[3]_net_1 ), .D(\receive_count[2]_net_1 ), .Y(
        N_24_mux));
    CFG3 #( .INIT(8'h10) )  un1_framing_error11_i_a2_0_inst_1 (.A(
        N_7110_reto), .B(N_7111_reto), .C(N_7109_reto), .Y(
        un1_framing_error11_i_a2_0));
    CFG3 #( .INIT(8'hB8) )  samples_72 (.A(\samples[1]_net_1 ), .B(
        baud_clock), .C(\samples[0]_net_1 ), .Y(samples_72_net_1));
    SLE \rx_byte[2]  (.D(\rx_shift[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[2]));
    CFG3 #( .INIT(8'hD8) )  samples_74 (.A(baud_clock), .B(RX_c), .C(
        \samples[2]_net_1 ), .Y(samples_74_net_1));
    SLE \rx_shift[6]  (.D(\rx_shift_11[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[6]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \rx_state_RNO[0]  (.A(\rx_state[0]_net_1 ), 
        .B(baud_clock), .C(rx_state_99_3_net_1), .Y(
        \rx_state_RNO[0]_net_1 ));
    SLE \rx_shift[1]  (.D(\rx_shift_11[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[4]  (.A(
        rx_state_78_d), .B(\rx_shift[5]_net_1 ), .Y(\rx_shift_11[4] ));
    SLE \rx_shift[3]  (.D(\rx_shift_11[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[3]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[6]  (.A(
        rx_state_78_d), .B(\rx_shift[7]_net_1 ), .Y(\rx_shift_11[6] ));
    SLE framing_error_int (.D(framing_error_int_0_sqmuxa), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(baud_clock), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(framing_error_int_net_1));
    SLE \rx_state[0]  (.D(\rx_state_RNO[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_state[0]_net_1 ));
    CFG3 #( .INIT(8'h20) )  \rcv_cnt.receive_count_3_i_a2_0_1[0]  (.A(
        \rx_state[0]_net_1 ), .B(\receive_count[3]_net_1 ), .C(
        \rx_state[1]_net_1 ), .Y(\receive_count_3_i_a2_0_1[0] ));
    SLE \samples[2]  (.D(samples_74_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\samples[2]_net_1 ));
    CFG4 #( .INIT(16'hF30A) )  rx_state_99_2 (.A(rx_state_99_2_1_net_1)
        , .B(rx_state19), .C(\rx_state[1]_net_1 ), .D(
        \rx_state[0]_net_1 ), .Y(rx_state_99_2_net_1));
    SLE \receive_count[0]  (.D(receive_count_86_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\receive_count[0]_net_1 ));
    SLE \rx_byte[5]  (.D(\rx_shift[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_byte_1_sqmuxa), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_byte[5]));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[5]  (.A(
        rx_state_78_d), .B(\rx_shift[6]_net_1 ), .Y(\rx_shift_11[5] ));
    CFG4 #( .INIT(16'h0107) )  \rx_state_ns_1_0_.m14  (.A(
        \samples[2]_net_1 ), .B(\samples[0]_net_1 ), .C(N_24_mux), .D(
        \samples[1]_net_1 ), .Y(i5_mux));
    CFG4 #( .INIT(16'h4000) )  framing_error_int_0_sqmuxa_0_a2 (.A(
        rx_filtered), .B(framing_error_int_0_sqmuxa_0_a2_2_net_1), .C(
        \receive_count[1]_net_1 ), .D(\receive_count[2]_net_1 ), .Y(
        framing_error_int_0_sqmuxa));
    CFG3 #( .INIT(8'h12) )  \receive_shift.rx_bit_cnt_4[0]  (.A(
        \rx_bit_cnt[0]_net_1 ), .B(rx_bit_cnt_0_sqmuxa), .C(
        rx_bit_cnt_1_sqmuxa), .Y(\rx_bit_cnt_4[0] ));
    SLE \rx_shift[5]  (.D(\rx_shift_11[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_samples7_1_0_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_shift[5]_net_1 ));
    CFG4 #( .INIT(16'hE800) )  \rcv_cnt.receive_count_3_i_a2[3]  (.A(
        \samples[0]_net_1 ), .B(\samples[1]_net_1 ), .C(
        \samples[2]_net_1 ), .D(rx_state_78_d), .Y(N_167));
    CFG2 #( .INIT(4'h7) )  \rcv_cnt.receive_count_3_i_o2[1]  (.A(
        \receive_count[0]_net_1 ), .B(\receive_count[1]_net_1 ), .Y(
        N_153));
    SLE \rx_bit_cnt[0]  (.D(\rx_bit_cnt_4[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_bit_cnt[0]_net_1 ));
    CFG4 #( .INIT(16'h0002) )  \make_parity_err.parity_err15  (.A(
        \rx_bit_cnt[3]_net_1 ), .B(\rx_bit_cnt[2]_net_1 ), .C(
        \rx_bit_cnt[1]_net_1 ), .D(\rx_bit_cnt[0]_net_1 ), .Y(
        parity_err15));
    CFG2 #( .INIT(4'h4) )  \receive_shift.rx_shift_11[1]  (.A(
        rx_state_78_d), .B(\rx_shift[2]_net_1 ), .Y(\rx_shift_11[1] ));
    SLE framing_error (.D(framing_error_0_sqmuxa), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_framing_error11_i_0_net_1), 
        .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(FRAMING_ERR));
    SLE \last_bit[0]  (.D(GND_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(rx_state_0_sqmuxa), .ALn(COREABC_0_PRESETN), .ADn(
        GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\last_bit[0]_net_1 ));
    CFG3 #( .INIT(8'h08) )  \rx_state_ns_1_0_.m8  (.A(
        \receive_count[3]_net_1 ), .B(\receive_count[2]_net_1 ), .C(
        N_153), .Y(N_23_mux));
    CFG2 #( .INIT(4'h8) )  framing_error_0_sqmuxa_0_a2 (.A(baud_clock), 
        .B(framing_error_int_net_1), .Y(framing_error_0_sqmuxa));
    CFG2 #( .INIT(4'hB) )  \rcv_sm.rx_state19_NE_0  (.A(
        \rx_bit_cnt[1]_net_1 ), .B(\rx_bit_cnt[3]_net_1 ), .Y(
        rx_state19_NE_0));
    SLE \rx_bit_cnt[3]  (.D(\rx_bit_cnt_4[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_bit_cnt[3]_net_1 ));
    CFG4 #( .INIT(16'h006C) )  \receive_shift.rx_bit_cnt_4[1]  (.A(
        \rx_bit_cnt[0]_net_1 ), .B(\rx_bit_cnt[1]_net_1 ), .C(
        rx_bit_cnt_1_sqmuxa), .D(rx_bit_cnt_0_sqmuxa), .Y(
        \rx_bit_cnt_4[1] ));
    CFG4 #( .INIT(16'h21F0) )  receive_count_88 (.A(N_153), .B(N_152), 
        .C(\receive_count[2]_net_1 ), .D(baud_clock), .Y(
        receive_count_88_net_1));
    
endmodule


module UART_top_CoreUARTapb_0_ram16x8(
       tx_hold_reg,
       wr_pointer,
       rd_pointer,
       data_out_0,
       fifo_read_tx_i,
       my_hpms_top_0_FIC32_0_CLK,
       fifo_write_tx
    );
input  [7:0] tx_hold_reg;
input  [3:0] wr_pointer;
input  [3:0] rd_pointer;
output [7:0] data_out_0;
input  fifo_read_tx_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  fifo_write_tx;

    wire fifo_write_tx_i, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    RAM64x18 memory_memory_0_0 (.A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, 
        nc6, nc7, nc8, nc9, data_out_0[7], data_out_0[6], 
        data_out_0[5], data_out_0[4], data_out_0[3], data_out_0[2], 
        data_out_0[1], data_out_0[0]}), .B_DOUT({nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, 
        nc23, nc24, nc25, nc26, nc27}), .BUSY(), .A_ADDR_CLK(VCC_net_1)
        , .A_DOUT_CLK(my_hpms_top_0_FIC32_0_CLK), .A_ADDR_SRST_N(
        VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_ADDR_ARST_N(
        VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), .A_ADDR_EN(VCC_net_1), 
        .A_DOUT_EN(fifo_read_tx_i), .A_BLK({VCC_net_1, VCC_net_1}), 
        .A_ADDR({GND_net_1, GND_net_1, GND_net_1, rd_pointer[3], 
        rd_pointer[2], rd_pointer[1], rd_pointer[0], GND_net_1, 
        GND_net_1, GND_net_1}), .B_ADDR_CLK(VCC_net_1), .B_DOUT_CLK(
        VCC_net_1), .B_ADDR_SRST_N(VCC_net_1), .B_DOUT_SRST_N(
        VCC_net_1), .B_ADDR_ARST_N(VCC_net_1), .B_DOUT_ARST_N(
        VCC_net_1), .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(VCC_net_1), 
        .B_BLK({VCC_net_1, VCC_net_1}), .B_ADDR({GND_net_1, GND_net_1, 
        GND_net_1, rd_pointer[3], rd_pointer[2], rd_pointer[1], 
        rd_pointer[0], GND_net_1, GND_net_1, GND_net_1}), .C_CLK(
        my_hpms_top_0_FIC32_0_CLK), .C_ADDR({GND_net_1, GND_net_1, 
        GND_net_1, wr_pointer[3], wr_pointer[2], wr_pointer[1], 
        wr_pointer[0], GND_net_1, GND_net_1, GND_net_1}), .C_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        tx_hold_reg[7], tx_hold_reg[6], tx_hold_reg[5], tx_hold_reg[4], 
        tx_hold_reg[3], tx_hold_reg[2], tx_hold_reg[1], tx_hold_reg[0]})
        , .C_WEN(fifo_write_tx_i), .C_BLK({VCC_net_1, VCC_net_1}), 
        .A_EN(VCC_net_1), .A_ADDR_LAT(VCC_net_1), .A_DOUT_LAT(
        GND_net_1), .A_WIDTH({GND_net_1, VCC_net_1, VCC_net_1}), .B_EN(
        GND_net_1), .B_ADDR_LAT(VCC_net_1), .B_DOUT_LAT(VCC_net_1), 
        .B_WIDTH({GND_net_1, VCC_net_1, VCC_net_1}), .C_EN(VCC_net_1), 
        .C_WIDTH({GND_net_1, VCC_net_1, VCC_net_1}), .SII_LOCK(
        GND_net_1));
    CFG1 #( .INIT(2'h1) )  memory_memory_0_0_RNO (.A(fifo_write_tx), 
        .Y(fifo_write_tx_i));
    
endmodule


module UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s(
       tx_hold_reg,
       xmit_state,
       tx_byte,
       xmit_bit_sel,
       tx_dout_reg,
       xmit_state_ns_0,
       xmit_state_ns_i_0,
       fifo_read_tx_i,
       N_102_i,
       N_101_mux_i,
       N_95_mux_i,
       N_130_i,
       xmit_pulse,
       N_54,
       fifo_full_tx_i,
       N_94_mux,
       fifo_write_tx,
       N_46_i,
       N_47_i,
       N_45_0,
       xmit_clock,
       baud_clock,
       fifo_read_tx,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
input  [7:0] tx_hold_reg;
input  [6:0] xmit_state;
input  [7:0] tx_byte;
input  [3:0] xmit_bit_sel;
output [7:0] tx_dout_reg;
output xmit_state_ns_0;
output xmit_state_ns_i_0;
input  fifo_read_tx_i;
output N_102_i;
output N_101_mux_i;
output N_95_mux_i;
output N_130_i;
input  xmit_pulse;
output N_54;
output fifo_full_tx_i;
output N_94_mux;
input  fifo_write_tx;
output N_46_i;
output N_47_i;
output N_45_0;
input  xmit_clock;
input  baud_clock;
input  fifo_read_tx;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire \wr_pointer[0]_net_1 , VCC_net_1, N_423_i, GND_net_1, 
        \wr_pointer[1]_net_1 , N_30_0_i, \wr_pointer[2]_net_1 , 
        N_29_0_i, \wr_pointer[3]_net_1 , N_28_0_i, \counter[0]_net_1 , 
        N_24_0_i, \counter[1]_net_1 , N_22_0_i, \counter[2]_net_1 , 
        N_20_0_i, \counter[3]_net_1 , N_18_0_i, \rd_pointer[0]_net_1 , 
        N_422_i, \rd_pointer[1]_net_1 , N_37_0_i, 
        \rd_pointer[2]_net_1 , N_36_0_i, \rd_pointer[3]_net_1 , 
        N_35_0_i, \data_out_0[0] , data_out_0_sqmuxa_net_1, 
        \data_out_0[1] , \data_out_0[2] , \data_out_0[3] , 
        \data_out_0[4] , \data_out_0[5] , \data_out_0[6] , 
        \data_out_0[7] , read_n_hold_net_1, N_53, m71_1_1_0_net_1, 
        m71_1_net_1, m71_3_1_0_net_1, m71_3_net_1, N_72, N_99_mux, 
        N_32_0, N_25_0, i20_mux, N_19_0;
    
    CFG4 #( .INIT(16'hFFFE) )  N_130_i_inst_1 (.A(xmit_state[0]), .B(
        xmit_state[1]), .C(xmit_pulse), .D(xmit_state[6]), .Y(N_130_i));
    CFG2 #( .INIT(4'h4) )  \counter_RNIA6RA1_0[3]  (.A(N_99_mux), .B(
        xmit_state[0]), .Y(xmit_state_ns_0));
    CFG2 #( .INIT(4'h8) )  m53 (.A(N_53), .B(xmit_state[3]), .Y(N_54));
    CFG4 #( .INIT(16'h7FFF) )  \counter_RNIAHEA1[3]  (.A(
        \counter[3]_net_1 ), .B(\counter[2]_net_1 ), .C(
        \counter[1]_net_1 ), .D(\counter[0]_net_1 ), .Y(fifo_full_tx_i)
        );
    CFG3 #( .INIT(8'h78) )  \rd_pointer_RNO[2]  (.A(
        \rd_pointer[1]_net_1 ), .B(N_32_0), .C(\rd_pointer[2]_net_1 ), 
        .Y(N_36_0_i));
    CFG3 #( .INIT(8'h80) )  m44 (.A(xmit_state[2]), .B(baud_clock), .C(
        xmit_clock), .Y(N_45_0));
    SLE \rd_pointer[2]  (.D(N_36_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rd_pointer[2]_net_1 ));
    SLE \counter[2]  (.D(N_20_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[2]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \counter_RNI8GPP1[3]  (.A(xmit_state[5])
        , .B(xmit_state[0]), .C(N_99_mux), .D(xmit_pulse), .Y(
        N_101_mux_i));
    CFG4 #( .INIT(16'h4AEA) )  N_102_i_inst_1 (.A(xmit_state[3]), .B(
        xmit_state[2]), .C(xmit_pulse), .D(N_53), .Y(N_102_i));
    CFG4 #( .INIT(16'h89CD) )  m71_1 (.A(xmit_bit_sel[0]), .B(
        m71_1_1_0_net_1), .C(tx_byte[2]), .D(tx_byte[0]), .Y(
        m71_1_net_1));
    SLE \data_out[3]  (.D(\data_out_0[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[3]));
    UART_top_CoreUARTapb_0_ram16x8 ram16x8 (.tx_hold_reg({
        tx_hold_reg[7], tx_hold_reg[6], tx_hold_reg[5], tx_hold_reg[4], 
        tx_hold_reg[3], tx_hold_reg[2], tx_hold_reg[1], tx_hold_reg[0]})
        , .wr_pointer({\wr_pointer[3]_net_1 , \wr_pointer[2]_net_1 , 
        \wr_pointer[1]_net_1 , \wr_pointer[0]_net_1 }), .rd_pointer({
        \rd_pointer[3]_net_1 , \rd_pointer[2]_net_1 , 
        \rd_pointer[1]_net_1 , \rd_pointer[0]_net_1 }), .data_out_0({
        \data_out_0[7] , \data_out_0[6] , \data_out_0[5] , 
        \data_out_0[4] , \data_out_0[3] , \data_out_0[2] , 
        \data_out_0[1] , \data_out_0[0] }), .fifo_read_tx_i(
        fifo_read_tx_i), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .fifo_write_tx(fifo_write_tx));
    CFG4 #( .INIT(16'h0810) )  \counter_RNO_0[3]  (.A(
        \counter[2]_net_1 ), .B(\counter[0]_net_1 ), .C(fifo_write_tx), 
        .D(fifo_read_tx), .Y(i20_mux));
    CFG3 #( .INIT(8'h96) )  \counter_RNO[0]  (.A(\counter[0]_net_1 ), 
        .B(fifo_write_tx), .C(fifo_read_tx), .Y(N_24_0_i));
    CFG2 #( .INIT(4'h6) )  \wr_pointer_RNO[1]  (.A(N_25_0), .B(
        \wr_pointer[1]_net_1 ), .Y(N_30_0_i));
    SLE read_n_hold (.D(fifo_read_tx), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        read_n_hold_net_1));
    CFG3 #( .INIT(8'h80) )  m46 (.A(xmit_bit_sel[2]), .B(
        xmit_bit_sel[1]), .C(xmit_bit_sel[0]), .Y(N_47_i));
    SLE \wr_pointer[1]  (.D(N_30_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \wr_pointer[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  m45 (.A(xmit_bit_sel[0]), .B(
        xmit_bit_sel[1]), .Y(N_46_i));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h2) )  data_out_0_sqmuxa (.A(COREABC_0_PRESETN), 
        .B(read_n_hold_net_1), .Y(data_out_0_sqmuxa_net_1));
    CFG3 #( .INIT(8'h15) )  m43 (.A(xmit_state[2]), .B(xmit_state[3]), 
        .C(N_72), .Y(N_94_mux));
    CFG4 #( .INIT(16'hA69A) )  \counter_RNO[1]  (.A(\counter[1]_net_1 )
        , .B(\counter[0]_net_1 ), .C(fifo_write_tx), .D(fifo_read_tx), 
        .Y(N_22_0_i));
    CFG2 #( .INIT(4'h2) )  \wr_pointer_RNIQAMO[0]  (.A(
        \wr_pointer[0]_net_1 ), .B(fifo_write_tx), .Y(N_25_0));
    SLE \data_out[7]  (.D(\data_out_0[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[7]));
    SLE \data_out[4]  (.D(\data_out_0[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[4]));
    SLE \wr_pointer[3]  (.D(N_28_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \wr_pointer[3]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \rd_pointer[0]  (.D(N_422_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rd_pointer[0]_net_1 ));
    SLE \data_out[5]  (.D(\data_out_0[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[5]));
    CFG2 #( .INIT(4'h6) )  \counter_RNO[2]  (.A(N_19_0), .B(
        \counter[2]_net_1 ), .Y(N_20_0_i));
    CFG4 #( .INIT(16'h78F0) )  \wr_pointer_RNO[3]  (.A(
        \wr_pointer[1]_net_1 ), .B(N_25_0), .C(\wr_pointer[3]_net_1 ), 
        .D(\wr_pointer[2]_net_1 ), .Y(N_28_0_i));
    CFG4 #( .INIT(16'h78B4) )  \counter_RNO[3]  (.A(\counter[1]_net_1 )
        , .B(i20_mux), .C(\counter[3]_net_1 ), .D(\counter[2]_net_1 ), 
        .Y(N_18_0_i));
    CFG2 #( .INIT(4'h9) )  \wr_pointer_RNO[0]  (.A(
        \wr_pointer[0]_net_1 ), .B(fifo_write_tx), .Y(N_423_i));
    SLE \data_out[0]  (.D(\data_out_0[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[0]));
    SLE \counter[1]  (.D(N_22_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[1]_net_1 ));
    CFG4 #( .INIT(16'h0810) )  \counter_RNO_0[2]  (.A(
        \counter[1]_net_1 ), .B(\counter[0]_net_1 ), .C(fifo_write_tx), 
        .D(fifo_read_tx), .Y(N_19_0));
    CFG4 #( .INIT(16'h530F) )  m71_3_1_0 (.A(tx_byte[7]), .B(
        tx_byte[5]), .C(xmit_bit_sel[1]), .D(xmit_bit_sel[0]), .Y(
        m71_3_1_0_net_1));
    CFG3 #( .INIT(8'hAE) )  N_95_mux_i_inst_1 (.A(xmit_state[1]), .B(
        xmit_state[2]), .C(xmit_pulse), .Y(N_95_mux_i));
    SLE \data_out[2]  (.D(\data_out_0[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[2]));
    SLE \counter[3]  (.D(N_18_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[3]_net_1 ));
    CFG3 #( .INIT(8'h78) )  \wr_pointer_RNO[2]  (.A(
        \wr_pointer[1]_net_1 ), .B(N_25_0), .C(\wr_pointer[2]_net_1 ), 
        .Y(N_29_0_i));
    SLE \wr_pointer[0]  (.D(N_423_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \wr_pointer[0]_net_1 ));
    SLE \data_out[6]  (.D(\data_out_0[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[6]));
    CFG2 #( .INIT(4'h2) )  \rd_pointer_RNI6EK7[0]  (.A(
        \rd_pointer[0]_net_1 ), .B(fifo_read_tx), .Y(N_32_0));
    CFG3 #( .INIT(8'hD8) )  m71_4 (.A(xmit_bit_sel[2]), .B(m71_3_net_1)
        , .C(m71_1_net_1), .Y(N_72));
    CFG2 #( .INIT(4'h6) )  \rd_pointer_RNO[1]  (.A(N_32_0), .B(
        \rd_pointer[1]_net_1 ), .Y(N_37_0_i));
    CFG4 #( .INIT(16'h89CD) )  m71_3 (.A(xmit_bit_sel[0]), .B(
        m71_3_1_0_net_1), .C(tx_byte[6]), .D(tx_byte[4]), .Y(
        m71_3_net_1));
    CFG2 #( .INIT(4'hB) )  \counter_RNIA6RA1[3]  (.A(N_99_mux), .B(
        xmit_state[0]), .Y(xmit_state_ns_i_0));
    SLE \wr_pointer[2]  (.D(N_29_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \wr_pointer[2]_net_1 ));
    CFG4 #( .INIT(16'h78F0) )  \rd_pointer_RNO[3]  (.A(
        \rd_pointer[1]_net_1 ), .B(N_32_0), .C(\rd_pointer[3]_net_1 ), 
        .D(\rd_pointer[2]_net_1 ), .Y(N_35_0_i));
    SLE \rd_pointer[1]  (.D(N_37_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rd_pointer[1]_net_1 ));
    CFG4 #( .INIT(16'h0800) )  m52 (.A(xmit_bit_sel[1]), .B(
        xmit_bit_sel[0]), .C(xmit_bit_sel[3]), .D(xmit_bit_sel[2]), .Y(
        N_53));
    CFG2 #( .INIT(4'h9) )  \rd_pointer_RNO[0]  (.A(
        \rd_pointer[0]_net_1 ), .B(fifo_read_tx), .Y(N_422_i));
    CFG4 #( .INIT(16'h530F) )  m71_1_1_0 (.A(tx_byte[3]), .B(
        tx_byte[1]), .C(xmit_bit_sel[1]), .D(xmit_bit_sel[0]), .Y(
        m71_1_1_0_net_1));
    CFG4 #( .INIT(16'h0001) )  \counter_RNIAHEA1_0[3]  (.A(
        \counter[3]_net_1 ), .B(\counter[2]_net_1 ), .C(
        \counter[1]_net_1 ), .D(\counter[0]_net_1 ), .Y(N_99_mux));
    SLE \rd_pointer[3]  (.D(N_35_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rd_pointer[3]_net_1 ));
    SLE \data_out[1]  (.D(\data_out_0[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(tx_dout_reg[1]));
    SLE \counter[0]  (.D(N_24_0_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[0]_net_1 ));
    
endmodule


module UART_top_CoreUARTapb_0_fifo_256x8_0s_64s(
       tx_dout_reg,
       xmit_bit_sel,
       tx_byte,
       xmit_state,
       tx_hold_reg,
       xmit_state_ns_i_0,
       xmit_state_ns_0,
       COREABC_0_PRESETN,
       my_hpms_top_0_FIC32_0_CLK,
       fifo_read_tx,
       baud_clock,
       xmit_clock,
       N_45_0,
       N_47_i,
       N_46_i,
       fifo_write_tx,
       N_94_mux,
       fifo_full_tx_i,
       N_54,
       xmit_pulse,
       N_130_i,
       N_95_mux_i,
       N_101_mux_i,
       N_102_i,
       fifo_read_tx_i
    );
output [7:0] tx_dout_reg;
input  [3:0] xmit_bit_sel;
input  [7:0] tx_byte;
input  [6:0] xmit_state;
input  [7:0] tx_hold_reg;
output xmit_state_ns_i_0;
output xmit_state_ns_0;
input  COREABC_0_PRESETN;
input  my_hpms_top_0_FIC32_0_CLK;
input  fifo_read_tx;
input  baud_clock;
input  xmit_clock;
output N_45_0;
output N_47_i;
output N_46_i;
input  fifo_write_tx;
output N_94_mux;
output fifo_full_tx_i;
output N_54;
input  xmit_pulse;
output N_130_i;
output N_95_mux_i;
output N_101_mux_i;
output N_102_i;
input  fifo_read_tx_i;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s fifo_ctrl_256 (
        .tx_hold_reg({tx_hold_reg[7], tx_hold_reg[6], tx_hold_reg[5], 
        tx_hold_reg[4], tx_hold_reg[3], tx_hold_reg[2], tx_hold_reg[1], 
        tx_hold_reg[0]}), .xmit_state({xmit_state[6], xmit_state[5], 
        nc0, xmit_state[3], xmit_state[2], xmit_state[1], 
        xmit_state[0]}), .tx_byte({tx_byte[7], tx_byte[6], tx_byte[5], 
        tx_byte[4], tx_byte[3], tx_byte[2], tx_byte[1], tx_byte[0]}), 
        .xmit_bit_sel({xmit_bit_sel[3], xmit_bit_sel[2], 
        xmit_bit_sel[1], xmit_bit_sel[0]}), .tx_dout_reg({
        tx_dout_reg[7], tx_dout_reg[6], tx_dout_reg[5], tx_dout_reg[4], 
        tx_dout_reg[3], tx_dout_reg[2], tx_dout_reg[1], tx_dout_reg[0]})
        , .xmit_state_ns_0(xmit_state_ns_0), .xmit_state_ns_i_0(
        xmit_state_ns_i_0), .fifo_read_tx_i(fifo_read_tx_i), .N_102_i(
        N_102_i), .N_101_mux_i(N_101_mux_i), .N_95_mux_i(N_95_mux_i), 
        .N_130_i(N_130_i), .xmit_pulse(xmit_pulse), .N_54(N_54), 
        .fifo_full_tx_i(fifo_full_tx_i), .N_94_mux(N_94_mux), 
        .fifo_write_tx(fifo_write_tx), .N_46_i(N_46_i), .N_47_i(N_47_i)
        , .N_45_0(N_45_0), .xmit_clock(xmit_clock), .baud_clock(
        baud_clock), .fifo_read_tx(fifo_read_tx), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .COREABC_0_PRESETN(COREABC_0_PRESETN));
    
endmodule


module UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(
       xmit_state,
       tx_dout_reg,
       tx_byte,
       xmit_bit_sel,
       xmit_state_ns_0,
       xmit_state_ns_i_0,
       N_47_i,
       N_46_i,
       xmit_pulse,
       N_54,
       N_102_i,
       N_95_mux_i,
       N_101_mux_i,
       fifo_full_tx_i,
       CoreUARTapb_0_TXRDY,
       N_130_i,
       N_94_mux,
       TX_c,
       N_45_0,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN,
       fifo_read_tx_i,
       fifo_read_tx
    );
output [6:0] xmit_state;
input  [7:0] tx_dout_reg;
output [7:0] tx_byte;
output [3:0] xmit_bit_sel;
input  xmit_state_ns_0;
input  xmit_state_ns_i_0;
input  N_47_i;
input  N_46_i;
input  xmit_pulse;
input  N_54;
input  N_102_i;
input  N_95_mux_i;
input  N_101_mux_i;
input  fifo_full_tx_i;
output CoreUARTapb_0_TXRDY;
input  N_130_i;
input  N_94_mux;
output TX_c;
input  N_45_0;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;
output fifo_read_tx_i;
output fifo_read_tx;

    wire VCC_net_1, GND_net_1, xmit_bit_sel_100_net_1, 
        xmit_bit_sel_101_net_1, xmit_bit_sel_102_net_1, 
        xmit_bit_sel_103_net_1;
    
    SLE \xmit_bit_sel[2]  (.D(xmit_bit_sel_102_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_bit_sel[2]));
    SLE \xmit_bit_sel[1]  (.D(xmit_bit_sel_101_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_bit_sel[1]));
    SLE txrdy_int (.D(fifo_full_tx_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreUARTapb_0_TXRDY));
    SLE \xmit_state[6]  (.D(xmit_state_ns_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_state[6]));
    SLE \tx_byte[1]  (.D(tx_dout_reg[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[1]));
    SLE \tx_byte[0]  (.D(tx_dout_reg[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[0]));
    SLE fifo_read_en0 (.D(xmit_state_ns_i_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_130_i), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(fifo_read_tx));
    SLE \tx_byte[6]  (.D(tx_dout_reg[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[6]));
    SLE \tx_byte[5]  (.D(tx_dout_reg[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[5]));
    CFG1 #( .INIT(2'h1) )  fifo_read_en0_RNIN362 (.A(fifo_read_tx), .Y(
        fifo_read_tx_i));
    GND GND (.Y(GND_net_1));
    SLE \tx_byte[3]  (.D(tx_dout_reg[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[3]));
    CFG4 #( .INIT(16'h7830) )  xmit_bit_sel_101 (.A(xmit_bit_sel[0]), 
        .B(xmit_pulse), .C(xmit_bit_sel[1]), .D(xmit_state[3]), .Y(
        xmit_bit_sel_101_net_1));
    SLE tx (.D(N_94_mux), .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(N_130_i)
        , .ALn(COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(TX_c));
    SLE \xmit_state[0]  (.D(N_101_mux_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_state[0]));
    SLE \xmit_bit_sel[0]  (.D(xmit_bit_sel_100_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_bit_sel[0]));
    SLE \tx_byte[7]  (.D(tx_dout_reg[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[7]));
    SLE \tx_byte[2]  (.D(tx_dout_reg[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[2]));
    SLE \xmit_state[1]  (.D(xmit_state[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_state[1]));
    CFG3 #( .INIT(8'h62) )  xmit_bit_sel_100 (.A(xmit_bit_sel[0]), .B(
        xmit_pulse), .C(xmit_state[3]), .Y(xmit_bit_sel_100_net_1));
    SLE \xmit_state[3]  (.D(N_102_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(xmit_state[3]));
    CFG4 #( .INIT(16'h2C8C) )  xmit_bit_sel_103 (.A(xmit_state[3]), .B(
        xmit_bit_sel[3]), .C(xmit_pulse), .D(N_47_i), .Y(
        xmit_bit_sel_103_net_1));
    SLE \xmit_state[5]  (.D(N_54), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(xmit_pulse), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        xmit_state[5]));
    CFG4 #( .INIT(16'h2C8C) )  xmit_bit_sel_102 (.A(xmit_state[3]), .B(
        xmit_bit_sel[2]), .C(xmit_pulse), .D(N_46_i), .Y(
        xmit_bit_sel_102_net_1));
    SLE \xmit_bit_sel[3]  (.D(xmit_bit_sel_103_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_bit_sel[3]));
    SLE \xmit_state[2]  (.D(N_95_mux_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_state[2]));
    VCC VCC (.Y(VCC_net_1));
    SLE \tx_byte[4]  (.D(tx_dout_reg[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_45_0), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(tx_byte[4]));
    
endmodule


module UART_top_CoreUARTapb_0_Clock_gen_0s_0s(
       xmit_pulse,
       baud_clock,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN,
       xmit_clock
    );
output xmit_pulse;
output baud_clock;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;
output xmit_clock;

    wire VCC_net_1, xmit_clock5, GND_net_1, \xmit_cntr[0]_net_1 , 
        N_148_i, \xmit_cntr[1]_net_1 , N_149_i_i, \xmit_cntr[2]_net_1 , 
        N_150_i_i, \xmit_cntr[3]_net_1 , N_168_i_i, 
        baud_cntr8_1_RNIIBTS_Y, \baud_cntr[0] , \baud_cntr_s[0] , 
        \baud_cntr[1] , \baud_cntr_s[1] , \baud_cntr[2] , 
        \baud_cntr_s[2] , \baud_cntr[3] , \baud_cntr_s[3] , 
        \baud_cntr[4] , \baud_cntr_s[4] , \baud_cntr[5] , 
        \baud_cntr_s[5] , \baud_cntr[6] , \baud_cntr_s[6] , 
        \baud_cntr[7] , \baud_cntr_s[7] , \baud_cntr[8] , 
        \baud_cntr_s[8] , \baud_cntr[9] , \baud_cntr_s[9] , 
        \baud_cntr[10] , \baud_cntr_s[10] , \baud_cntr[11] , 
        \baud_cntr_s[11] , \baud_cntr[12] , \baud_cntr_s[12] , 
        baud_cntr_cry_cy, baud_cntr8_1, baud_cntr8_7, baud_cntr8_8, 
        \baud_cntr_cry[0] , \baud_cntr_cry[1] , \baud_cntr_cry[2] , 
        \baud_cntr_cry[3] , \baud_cntr_cry[4] , \baud_cntr_cry[5] , 
        \baud_cntr_cry[6] , \baud_cntr_cry[7] , \baud_cntr_cry[8] , 
        \baud_cntr_cry[9] , \baud_cntr_cry[10] , \baud_cntr_cry[11] , 
        \SUM_0_o2[1] ;
    
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNI09V18[7]  (.A(
        VCC_net_1), .B(\baud_cntr[7] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[6] ), .S(\baud_cntr_s[7] ), .Y(), .FCO(
        \baud_cntr_cry[7] ));
    SLE \genblk1.baud_cntr[4]  (.D(\baud_cntr_s[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[4] ));
    CFG4 #( .INIT(16'hD2F0) )  
        \make_xmit_clock.xmit_cntr_3_1.N_168_i_i  (.A(
        \xmit_cntr[1]_net_1 ), .B(\SUM_0_o2[1] ), .C(
        \xmit_cntr[3]_net_1 ), .D(\xmit_cntr[2]_net_1 ), .Y(N_168_i_i));
    SLE \genblk1.baud_cntr[1]  (.D(\baud_cntr_s[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[1] ));
    SLE \genblk1.baud_cntr[3]  (.D(\baud_cntr_s[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[3] ));
    ARI1 #( .INIT(20'h44000) )  
        \genblk1.make_baud_cntr.baud_cntr8_1_RNIIBTS  (.A(baud_cntr8_8)
        , .B(\baud_cntr[2] ), .C(baud_cntr8_1), .D(baud_cntr8_7), .FCI(
        VCC_net_1), .S(), .Y(baud_cntr8_1_RNIIBTS_Y), .FCO(
        baud_cntr_cry_cy));
    SLE \xmit_cntr[3]  (.D(N_168_i_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \xmit_cntr[3]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNIPKE85[4]  (.A(
        VCC_net_1), .B(\baud_cntr[4] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[3] ), .S(\baud_cntr_s[4] ), .Y(), .FCO(
        \baud_cntr_cry[4] ));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNI02OF9[11]  (.A(
        VCC_net_1), .B(\baud_cntr[11] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[10] ), .S(\baud_cntr_s[11] ), .Y(), .FCO(
        \baud_cntr_cry[11] ));
    SLE \genblk1.baud_cntr[9]  (.D(\baud_cntr_s[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[9] ));
    SLE \genblk1.baud_clock_int  (.D(baud_cntr8_1_RNIIBTS_Y), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(baud_clock));
    CFG4 #( .INIT(16'h0001) )  \genblk1.make_baud_cntr.baud_cntr8_8  (
        .A(\baud_cntr[12] ), .B(\baud_cntr[7] ), .C(\baud_cntr[6] ), 
        .D(\baud_cntr[5] ), .Y(baud_cntr8_8));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNI3AHC8[8]  (.A(
        VCC_net_1), .B(\baud_cntr[8] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[7] ), .S(\baud_cntr_s[8] ), .Y(), .FCO(
        \baud_cntr_cry[8] ));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'h8000) )  \make_xmit_clock.xmit_clock5_0_a2  (.A(
        \xmit_cntr[2]_net_1 ), .B(\xmit_cntr[3]_net_1 ), .C(
        \xmit_cntr[1]_net_1 ), .D(\xmit_cntr[0]_net_1 ), .Y(
        xmit_clock5));
    CFG3 #( .INIT(8'hD2) )  \make_xmit_clock.xmit_cntr_3_1.N_150_i_i  
        (.A(\xmit_cntr[1]_net_1 ), .B(\SUM_0_o2[1] ), .C(
        \xmit_cntr[2]_net_1 ), .Y(N_150_i_i));
    ARI1 #( .INIT(20'h61100) )  \genblk1.baud_cntr_RNIDLRB3[1]  (.A(
        VCC_net_1), .B(baud_cntr8_1_RNIIBTS_Y), .C(\baud_cntr[1] ), .D(
        GND_net_1), .FCI(\baud_cntr_cry[0] ), .S(\baud_cntr_s[1] ), .Y(
        ), .FCO(\baud_cntr_cry[1] ));
    SLE \genblk1.baud_cntr[7]  (.D(\baud_cntr_s[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[7] ));
    SLE \genblk1.baud_cntr[5]  (.D(\baud_cntr_s[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[5] ));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNIJMD39[10]  (.A(
        VCC_net_1), .B(\baud_cntr[10] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[9] ), .S(\baud_cntr_s[10] ), .Y(), .FCO(
        \baud_cntr_cry[10] ));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h0001) )  \genblk1.make_baud_cntr.baud_cntr8_1  (
        .A(\baud_cntr[4] ), .B(\baud_cntr[3] ), .C(\baud_cntr[1] ), .D(
        \baud_cntr[0] ), .Y(baud_cntr8_1));
    ARI1 #( .INIT(20'h61100) )  \genblk1.baud_cntr_RNIBUTF6[5]  (.A(
        VCC_net_1), .B(baud_cntr8_1_RNIIBTS_Y), .C(\baud_cntr[5] ), .D(
        GND_net_1), .FCI(\baud_cntr_cry[4] ), .S(\baud_cntr_s[5] ), .Y(
        ), .FCO(\baud_cntr_cry[5] ));
    SLE \genblk1.baud_cntr[8]  (.D(\baud_cntr_s[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[8] ));
    ARI1 #( .INIT(20'h61100) )  \genblk1.baud_cntr_RNIU8DN7[6]  (.A(
        VCC_net_1), .B(baud_cntr8_1_RNIIBTS_Y), .C(\baud_cntr[6] ), .D(
        GND_net_1), .FCI(\baud_cntr_cry[5] ), .S(\baud_cntr_s[6] ), .Y(
        ), .FCO(\baud_cntr_cry[6] ));
    CFG2 #( .INIT(4'h6) )  \make_xmit_clock.xmit_cntr_3_1.SUM_0_x2[0]  
        (.A(baud_clock), .B(\xmit_cntr[0]_net_1 ), .Y(N_148_i));
    SLE \genblk1.baud_cntr[0]  (.D(\baud_cntr_s[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[0] ));
    ARI1 #( .INIT(20'h61100) )  \genblk1.baud_cntr_RNIQNST4[3]  (.A(
        VCC_net_1), .B(baud_cntr8_1_RNIIBTS_Y), .C(\baud_cntr[3] ), .D(
        GND_net_1), .FCI(\baud_cntr_cry[2] ), .S(\baud_cntr_s[3] ), .Y(
        ), .FCO(\baud_cntr_cry[3] ));
    CFG4 #( .INIT(16'h0001) )  \genblk1.make_baud_cntr.baud_cntr8_7  (
        .A(\baud_cntr[11] ), .B(\baud_cntr[10] ), .C(\baud_cntr[9] ), 
        .D(\baud_cntr[8] ), .Y(baud_cntr8_7));
    SLE \xmit_cntr[2]  (.D(N_150_i_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \xmit_cntr[2]_net_1 ));
    SLE \genblk1.baud_cntr[10]  (.D(\baud_cntr_s[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[10] ));
    SLE \genblk1.baud_cntr[6]  (.D(\baud_cntr_s[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[6] ));
    CFG2 #( .INIT(4'h9) )  \make_xmit_clock.xmit_cntr_3_1.N_149_i_i  (
        .A(\SUM_0_o2[1] ), .B(\xmit_cntr[1]_net_1 ), .Y(N_149_i_i));
    SLE xmit_clock_inst_1 (.D(xmit_clock5), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(baud_clock), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(xmit_clock));
    ARI1 #( .INIT(20'h45500) )  \genblk1.baud_cntr_RNO[12]  (.A(
        VCC_net_1), .B(\baud_cntr[12] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[11] ), .S(\baud_cntr_s[12] ), .Y(), .FCO());
    ARI1 #( .INIT(20'h61100) )  \genblk1.baud_cntr_RNIVFC42[0]  (.A(
        VCC_net_1), .B(baud_cntr8_1_RNIIBTS_Y), .C(\baud_cntr[0] ), .D(
        GND_net_1), .FCI(baud_cntr_cry_cy), .S(\baud_cntr_s[0] ), .Y(), 
        .FCO(\baud_cntr_cry[0] ));
    SLE \genblk1.baud_cntr[12]  (.D(\baud_cntr_s[12] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[12] ));
    SLE \xmit_cntr[1]  (.D(N_149_i_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \xmit_cntr[1]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \make_xmit_clock.xmit_cntr_3_1.SUM_0_o2[1]  
        (.A(baud_clock), .B(\xmit_cntr[0]_net_1 ), .Y(\SUM_0_o2[1] ));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNIAGDM3[2]  (.A(
        VCC_net_1), .B(\baud_cntr[2] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[1] ), .S(\baud_cntr_s[2] ), .Y(), .FCO(
        \baud_cntr_cry[2] ));
    SLE \genblk1.baud_cntr[2]  (.D(\baud_cntr_s[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[2] ));
    CFG2 #( .INIT(4'h8) )  xmit_pulse_inst_1 (.A(baud_clock), .B(
        xmit_clock), .Y(xmit_pulse));
    SLE \xmit_cntr[0]  (.D(N_148_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \xmit_cntr[0]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \genblk1.baud_cntr_RNI7C3N8[9]  (.A(
        VCC_net_1), .B(\baud_cntr[9] ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\baud_cntr_cry[8] ), .S(\baud_cntr_s[9] ), .Y(), .FCO(
        \baud_cntr_cry[9] ));
    SLE \genblk1.baud_cntr[11]  (.D(\baud_cntr_s[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\baud_cntr[11] ));
    
endmodule


module UART_top_CoreUARTapb_0_ram16x8_0(
       counter,
       rx_byte,
       wr_pointer,
       rd_pointer,
       data_out_0,
       fifo_write,
       fifo_read_rx_0_sqmuxa,
       my_hpms_top_0_FIC32_0_CLK
    );
input  [3:0] counter;
input  [7:0] rx_byte;
input  [3:0] wr_pointer;
input  [3:0] rd_pointer;
output [7:0] data_out_0;
input  fifo_write;
input  fifo_read_rx_0_sqmuxa;
input  my_hpms_top_0_FIC32_0_CLK;

    wire VCC_net_1, GND_net_1, memory_memory_0_0_we_0, fifo_full_rx_i;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    RAM64x18 memory_memory_0_0 (.A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, 
        nc6, nc7, nc8, nc9, data_out_0[7], data_out_0[6], 
        data_out_0[5], data_out_0[4], data_out_0[3], data_out_0[2], 
        data_out_0[1], data_out_0[0]}), .B_DOUT({nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, 
        nc23, nc24, nc25, nc26, nc27}), .BUSY(), .A_ADDR_CLK(VCC_net_1)
        , .A_DOUT_CLK(my_hpms_top_0_FIC32_0_CLK), .A_ADDR_SRST_N(
        VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_ADDR_ARST_N(
        VCC_net_1), .A_DOUT_ARST_N(VCC_net_1), .A_ADDR_EN(VCC_net_1), 
        .A_DOUT_EN(fifo_read_rx_0_sqmuxa), .A_BLK({VCC_net_1, 
        VCC_net_1}), .A_ADDR({GND_net_1, GND_net_1, GND_net_1, 
        rd_pointer[3], rd_pointer[2], rd_pointer[1], rd_pointer[0], 
        GND_net_1, GND_net_1, GND_net_1}), .B_ADDR_CLK(VCC_net_1), 
        .B_DOUT_CLK(VCC_net_1), .B_ADDR_SRST_N(VCC_net_1), 
        .B_DOUT_SRST_N(VCC_net_1), .B_ADDR_ARST_N(VCC_net_1), 
        .B_DOUT_ARST_N(VCC_net_1), .B_ADDR_EN(VCC_net_1), .B_DOUT_EN(
        VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1}), .B_ADDR({GND_net_1, 
        GND_net_1, GND_net_1, rd_pointer[3], rd_pointer[2], 
        rd_pointer[1], rd_pointer[0], GND_net_1, GND_net_1, GND_net_1})
        , .C_CLK(my_hpms_top_0_FIC32_0_CLK), .C_ADDR({GND_net_1, 
        GND_net_1, GND_net_1, wr_pointer[3], wr_pointer[2], 
        wr_pointer[1], wr_pointer[0], GND_net_1, GND_net_1, GND_net_1})
        , .C_DIN({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, rx_byte[7], rx_byte[6], rx_byte[5], rx_byte[4], 
        rx_byte[3], rx_byte[2], rx_byte[1], rx_byte[0]}), .C_WEN(
        memory_memory_0_0_we_0), .C_BLK({VCC_net_1, VCC_net_1}), .A_EN(
        VCC_net_1), .A_ADDR_LAT(VCC_net_1), .A_DOUT_LAT(GND_net_1), 
        .A_WIDTH({GND_net_1, VCC_net_1, VCC_net_1}), .B_EN(GND_net_1), 
        .B_ADDR_LAT(VCC_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({
        GND_net_1, VCC_net_1, VCC_net_1}), .C_EN(VCC_net_1), .C_WIDTH({
        GND_net_1, VCC_net_1, VCC_net_1}), .SII_LOCK(GND_net_1));
    CFG4 #( .INIT(16'h7FFF) )  memory_memory_0_0_RNO_0 (.A(counter[3]), 
        .B(counter[2]), .C(counter[1]), .D(counter[0]), .Y(
        fifo_full_rx_i));
    CFG2 #( .INIT(4'h2) )  memory_memory_0_0_RNO (.A(fifo_full_rx_i), 
        .B(fifo_write), .Y(memory_memory_0_0_we_0));
    
endmodule


module UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s_0(
       rx_byte,
       rx_state,
       rx_dout,
       counter,
       fifo_write,
       N_224,
       next_rx_state4,
       fifo_read_rx_0_sqmuxa,
       fifo_full_rx,
       fifo_empty_rx_1,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
input  [7:0] rx_byte;
input  [1:0] rx_state;
output [7:0] rx_dout;
output [3:2] counter;
input  fifo_write;
input  N_224;
input  next_rx_state4;
input  fifo_read_rx_0_sqmuxa;
output fifo_full_rx;
output fifo_empty_rx_1;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire VCC_net_1, \SUM[2] , GND_net_1, \SUM[3] , 
        \rd_pointer[0]_net_1 , \rd_pointer_4[0] , 
        \rd_pointer[1]_net_1 , \rd_pointer_4[1] , 
        \rd_pointer[2]_net_1 , \rd_pointer_4[2] , 
        \rd_pointer[3]_net_1 , \rd_pointer_4[3] , 
        \wr_pointer[0]_net_1 , N_421_i, \wr_pointer[1]_net_1 , 
        \wr_pointer_4[1] , \wr_pointer[2]_net_1 , \wr_pointer_4[2] , 
        \wr_pointer[3]_net_1 , \wr_pointer_4[3] , \counter[0]_net_1 , 
        \SUM[0] , \counter[1]_net_1 , \SUM[1] , \data_out_0[5] , 
        data_out_0_sqmuxa_net_1, \data_out_0[6] , \data_out_0[7] , 
        \data_out_0[0] , \data_out_0[1] , \data_out_0[2] , 
        \data_out_0[3] , \data_out_0[4] , read_n_hold_net_1, 
        fifo_read_rx_0_sqmuxa_i, counter_0_sqmuxa_net_1, CO1, CO0, 
        CO1_0;
    
    SLE \rd_pointer[2]  (.D(\rd_pointer_4[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rd_pointer[2]_net_1 ));
    SLE \counter[2]  (.D(\SUM[2] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(counter[2]));
    CFG4 #( .INIT(16'hD2B4) )  \un1_counter_1.SUM[1]  (.A(N_224), .B(
        fifo_read_rx_0_sqmuxa), .C(\counter[1]_net_1 ), .D(
        \counter[0]_net_1 ), .Y(\SUM[1] ));
    CFG2 #( .INIT(4'h8) )  \wr_pointer_4_1.CO0  (.A(N_224), .B(
        \wr_pointer[0]_net_1 ), .Y(CO0));
    CFG2 #( .INIT(4'h6) )  \wr_pointer_4_1.N_421_i  (.A(N_224), .B(
        \wr_pointer[0]_net_1 ), .Y(N_421_i));
    SLE \data_out[3]  (.D(\data_out_0[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[3]));
    CFG3 #( .INIT(8'h78) )  \rd_pointer_4_1.SUM[3]  (.A(
        \rd_pointer[2]_net_1 ), .B(CO1_0), .C(\rd_pointer[3]_net_1 ), 
        .Y(\rd_pointer_4[3] ));
    UART_top_CoreUARTapb_0_ram16x8_0 ram16x8 (.counter({counter[3], 
        counter[2], \counter[1]_net_1 , \counter[0]_net_1 }), .rx_byte({
        rx_byte[7], rx_byte[6], rx_byte[5], rx_byte[4], rx_byte[3], 
        rx_byte[2], rx_byte[1], rx_byte[0]}), .wr_pointer({
        \wr_pointer[3]_net_1 , \wr_pointer[2]_net_1 , 
        \wr_pointer[1]_net_1 , \wr_pointer[0]_net_1 }), .rd_pointer({
        \rd_pointer[3]_net_1 , \rd_pointer[2]_net_1 , 
        \rd_pointer[1]_net_1 , \rd_pointer[0]_net_1 }), .data_out_0({
        \data_out_0[7] , \data_out_0[6] , \data_out_0[5] , 
        \data_out_0[4] , \data_out_0[3] , \data_out_0[2] , 
        \data_out_0[1] , \data_out_0[0] }), .fifo_write(fifo_write), 
        .fifo_read_rx_0_sqmuxa(fifo_read_rx_0_sqmuxa), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK));
    SLE read_n_hold (.D(fifo_read_rx_0_sqmuxa_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(read_n_hold_net_1));
    SLE \wr_pointer[1]  (.D(\wr_pointer_4[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wr_pointer[1]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h2) )  data_out_0_sqmuxa (.A(COREABC_0_PRESETN), 
        .B(read_n_hold_net_1), .Y(data_out_0_sqmuxa_net_1));
    CFG3 #( .INIT(8'h96) )  \un1_counter_1.SUM[0]  (.A(N_224), .B(
        fifo_read_rx_0_sqmuxa), .C(\counter[0]_net_1 ), .Y(\SUM[0] ));
    CFG3 #( .INIT(8'hEF) )  read_n_hold_RNO (.A(rx_state[1]), .B(
        rx_state[0]), .C(next_rx_state4), .Y(fifo_read_rx_0_sqmuxa_i));
    SLE \data_out[7]  (.D(\data_out_0[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[7]));
    SLE \data_out[4]  (.D(\data_out_0[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[4]));
    CFG3 #( .INIT(8'h80) )  \rd_pointer_4_1.CO1  (.A(
        \rd_pointer[1]_net_1 ), .B(\rd_pointer[0]_net_1 ), .C(
        fifo_read_rx_0_sqmuxa), .Y(CO1_0));
    CFG2 #( .INIT(4'h1) )  empty_1 (.A(\counter[0]_net_1 ), .B(
        \counter[1]_net_1 ), .Y(fifo_empty_rx_1));
    SLE \wr_pointer[3]  (.D(\wr_pointer_4[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wr_pointer[3]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \rd_pointer[0]  (.D(\rd_pointer_4[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rd_pointer[0]_net_1 ));
    SLE \data_out[5]  (.D(\data_out_0[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[5]));
    CFG2 #( .INIT(4'h6) )  \rd_pointer_4_1.SUM[2]  (.A(CO1_0), .B(
        \rd_pointer[2]_net_1 ), .Y(\rd_pointer_4[2] ));
    CFG4 #( .INIT(16'h6440) )  \un1_counter_1.CO1  (.A(N_224), .B(
        fifo_read_rx_0_sqmuxa), .C(\counter[1]_net_1 ), .D(
        \counter[0]_net_1 ), .Y(CO1));
    SLE \data_out[0]  (.D(\data_out_0[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[0]));
    SLE \counter[1]  (.D(\SUM[1] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[1]_net_1 ));
    CFG4 #( .INIT(16'h78F0) )  \wr_pointer_4_1.SUM[3]  (.A(
        \wr_pointer[1]_net_1 ), .B(CO0), .C(\wr_pointer[3]_net_1 ), .D(
        \wr_pointer[2]_net_1 ), .Y(\wr_pointer_4[3] ));
    SLE \data_out[2]  (.D(\data_out_0[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[2]));
    SLE \counter[3]  (.D(\SUM[3] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(counter[3]));
    SLE \wr_pointer[0]  (.D(N_421_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \wr_pointer[0]_net_1 ));
    CFG2 #( .INIT(4'h6) )  \rd_pointer_4_1.SUM[0]  (.A(
        fifo_read_rx_0_sqmuxa), .B(\rd_pointer[0]_net_1 ), .Y(
        \rd_pointer_4[0] ));
    SLE \data_out[6]  (.D(\data_out_0[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[6]));
    CFG4 #( .INIT(16'h0002) )  counter_0_sqmuxa (.A(next_rx_state4), 
        .B(N_224), .C(rx_state[1]), .D(rx_state[0]), .Y(
        counter_0_sqmuxa_net_1));
    CFG4 #( .INIT(16'hA69A) )  \un1_counter_1.SUM[3]  (.A(counter[3]), 
        .B(counter[2]), .C(counter_0_sqmuxa_net_1), .D(CO1), .Y(
        \SUM[3] ));
    SLE \wr_pointer[2]  (.D(\wr_pointer_4[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wr_pointer[2]_net_1 ));
    SLE \rd_pointer[1]  (.D(\rd_pointer_4[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rd_pointer[1]_net_1 ));
    SLE \rd_pointer[3]  (.D(\rd_pointer_4[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rd_pointer[3]_net_1 ));
    SLE \data_out[1]  (.D(\data_out_0[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(data_out_0_sqmuxa_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(rx_dout[1]));
    CFG3 #( .INIT(8'h6A) )  \rd_pointer_4_1.SUM[1]  (.A(
        \rd_pointer[1]_net_1 ), .B(\rd_pointer[0]_net_1 ), .C(
        fifo_read_rx_0_sqmuxa), .Y(\rd_pointer_4[1] ));
    CFG4 #( .INIT(16'h8000) )  full (.A(counter[3]), .B(counter[2]), 
        .C(\counter[1]_net_1 ), .D(\counter[0]_net_1 ), .Y(
        fifo_full_rx));
    CFG2 #( .INIT(4'h6) )  \wr_pointer_4_1.SUM[1]  (.A(CO0), .B(
        \wr_pointer[1]_net_1 ), .Y(\wr_pointer_4[1] ));
    SLE \counter[0]  (.D(\SUM[0] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \counter[0]_net_1 ));
    CFG3 #( .INIT(8'h96) )  \un1_counter_1.SUM[2]  (.A(counter[2]), .B(
        counter_0_sqmuxa_net_1), .C(CO1), .Y(\SUM[2] ));
    CFG3 #( .INIT(8'h78) )  \wr_pointer_4_1.SUM[2]  (.A(
        \wr_pointer[1]_net_1 ), .B(CO0), .C(\wr_pointer[2]_net_1 ), .Y(
        \wr_pointer_4[2] ));
    
endmodule


module UART_top_CoreUARTapb_0_fifo_256x8_0s_64s_0(
       counter,
       rx_dout,
       rx_state,
       rx_byte,
       COREABC_0_PRESETN,
       my_hpms_top_0_FIC32_0_CLK,
       fifo_empty_rx_1,
       fifo_full_rx,
       fifo_read_rx_0_sqmuxa,
       next_rx_state4,
       N_224,
       fifo_write
    );
output [3:2] counter;
output [7:0] rx_dout;
input  [1:0] rx_state;
input  [7:0] rx_byte;
input  COREABC_0_PRESETN;
input  my_hpms_top_0_FIC32_0_CLK;
output fifo_empty_rx_1;
output fifo_full_rx;
input  fifo_read_rx_0_sqmuxa;
input  next_rx_state4;
input  N_224;
input  fifo_write;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s_0 fifo_ctrl_256 
        (.rx_byte({rx_byte[7], rx_byte[6], rx_byte[5], rx_byte[4], 
        rx_byte[3], rx_byte[2], rx_byte[1], rx_byte[0]}), .rx_state({
        rx_state[1], rx_state[0]}), .rx_dout({rx_dout[7], rx_dout[6], 
        rx_dout[5], rx_dout[4], rx_dout[3], rx_dout[2], rx_dout[1], 
        rx_dout[0]}), .counter({counter[3], counter[2]}), .fifo_write(
        fifo_write), .N_224(N_224), .next_rx_state4(next_rx_state4), 
        .fifo_read_rx_0_sqmuxa(fifo_read_rx_0_sqmuxa), .fifo_full_rx(
        fifo_full_rx), .fifo_empty_rx_1(fifo_empty_rx_1), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .COREABC_0_PRESETN(COREABC_0_PRESETN));
    
endmodule


module UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(
       COREABC_0_APB3master_PWDATA,
       rx_dout_reg,
       FRAMING_ERR,
       RX_c,
       TX_c,
       CoreUARTapb_0_TXRDY,
       un1_framing_error11_i_a2_0,
       CoreAPB3_0_APBmslave1_PSELx,
       COREABC_0_APB3master_PENABLE,
       COREABC_0_APB3master_PWRITE,
       N_7110_reto,
       N_316,
       N_7111_reto,
       N_7109_reto,
       CoreUARTapb_0_RXRDY,
       OVERFLOW,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
input  [7:0] COREABC_0_APB3master_PWDATA;
output [7:0] rx_dout_reg;
output FRAMING_ERR;
input  RX_c;
output TX_c;
output CoreUARTapb_0_TXRDY;
output un1_framing_error11_i_a2_0;
input  CoreAPB3_0_APBmslave1_PSELx;
input  COREABC_0_APB3master_PENABLE;
input  COREABC_0_APB3master_PWRITE;
input  N_7110_reto;
output N_316;
input  N_7111_reto;
input  N_7109_reto;
output CoreUARTapb_0_RXRDY;
output OVERFLOW;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire rx_dout_reg_empty_net_1, rx_dout_reg_empty_i, 
        \tx_hold_reg[4]_net_1 , VCC_net_1, tx_hold_reg5, GND_net_1, 
        \tx_hold_reg[5]_net_1 , \tx_hold_reg[6]_net_1 , 
        \tx_hold_reg[7]_net_1 , \rx_dout[0] , rx_dout_reg4_i, 
        \rx_dout[1] , \rx_dout[2] , \rx_dout[3] , \rx_dout[4] , 
        \rx_dout[5] , \rx_dout[6] , \rx_dout[7] , 
        \tx_hold_reg[0]_net_1 , \tx_hold_reg[1]_net_1 , 
        \tx_hold_reg[2]_net_1 , \tx_hold_reg[3]_net_1 , rx_dout_reg4, 
        rx_dout_reg_empty_1_sqmuxa_i_net_1, overflow_reg5, 
        un2_clear_framing_error_0_net_1, \rx_state[0]_net_1 , 
        \rx_state_ns[0] , \rx_state[1]_net_1 , N_211_i, 
        clear_parity_reg_net_1, clear_parity_reg0, clear_parity_en, 
        fifo_write_tx_net_1, tx_hold_reg5_i, next_rx_state4_net_1, 
        fifo_read_rx_0_sqmuxa, \counter[3] , \counter[2] , 
        fifo_empty_rx_1, fifo_full_rx, fifo_write, N_224, N_238, 
        xmit_pulse, baud_clock, xmit_clock, \xmit_state_ns[6] , 
        \xmit_state[0] , \xmit_state[1] , \xmit_state[2] , 
        \xmit_state[3] , \xmit_state[5] , \xmit_state[6] , 
        \xmit_state_ns_i[6] , \tx_dout_reg[0] , \tx_dout_reg[1] , 
        \tx_dout_reg[2] , \tx_dout_reg[3] , \tx_dout_reg[4] , 
        \tx_dout_reg[5] , \tx_dout_reg[6] , \tx_dout_reg[7] , 
        \tx_byte[0] , \tx_byte[1] , \tx_byte[2] , \tx_byte[3] , 
        \tx_byte[4] , \tx_byte[5] , \tx_byte[6] , \tx_byte[7] , 
        \xmit_bit_sel[0] , \xmit_bit_sel[1] , \xmit_bit_sel[2] , 
        \xmit_bit_sel[3] , N_47_i, N_46_i, N_54, N_102_i, N_95_mux_i, 
        N_101_mux_i, fifo_full_tx_i, N_130_i, N_94_mux, N_45_0, 
        fifo_read_tx_i, fifo_read_tx, \rx_byte[0] , \rx_byte[1] , 
        \rx_byte[2] , \rx_byte[3] , \rx_byte[4] , \rx_byte[5] , 
        \rx_byte[6] , \rx_byte[7] ;
    
    SLE \tx_hold_reg[5]  (.D(COREABC_0_APB3master_PWDATA[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[5]_net_1 ));
    SLE \rx_dout_reg[0]  (.D(\rx_dout[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[0]));
    CFG2 #( .INIT(4'h6) )  \rx_state_ns_0_x3[1]  (.A(
        \rx_state[0]_net_1 ), .B(\rx_state[1]_net_1 ), .Y(N_211_i));
    UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s make_RX (
        .rx_byte({\rx_byte[7] , \rx_byte[6] , \rx_byte[5] , 
        \rx_byte[4] , \rx_byte[3] , \rx_byte[2] , \rx_byte[1] , 
        \rx_byte[0] }), .N_238(N_238), .clear_parity_reg(
        clear_parity_reg_net_1), .un1_framing_error11_i_a2_0(
        un1_framing_error11_i_a2_0), .N_7109_reto(N_7109_reto), 
        .N_7111_reto(N_7111_reto), .N_7110_reto(N_7110_reto), .RX_c(
        RX_c), .fifo_write(fifo_write), .clear_parity_en(
        clear_parity_en), .FRAMING_ERR(FRAMING_ERR), .baud_clock(
        baud_clock), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN));
    SLE \tx_hold_reg[0]  (.D(COREABC_0_APB3master_PWDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[0]_net_1 ));
    CFG3 #( .INIT(8'h32) )  \rx_state_ns_0_a2[0]  (.A(
        \rx_state[1]_net_1 ), .B(\rx_state[0]_net_1 ), .C(
        next_rx_state4_net_1), .Y(\rx_state_ns[0] ));
    SLE \rx_dout_reg[3]  (.D(\rx_dout[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[3]));
    UART_top_CoreUARTapb_0_fifo_256x8_0s_64s \genblk2.tx_fifo  (
        .tx_dout_reg({\tx_dout_reg[7] , \tx_dout_reg[6] , 
        \tx_dout_reg[5] , \tx_dout_reg[4] , \tx_dout_reg[3] , 
        \tx_dout_reg[2] , \tx_dout_reg[1] , \tx_dout_reg[0] }), 
        .xmit_bit_sel({\xmit_bit_sel[3] , \xmit_bit_sel[2] , 
        \xmit_bit_sel[1] , \xmit_bit_sel[0] }), .tx_byte({\tx_byte[7] , 
        \tx_byte[6] , \tx_byte[5] , \tx_byte[4] , \tx_byte[3] , 
        \tx_byte[2] , \tx_byte[1] , \tx_byte[0] }), .xmit_state({
        \xmit_state[6] , \xmit_state[5] , nc0, \xmit_state[3] , 
        \xmit_state[2] , \xmit_state[1] , \xmit_state[0] }), 
        .tx_hold_reg({\tx_hold_reg[7]_net_1 , \tx_hold_reg[6]_net_1 , 
        \tx_hold_reg[5]_net_1 , \tx_hold_reg[4]_net_1 , 
        \tx_hold_reg[3]_net_1 , \tx_hold_reg[2]_net_1 , 
        \tx_hold_reg[1]_net_1 , \tx_hold_reg[0]_net_1 }), 
        .xmit_state_ns_i_0(\xmit_state_ns_i[6] ), .xmit_state_ns_0(
        \xmit_state_ns[6] ), .COREABC_0_PRESETN(COREABC_0_PRESETN), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .fifo_read_tx(fifo_read_tx), .baud_clock(baud_clock), 
        .xmit_clock(xmit_clock), .N_45_0(N_45_0), .N_47_i(N_47_i), 
        .N_46_i(N_46_i), .fifo_write_tx(fifo_write_tx_net_1), 
        .N_94_mux(N_94_mux), .fifo_full_tx_i(fifo_full_tx_i), .N_54(
        N_54), .xmit_pulse(xmit_pulse), .N_130_i(N_130_i), .N_95_mux_i(
        N_95_mux_i), .N_101_mux_i(N_101_mux_i), .N_102_i(N_102_i), 
        .fifo_read_tx_i(fifo_read_tx_i));
    CFG2 #( .INIT(4'h7) )  rx_dout_reg4_0 (.A(\rx_state[0]_net_1 ), .B(
        \rx_state[1]_net_1 ), .Y(rx_dout_reg4));
    SLE clear_framing_error_reg0 (.D(clear_parity_en), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(clear_parity_reg0));
    SLE \tx_hold_reg[2]  (.D(COREABC_0_APB3master_PWDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  rx_dout_reg4_0_i (.A(\rx_state[0]_net_1 ), 
        .B(\rx_state[1]_net_1 ), .Y(rx_dout_reg4_i));
    SLE rx_dout_reg_empty (.D(rx_dout_reg4), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        rx_dout_reg_empty_1_sqmuxa_i_net_1), .ALn(COREABC_0_PRESETN), 
        .ADn(GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(rx_dout_reg_empty_net_1));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h10) )  fifo_read_rx_0_sqmuxa_0_a2 (.A(
        \rx_state[1]_net_1 ), .B(\rx_state[0]_net_1 ), .C(
        next_rx_state4_net_1), .Y(fifo_read_rx_0_sqmuxa));
    UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s make_TX 
        (.xmit_state({\xmit_state[6] , \xmit_state[5] , nc1, 
        \xmit_state[3] , \xmit_state[2] , \xmit_state[1] , 
        \xmit_state[0] }), .tx_dout_reg({\tx_dout_reg[7] , 
        \tx_dout_reg[6] , \tx_dout_reg[5] , \tx_dout_reg[4] , 
        \tx_dout_reg[3] , \tx_dout_reg[2] , \tx_dout_reg[1] , 
        \tx_dout_reg[0] }), .tx_byte({\tx_byte[7] , \tx_byte[6] , 
        \tx_byte[5] , \tx_byte[4] , \tx_byte[3] , \tx_byte[2] , 
        \tx_byte[1] , \tx_byte[0] }), .xmit_bit_sel({\xmit_bit_sel[3] , 
        \xmit_bit_sel[2] , \xmit_bit_sel[1] , \xmit_bit_sel[0] }), 
        .xmit_state_ns_0(\xmit_state_ns[6] ), .xmit_state_ns_i_0(
        \xmit_state_ns_i[6] ), .N_47_i(N_47_i), .N_46_i(N_46_i), 
        .xmit_pulse(xmit_pulse), .N_54(N_54), .N_102_i(N_102_i), 
        .N_95_mux_i(N_95_mux_i), .N_101_mux_i(N_101_mux_i), 
        .fifo_full_tx_i(fifo_full_tx_i), .CoreUARTapb_0_TXRDY(
        CoreUARTapb_0_TXRDY), .N_130_i(N_130_i), .N_94_mux(N_94_mux), 
        .TX_c(TX_c), .N_45_0(N_45_0), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN), .fifo_read_tx_i(fifo_read_tx_i), 
        .fifo_read_tx(fifo_read_tx));
    SLE \tx_hold_reg[6]  (.D(COREABC_0_APB3master_PWDATA[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[6]_net_1 ));
    CFG4 #( .INIT(16'h0800) )  rx_dout_reg_empty_0_sqmuxa_0_a2 (.A(
        COREABC_0_APB3master_PENABLE), .B(CoreAPB3_0_APBmslave1_PSELx), 
        .C(COREABC_0_APB3master_PWRITE), .D(un1_framing_error11_i_a2_0)
        , .Y(N_238));
    CFG2 #( .INIT(4'hE) )  un2_clear_framing_error_0 (.A(N_238), .B(
        overflow_reg5), .Y(un2_clear_framing_error_0_net_1));
    SLE \rx_dout_reg[4]  (.D(\rx_dout[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[4]));
    CFG4 #( .INIT(16'h0010) )  \reg_write.tx_hold_reg5_0_a2  (.A(
        N_7109_reto), .B(N_7111_reto), .C(N_316), .D(N_7110_reto), .Y(
        tx_hold_reg5));
    UART_top_CoreUARTapb_0_Clock_gen_0s_0s make_CLOCK_GEN (.xmit_pulse(
        xmit_pulse), .baud_clock(baud_clock), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .COREABC_0_PRESETN(COREABC_0_PRESETN), .xmit_clock(xmit_clock));
    CFG4 #( .INIT(16'hA8AA) )  next_rx_state4 (.A(
        rx_dout_reg_empty_net_1), .B(\counter[3] ), .C(\counter[2] ), 
        .D(fifo_empty_rx_1), .Y(next_rx_state4_net_1));
    SLE \rx_state[1]  (.D(N_211_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \rx_state[1]_net_1 ));
    SLE \rx_dout_reg[7]  (.D(\rx_dout[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[7]));
    GND GND (.Y(GND_net_1));
    SLE \rx_dout_reg[1]  (.D(\rx_dout[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[1]));
    SLE clear_parity_reg (.D(clear_parity_reg0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(clear_parity_reg_net_1));
    CFG4 #( .INIT(16'hFFEF) )  \reg_write.tx_hold_reg5_0_a2_i  (.A(
        N_7109_reto), .B(N_7111_reto), .C(N_316), .D(N_7110_reto), .Y(
        tx_hold_reg5_i));
    SLE \rx_dout_reg[5]  (.D(\rx_dout[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[5]));
    SLE overflow_reg (.D(overflow_reg5), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un2_clear_framing_error_0_net_1), .ALn(COREABC_0_PRESETN), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(OVERFLOW));
    CFG1 #( .INIT(2'h1) )  \genblk1.RXRDY_RNO  (.A(
        rx_dout_reg_empty_net_1), .Y(rx_dout_reg_empty_i));
    CFG3 #( .INIT(8'h80) )  \reg_write.tx_hold_reg5_0_a2_1  (.A(
        COREABC_0_APB3master_PWRITE), .B(COREABC_0_APB3master_PENABLE), 
        .C(CoreAPB3_0_APBmslave1_PSELx), .Y(N_316));
    CFG2 #( .INIT(4'h1) )  fifo_write_rx_1_i_a2 (.A(fifo_full_rx), .B(
        fifo_write), .Y(N_224));
    CFG2 #( .INIT(4'h2) )  un2_clear_framing_error_0_a2 (.A(
        fifo_full_rx), .B(fifo_write), .Y(overflow_reg5));
    SLE \rx_dout_reg[6]  (.D(\rx_dout[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[6]));
    SLE \rx_state[0]  (.D(\rx_state_ns[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rx_state[0]_net_1 ));
    SLE \tx_hold_reg[7]  (.D(COREABC_0_APB3master_PWDATA[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[7]_net_1 ));
    SLE \genblk1.RXRDY  (.D(rx_dout_reg_empty_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CoreUARTapb_0_RXRDY));
    UART_top_CoreUARTapb_0_fifo_256x8_0s_64s_0 \genblk3.rx_fifo  (
        .counter({\counter[3] , \counter[2] }), .rx_dout({\rx_dout[7] , 
        \rx_dout[6] , \rx_dout[5] , \rx_dout[4] , \rx_dout[3] , 
        \rx_dout[2] , \rx_dout[1] , \rx_dout[0] }), .rx_state({
        \rx_state[1]_net_1 , \rx_state[0]_net_1 }), .rx_byte({
        \rx_byte[7] , \rx_byte[6] , \rx_byte[5] , \rx_byte[4] , 
        \rx_byte[3] , \rx_byte[2] , \rx_byte[1] , \rx_byte[0] }), 
        .COREABC_0_PRESETN(COREABC_0_PRESETN), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .fifo_empty_rx_1(fifo_empty_rx_1), .fifo_full_rx(fifo_full_rx), 
        .fifo_read_rx_0_sqmuxa(fifo_read_rx_0_sqmuxa), .next_rx_state4(
        next_rx_state4_net_1), .N_224(N_224), .fifo_write(fifo_write));
    SLE \tx_hold_reg[3]  (.D(COREABC_0_APB3master_PWDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[3]_net_1 ));
    SLE fifo_write_tx (.D(tx_hold_reg5_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        COREABC_0_PRESETN), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(fifo_write_tx_net_1));
    SLE \tx_hold_reg[1]  (.D(COREABC_0_APB3master_PWDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[1]_net_1 ));
    CFG2 #( .INIT(4'hB) )  rx_dout_reg_empty_1_sqmuxa_i (.A(N_238), .B(
        rx_dout_reg4), .Y(rx_dout_reg_empty_1_sqmuxa_i_net_1));
    SLE \rx_dout_reg[2]  (.D(\rx_dout[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(rx_dout_reg4_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(rx_dout_reg[2]));
    SLE \tx_hold_reg[4]  (.D(COREABC_0_APB3master_PWDATA[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(tx_hold_reg5), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\tx_hold_reg[4]_net_1 ));
    
endmodule


module UART_top_CoreUARTapb_0_CoreUARTapb_Z12(
       iPRDATA,
       COREABC_0_APB3master_PWDATA,
       TX_c,
       RX_c,
       COREABC_0_APB3master_PENABLE,
       COREABC_0_APB3master_PWRITE,
       CoreAPB3_0_APBmslave1_PSELx,
       CoreUARTapb_0_TXRDY,
       CoreUARTapb_0_RXRDY,
       N_7109_reto,
       N_7111_reto,
       N_7110_reto,
       my_hpms_top_0_FIC32_0_CLK,
       COREABC_0_PRESETN
    );
output [7:0] iPRDATA;
input  [7:0] COREABC_0_APB3master_PWDATA;
output TX_c;
input  RX_c;
input  COREABC_0_APB3master_PENABLE;
input  COREABC_0_APB3master_PWRITE;
input  CoreAPB3_0_APBmslave1_PSELx;
output CoreUARTapb_0_TXRDY;
output CoreUARTapb_0_RXRDY;
input  N_7109_reto;
input  N_7111_reto;
input  N_7110_reto;
input  my_hpms_top_0_FIC32_0_CLK;
input  COREABC_0_PRESETN;

    wire \controlReg1[1]_net_1 , VCC_net_1, controlReg14, GND_net_1, 
        \controlReg1[2]_net_1 , \controlReg1[3]_net_1 , 
        \controlReg1[4]_net_1 , \controlReg1[5]_net_1 , 
        \controlReg1[6]_net_1 , \controlReg1[7]_net_1 , \NxtPrdata[2] , 
        un1_NxtPrdata23_i, \NxtPrdata[3] , \NxtPrdata[4] , 
        \NxtPrdata[5] , \NxtPrdata[6] , \NxtPrdata[7] , 
        \controlReg2[0]_net_1 , controlReg24, \controlReg2[1]_net_1 , 
        \controlReg2[2]_net_1 , \controlReg2[3]_net_1 , 
        \controlReg2[4]_net_1 , \controlReg2[5]_net_1 , 
        \controlReg2[6]_net_1 , \controlReg2[7]_net_1 , 
        \controlReg1[0]_net_1 , \NxtPrdata[0] , \NxtPrdata[1] , N_236, 
        N_166, N_165, N_163, N_162, N_253, N_249, N_245, N_241, 
        FRAMING_ERR, N_254, OVERFLOW, N_250, N_246, N_242, N_316, 
        \rx_dout_reg[5] , un1_framing_error11_i_a2_0, \rx_dout_reg[6] , 
        \rx_dout_reg[7] , \rx_dout_reg[2] , \rx_dout_reg[3] , 
        \rx_dout_reg[1] , \rx_dout_reg[0] , \rx_dout_reg[4] ;
    
    SLE \controlReg1[5]  (.D(COREABC_0_APB3master_PWDATA[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[5]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \NxtPrdata_4_i_m2[5]  (.A(
        \controlReg2[5]_net_1 ), .B(\controlReg1[5]_net_1 ), .C(
        N_7109_reto), .Y(N_165));
    CFG4 #( .INIT(16'hFEFC) )  \NxtPrdata_5_0[0]  (.A(\rx_dout_reg[0] )
        , .B(N_242), .C(N_241), .D(un1_framing_error11_i_a2_0), .Y(
        \NxtPrdata[0] ));
    SLE \controlReg1[7]  (.D(COREABC_0_APB3master_PWDATA[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[7]_net_1 ));
    SLE \iPRDATA[1]  (.D(\NxtPrdata[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[1]));
    CFG4 #( .INIT(16'hC0A0) )  \NxtPrdata_5_0_a2[1]  (.A(
        \controlReg1[1]_net_1 ), .B(\controlReg2[1]_net_1 ), .C(
        N_7110_reto), .D(N_7109_reto), .Y(N_245));
    SLE \controlReg2[4]  (.D(COREABC_0_APB3master_PWDATA[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[4]_net_1 ));
    SLE \iPRDATA[4]  (.D(\NxtPrdata[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[4]));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hAC) )  \NxtPrdata_4_i_m2[7]  (.A(
        \controlReg2[7]_net_1 ), .B(\controlReg1[7]_net_1 ), .C(
        N_7109_reto), .Y(N_162));
    CFG3 #( .INIT(8'hAC) )  \NxtPrdata_4_i_m2[6]  (.A(
        \controlReg2[6]_net_1 ), .B(\controlReg1[6]_net_1 ), .C(
        N_7109_reto), .Y(N_163));
    CFG2 #( .INIT(4'h8) )  un1_NxtPrdata23_0_a2_0 (.A(N_7110_reto), .B(
        N_7111_reto), .Y(N_236));
    SLE \iPRDATA[3]  (.D(\NxtPrdata[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[3]));
    SLE \controlReg2[6]  (.D(COREABC_0_APB3master_PWDATA[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[6]_net_1 ));
    SLE \controlReg1[3]  (.D(COREABC_0_APB3master_PWDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[3]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \NxtPrdata_5_0_a2[4]  (.A(
        \controlReg1[4]_net_1 ), .B(\controlReg2[4]_net_1 ), .C(
        N_7110_reto), .D(N_7109_reto), .Y(N_253));
    CFG3 #( .INIT(8'hAC) )  \NxtPrdata_4_i_m2[2]  (.A(
        \controlReg2[2]_net_1 ), .B(\controlReg1[2]_net_1 ), .C(
        N_7109_reto), .Y(N_166));
    CFG4 #( .INIT(16'hC0A0) )  \NxtPrdata_5_0_a2[3]  (.A(
        \controlReg1[3]_net_1 ), .B(\controlReg2[3]_net_1 ), .C(
        N_7110_reto), .D(N_7109_reto), .Y(N_249));
    CFG4 #( .INIT(16'h0008) )  \NxtPrdata_5_0_a2_0[0]  (.A(N_7111_reto)
        , .B(CoreUARTapb_0_TXRDY), .C(N_7110_reto), .D(N_7109_reto), 
        .Y(N_242));
    CFG4 #( .INIT(16'hEAC0) )  \NxtPrdata_5_0[5]  (.A(N_7110_reto), .B(
        \rx_dout_reg[5] ), .C(un1_framing_error11_i_a2_0), .D(N_165), 
        .Y(\NxtPrdata[5] ));
    CFG4 #( .INIT(16'hFEFC) )  \NxtPrdata_5_0[4]  (.A(\rx_dout_reg[4] )
        , .B(N_254), .C(N_253), .D(un1_framing_error11_i_a2_0), .Y(
        \NxtPrdata[4] ));
    SLE \controlReg1[6]  (.D(COREABC_0_APB3master_PWDATA[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[6]_net_1 ));
    SLE \controlReg2[3]  (.D(COREABC_0_APB3master_PWDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[3]_net_1 ));
    SLE \controlReg1[2]  (.D(COREABC_0_APB3master_PWDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[2]_net_1 ));
    SLE \controlReg1[4]  (.D(COREABC_0_APB3master_PWDATA[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[4]_net_1 ));
    SLE \iPRDATA[5]  (.D(\NxtPrdata[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[5]));
    CFG4 #( .INIT(16'hC0A0) )  \NxtPrdata_5_0_a2[0]  (.A(
        \controlReg1[0]_net_1 ), .B(\controlReg2[0]_net_1 ), .C(
        N_7110_reto), .D(N_7109_reto), .Y(N_241));
    SLE \iPRDATA[7]  (.D(\NxtPrdata[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[7]));
    CFG4 #( .INIT(16'h0002) )  un1_NxtPrdata23_0_a2_0_RNI0BDK1 (.A(
        CoreAPB3_0_APBmslave1_PSELx), .B(COREABC_0_APB3master_PWRITE), 
        .C(COREABC_0_APB3master_PENABLE), .D(N_236), .Y(
        un1_NxtPrdata23_i));
    CFG4 #( .INIT(16'hFEFC) )  \NxtPrdata_5_0[3]  (.A(\rx_dout_reg[3] )
        , .B(N_250), .C(N_249), .D(un1_framing_error11_i_a2_0), .Y(
        \NxtPrdata[3] ));
    SLE \controlReg2[1]  (.D(COREABC_0_APB3master_PWDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[1]_net_1 ));
    CFG4 #( .INIT(16'h2000) )  \p_CtrlReg2Seq.controlReg24_0_a2  (.A(
        N_7109_reto), .B(N_7111_reto), .C(N_316), .D(N_7110_reto), .Y(
        controlReg24));
    GND GND (.Y(GND_net_1));
    SLE \controlReg2[7]  (.D(COREABC_0_APB3master_PWDATA[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[7]_net_1 ));
    SLE \iPRDATA[2]  (.D(\NxtPrdata[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[2]));
    CFG4 #( .INIT(16'h1000) )  \NxtPrdata_5_0_a2_0[3]  (.A(N_7109_reto)
        , .B(N_7110_reto), .C(OVERFLOW), .D(N_7111_reto), .Y(N_250));
    SLE \controlReg2[5]  (.D(COREABC_0_APB3master_PWDATA[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[5]_net_1 ));
    SLE \controlReg2[2]  (.D(COREABC_0_APB3master_PWDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[2]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  \NxtPrdata_5_0_a2_0[1]  (.A(N_7111_reto)
        , .B(CoreUARTapb_0_RXRDY), .C(N_7110_reto), .D(N_7109_reto), 
        .Y(N_246));
    SLE \iPRDATA[6]  (.D(\NxtPrdata[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[6]));
    SLE \iPRDATA[0]  (.D(\NxtPrdata[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_NxtPrdata23_i), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(iPRDATA[0]));
    UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s uUART (
        .COREABC_0_APB3master_PWDATA({COREABC_0_APB3master_PWDATA[7], 
        COREABC_0_APB3master_PWDATA[6], COREABC_0_APB3master_PWDATA[5], 
        COREABC_0_APB3master_PWDATA[4], COREABC_0_APB3master_PWDATA[3], 
        COREABC_0_APB3master_PWDATA[2], COREABC_0_APB3master_PWDATA[1], 
        COREABC_0_APB3master_PWDATA[0]}), .rx_dout_reg({
        \rx_dout_reg[7] , \rx_dout_reg[6] , \rx_dout_reg[5] , 
        \rx_dout_reg[4] , \rx_dout_reg[3] , \rx_dout_reg[2] , 
        \rx_dout_reg[1] , \rx_dout_reg[0] }), .FRAMING_ERR(FRAMING_ERR)
        , .RX_c(RX_c), .TX_c(TX_c), .CoreUARTapb_0_TXRDY(
        CoreUARTapb_0_TXRDY), .un1_framing_error11_i_a2_0(
        un1_framing_error11_i_a2_0), .CoreAPB3_0_APBmslave1_PSELx(
        CoreAPB3_0_APBmslave1_PSELx), .COREABC_0_APB3master_PENABLE(
        COREABC_0_APB3master_PENABLE), .COREABC_0_APB3master_PWRITE(
        COREABC_0_APB3master_PWRITE), .N_7110_reto(N_7110_reto), 
        .N_316(N_316), .N_7111_reto(N_7111_reto), .N_7109_reto(
        N_7109_reto), .CoreUARTapb_0_RXRDY(CoreUARTapb_0_RXRDY), 
        .OVERFLOW(OVERFLOW), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN));
    CFG4 #( .INIT(16'h1000) )  \NxtPrdata_5_0_a2_0[4]  (.A(N_7109_reto)
        , .B(N_7110_reto), .C(FRAMING_ERR), .D(N_7111_reto), .Y(N_254));
    CFG4 #( .INIT(16'hEAC0) )  \NxtPrdata_5_0[2]  (.A(N_7110_reto), .B(
        \rx_dout_reg[2] ), .C(un1_framing_error11_i_a2_0), .D(N_166), 
        .Y(\NxtPrdata[2] ));
    CFG4 #( .INIT(16'hEAC0) )  \NxtPrdata_5_0[7]  (.A(N_7110_reto), .B(
        \rx_dout_reg[7] ), .C(un1_framing_error11_i_a2_0), .D(N_162), 
        .Y(\NxtPrdata[7] ));
    CFG4 #( .INIT(16'hEAC0) )  \NxtPrdata_5_0[6]  (.A(N_7110_reto), .B(
        \rx_dout_reg[6] ), .C(un1_framing_error11_i_a2_0), .D(N_163), 
        .Y(\NxtPrdata[6] ));
    SLE \controlReg2[0]  (.D(COREABC_0_APB3master_PWDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg24), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg2[0]_net_1 ));
    SLE \controlReg1[1]  (.D(COREABC_0_APB3master_PWDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[1]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  \p_CtrlReg1Seq.controlReg14_0_a2  (.A(
        N_7109_reto), .B(N_7111_reto), .C(N_316), .D(N_7110_reto), .Y(
        controlReg14));
    CFG4 #( .INIT(16'hFEFC) )  \NxtPrdata_5_0[1]  (.A(\rx_dout_reg[1] )
        , .B(N_246), .C(N_245), .D(un1_framing_error11_i_a2_0), .Y(
        \NxtPrdata[1] ));
    SLE \controlReg1[0]  (.D(COREABC_0_APB3master_PWDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(controlReg14), .ALn(
        COREABC_0_PRESETN), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\controlReg1[0]_net_1 ));
    
endmodule


module UART_top(
       syssvc_blk_0_NRBG_HANDLE,
       syssvc_blk_0_NRBG_DATA,
       SMADDR_i_4,
       SMADDR_i_1,
       SMADDR_i_0,
       RX_c,
       TX_c,
       my_hpms_top_0_HPMS_READY,
       RSTSYNC1,
       syssvc_blk_0_NRBG_SVC_DONE,
       m10,
       G_622,
       my_hpms_top_0_FIC32_0_CLK,
       UART_top_0_GENERATE_SERVICE,
       UART_top_0_START_sysservice,
       UART_top_0_SELF_TEST_SERVICE,
       UART_top_0_INSTANTIATE_SERVICE
    );
input  [7:0] syssvc_blk_0_NRBG_HANDLE;
input  [31:0] syssvc_blk_0_NRBG_DATA;
output SMADDR_i_4;
output SMADDR_i_1;
output SMADDR_i_0;
input  RX_c;
output TX_c;
input  my_hpms_top_0_HPMS_READY;
input  RSTSYNC1;
input  syssvc_blk_0_NRBG_SVC_DONE;
output m10;
input  G_622;
input  my_hpms_top_0_FIC32_0_CLK;
output UART_top_0_GENERATE_SERVICE;
output UART_top_0_START_sysservice;
output UART_top_0_SELF_TEST_SERVICE;
output UART_top_0_INSTANTIATE_SERVICE;

    wire \COREABC_0_APB3master_PADDR_i[11] , 
        \COREABC_0_APB3master_PWDATA[0] , 
        \COREABC_0_APB3master_PWDATA[1] , 
        \COREABC_0_APB3master_PWDATA[2] , 
        \COREABC_0_APB3master_PWDATA[3] , 
        \APB_register_blk_0_PRDATA[0] , \APB_register_blk_0_PRDATA[1] , 
        \APB_register_blk_0_PRDATA[2] , \APB_register_blk_0_PRDATA[3] , 
        \APB_register_blk_0_PRDATA[4] , \APB_register_blk_0_PRDATA[6] , 
        \APB_register_blk_0_PRDATA[8] , \APB_register_blk_0_PRDATA[9] , 
        \APB_register_blk_0_PRDATA[10] , 
        \APB_register_blk_0_PRDATA[11] , 
        \APB_register_blk_0_PRDATA[12] , 
        \APB_register_blk_0_PRDATA[14] , N_7112_reto, N_7107_reto, 
        CoreAPB3_0_APBmslave0_PSELx, COREABC_0_APB3master_PENABLE, 
        COREABC_0_APB3master_PWRITE, N_7108_reto, N_7115_reto, 
        N_7109_reto, N_7110_reto, N_7119_reto, N_7111_reto, 
        APB_register_blk_0_PREADY, COREABC_0_PRESETN, \iPRDATA[6] , 
        \iPRDATA[5] , \iPRDATA[4] , \iPRDATA[1] , \iPRDATA[7] , 
        \COREABC_0_APB3master_PWDATA[4] , 
        \COREABC_0_APB3master_PWDATA[5] , 
        \COREABC_0_APB3master_PWDATA[6] , 
        \COREABC_0_APB3master_PWDATA[7] , \PRDATA_0_iv_0_0_0[3] , 
        \PRDATA_0_iv_0_0_0[2] , \PRDATA_0_iv_0_0_0[0] , N_180, 
        iPRDATA_0_sqmuxa, CoreAPB3_0_APBmslave1_PSELx, 
        CoreUARTapb_0_TXRDY, CoreUARTapb_0_RXRDY, \iPRDATA[2] , 
        \iPRDATA[0] , \iPRDATA[3] , GND_net_1, VCC_net_1;
    
    CoreAPB3_Z11 CoreAPB3_0 (.iPRDATA_2(\iPRDATA[2] ), .iPRDATA_0(
        \iPRDATA[0] ), .iPRDATA_3(\iPRDATA[3] ), 
        .APB_register_blk_0_PRDATA_12(\APB_register_blk_0_PRDATA[12] ), 
        .APB_register_blk_0_PRDATA_2(\APB_register_blk_0_PRDATA[2] ), 
        .APB_register_blk_0_PRDATA_0(\APB_register_blk_0_PRDATA[0] ), 
        .APB_register_blk_0_PRDATA_3(\APB_register_blk_0_PRDATA[3] ), 
        .PRDATA_0_iv_0_0_0_2(\PRDATA_0_iv_0_0_0[2] ), 
        .PRDATA_0_iv_0_0_0_0(\PRDATA_0_iv_0_0_0[0] ), 
        .PRDATA_0_iv_0_0_0_3(\PRDATA_0_iv_0_0_0[3] ), 
        .CoreAPB3_0_APBmslave1_PSELx(CoreAPB3_0_APBmslave1_PSELx), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .iPRDATA_0_sqmuxa(iPRDATA_0_sqmuxa), .N_180(N_180));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    UART_top_COREABC_0_COREABC_Z9 COREABC_0 (
        .COREABC_0_APB3master_PWDATA({\COREABC_0_APB3master_PWDATA[7] , 
        \COREABC_0_APB3master_PWDATA[6] , 
        \COREABC_0_APB3master_PWDATA[5] , 
        \COREABC_0_APB3master_PWDATA[4] , 
        \COREABC_0_APB3master_PWDATA[3] , 
        \COREABC_0_APB3master_PWDATA[2] , 
        \COREABC_0_APB3master_PWDATA[1] , 
        \COREABC_0_APB3master_PWDATA[0] }), 
        .COREABC_0_APB3master_PADDR_i_0(
        \COREABC_0_APB3master_PADDR_i[11] ), .iPRDATA_5(\iPRDATA[6] ), 
        .iPRDATA_4(\iPRDATA[5] ), .iPRDATA_3(\iPRDATA[4] ), .iPRDATA_0(
        \iPRDATA[1] ), .iPRDATA_6(\iPRDATA[7] ), 
        .APB_register_blk_0_PRDATA_5(\APB_register_blk_0_PRDATA[6] ), 
        .APB_register_blk_0_PRDATA_3(\APB_register_blk_0_PRDATA[4] ), 
        .APB_register_blk_0_PRDATA_0(\APB_register_blk_0_PRDATA[1] ), 
        .APB_register_blk_0_PRDATA_13(\APB_register_blk_0_PRDATA[14] ), 
        .APB_register_blk_0_PRDATA_10(\APB_register_blk_0_PRDATA[11] ), 
        .APB_register_blk_0_PRDATA_9(\APB_register_blk_0_PRDATA[10] ), 
        .APB_register_blk_0_PRDATA_8(\APB_register_blk_0_PRDATA[9] ), 
        .APB_register_blk_0_PRDATA_7(\APB_register_blk_0_PRDATA[8] ), 
        .PRDATA_0_iv_0_0_0_3(\PRDATA_0_iv_0_0_0[3] ), 
        .PRDATA_0_iv_0_0_0_2(\PRDATA_0_iv_0_0_0[2] ), 
        .PRDATA_0_iv_0_0_0_0(\PRDATA_0_iv_0_0_0[0] ), .SMADDR_i_4(
        SMADDR_i_4), .SMADDR_i_1(SMADDR_i_1), .SMADDR_i_0(SMADDR_i_0), 
        .N_7119_reto(N_7119_reto), .G_622(G_622), .m10(m10), .N_180(
        N_180), .APB_register_blk_0_PREADY(APB_register_blk_0_PREADY), 
        .iPRDATA_0_sqmuxa(iPRDATA_0_sqmuxa), 
        .COREABC_0_APB3master_PWRITE(COREABC_0_APB3master_PWRITE), 
        .N_7112_reto(N_7112_reto), .CoreAPB3_0_APBmslave1_PSELx(
        CoreAPB3_0_APBmslave1_PSELx), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .CoreUARTapb_0_TXRDY(
        CoreUARTapb_0_TXRDY), .CoreUARTapb_0_RXRDY(CoreUARTapb_0_RXRDY)
        , .syssvc_blk_0_NRBG_SVC_DONE(syssvc_blk_0_NRBG_SVC_DONE), 
        .N_7107_reto(N_7107_reto), .N_7108_reto(N_7108_reto), 
        .N_7109_reto(N_7109_reto), .N_7110_reto(N_7110_reto), 
        .N_7111_reto(N_7111_reto), .N_7115_reto(N_7115_reto), 
        .RSTSYNC1(RSTSYNC1), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .COREABC_0_APB3master_PENABLE(
        COREABC_0_APB3master_PENABLE), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN));
    APB_register_blk APB_register_blk_0 (.syssvc_blk_0_NRBG_DATA({
        syssvc_blk_0_NRBG_DATA[31], syssvc_blk_0_NRBG_DATA[30], 
        syssvc_blk_0_NRBG_DATA[29], syssvc_blk_0_NRBG_DATA[28], 
        syssvc_blk_0_NRBG_DATA[27], syssvc_blk_0_NRBG_DATA[26], 
        syssvc_blk_0_NRBG_DATA[25], syssvc_blk_0_NRBG_DATA[24], 
        syssvc_blk_0_NRBG_DATA[23], syssvc_blk_0_NRBG_DATA[22], 
        syssvc_blk_0_NRBG_DATA[21], syssvc_blk_0_NRBG_DATA[20], 
        syssvc_blk_0_NRBG_DATA[19], syssvc_blk_0_NRBG_DATA[18], 
        syssvc_blk_0_NRBG_DATA[17], syssvc_blk_0_NRBG_DATA[16], 
        syssvc_blk_0_NRBG_DATA[15], syssvc_blk_0_NRBG_DATA[14], 
        syssvc_blk_0_NRBG_DATA[13], syssvc_blk_0_NRBG_DATA[12], 
        syssvc_blk_0_NRBG_DATA[11], syssvc_blk_0_NRBG_DATA[10], 
        syssvc_blk_0_NRBG_DATA[9], syssvc_blk_0_NRBG_DATA[8], 
        syssvc_blk_0_NRBG_DATA[7], syssvc_blk_0_NRBG_DATA[6], 
        syssvc_blk_0_NRBG_DATA[5], syssvc_blk_0_NRBG_DATA[4], 
        syssvc_blk_0_NRBG_DATA[3], syssvc_blk_0_NRBG_DATA[2], 
        syssvc_blk_0_NRBG_DATA[1], syssvc_blk_0_NRBG_DATA[0]}), 
        .syssvc_blk_0_NRBG_HANDLE({syssvc_blk_0_NRBG_HANDLE[7], 
        syssvc_blk_0_NRBG_HANDLE[6], syssvc_blk_0_NRBG_HANDLE[5], 
        syssvc_blk_0_NRBG_HANDLE[4], syssvc_blk_0_NRBG_HANDLE[3], 
        syssvc_blk_0_NRBG_HANDLE[2], syssvc_blk_0_NRBG_HANDLE[1], 
        syssvc_blk_0_NRBG_HANDLE[0]}), .COREABC_0_APB3master_PWDATA({
        \COREABC_0_APB3master_PWDATA[3] , 
        \COREABC_0_APB3master_PWDATA[2] , 
        \COREABC_0_APB3master_PWDATA[1] , 
        \COREABC_0_APB3master_PWDATA[0] }), .APB_register_blk_0_PRDATA({
        \APB_register_blk_0_PRDATA[14] , nc0, 
        \APB_register_blk_0_PRDATA[12] , 
        \APB_register_blk_0_PRDATA[11] , 
        \APB_register_blk_0_PRDATA[10] , 
        \APB_register_blk_0_PRDATA[9] , \APB_register_blk_0_PRDATA[8] , 
        nc1, \APB_register_blk_0_PRDATA[6] , nc2, 
        \APB_register_blk_0_PRDATA[4] , \APB_register_blk_0_PRDATA[3] , 
        \APB_register_blk_0_PRDATA[2] , \APB_register_blk_0_PRDATA[1] , 
        \APB_register_blk_0_PRDATA[0] }), 
        .COREABC_0_APB3master_PADDR_i_0(
        \COREABC_0_APB3master_PADDR_i[11] ), .N_7112_reto(N_7112_reto), 
        .N_7107_reto(N_7107_reto), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .COREABC_0_APB3master_PENABLE(
        COREABC_0_APB3master_PENABLE), .COREABC_0_APB3master_PWRITE(
        COREABC_0_APB3master_PWRITE), .N_7108_reto(N_7108_reto), 
        .N_7115_reto(N_7115_reto), .N_7109_reto(N_7109_reto), 
        .N_7110_reto(N_7110_reto), .N_7119_reto(N_7119_reto), 
        .N_7111_reto(N_7111_reto), .UART_top_0_INSTANTIATE_SERVICE(
        UART_top_0_INSTANTIATE_SERVICE), .UART_top_0_SELF_TEST_SERVICE(
        UART_top_0_SELF_TEST_SERVICE), .UART_top_0_START_sysservice(
        UART_top_0_START_sysservice), .APB_register_blk_0_PREADY(
        APB_register_blk_0_PREADY), .UART_top_0_GENERATE_SERVICE(
        UART_top_0_GENERATE_SERVICE), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN));
    UART_top_CoreUARTapb_0_CoreUARTapb_Z12 CoreUARTapb_0 (.iPRDATA({
        \iPRDATA[7] , \iPRDATA[6] , \iPRDATA[5] , \iPRDATA[4] , 
        \iPRDATA[3] , \iPRDATA[2] , \iPRDATA[1] , \iPRDATA[0] }), 
        .COREABC_0_APB3master_PWDATA({\COREABC_0_APB3master_PWDATA[7] , 
        \COREABC_0_APB3master_PWDATA[6] , 
        \COREABC_0_APB3master_PWDATA[5] , 
        \COREABC_0_APB3master_PWDATA[4] , 
        \COREABC_0_APB3master_PWDATA[3] , 
        \COREABC_0_APB3master_PWDATA[2] , 
        \COREABC_0_APB3master_PWDATA[1] , 
        \COREABC_0_APB3master_PWDATA[0] }), .TX_c(TX_c), .RX_c(RX_c), 
        .COREABC_0_APB3master_PENABLE(COREABC_0_APB3master_PENABLE), 
        .COREABC_0_APB3master_PWRITE(COREABC_0_APB3master_PWRITE), 
        .CoreAPB3_0_APBmslave1_PSELx(CoreAPB3_0_APBmslave1_PSELx), 
        .CoreUARTapb_0_TXRDY(CoreUARTapb_0_TXRDY), 
        .CoreUARTapb_0_RXRDY(CoreUARTapb_0_RXRDY), .N_7109_reto(
        N_7109_reto), .N_7111_reto(N_7111_reto), .N_7110_reto(
        N_7110_reto), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .COREABC_0_PRESETN(
        COREABC_0_PRESETN));
    
endmodule


module my_hpms_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module CoreResetP_Z5(
       my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N,
       my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F,
       SYSRESET_POR,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N;
input  my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F;
input  SYSRESET_POR;
input  my_hpms_top_0_FIC32_0_CLK;
output my_hpms_top_0_HPMS_READY;

    wire MSS_HPMS_READY_int_net_1, mss_ready_select_net_1, VCC_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        GND_net_1, mss_ready_state_net_1, RESET_N_M2F_clk_base_net_1, 
        POWER_ON_RESET_N_q1_net_1, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, MSS_HPMS_READY_int_4_net_1;
    
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_clk_base_net_1));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(SYSRESET_POR), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(POWER_ON_RESET_N_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(mss_ready_select4_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_select_net_1));
    CLKINT MSS_HPMS_READY_int_RNI7NKB (.A(MSS_HPMS_READY_int_net_1), 
        .Y(my_hpms_top_0_HPMS_READY));
    GND GND (.Y(GND_net_1));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(RESET_N_M2F_clk_base_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    VCC VCC (.Y(VCC_net_1));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(RESET_N_M2F_q1_net_1));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(VCC_net_1), .ALn(my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(FIC_2_APB_M_PRESET_N_clk_base_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(SYSRESET_POR), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q1_net_1));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       SDATASELInt_RNI4ATG_0,
       masterDataInProg_0,
       SDATASELInt_RNI2GKS_0,
       SDATASELInt_RNI4FPD1_0,
       DEFSLAVEDATASEL,
       mchready_i,
       CoreAHBLite_0_AHBmslave16_HREADY,
       g3_8,
       defSlaveSMNextState,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  SDATASELInt_RNI4ATG_0;
input  masterDataInProg_0;
input  SDATASELInt_RNI2GKS_0;
input  SDATASELInt_RNI4FPD1_0;
input  DEFSLAVEDATASEL;
output mchready_i;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  g3_8;
output defSlaveSMNextState;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire defSlaveSMCurrentState_net_1, VCC_net_1, GND_net_1, 
        defSlaveSMCurrentState_RNIOCGD4_net_1;
    
    CFG2 #( .INIT(4'h2) )  defSlaveSMNextState_0_a5 (.A(
        DEFSLAVEDATASEL), .B(defSlaveSMCurrentState_net_1), .Y(
        defSlaveSMNextState));
    CFG4 #( .INIT(16'h5540) )  defSlaveSMCurrentState_RNIPO855 (.A(
        defSlaveSMCurrentState_RNIOCGD4_net_1), .B(masterDataInProg_0), 
        .C(CoreAHBLite_0_AHBmslave16_HREADY), .D(SDATASELInt_RNI4ATG_0)
        , .Y(mchready_i));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h070F) )  defSlaveSMCurrentState_RNIOCGD4 (.A(
        SDATASELInt_RNI4FPD1_0), .B(SDATASELInt_RNI2GKS_0), .C(
        defSlaveSMCurrentState_net_1), .D(g3_8), .Y(
        defSlaveSMCurrentState_RNIOCGD4_net_1));
    SLE defSlaveSMCurrentState (.D(defSlaveSMNextState), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState_net_1));
    
endmodule


module COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0(
       M0GATEDHADDR,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       regHADDR,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       masterDataInProg_0,
       masterAddrInProg_0,
       mchready_i,
       PREVDATASLAVEREADY_iv,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       CoreAHBLite_0_AHBmslave16_HRESP,
       N_63,
       CoreAHBLite_0_AHBmslave16_HREADY,
       N_50_i,
       HREADY_M_pre37,
       masterRegAddrSel,
       regHTRANS,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       regHWRITE,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY,
       m0s16DataSel
    );
output [31:28] M0GATEDHADDR;
input  [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
output [27:2] regHADDR;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
input  masterDataInProg_0;
input  masterAddrInProg_0;
output mchready_i;
output PREVDATASLAVEREADY_iv;
output syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  CoreAHBLite_0_AHBmslave16_HRESP;
input  N_63;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output N_50_i;
output HREADY_M_pre37;
output masterRegAddrSel;
output regHTRANS;
input  syssvc_blk_0_AHBL_MASTER_HWRITE;
output regHWRITE;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;
output m0s16DataSel;

    wire VCC_net_1, SDATASELInt_18_net_1, GND_net_1, 
        \regHADDR[30]_net_1 , N_60_i, \regHADDR[31]_net_1 , 
        \SDATASELInt[1]_net_1 , SDATASELInt_3_net_1, 
        \SDATASELInt[3]_net_1 , SDATASELInt_5_net_1, 
        \SDATASELInt[5]_net_1 , SDATASELInt_7_net_1, 
        \SDATASELInt[7]_net_1 , SDATASELInt_9_net_1, 
        \SDATASELInt[8]_net_1 , SDATASELInt_10_net_1, 
        \SDATASELInt[9]_net_1 , SDATASELInt_11_net_1, 
        \SDATASELInt[10]_net_1 , SDATASELInt_12_net_1, 
        \SDATASELInt[11]_net_1 , SDATASELInt_13_net_1, 
        \SDATASELInt[12]_net_1 , SDATASELInt_14_net_1, 
        \SDATASELInt[13]_net_1 , SDATASELInt_15_net_1, 
        \SDATASELInt[14]_net_1 , SDATASELInt_16_net_1, 
        \SDATASELInt[15]_net_1 , SDATASELInt_17_net_1, 
        \regHADDR[28]_net_1 , \regHADDR[29]_net_1 , N_62_i, 
        \SDATASELInt_RNI2GKS[12]_net_1 , 
        \SDATASELInt_RNI4FPD1[10]_net_1 , 
        \SDATASELInt_RNI4ATG[16]_net_1 , g3_8, HREADY_M_pre37_8_net_1, 
        HREADY_M_pre37_7_net_1, HREADY_M_pre37_1_net_1, 
        DEFSLAVEDATASEL_9_3_net_1, N_60_2, N_77, N_76, N_75, N_74, 
        DEFSLAVEDATASEL_9_4_net_1, DEFSLAVEDATASEL_8_net_1, N_73, 
        DEFSLAVEDATASEL_9_net_1, N_71, N_70, N_69, 
        DEFSLAVEDATASEL_net_1, defSlaveSMNextState, N_72;
    
    SLE \regHADDR[21]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[21]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[21]));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_12 (.A(N_75), .B(
        \SDATASELInt[10]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_71), 
        .Y(SDATASELInt_12_net_1));
    CFG3 #( .INIT(8'hE2) )  \PREGATEDHADDR[31]  (.A(
        syssvc_blk_0_AHBL_MASTER_HADDR[31]), .B(masterRegAddrSel), .C(
        \regHADDR[31]_net_1 ), .Y(M0GATEDHADDR[31]));
    SLE \regHADDR[15]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[15]));
    SLE \regHADDR[30]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[30]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[30]_net_1 ));
    SLE \regHADDR[7]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[7]));
    CFG2 #( .INIT(4'h7) )  \SDATASELInt_RNI4ATG[16]  (.A(
        HREADY_M_pre37), .B(m0s16DataSel), .Y(
        \SDATASELInt_RNI4ATG[16]_net_1 ));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_13 (.A(N_75), .B(
        \SDATASELInt[11]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_70), 
        .Y(SDATASELInt_13_net_1));
    CFG3 #( .INIT(8'h10) )  \PREGATEDHADDR_RNI1BJA1[28]  (.A(
        M0GATEDHADDR[31]), .B(M0GATEDHADDR[28]), .C(N_63), .Y(N_50_i));
    CFG3 #( .INIT(8'hE2) )  \PREGATEDHADDR[30]  (.A(
        syssvc_blk_0_AHBL_MASTER_HADDR[30]), .B(masterRegAddrSel), .C(
        \regHADDR[30]_net_1 ), .Y(M0GATEDHADDR[30]));
    SLE \regHADDR[9]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[9]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[9]));
    SLE masterRegAddrSel_inst_1 (.D(N_62_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterRegAddrSel));
    SLE regHTRANS_inst_1 (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHTRANS));
    VCC VCC (.Y(VCC_net_1));
    SLE \regHADDR[29]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[29]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[29]_net_1 ));
    SLE \regHADDR[24]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[24]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[24]));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_15 (.A(N_76), .B(
        \SDATASELInt[13]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_70), 
        .Y(SDATASELInt_15_net_1));
    CFG3 #( .INIT(8'h7F) )  \SADDRSEL_i_o5[9]  (.A(M0GATEDHADDR[31]), 
        .B(M0GATEDHADDR[28]), .C(N_63), .Y(N_70));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_9_4 (.A(
        \SDATASELInt[7]_net_1 ), .B(\SDATASELInt[5]_net_1 ), .C(
        \SDATASELInt[3]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        DEFSLAVEDATASEL_9_4_net_1));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_14 (.A(N_76), .B(
        \SDATASELInt[12]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_71), 
        .Y(SDATASELInt_14_net_1));
    SLE \regHADDR[28]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[28]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[28]_net_1 ));
    CFG2 #( .INIT(4'h7) )  masterAddrClockEnable_i_o5 (.A(mchready_i), 
        .B(syssvc_blk_0_AHBL_MASTER_HTRANS_0), .Y(N_72));
    CFG4 #( .INIT(16'h0100) )  HREADY_M_pre37_1 (.A(
        \SDATASELInt[13]_net_1 ), .B(\SDATASELInt[9]_net_1 ), .C(
        \SDATASELInt[5]_net_1 ), .D(m0s16DataSel), .Y(
        HREADY_M_pre37_1_net_1));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_10 (.A(N_74), .B(
        \SDATASELInt[8]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_71), 
        .Y(SDATASELInt_10_net_1));
    CFG3 #( .INIT(8'hBF) )  \SADDRSEL_i_o5[1]  (.A(M0GATEDHADDR[31]), 
        .B(M0GATEDHADDR[28]), .C(N_63), .Y(N_69));
    CFG2 #( .INIT(4'hB) )  \SADDRSEL_i_o5[12]  (.A(M0GATEDHADDR[29]), 
        .B(M0GATEDHADDR[30]), .Y(N_76));
    SLE \regHADDR[31]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[31]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[31]_net_1 ));
    SLE \regHADDR[10]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[10]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[10]));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_17 (.A(N_77), .B(
        \SDATASELInt[15]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_70), 
        .Y(SDATASELInt_17_net_1));
    CFG2 #( .INIT(4'hE) )  DEFSLAVEDATASEL_9_3 (.A(
        \SDATASELInt[14]_net_1 ), .B(\SDATASELInt[15]_net_1 ), .Y(
        DEFSLAVEDATASEL_9_3_net_1));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_11 (.A(N_74), .B(
        \SDATASELInt[9]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_70), 
        .Y(SDATASELInt_11_net_1));
    SLE \regHADDR[13]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[13]));
    SLE \regHADDR[12]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[12]));
    SLE \regHADDR[5]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[5]));
    CFG2 #( .INIT(4'hD) )  d_masterRegAddrSel_i_2 (.A(N_50_i), .B(
        M0GATEDHADDR[31]), .Y(N_60_2));
    SLE \regHADDR[2]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[2]));
    SLE \SDATASELInt[15]  (.D(SDATASELInt_17_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[15]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \PREGATEDHADDR[28]  (.A(
        syssvc_blk_0_AHBL_MASTER_HADDR[28]), .B(masterRegAddrSel), .C(
        \regHADDR[28]_net_1 ), .Y(M0GATEDHADDR[28]));
    SLE \SDATASELInt[14]  (.D(SDATASELInt_16_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[14]_net_1 ));
    SLE \regHADDR[8]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[8]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[8]));
    SLE \regHADDR[25]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[25]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[25]));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'hE) )  \SADDRSEL_i_o5_0[9]  (.A(M0GATEDHADDR[29]), 
        .B(M0GATEDHADDR[30]), .Y(N_74));
    CFG4 #( .INIT(16'h0001) )  masterAddrClockEnable_i_o5_0_RNI7I0Q (
        .A(N_73), .B(N_72), .C(masterRegAddrSel), .D(N_60_2), .Y(
        N_60_i));
    CFG4 #( .INIT(16'h0001) )  HREADY_M_pre37_7 (.A(
        \SDATASELInt[12]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[8]_net_1 ), .D(\SDATASELInt[3]_net_1 ), .Y(
        HREADY_M_pre37_7_net_1));
    SLE \regHADDR[17]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[17]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[17]));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNI08UU1[1]  (.A(
        \SDATASELInt[7]_net_1 ), .B(\SDATASELInt[5]_net_1 ), .C(
        \SDATASELInt[3]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(g3_8));
    CFG3 #( .INIT(8'hEC) )  masterAddrClockEnable_i_o5_0 (.A(
        masterAddrInProg_0), .B(M0GATEDHADDR[28]), .C(
        CoreAHBLite_0_AHBmslave16_HREADY), .Y(N_73));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_16 (.A(N_77), .B(
        \SDATASELInt[14]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_71), 
        .Y(SDATASELInt_16_net_1));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNI4FPD1[10]  (.A(
        \SDATASELInt[11]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[9]_net_1 ), .D(\SDATASELInt[8]_net_1 ), .Y(
        \SDATASELInt_RNI4FPD1[10]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \SADDRSEL_i_o5[14]  (.A(M0GATEDHADDR[29]), 
        .B(M0GATEDHADDR[30]), .Y(N_77));
    SLE \regHADDR[6]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[6]));
    SLE \regHADDR[16]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[16]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[16]));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_9 (.A(
        \SDATASELInt[12]_net_1 ), .B(\SDATASELInt[13]_net_1 ), .C(
        DEFSLAVEDATASEL_9_4_net_1), .D(DEFSLAVEDATASEL_9_3_net_1), .Y(
        DEFSLAVEDATASEL_9_net_1));
    SLE \SDATASELInt[13]  (.D(SDATASELInt_15_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[13]_net_1 ));
    SLE regHWRITE_inst_1 (.D(syssvc_blk_0_AHBL_MASTER_HWRITE), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHWRITE));
    CFG3 #( .INIT(8'hCE) )  PREVDATASLAVEREADY_iv_0_o5 (.A(
        HREADY_M_pre37), .B(defSlaveSMNextState), .C(
        CoreAHBLite_0_AHBmslave16_HREADY), .Y(PREVDATASLAVEREADY_iv));
    SLE \SDATASELInt[9]  (.D(SDATASELInt_11_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[9]_net_1 ));
    SLE \SDATASELInt[1]  (.D(SDATASELInt_3_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[1]_net_1 ));
    SLE \SDATASELInt[12]  (.D(SDATASELInt_14_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[12]_net_1 ));
    CFG2 #( .INIT(4'hD) )  \SADDRSEL_i_o5_0[10]  (.A(M0GATEDHADDR[29]), 
        .B(M0GATEDHADDR[30]), .Y(N_75));
    SLE \regHADDR[11]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[11]));
    SLE \SDATASELInt[5]  (.D(SDATASELInt_7_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[5]_net_1 ));
    SLE \regHADDR[3]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[3]));
    CFG3 #( .INIT(8'hE2) )  SDATASELInt_18 (.A(N_50_i), .B(
        PREVDATASLAVEREADY_iv), .C(m0s16DataSel), .Y(
        SDATASELInt_18_net_1));
    CFG4 #( .INIT(16'h0800) )  HREADY_M_pre37_inst_1 (.A(
        HREADY_M_pre37_8_net_1), .B(HREADY_M_pre37_7_net_1), .C(
        \SDATASELInt[11]_net_1 ), .D(HREADY_M_pre37_1_net_1), .Y(
        HREADY_M_pre37));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_9 (.A(N_77), .B(
        \SDATASELInt[7]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_69), 
        .Y(SDATASELInt_9_net_1));
    SLE \SDATASELInt[3]  (.D(SDATASELInt_5_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[3]_net_1 ));
    CFG4 #( .INIT(16'hEAAA) )  HRESP_0_iv_0 (.A(DEFSLAVEDATASEL_net_1), 
        .B(CoreAHBLite_0_AHBmslave16_HRESP), .C(masterDataInProg_0), 
        .D(HREADY_M_pre37), .Y(syssvc_blk_0_AHBL_MASTER_HRESP_0));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_5 (.A(N_75), .B(
        \SDATASELInt[3]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_69), 
        .Y(SDATASELInt_5_net_1));
    SLE \regHADDR[20]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[20]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[20]));
    SLE \regHADDR[23]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[23]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[23]));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_3 (.A(N_74), .B(
        \SDATASELInt[1]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_69), 
        .Y(SDATASELInt_3_net_1));
    SLE \regHADDR[22]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[22]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[22]));
    SLE \SDATASELInt[7]  (.D(SDATASELInt_9_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[7]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  HREADY_M_pre37_8 (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[14]_net_1 ), .C(
        \SDATASELInt[7]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        HREADY_M_pre37_8_net_1));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_8 (.A(
        \SDATASELInt[11]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[9]_net_1 ), .D(\SDATASELInt[8]_net_1 ), .Y(
        DEFSLAVEDATASEL_8_net_1));
    CFG2 #( .INIT(4'hE) )  DEFSLAVEDATASEL (.A(DEFSLAVEDATASEL_9_net_1)
        , .B(DEFSLAVEDATASEL_8_net_1), .Y(DEFSLAVEDATASEL_net_1));
    CFG3 #( .INIT(8'hE2) )  \PREGATEDHADDR[29]  (.A(
        syssvc_blk_0_AHBL_MASTER_HADDR[29]), .B(masterRegAddrSel), .C(
        \regHADDR[29]_net_1 ), .Y(M0GATEDHADDR[29]));
    CFG4 #( .INIT(16'h0051) )  masterRegAddrSel_RNO (.A(N_73), .B(N_72)
        , .C(masterRegAddrSel), .D(N_60_2), .Y(N_62_i));
    CFG4 #( .INIT(16'hC0C5) )  SDATASELInt_7 (.A(N_76), .B(
        \SDATASELInt[5]_net_1 ), .C(PREVDATASLAVEREADY_iv), .D(N_69), 
        .Y(SDATASELInt_7_net_1));
    SLE \regHADDR[19]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[19]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[19]));
    SLE \regHADDR[14]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[14]));
    SLE \regHADDR[27]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[27]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[27]));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNI2GKS[12]  (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[14]_net_1 ), .C(
        \SDATASELInt[13]_net_1 ), .D(\SDATASELInt[12]_net_1 ), .Y(
        \SDATASELInt_RNI2GKS[12]_net_1 ));
    SLE \SDATASELInt[16]  (.D(SDATASELInt_18_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(m0s16DataSel));
    SLE \regHADDR[18]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[18]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[18]));
    SLE \SDATASELInt[11]  (.D(SDATASELInt_13_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[11]_net_1 ));
    CFG3 #( .INIT(8'hDF) )  \SADDRSEL_i_o5[10]  (.A(M0GATEDHADDR[31]), 
        .B(M0GATEDHADDR[28]), .C(N_63), .Y(N_71));
    SLE \SDATASELInt[8]  (.D(SDATASELInt_10_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[8]_net_1 ));
    SLE \regHADDR[4]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[4]));
    SLE \regHADDR[26]  (.D(syssvc_blk_0_AHBL_MASTER_HADDR[26]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_60_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR[26]));
    SLE \SDATASELInt[10]  (.D(SDATASELInt_12_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[10]_net_1 ));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (
        .SDATASELInt_RNI4ATG_0(\SDATASELInt_RNI4ATG[16]_net_1 ), 
        .masterDataInProg_0(masterDataInProg_0), 
        .SDATASELInt_RNI2GKS_0(\SDATASELInt_RNI2GKS[12]_net_1 ), 
        .SDATASELInt_RNI4FPD1_0(\SDATASELInt_RNI4FPD1[10]_net_1 ), 
        .DEFSLAVEDATASEL(DEFSLAVEDATASEL_net_1), .mchready_i(
        mchready_i), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .g3_8(g3_8), 
        .defSlaveSMNextState(defSlaveSMNextState), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z3_1(
       M0GATEDHADDR,
       masterAddrInProg_0,
       N_46_i,
       regHTRANS,
       masterRegAddrSel,
       N_38_i,
       N_40_i,
       N_42_i,
       N_44_i,
       un1_masterAddrInProg_6_1_i,
       CoreAHBLite_0_AHBmslave16_HREADY,
       N_50_i,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  [31:28] M0GATEDHADDR;
output masterAddrInProg_0;
output N_46_i;
input  regHTRANS;
input  masterRegAddrSel;
output N_38_i;
output N_40_i;
output N_42_i;
output N_44_i;
output un1_masterAddrInProg_6_1_i;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  N_50_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire \arbRegSMCurrentState[0]_net_1 , VCC_net_1, N_104_i, 
        GND_net_1, \arbRegSMCurrentState[1]_net_1 , N_106_i, 
        \arbRegSMCurrentState[2]_net_1 , N_108_i, 
        \arbRegSMCurrentState[3]_net_1 , N_110_i, 
        \arbRegSMCurrentState[5]_net_1 , 
        \arbRegSMCurrentState_ns[5]_net_1 , 
        \arbRegSMCurrentState[6]_net_1 , N_114_i, HSEL7_sn, N_116_i, 
        \arbRegSMCurrentState[13]_net_1 , N_106_i_1, N_157, N_158;
    
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_a2_RNISV161[0]  
        (.A(masterAddrInProg_0), .B(M0GATEDHADDR[31]), .Y(N_44_i));
    CFG3 #( .INIT(8'hAE) )  \arbRegSMCurrentState_ns[5]  (.A(
        \arbRegSMCurrentState[6]_net_1 ), .B(
        \arbRegSMCurrentState[5]_net_1 ), .C(N_50_i), .Y(
        \arbRegSMCurrentState_ns[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[2]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_108_i));
    SLE \arbRegSMCurrentState[7]  (.D(N_116_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(HSEL7_sn));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'hD) )  \arbRegSMCurrentState_ns_i_a2_RNIP32M[0]  (
        .A(N_158), .B(\arbRegSMCurrentState[3]_net_1 ), .Y(
        masterAddrInProg_0));
    SLE \arbRegSMCurrentState[3]  (.D(N_110_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[3]_net_1 ));
    SLE \arbRegSMCurrentState[0]  (.D(N_104_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[0]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \arbRegSMCurrentState_RNO[0]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_158), .Y(N_104_i));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_a2_RNI36161[0]  
        (.A(masterAddrInProg_0), .B(M0GATEDHADDR[29]), .Y(N_40_i));
    SLE \arbRegSMCurrentState[5]  (.D(
        \arbRegSMCurrentState_ns[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[6]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(HSEL7_sn), .Y(N_114_i));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[3]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_110_i));
    CFG4 #( .INIT(16'h1D15) )  \arbRegSMCurrentState_RNO_0[1]  (.A(
        N_50_i), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        \arbRegSMCurrentState[0]_net_1 ), .D(N_157), .Y(N_106_i_1));
    SLE \arbRegSMCurrentState[6]  (.D(N_114_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[6]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_a2_RNIRU161[0]  
        (.A(masterAddrInProg_0), .B(M0GATEDHADDR[30]), .Y(N_42_i));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_a2_RNI25161[0]  
        (.A(masterAddrInProg_0), .B(M0GATEDHADDR[28]), .Y(N_38_i));
    SLE \arbRegSMCurrentState[1]  (.D(N_106_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[1]_net_1 ));
    CFG4 #( .INIT(16'hFEF2) )  \arbRegSMCurrentState_RNO[1]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_106_i_1), .C(
        \arbRegSMCurrentState[2]_net_1 ), .D(
        \arbRegSMCurrentState[1]_net_1 ), .Y(N_106_i));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'hE) )  \arbRegSMCurrentState_RNIEVFT[7]  (.A(
        masterAddrInProg_0), .B(HSEL7_sn), .Y(
        un1_masterAddrInProg_6_1_i));
    CFG3 #( .INIT(8'hC4) )  \arbRegSMCurrentState_ns_i_a2_RNI06441[0]  
        (.A(masterRegAddrSel), .B(masterAddrInProg_0), .C(regHTRANS), 
        .Y(N_46_i));
    CFG2 #( .INIT(4'h1) )  \arbRegSMCurrentState_ns_i_a2_0_0[0]  (.A(
        \arbRegSMCurrentState[5]_net_1 ), .B(
        \arbRegSMCurrentState[13]_net_1 ), .Y(N_157));
    SLE \arbRegSMCurrentState[2]  (.D(N_108_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[2]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[7]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(HSEL7_sn), .Y(N_116_i));
    CFG4 #( .INIT(16'h1033) )  \arbRegSMCurrentState_ns_i_a2[0]  (.A(
        \arbRegSMCurrentState[1]_net_1 ), .B(
        \arbRegSMCurrentState[0]_net_1 ), .C(N_157), .D(N_50_i), .Y(
        N_158));
    SLE \arbRegSMCurrentState[13]  (.D(GND_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_50_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[13]_net_1 ));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_0(
       M0GATEDHADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       regHADDR,
       cfdatain_o_iv_0_7_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_0_iv_0_0_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       memwr_desc_int_m_9,
       memwr_desc_int_m_16,
       memwr_desc_int_m_15,
       memwr_desc_int_m_14,
       memwr_desc_int_m_17,
       memwr_desc_int_m_19,
       memwr_desc_int_m_0,
       cfdatain_d1_5,
       cfdatain_d1_2,
       cfdatain_d1_0,
       cfdatain_d1_20,
       cfdatain_d1_27,
       cfdatain_d1_26,
       cfdatain_d1_25,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       masterAddrInProg_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_curr_state_RNI9FH21_0,
       req_dstreg_data_0_0,
       masterDataInProg_0,
       N_50_i,
       un1_masterAddrInProg_6_1_i,
       N_44_i,
       N_42_i,
       N_40_i,
       N_38_i,
       N_46_i,
       cfdatain_N_8_mux_i_0,
       N_36_i,
       PREVDATASLAVEREADY_iv,
       m0s16DataSel,
       cfdatain_o27,
       un1_cfdatain_o26_1_out,
       cfdatain_o28,
       N_7928,
       N_7344,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       cfrd_resp_o,
       regHWRITE,
       N_5111_i,
       cfwr_req_o,
       idle_trigger,
       fmhwrite_d1,
       cfrd_req_o,
       N_63,
       masterRegAddrSel,
       regHTRANS,
       CoreAHBLite_0_AHBmslave16_HREADY,
       g0_0,
       g2_0,
       g0_0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0_1,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_2,
       g3,
       un2_cudata_wrdy_int_9,
       g2,
       N_10_0_0,
       N_12_1,
       g2_0_0_0,
       N_7903_0,
       cfdatain_N_5,
       un2_cudata_wrdy_int_1_0,
       N_8225,
       N_7894_i,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  [31:28] M0GATEDHADDR;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:2] CoreAHBLite_0_AHBmslave16_HADDR;
input  [27:2] syssvc_blk_0_AHBL_MASTER_HADDR;
input  [27:2] regHADDR;
input  cfdatain_o_iv_0_7_0;
input  cfdatain_o_iv_0_4_0;
input  cfdatain_o_0_iv_0_1_0;
input  cfdatain_o_0_iv_0_0_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_15;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_13;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_11;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_8;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_9;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_10;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_14;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_16;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_23;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_1;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_2;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_7;
input  memwr_desc_int_m_9;
input  memwr_desc_int_m_16;
input  memwr_desc_int_m_15;
input  memwr_desc_int_m_14;
input  memwr_desc_int_m_17;
input  memwr_desc_int_m_19;
input  memwr_desc_int_m_0;
input  cfdatain_d1_5;
input  cfdatain_d1_2;
input  cfdatain_d1_0;
input  cfdatain_d1_20;
input  cfdatain_d1_27;
input  cfdatain_d1_26;
input  cfdatain_d1_25;
input  cfdatain_d1_28;
input  cfdatain_d1_30;
input  cfdatain_d1_11;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output masterAddrInProg_0;
input  cfdatain_o_0_iv_0_a2_3_0_0;
input  req_curr_state_RNI9FH21_0;
input  req_dstreg_data_0_0;
output masterDataInProg_0;
input  N_50_i;
output un1_masterAddrInProg_6_1_i;
output N_44_i;
output N_42_i;
output N_40_i;
output N_38_i;
output N_46_i;
input  cfdatain_N_8_mux_i_0;
output N_36_i;
input  PREVDATASLAVEREADY_iv;
input  m0s16DataSel;
input  cfdatain_o27;
input  un1_cfdatain_o26_1_out;
input  cfdatain_o28;
input  N_7928;
input  N_7344;
output CoreAHBLite_0_AHBmslave16_HWRITE;
input  cfrd_resp_o;
input  regHWRITE;
input  N_5111_i;
input  cfwr_req_o;
input  idle_trigger;
input  fmhwrite_d1;
input  cfrd_req_o;
output N_63;
input  masterRegAddrSel;
input  regHTRANS;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  g0_0;
input  g2_0;
input  g0_0_0;
input  cfdatain_o_iv_N_5_3_0;
input  g0_0_1;
input  cfdatain_o_iv_0_N_5_3_0;
input  g0_0_2;
input  g3;
input  un2_cudata_wrdy_int_9;
input  g2;
input  N_10_0_0;
input  N_12_1;
input  g2_0_0_0;
input  N_7903_0;
input  cfdatain_N_5;
input  un2_cudata_wrdy_int_1_0;
input  N_8225;
input  N_7894_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire VCC_net_1, masterDataInProg_55_net_1, GND_net_1, 
        \HWDATA_1[5]_net_1 , g1_0_net_1, \HWDATA_0_bm[0]_net_1 , 
        \HWDATA_0_ns_1[0]_net_1 , HWRITE_m4_0_a2_1_net_1, d_m3_i_a3_0, 
        \HWDATA_a0_1[12]_net_1 , HWRITE_N_9_mux, HWRITE_0_iv_RNO_net_1, 
        \HWDATA_a0_1_1[12]_net_1 , \HWDATA_a0_1[14]_net_1 ;
    
    CFG4 #( .INIT(16'hC0EA) )  \HWDATA_0[12]  (.A(
        \HWDATA_a0_1_1[12]_net_1 ), .B(cfdatain_o_0_iv_0_0_0), .C(
        masterDataInProg_0), .D(N_8225), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[12]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[4]  (.A(regHADDR[4]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[4]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[4]));
    CFG4 #( .INIT(16'hA0A2) )  \masterDataInProg_RNIRJH1A[0]  (.A(
        masterDataInProg_0), .B(cfdatain_o_iv_0_N_5_3_0), .C(g0_0_1), 
        .D(un2_cudata_wrdy_int_9), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[7]));
    CFG4 #( .INIT(16'hA0A2) )  \masterDataInProg_RNI546FA[0]  (.A(
        masterDataInProg_0), .B(cfdatain_o_iv_N_5_3_0), .C(g0_0_0), .D(
        un2_cudata_wrdy_int_9), .Y(CoreAHBLite_0_AHBmslave16_HWDATA[1])
        );
    CFG4 #( .INIT(16'h0001) )  \HWDATA_0_bm[0]  (.A(cfdatain_o28), .B(
        un2_cudata_wrdy_int_1_0), .C(un1_cfdatain_o26_1_out), .D(
        cfdatain_o27), .Y(\HWDATA_0_bm[0]_net_1 ));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[5]  (.A(regHADDR[5]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[5]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[5]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[22]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[22]));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[20]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_20), .C(N_7894_i), .D(memwr_desc_int_m_9), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[20]));
    CFG4 #( .INIT(16'hA0A8) )  \masterDataInProg_RNI8NG0B[0]  (.A(
        masterDataInProg_0), .B(g2_0), .C(g0_0), .D(
        un2_cudata_wrdy_int_9), .Y(CoreAHBLite_0_AHBmslave16_HWDATA[4])
        );
    CFG2 #( .INIT(4'h8) )  \HWDATA[23]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[23]));
    CFG2 #( .INIT(4'h4) )  HWRITE_0_iv_RNO_0 (.A(idle_trigger), .B(
        fmhwrite_d1), .Y(d_m3_i_a3_0));
    CFG4 #( .INIT(16'h5D55) )  \HWDATA_0_ns_1[0]  (.A(
        masterDataInProg_0), .B(req_curr_state_RNI9FH21_0), .C(
        cfdatain_o_0_iv_0_a2_3_0_0), .D(N_7894_i), .Y(
        \HWDATA_0_ns_1[0]_net_1 ));
    CFG4 #( .INIT(16'h00E2) )  \HWDATA_0_ns[0]  (.A(cfdatain_d1_0), .B(
        N_7894_i), .C(\HWDATA_0_bm[0]_net_1 ), .D(
        \HWDATA_0_ns_1[0]_net_1 ), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[0]));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h20) )  \HWDATA_a0_1_1[12]  (.A(
        \HWDATA_a0_1[12]_net_1 ), .B(N_7344), .C(N_7894_i), .Y(
        \HWDATA_a0_1_1[12]_net_1 ));
    CFG4 #( .INIT(16'hAA8A) )  \HWDATA[29]  (.A(masterDataInProg_0), 
        .B(cfdatain_o_iv_0_4_0), .C(cfdatain_N_8_mux_i_0), .D(
        cfdatain_o_iv_0_7_0), .Y(CoreAHBLite_0_AHBmslave16_HWDATA[29]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[10]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[10]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[31]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[31]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[10]  (.A(regHADDR[10]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[10]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[10]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[14]  (.A(regHADDR[14]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[14]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[14]));
    CFG4 #( .INIT(16'hCCC8) )  \masterDataInProg_RNIK0AC91[0]  (.A(
        g1_0_net_1), .B(masterDataInProg_0), .C(N_12_1), .D(N_10_0_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[2]));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[28]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_28), .C(N_7894_i), .D(memwr_desc_int_m_17), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[28]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[19]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[19]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[19]  (.A(regHADDR[19]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[19]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[19]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[15]  (.A(regHADDR[15]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[15]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[15]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[11]  (.A(regHADDR[11]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[11]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[11]));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[25]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_25), .C(N_7894_i), .D(memwr_desc_int_m_14), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[25]));
    CFG3 #( .INIT(8'h20) )  \HWDATA_a0_1[14]  (.A(
        \HWDATA_a0_1[12]_net_1 ), .B(N_7928), .C(N_7894_i), .Y(
        \HWDATA_a0_1[14]_net_1 ));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[17]  (.A(regHADDR[17]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[17]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[17]));
    CFG4 #( .INIT(16'h0255) )  \HWDATA_1[5]  (.A(masterDataInProg_0), 
        .B(un2_cudata_wrdy_int_1_0), .C(cfdatain_N_5), .D(N_7894_i), 
        .Y(\HWDATA_1[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HWDATA[24]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[24]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[16]  (.A(regHADDR[16]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[16]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[16]));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[27]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_27), .C(N_7894_i), .D(memwr_desc_int_m_16), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[27]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[18]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[18]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[18]  (.A(regHADDR[18]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[18]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[18]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[3]  (.A(regHADDR[3]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[3]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[3]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[20]  (.A(regHADDR[20]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[20]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[20]));
    GND GND (.Y(GND_net_1));
    SLE \masterDataInProg[0]  (.D(masterDataInProg_55_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterDataInProg_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[15]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[15]));
    CFG3 #( .INIT(8'hCA) )  HTRANS_i_m3 (.A(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .B(regHTRANS), .C(
        masterRegAddrSel), .Y(N_63));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[24]  (.A(regHADDR[24]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[24]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[24]));
    CFG4 #( .INIT(16'hA0A8) )  \masterDataInProg_RNIHRGOA[0]  (.A(
        masterDataInProg_0), .B(g3), .C(g0_0_2), .D(
        un2_cudata_wrdy_int_9), .Y(CoreAHBLite_0_AHBmslave16_HWDATA[3])
        );
    CFG2 #( .INIT(4'h8) )  \HWDATA[8]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[8]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[6]  (.A(regHADDR[6]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[6]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[6]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[17]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[17]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[25]  (.A(regHADDR[25]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[25]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[25]));
    CFG4 #( .INIT(16'hC088) )  HWRITE_0_iv_RNO (.A(d_m3_i_a3_0), .B(
        masterAddrInProg_0), .C(regHWRITE), .D(masterRegAddrSel), .Y(
        HWRITE_0_iv_RNO_net_1));
    CFG3 #( .INIT(8'h2E) )  HWRITE_0_iv (.A(HWRITE_0_iv_RNO_net_1), .B(
        HWRITE_N_9_mux), .C(cfrd_resp_o), .Y(
        CoreAHBLite_0_AHBmslave16_HWRITE));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[7]  (.A(regHADDR[7]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[7]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[7]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[21]  (.A(regHADDR[21]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[21]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[21]));
    CFG4 #( .INIT(16'h04A4) )  \HWDATA[5]  (.A(N_7894_i), .B(
        cfdatain_d1_5), .C(\HWDATA_1[5]_net_1 ), .D(N_8225), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[5]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[27]  (.A(regHADDR[27]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[27]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[27]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[26]  (.A(regHADDR[26]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[26]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[26]));
    CFG3 #( .INIT(8'h40) )  HWRITE_m4_0_a2 (.A(masterRegAddrSel), .B(
        HWRITE_m4_0_a2_1_net_1), .C(masterAddrInProg_0), .Y(
        HWRITE_N_9_mux));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[12]  (.A(regHADDR[12]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[12]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[12]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[13]  (.A(regHADDR[13]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[13]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[13]));
    CFG3 #( .INIT(8'hD8) )  masterDataInProg_55 (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(masterAddrInProg_0), .C(
        masterDataInProg_0), .Y(masterDataInProg_55_net_1));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[30]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_30), .C(N_7894_i), .D(memwr_desc_int_m_19), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[30]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[9]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[9]));
    CFG4 #( .INIT(16'hA0A8) )  \masterDataInProg_RNI434S8[0]  (.A(
        masterDataInProg_0), .B(req_dstreg_data_0_0), .C(g2), .D(
        un2_cudata_wrdy_int_9), .Y(CoreAHBLite_0_AHBmslave16_HWDATA[6])
        );
    CFG3 #( .INIT(8'h02) )  \HWDATA_a0_1[12]  (.A(masterDataInProg_0), 
        .B(N_5111_i), .C(un2_cudata_wrdy_int_1_0), .Y(
        \HWDATA_a0_1[12]_net_1 ));
    CFG4 #( .INIT(16'hBA30) )  g1_0 (.A(N_7903_0), .B(N_7894_i), .C(
        cfdatain_d1_2), .D(g2_0_0_0), .Y(g1_0_net_1));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[8]  (.A(regHADDR[8]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[8]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[8]));
    COREAHBLITE_SLAVEARBITER_Z3_1 slave_arbiter (.M0GATEDHADDR({
        M0GATEDHADDR[31], M0GATEDHADDR[30], M0GATEDHADDR[29], 
        M0GATEDHADDR[28]}), .masterAddrInProg_0(masterAddrInProg_0), 
        .N_46_i(N_46_i), .regHTRANS(regHTRANS), .masterRegAddrSel(
        masterRegAddrSel), .N_38_i(N_38_i), .N_40_i(N_40_i), .N_42_i(
        N_42_i), .N_44_i(N_44_i), .un1_masterAddrInProg_6_1_i(
        un1_masterAddrInProg_6_1_i), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .N_50_i(N_50_i), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY));
    CFG4 #( .INIT(16'hC0EA) )  \HWDATA_0[14]  (.A(
        \HWDATA_a0_1[14]_net_1 ), .B(cfdatain_o_0_iv_0_1_0), .C(
        masterDataInProg_0), .D(N_8225), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[14]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[21]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), .B(masterDataInProg_0), 
        .Y(CoreAHBLite_0_AHBmslave16_HWDATA[21]));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[26]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_26), .C(N_7894_i), .D(memwr_desc_int_m_15), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[26]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[9]  (.A(regHADDR[9]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[9]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[9]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[22]  (.A(regHADDR[22]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[22]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[22]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[23]  (.A(regHADDR[23]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[23]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[23]));
    CFG4 #( .INIT(16'h5040) )  HWRITE_m4_0_a2_1 (.A(cfrd_req_o), .B(
        fmhwrite_d1), .C(idle_trigger), .D(cfwr_req_o), .Y(
        HWRITE_m4_0_a2_1_net_1));
    CFG4 #( .INIT(16'h80C0) )  HTRANS_i_m3_RNIG54C1 (.A(m0s16DataSel), 
        .B(N_63), .C(masterAddrInProg_0), .D(PREVDATASLAVEREADY_iv), 
        .Y(N_36_i));
    CFG4 #( .INIT(16'hAA08) )  \HWDATA[11]  (.A(masterDataInProg_0), 
        .B(cfdatain_d1_11), .C(N_7894_i), .D(memwr_desc_int_m_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[11]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[16]  (.A(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), .B(masterDataInProg_0), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[16]));
    CFG4 #( .INIT(16'hAC00) )  \HADDR[2]  (.A(regHADDR[2]), .B(
        syssvc_blk_0_AHBL_MASTER_HADDR[2]), .C(masterRegAddrSel), .D(
        masterAddrInProg_0), .Y(CoreAHBLite_0_AHBmslave16_HADDR[2]));
    
endmodule


module COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(
       CoreAHBLite_0_AHBmslave16_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       req_dstreg_data_0_0,
       req_curr_state_RNI9FH21_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       cfdatain_d1_5,
       cfdatain_d1_2,
       cfdatain_d1_0,
       cfdatain_d1_20,
       cfdatain_d1_27,
       cfdatain_d1_26,
       cfdatain_d1_25,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       memwr_desc_int_m_9,
       memwr_desc_int_m_16,
       memwr_desc_int_m_15,
       memwr_desc_int_m_14,
       memwr_desc_int_m_17,
       memwr_desc_int_m_19,
       memwr_desc_int_m_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       cfdatain_o_0_iv_0_0_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_iv_0_7_0,
       masterDataInProg_0,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       N_7894_i,
       N_8225,
       un2_cudata_wrdy_int_1_0,
       cfdatain_N_5,
       N_7903_0,
       g2_0_0_0,
       N_12_1,
       N_10_0_0,
       g2,
       un2_cudata_wrdy_int_9,
       g3,
       g0_0_2,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_1,
       cfdatain_o_iv_N_5_3_0,
       g0_0_0,
       g2_0,
       g0_0,
       cfrd_req_o,
       fmhwrite_d1,
       idle_trigger,
       cfwr_req_o,
       N_5111_i,
       cfrd_resp_o,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       N_7344,
       N_7928,
       cfdatain_o28,
       un1_cfdatain_o26_1_out,
       cfdatain_o27,
       N_36_i,
       cfdatain_N_8_mux_i_0,
       N_46_i,
       N_38_i,
       N_40_i,
       N_42_i,
       N_44_i,
       un1_masterAddrInProg_6_1_i,
       my_hpms_top_0_HPMS_READY,
       my_hpms_top_0_FIC32_0_CLK,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       HREADY_M_pre37,
       CoreAHBLite_0_AHBmslave16_HREADY,
       CoreAHBLite_0_AHBmslave16_HRESP,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       mchready_i
    );
output [27:2] CoreAHBLite_0_AHBmslave16_HADDR;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
input  req_dstreg_data_0_0;
input  req_curr_state_RNI9FH21_0;
input  cfdatain_o_0_iv_0_a2_3_0_0;
input  cfdatain_d1_5;
input  cfdatain_d1_2;
input  cfdatain_d1_0;
input  cfdatain_d1_20;
input  cfdatain_d1_27;
input  cfdatain_d1_26;
input  cfdatain_d1_25;
input  cfdatain_d1_28;
input  cfdatain_d1_30;
input  cfdatain_d1_11;
input  memwr_desc_int_m_9;
input  memwr_desc_int_m_16;
input  memwr_desc_int_m_15;
input  memwr_desc_int_m_14;
input  memwr_desc_int_m_17;
input  memwr_desc_int_m_19;
input  memwr_desc_int_m_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_15;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_13;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_11;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_8;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_9;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_10;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_14;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_16;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_23;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_1;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_2;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_7;
input  cfdatain_o_0_iv_0_0_0;
input  cfdatain_o_0_iv_0_1_0;
input  cfdatain_o_iv_0_4_0;
input  cfdatain_o_iv_0_7_0;
output masterDataInProg_0;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
input  N_7894_i;
input  N_8225;
input  un2_cudata_wrdy_int_1_0;
input  cfdatain_N_5;
input  N_7903_0;
input  g2_0_0_0;
input  N_12_1;
input  N_10_0_0;
input  g2;
input  un2_cudata_wrdy_int_9;
input  g3;
input  g0_0_2;
input  cfdatain_o_iv_0_N_5_3_0;
input  g0_0_1;
input  cfdatain_o_iv_N_5_3_0;
input  g0_0_0;
input  g2_0;
input  g0_0;
input  cfrd_req_o;
input  fmhwrite_d1;
input  idle_trigger;
input  cfwr_req_o;
input  N_5111_i;
input  cfrd_resp_o;
output CoreAHBLite_0_AHBmslave16_HWRITE;
input  N_7344;
input  N_7928;
input  cfdatain_o28;
input  un1_cfdatain_o26_1_out;
input  cfdatain_o27;
output N_36_i;
input  cfdatain_N_8_mux_i_0;
output N_46_i;
output N_38_i;
output N_40_i;
output N_42_i;
output N_44_i;
output un1_masterAddrInProg_6_1_i;
input  my_hpms_top_0_HPMS_READY;
input  my_hpms_top_0_FIC32_0_CLK;
input  syssvc_blk_0_AHBL_MASTER_HWRITE;
output HREADY_M_pre37;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  CoreAHBLite_0_AHBmslave16_HRESP;
output syssvc_blk_0_AHBL_MASTER_HRESP_0;
output mchready_i;

    wire \masterAddrInProg[0] , \M0GATEDHADDR[28] , \M0GATEDHADDR[29] , 
        \M0GATEDHADDR[30] , \M0GATEDHADDR[31] , \regHADDR[2] , 
        \regHADDR[3] , \regHADDR[4] , \regHADDR[5] , \regHADDR[6] , 
        \regHADDR[7] , \regHADDR[8] , \regHADDR[9] , \regHADDR[10] , 
        \regHADDR[11] , \regHADDR[12] , \regHADDR[13] , \regHADDR[14] , 
        \regHADDR[15] , \regHADDR[16] , \regHADDR[17] , \regHADDR[18] , 
        \regHADDR[19] , \regHADDR[20] , \regHADDR[21] , \regHADDR[22] , 
        \regHADDR[23] , \regHADDR[24] , \regHADDR[25] , \regHADDR[26] , 
        \regHADDR[27] , PREVDATASLAVEREADY_iv, N_63, N_50_i, 
        masterRegAddrSel, regHTRANS, regHWRITE, m0s16DataSel, 
        GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 masterstage_0 (
        .M0GATEDHADDR({\M0GATEDHADDR[31] , \M0GATEDHADDR[30] , 
        \M0GATEDHADDR[29] , \M0GATEDHADDR[28] }), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), .regHADDR({\regHADDR[27] , 
        \regHADDR[26] , \regHADDR[25] , \regHADDR[24] , \regHADDR[23] , 
        \regHADDR[22] , \regHADDR[21] , \regHADDR[20] , \regHADDR[19] , 
        \regHADDR[18] , \regHADDR[17] , \regHADDR[16] , \regHADDR[15] , 
        \regHADDR[14] , \regHADDR[13] , \regHADDR[12] , \regHADDR[11] , 
        \regHADDR[10] , \regHADDR[9] , \regHADDR[8] , \regHADDR[7] , 
        \regHADDR[6] , \regHADDR[5] , \regHADDR[4] , \regHADDR[3] , 
        \regHADDR[2] }), .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .masterDataInProg_0(
        masterDataInProg_0), .masterAddrInProg_0(\masterAddrInProg[0] )
        , .mchready_i(mchready_i), .PREVDATASLAVEREADY_iv(
        PREVDATASLAVEREADY_iv), .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), 
        .CoreAHBLite_0_AHBmslave16_HRESP(
        CoreAHBLite_0_AHBmslave16_HRESP), .N_63(N_63), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .N_50_i(N_50_i), 
        .HREADY_M_pre37(HREADY_M_pre37), .masterRegAddrSel(
        masterRegAddrSel), .regHTRANS(regHTRANS), 
        .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .regHWRITE(regHWRITE), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY), 
        .m0s16DataSel(m0s16DataSel));
    COREAHBLITE_SLAVESTAGE_0s_0_0_0 slavestage_16 (.M0GATEDHADDR({
        \M0GATEDHADDR[31] , \M0GATEDHADDR[30] , \M0GATEDHADDR[29] , 
        \M0GATEDHADDR[28] }), .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], nc0, 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9], 
        CoreAHBLite_0_AHBmslave16_HADDR[8], 
        CoreAHBLite_0_AHBmslave16_HADDR[7], 
        CoreAHBLite_0_AHBmslave16_HADDR[6], 
        CoreAHBLite_0_AHBmslave16_HADDR[5], 
        CoreAHBLite_0_AHBmslave16_HADDR[4], 
        CoreAHBLite_0_AHBmslave16_HADDR[3], 
        CoreAHBLite_0_AHBmslave16_HADDR[2]}), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), .regHADDR({\regHADDR[27] , 
        \regHADDR[26] , \regHADDR[25] , \regHADDR[24] , \regHADDR[23] , 
        \regHADDR[22] , \regHADDR[21] , \regHADDR[20] , \regHADDR[19] , 
        \regHADDR[18] , \regHADDR[17] , \regHADDR[16] , \regHADDR[15] , 
        \regHADDR[14] , \regHADDR[13] , \regHADDR[12] , \regHADDR[11] , 
        \regHADDR[10] , \regHADDR[9] , \regHADDR[8] , \regHADDR[7] , 
        \regHADDR[6] , \regHADDR[5] , \regHADDR[4] , \regHADDR[3] , 
        \regHADDR[2] }), .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0), 
        .cfdatain_o_iv_0_4_0(cfdatain_o_iv_0_4_0), 
        .cfdatain_o_0_iv_0_1_0(cfdatain_o_0_iv_0_1_0), 
        .cfdatain_o_0_iv_0_0_0(cfdatain_o_0_iv_0_0_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), .memwr_desc_int_m_9(
        memwr_desc_int_m_9), .memwr_desc_int_m_16(memwr_desc_int_m_16), 
        .memwr_desc_int_m_15(memwr_desc_int_m_15), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_19(memwr_desc_int_m_19), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .cfdatain_d1_5(cfdatain_d1_5), 
        .cfdatain_d1_2(cfdatain_d1_2), .cfdatain_d1_0(cfdatain_d1_0), 
        .cfdatain_d1_20(cfdatain_d1_20), .cfdatain_d1_27(
        cfdatain_d1_27), .cfdatain_d1_26(cfdatain_d1_26), 
        .cfdatain_d1_25(cfdatain_d1_25), .cfdatain_d1_28(
        cfdatain_d1_28), .cfdatain_d1_30(cfdatain_d1_30), 
        .cfdatain_d1_11(cfdatain_d1_11), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .masterAddrInProg_0(
        \masterAddrInProg[0] ), .cfdatain_o_0_iv_0_a2_3_0_0(
        cfdatain_o_0_iv_0_a2_3_0_0), .req_curr_state_RNI9FH21_0(
        req_curr_state_RNI9FH21_0), .req_dstreg_data_0_0(
        req_dstreg_data_0_0), .masterDataInProg_0(masterDataInProg_0), 
        .N_50_i(N_50_i), .un1_masterAddrInProg_6_1_i(
        un1_masterAddrInProg_6_1_i), .N_44_i(N_44_i), .N_42_i(N_42_i), 
        .N_40_i(N_40_i), .N_38_i(N_38_i), .N_46_i(N_46_i), 
        .cfdatain_N_8_mux_i_0(cfdatain_N_8_mux_i_0), .N_36_i(N_36_i), 
        .PREVDATASLAVEREADY_iv(PREVDATASLAVEREADY_iv), .m0s16DataSel(
        m0s16DataSel), .cfdatain_o27(cfdatain_o27), 
        .un1_cfdatain_o26_1_out(un1_cfdatain_o26_1_out), .cfdatain_o28(
        cfdatain_o28), .N_7928(N_7928), .N_7344(N_7344), 
        .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .cfrd_resp_o(cfrd_resp_o), 
        .regHWRITE(regHWRITE), .N_5111_i(N_5111_i), .cfwr_req_o(
        cfwr_req_o), .idle_trigger(idle_trigger), .fmhwrite_d1(
        fmhwrite_d1), .cfrd_req_o(cfrd_req_o), .N_63(N_63), 
        .masterRegAddrSel(masterRegAddrSel), .regHTRANS(regHTRANS), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .g0_0(g0_0), .g2_0(g2_0), 
        .g0_0_0(g0_0_0), .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), 
        .g0_0_1(g0_0_1), .cfdatain_o_iv_0_N_5_3_0(
        cfdatain_o_iv_0_N_5_3_0), .g0_0_2(g0_0_2), .g3(g3), 
        .un2_cudata_wrdy_int_9(un2_cudata_wrdy_int_9), .g2(g2), 
        .N_10_0_0(N_10_0_0), .N_12_1(N_12_1), .g2_0_0_0(g2_0_0_0), 
        .N_7903_0(N_7903_0), .cfdatain_N_5(cfdatain_N_5), 
        .un2_cudata_wrdy_int_1_0(un2_cudata_wrdy_int_1_0), .N_8225(
        N_8225), .N_7894_i(N_7894_i), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY));
    
endmodule


module CoreAHBLite_Z4(
       syssvc_blk_0_AHBL_MASTER_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       masterDataInProg_0,
       cfdatain_o_iv_0_7_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_0_iv_0_0_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       memwr_desc_int_m_9,
       memwr_desc_int_m_16,
       memwr_desc_int_m_15,
       memwr_desc_int_m_14,
       memwr_desc_int_m_17,
       memwr_desc_int_m_19,
       memwr_desc_int_m_0,
       cfdatain_d1_5,
       cfdatain_d1_2,
       cfdatain_d1_0,
       cfdatain_d1_20,
       cfdatain_d1_27,
       cfdatain_d1_26,
       cfdatain_d1_25,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_curr_state_RNI9FH21_0,
       req_dstreg_data_0_0,
       mchready_i,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       CoreAHBLite_0_AHBmslave16_HRESP,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_pre37,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY,
       un1_masterAddrInProg_6_1_i,
       N_44_i,
       N_42_i,
       N_40_i,
       N_38_i,
       N_46_i,
       cfdatain_N_8_mux_i_0,
       N_36_i,
       cfdatain_o27,
       un1_cfdatain_o26_1_out,
       cfdatain_o28,
       N_7928,
       N_7344,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       cfrd_resp_o,
       N_5111_i,
       cfwr_req_o,
       idle_trigger,
       fmhwrite_d1,
       cfrd_req_o,
       g0_0,
       g2_0,
       g0_0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0_1,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_2,
       g3,
       un2_cudata_wrdy_int_9,
       g2,
       N_10_0_0,
       N_12_1,
       g2_0_0_0,
       N_7903_0,
       cfdatain_N_5,
       un2_cudata_wrdy_int_1_0,
       N_8225,
       N_7894_i
    );
input  [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:2] CoreAHBLite_0_AHBmslave16_HADDR;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output masterDataInProg_0;
input  cfdatain_o_iv_0_7_0;
input  cfdatain_o_iv_0_4_0;
input  cfdatain_o_0_iv_0_1_0;
input  cfdatain_o_0_iv_0_0_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_15;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_13;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_11;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_8;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_9;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_10;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_14;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_16;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_23;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_1;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_2;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_7;
input  memwr_desc_int_m_9;
input  memwr_desc_int_m_16;
input  memwr_desc_int_m_15;
input  memwr_desc_int_m_14;
input  memwr_desc_int_m_17;
input  memwr_desc_int_m_19;
input  memwr_desc_int_m_0;
input  cfdatain_d1_5;
input  cfdatain_d1_2;
input  cfdatain_d1_0;
input  cfdatain_d1_20;
input  cfdatain_d1_27;
input  cfdatain_d1_26;
input  cfdatain_d1_25;
input  cfdatain_d1_28;
input  cfdatain_d1_30;
input  cfdatain_d1_11;
input  cfdatain_o_0_iv_0_a2_3_0_0;
input  req_curr_state_RNI9FH21_0;
input  req_dstreg_data_0_0;
output mchready_i;
output syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  CoreAHBLite_0_AHBmslave16_HRESP;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_pre37;
input  syssvc_blk_0_AHBL_MASTER_HWRITE;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;
output un1_masterAddrInProg_6_1_i;
output N_44_i;
output N_42_i;
output N_40_i;
output N_38_i;
output N_46_i;
input  cfdatain_N_8_mux_i_0;
output N_36_i;
input  cfdatain_o27;
input  un1_cfdatain_o26_1_out;
input  cfdatain_o28;
input  N_7928;
input  N_7344;
output CoreAHBLite_0_AHBmslave16_HWRITE;
input  cfrd_resp_o;
input  N_5111_i;
input  cfwr_req_o;
input  idle_trigger;
input  fmhwrite_d1;
input  cfrd_req_o;
input  g0_0;
input  g2_0;
input  g0_0_0;
input  cfdatain_o_iv_N_5_3_0;
input  g0_0_1;
input  cfdatain_o_iv_0_N_5_3_0;
input  g0_0_2;
input  g3;
input  un2_cudata_wrdy_int_9;
input  g2;
input  N_10_0_0;
input  N_12_1;
input  g2_0_0_0;
input  N_7903_0;
input  cfdatain_N_5;
input  un2_cudata_wrdy_int_1_0;
input  N_8225;
input  N_7894_i;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s matrix4x16 (
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9], 
        CoreAHBLite_0_AHBmslave16_HADDR[8], 
        CoreAHBLite_0_AHBmslave16_HADDR[7], 
        CoreAHBLite_0_AHBmslave16_HADDR[6], 
        CoreAHBLite_0_AHBmslave16_HADDR[5], 
        CoreAHBLite_0_AHBmslave16_HADDR[4], 
        CoreAHBLite_0_AHBmslave16_HADDR[3], 
        CoreAHBLite_0_AHBmslave16_HADDR[2]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], nc0, 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), .req_dstreg_data_0_0(
        req_dstreg_data_0_0), .req_curr_state_RNI9FH21_0(
        req_curr_state_RNI9FH21_0), .cfdatain_o_0_iv_0_a2_3_0_0(
        cfdatain_o_0_iv_0_a2_3_0_0), .cfdatain_d1_5(cfdatain_d1_5), 
        .cfdatain_d1_2(cfdatain_d1_2), .cfdatain_d1_0(cfdatain_d1_0), 
        .cfdatain_d1_20(cfdatain_d1_20), .cfdatain_d1_27(
        cfdatain_d1_27), .cfdatain_d1_26(cfdatain_d1_26), 
        .cfdatain_d1_25(cfdatain_d1_25), .cfdatain_d1_28(
        cfdatain_d1_28), .cfdatain_d1_30(cfdatain_d1_30), 
        .cfdatain_d1_11(cfdatain_d1_11), .memwr_desc_int_m_9(
        memwr_desc_int_m_9), .memwr_desc_int_m_16(memwr_desc_int_m_16), 
        .memwr_desc_int_m_15(memwr_desc_int_m_15), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_19(memwr_desc_int_m_19), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), .cfdatain_o_0_iv_0_0_0(
        cfdatain_o_0_iv_0_0_0), .cfdatain_o_0_iv_0_1_0(
        cfdatain_o_0_iv_0_1_0), .cfdatain_o_iv_0_4_0(
        cfdatain_o_iv_0_4_0), .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0)
        , .masterDataInProg_0(masterDataInProg_0), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .N_7894_i(N_7894_i), 
        .N_8225(N_8225), .un2_cudata_wrdy_int_1_0(
        un2_cudata_wrdy_int_1_0), .cfdatain_N_5(cfdatain_N_5), 
        .N_7903_0(N_7903_0), .g2_0_0_0(g2_0_0_0), .N_12_1(N_12_1), 
        .N_10_0_0(N_10_0_0), .g2(g2), .un2_cudata_wrdy_int_9(
        un2_cudata_wrdy_int_9), .g3(g3), .g0_0_2(g0_0_2), 
        .cfdatain_o_iv_0_N_5_3_0(cfdatain_o_iv_0_N_5_3_0), .g0_0_1(
        g0_0_1), .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), 
        .g0_0_0(g0_0_0), .g2_0(g2_0), .g0_0(g0_0), .cfrd_req_o(
        cfrd_req_o), .fmhwrite_d1(fmhwrite_d1), .idle_trigger(
        idle_trigger), .cfwr_req_o(cfwr_req_o), .N_5111_i(N_5111_i), 
        .cfrd_resp_o(cfrd_resp_o), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .N_7344(N_7344), .N_7928(
        N_7928), .cfdatain_o28(cfdatain_o28), .un1_cfdatain_o26_1_out(
        un1_cfdatain_o26_1_out), .cfdatain_o27(cfdatain_o27), .N_36_i(
        N_36_i), .cfdatain_N_8_mux_i_0(cfdatain_N_8_mux_i_0), .N_46_i(
        N_46_i), .N_38_i(N_38_i), .N_40_i(N_40_i), .N_42_i(N_42_i), 
        .N_44_i(N_44_i), .un1_masterAddrInProg_6_1_i(
        un1_masterAddrInProg_6_1_i), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .HREADY_M_pre37(
        HREADY_M_pre37), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), 
        .CoreAHBLite_0_AHBmslave16_HRESP(
        CoreAHBLite_0_AHBmslave16_HRESP), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .mchready_i(mchready_i));
    GND GND (.Y(GND_net_1));
    
endmodule


module my_hpms_HPMS(
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       CoreAHBLite_0_AHBmslave16_HRDATA,
       my_hpms_top_0_FIC32_0_CLK,
       LOCK,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       N_36_i,
       N_46_i,
       un1_masterAddrInProg_6_1_i,
       N_44_i,
       N_42_i,
       N_40_i,
       N_38_i,
       my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F,
       CoreAHBLite_0_AHBmslave16_HRESP,
       CoreAHBLite_0_AHBmslave16_HREADY,
       my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N,
       my_hpms_top_0_COMM_BLK_INT,
       HREADY_M_pre37
    );
input  [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  [27:2] CoreAHBLite_0_AHBmslave16_HADDR;
output [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
inout  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
input  my_hpms_top_0_FIC32_0_CLK;
input  LOCK;
input  CoreAHBLite_0_AHBmslave16_HWRITE;
input  N_36_i;
input  N_46_i;
input  un1_masterAddrInProg_6_1_i;
input  N_44_i;
input  N_42_i;
input  N_40_i;
input  N_38_i;
output my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F;
output CoreAHBLite_0_AHBmslave16_HRESP;
inout  CoreAHBLite_0_AHBmslave16_HREADY;
output my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N;
output my_hpms_top_0_COMM_BLK_INT;
input  HREADY_M_pre37;

    wire \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , VCC_net_1, GND_net_1;
    
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_25 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[26]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[26]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_5 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[5]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[5]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_29 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[30]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[30]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_14 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[15]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[15]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_21 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[22]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[22]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_6 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[6]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[6]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_10 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[11]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[11]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_2 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[2]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[2]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_17 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[18]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[18]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_13 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[14]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[14]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_28 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[29]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[29]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_26 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[27]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[27]));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_4 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[4]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[4]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_22 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[23]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[23]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_30 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[31]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[31]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_15 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[16]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[16]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_7 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[8]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[8]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_19 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[20]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[20]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_8 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[9]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[9]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_11 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[12]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[12]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] ), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[1]));
    MSS_075 #( .INIT(1438'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE400000000000010000000000F11C000001FEDFFC010842108421000001FE34001FF8000000000000000000891007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFC00), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(0.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(), .CAN_TX_EBL_MGPIO4A_H2F_A(), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(), .CLK_CONFIG_APB(), .COMMS_INT(
        my_hpms_top_0_COMM_BLK_INT), .CONFIG_PRESET_N(
        my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), .EDAC_ERROR({nc0, 
        nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .F_FM0_RDATA({
        CoreAHBLite_0_AHBmslave16_HRDATA[31], 
        CoreAHBLite_0_AHBmslave16_HRDATA[30], 
        CoreAHBLite_0_AHBmslave16_HRDATA[29], 
        CoreAHBLite_0_AHBmslave16_HRDATA[28], 
        CoreAHBLite_0_AHBmslave16_HRDATA[27], 
        CoreAHBLite_0_AHBmslave16_HRDATA[26], 
        CoreAHBLite_0_AHBmslave16_HRDATA[25], 
        CoreAHBLite_0_AHBmslave16_HRDATA[24], 
        CoreAHBLite_0_AHBmslave16_HRDATA[23], 
        CoreAHBLite_0_AHBmslave16_HRDATA[22], 
        CoreAHBLite_0_AHBmslave16_HRDATA[21], 
        CoreAHBLite_0_AHBmslave16_HRDATA[20], 
        CoreAHBLite_0_AHBmslave16_HRDATA[19], 
        CoreAHBLite_0_AHBmslave16_HRDATA[18], 
        CoreAHBLite_0_AHBmslave16_HRDATA[17], 
        CoreAHBLite_0_AHBmslave16_HRDATA[16], 
        CoreAHBLite_0_AHBmslave16_HRDATA[15], 
        CoreAHBLite_0_AHBmslave16_HRDATA[14], 
        CoreAHBLite_0_AHBmslave16_HRDATA[13], 
        CoreAHBLite_0_AHBmslave16_HRDATA[12], 
        CoreAHBLite_0_AHBmslave16_HRDATA[11], 
        CoreAHBLite_0_AHBmslave16_HRDATA[10], 
        CoreAHBLite_0_AHBmslave16_HRDATA[9], 
        CoreAHBLite_0_AHBmslave16_HRDATA[8], 
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        CoreAHBLite_0_AHBmslave16_HRDATA[6], 
        CoreAHBLite_0_AHBmslave16_HRDATA[5], 
        CoreAHBLite_0_AHBmslave16_HRDATA[4], 
        CoreAHBLite_0_AHBmslave16_HRDATA[3], 
        CoreAHBLite_0_AHBmslave16_HRDATA[2], 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , 
        CoreAHBLite_0_AHBmslave16_HRDATA[0]}), .F_FM0_READYOUT(
        CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_RESP(
        CoreAHBLite_0_AHBmslave16_HRESP), .F_HM0_ADDR({nc8, nc9, nc10, 
        nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, 
        nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, 
        nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39}), 
        .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc40, nc41}), 
        .F_HM0_TRANS1(), .F_HM0_WDATA({nc42, nc43, nc44, nc45, nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63, nc64, nc65, nc66, 
        nc67, nc68, nc69, nc70, nc71, nc72, nc73}), .F_HM0_WRITE(), 
        .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc74, nc75}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc76, nc77, nc78, nc79}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc80, nc81}), 
        .FAB_XDATAOUT({nc82, nc83, nc84, nc85, nc86, nc87, nc88, nc89})
        , .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc90, nc91}), 
        .FIC32_1_MASTER({nc92, nc93}), .FPGA_RESET_N(
        my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), 
        .H2F_INTERRUPT({nc94, nc95, nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103, nc104, nc105, nc106, nc107, nc108, nc109})
        , .H2F_NMI(), .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({nc110, nc111, nc112, nc113, nc114, nc115, 
        nc116, nc117, nc118, nc119, nc120, nc121, nc122, nc123}), 
        .PER2_FABRIC_PENABLE(), .PER2_FABRIC_PSEL(), 
        .PER2_FABRIC_PWDATA({nc124, nc125, nc126, nc127, nc128, nc129, 
        nc130, nc131, nc132, nc133, nc134, nc135, nc136, nc137, nc138, 
        nc139, nc140, nc141, nc142, nc143, nc144, nc145, nc146, nc147, 
        nc148, nc149, nc150, nc151, nc152, nc153, nc154, nc155}), 
        .PER2_FABRIC_PWRITE(), .RTC_MATCH(), .SLEEPDEEP(), 
        .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), .SMBALERT_NO1(), 
        .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc156, nc157, nc158, nc159, 
        nc160, nc161, nc162, nc163, nc164, nc165}), .TRACECLK(), 
        .TRACEDATA({nc166, nc167, nc168, nc169}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc170, nc171, nc172, 
        nc173}), .TXDF({nc174, nc175, nc176, nc177, nc178, nc179, 
        nc180, nc181}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        ), .F_AWREADY_HREADYOUT0(), .F_BID({nc182, nc183, nc184, nc185})
        , .F_BRESP_HRESP0({nc186, nc187}), .F_BVALID(), 
        .F_RDATA_HRDATA01({nc188, nc189, nc190, nc191, nc192, nc193, 
        nc194, nc195, nc196, nc197, nc198, nc199, nc200, nc201, nc202, 
        nc203, nc204, nc205, nc206, nc207, nc208, nc209, nc210, nc211, 
        nc212, nc213, nc214, nc215, nc216, nc217, nc218, nc219, nc220, 
        nc221, nc222, nc223, nc224, nc225, nc226, nc227, nc228, nc229, 
        nc230, nc231, nc232, nc233, nc234, nc235, nc236, nc237, nc238, 
        nc239, nc240, nc241, nc242, nc243, nc244, nc245, nc246, nc247, 
        nc248, nc249, nc250, nc251}), .F_RID({nc252, nc253, nc254, 
        nc255}), .F_RLAST(), .F_RRESP_HRESP1({nc256, nc257}), 
        .F_RVALID(), .F_WREADY(), .MDDR_FABRIC_PRDATA({nc258, nc259, 
        nc260, nc261, nc262, nc263, nc264, nc265, nc266, nc267, nc268, 
        nc269, nc270, nc271, nc272, nc273}), .MDDR_FABRIC_PREADY(), 
        .MDDR_FABRIC_PSLVERR(), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({N_44_i, 
        N_42_i, N_40_i, N_38_i, CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9], 
        CoreAHBLite_0_AHBmslave16_HADDR[8], 
        CoreAHBLite_0_AHBmslave16_HADDR[7], 
        CoreAHBLite_0_AHBmslave16_HADDR[6], 
        CoreAHBLite_0_AHBmslave16_HADDR[5], 
        CoreAHBLite_0_AHBmslave16_HADDR[4], 
        CoreAHBLite_0_AHBmslave16_HADDR[3], 
        CoreAHBLite_0_AHBmslave16_HADDR[2], GND_net_1, GND_net_1}), 
        .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(GND_net_1), 
        .F_FM0_READY(CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_SEL(
        un1_masterAddrInProg_6_1_i), .F_FM0_SIZE({N_46_i, GND_net_1}), 
        .F_FM0_TRANS1(N_36_i), .F_FM0_WDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .F_FM0_WRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .F_HM0_RDATA({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_HM0_READY(VCC_net_1), .F_HM0_RESP(GND_net_1), 
        .FAB_AVALID(VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(
        VCC_net_1), .FAB_LINESTATE({VCC_net_1, VCC_net_1}), 
        .FAB_M3_RESET_N(GND_net_1), .FAB_PLL_LOCK(LOCK), .FAB_RXACTIVE(
        VCC_net_1), .FAB_RXERROR(VCC_net_1), .FAB_RXVALID(VCC_net_1), 
        .FAB_RXVALIDH(GND_net_1), .FAB_SESSEND(VCC_net_1), 
        .FAB_TXREADY(VCC_net_1), .FAB_VBUSVALID(VCC_net_1), 
        .FAB_VSTATUS({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .FAB_XDATAIN({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .GTX_CLKPF(VCC_net_1), 
        .I2C0_BCLK(VCC_net_1), .I2C0_SCL_F2H_SCP(VCC_net_1), 
        .I2C0_SDA_F2H_SCP(VCC_net_1), .I2C1_BCLK(VCC_net_1), 
        .I2C1_SCL_F2H_SCP(VCC_net_1), .I2C1_SDA_F2H_SCP(VCC_net_1), 
        .MDIF(VCC_net_1), .MGPIO0A_F2H_GPIN(VCC_net_1), 
        .MGPIO10A_F2H_GPIN(VCC_net_1), .MGPIO11A_F2H_GPIN(VCC_net_1), 
        .MGPIO11B_F2H_GPIN(VCC_net_1), .MGPIO12A_F2H_GPIN(VCC_net_1), 
        .MGPIO13A_F2H_GPIN(VCC_net_1), .MGPIO14A_F2H_GPIN(VCC_net_1), 
        .MGPIO15A_F2H_GPIN(VCC_net_1), .MGPIO16A_F2H_GPIN(VCC_net_1), 
        .MGPIO17B_F2H_GPIN(VCC_net_1), .MGPIO18B_F2H_GPIN(VCC_net_1), 
        .MGPIO19B_F2H_GPIN(VCC_net_1), .MGPIO1A_F2H_GPIN(VCC_net_1), 
        .MGPIO20B_F2H_GPIN(VCC_net_1), .MGPIO21B_F2H_GPIN(VCC_net_1), 
        .MGPIO22B_F2H_GPIN(VCC_net_1), .MGPIO24B_F2H_GPIN(VCC_net_1), 
        .MGPIO25B_F2H_GPIN(VCC_net_1), .MGPIO26B_F2H_GPIN(VCC_net_1), 
        .MGPIO27B_F2H_GPIN(VCC_net_1), .MGPIO28B_F2H_GPIN(VCC_net_1), 
        .MGPIO29B_F2H_GPIN(VCC_net_1), .MGPIO2A_F2H_GPIN(VCC_net_1), 
        .MGPIO30B_F2H_GPIN(VCC_net_1), .MGPIO31B_F2H_GPIN(VCC_net_1), 
        .MGPIO3A_F2H_GPIN(VCC_net_1), .MGPIO4A_F2H_GPIN(VCC_net_1), 
        .MGPIO5A_F2H_GPIN(VCC_net_1), .MGPIO6A_F2H_GPIN(VCC_net_1), 
        .MGPIO7A_F2H_GPIN(VCC_net_1), .MGPIO8A_F2H_GPIN(VCC_net_1), 
        .MGPIO9A_F2H_GPIN(VCC_net_1), .MMUART0_CTS_F2H_SCP(VCC_net_1), 
        .MMUART0_DCD_F2H_SCP(VCC_net_1), .MMUART0_DSR_F2H_SCP(
        VCC_net_1), .MMUART0_DTR_F2H_SCP(VCC_net_1), 
        .MMUART0_RI_F2H_SCP(VCC_net_1), .MMUART0_RTS_F2H_SCP(VCC_net_1)
        , .MMUART0_RXD_F2H_SCP(VCC_net_1), .MMUART0_SCK_F2H_SCP(
        VCC_net_1), .MMUART0_TXD_F2H_SCP(VCC_net_1), 
        .MMUART1_CTS_F2H_SCP(VCC_net_1), .MMUART1_DCD_F2H_SCP(
        VCC_net_1), .MMUART1_DSR_F2H_SCP(VCC_net_1), 
        .MMUART1_RI_F2H_SCP(VCC_net_1), .MMUART1_RTS_F2H_SCP(VCC_net_1)
        , .MMUART1_RXD_F2H_SCP(VCC_net_1), .MMUART1_SCK_F2H_SCP(
        VCC_net_1), .MMUART1_TXD_F2H_SCP(VCC_net_1), 
        .PER2_FABRIC_PRDATA({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .PER2_FABRIC_PREADY(VCC_net_1), .PER2_FABRIC_PSLVERR(GND_net_1)
        , .RCGF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .RX_CLKPF(VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), 
        .RX_EV(VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .SLEEPHOLDREQ(GND_net_1), .SMBALERT_NI0(VCC_net_1), 
        .SMBALERT_NI1(VCC_net_1), .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(
        VCC_net_1), .SPI0_CLK_IN(VCC_net_1), .SPI0_SDI_F2H_SCP(
        VCC_net_1), .SPI0_SDO_F2H_SCP(VCC_net_1), .SPI0_SS0_F2H_SCP(
        VCC_net_1), .SPI0_SS1_F2H_SCP(VCC_net_1), .SPI0_SS2_F2H_SCP(
        VCC_net_1), .SPI0_SS3_F2H_SCP(VCC_net_1), .SPI1_CLK_IN(
        VCC_net_1), .SPI1_SDI_F2H_SCP(VCC_net_1), .SPI1_SDO_F2H_SCP(
        VCC_net_1), .SPI1_SS0_F2H_SCP(VCC_net_1), .SPI1_SS1_F2H_SCP(
        VCC_net_1), .SPI1_SS2_F2H_SCP(VCC_net_1), .SPI1_SS3_F2H_SCP(
        VCC_net_1), .TX_CLKPF(VCC_net_1), .USER_MSS_GPIO_RESET_N(
        VCC_net_1), .USER_MSS_RESET_N(VCC_net_1), .XCLK_FAB(VCC_net_1), 
        .CLK_BASE(my_hpms_top_0_FIC32_0_CLK), .CLK_MDDR_APB(VCC_net_1), 
        .F_ARADDR_HADDR1({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .F_ARBURST_HTRANS1({
        GND_net_1, GND_net_1}), .F_ARID_HSEL1({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_ARLEN_HBURST1({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_ARLOCK_HMASTLOCK1({GND_net_1, 
        GND_net_1}), .F_ARSIZE_HSIZE1({GND_net_1, GND_net_1}), 
        .F_ARVALID_HWRITE1(GND_net_1), .F_AWADDR_HADDR0({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .F_AWBURST_HTRANS0({GND_net_1, GND_net_1}), 
        .F_AWID_HSEL0({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_AWLEN_HBURST0({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_AWLOCK_HMASTLOCK0({GND_net_1, GND_net_1}), .F_AWSIZE_HSIZE0({
        GND_net_1, GND_net_1}), .F_AWVALID_HWRITE0(GND_net_1), 
        .F_BREADY(GND_net_1), .F_RMW_AXI(GND_net_1), .F_RREADY(
        GND_net_1), .F_WDATA_HWDATA01({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .F_WID_HREADY01({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_WLAST(GND_net_1), .F_WSTRB({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_WVALID(GND_net_1), 
        .FPGA_MDDR_ARESET_N(VCC_net_1), .MDDR_FABRIC_PADDR({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .MDDR_FABRIC_PENABLE(
        VCC_net_1), .MDDR_FABRIC_PSEL(VCC_net_1), .MDDR_FABRIC_PWDATA({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .MDDR_FABRIC_PWRITE(VCC_net_1), .PRESET_N(
        GND_net_1), .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1}), 
        .DRAM_FIFO_WE_IN({GND_net_1, GND_net_1}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND_net_1), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({nc274, nc275, 
        nc276, nc277, nc278, nc279, nc280, nc281, nc282, nc283, nc284, 
        nc285, nc286, nc287, nc288, nc289}), .DRAM_BA({nc290, nc291, 
        nc292}), .DRAM_CASN(), .DRAM_CKE(), .DRAM_CLK(), .DRAM_CSN(), 
        .DRAM_DM_RDQS_OUT({nc293, nc294, nc295}), .DRAM_DQ_OUT({nc296, 
        nc297, nc298, nc299, nc300, nc301, nc302, nc303, nc304, nc305, 
        nc306, nc307, nc308, nc309, nc310, nc311, nc312, nc313}), 
        .DRAM_DQS_OUT({nc314, nc315, nc316}), .DRAM_FIFO_WE_OUT({nc317, 
        nc318}), .DRAM_ODT(), .DRAM_RASN(), .DRAM_RSTN(), .DRAM_WEN(), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc319, nc320, 
        nc321}), .DRAM_DQ_OE({nc322, nc323, nc324, nc325, nc326, nc327, 
        nc328, nc329, nc330, nc331, nc332, nc333, nc334, nc335, nc336, 
        nc337, nc338, nc339}), .DRAM_DQS_OE({nc340, nc341, nc342}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), .MMUART1_CTS_MGPIO13B_OE()
        , .MMUART1_DCD_MGPIO16B_OE(), .MMUART1_DSR_MGPIO14B_OE(), 
        .MMUART1_DTR_MGPIO12B_OE(), .MMUART1_RI_MGPIO15B_OE(), 
        .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_24 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[25]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[25]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_1 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[0]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_20 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[21]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[21]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_27 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[28]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[28]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_23 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[24]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[24]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_18 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[19]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[19]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_9 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[10]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[10]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_0 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] ), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[7]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_16 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[17]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[17]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_12 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[13]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[13]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNIJC0E_3 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[3]), .B(HREADY_M_pre37), .Y(
        syssvc_blk_0_AHBL_MASTER_HRDATA[3]));
    
endmodule


module my_hpms_CCC_0_FCCC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC,
       LOCK,
       my_hpms_top_0_FIC32_0_CLK
    );
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
output LOCK;
output my_hpms_top_0_FIC32_0_CLK;

    wire GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST (.A(GL0_net), .Y(my_hpms_top_0_FIC32_0_CLK));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6318C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(LOCK), 
        .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), .CLK2(VCC_net_1), 
        .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), .NGMUX1_SEL(
        GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(GND_net_1), 
        .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(VCC_net_1), 
        .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(VCC_net_1), 
        .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(VCC_net_1), 
        .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(VCC_net_1), 
        .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(VCC_net_1), 
        .PLL_POWERDOWN_N(VCC_net_1), .GPD0_ARST_N(VCC_net_1), 
        .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(VCC_net_1), .GPD3_ARST_N(
        VCC_net_1), .PRESET_N(GND_net_1), .PCLK(VCC_net_1), .PSEL(
        VCC_net_1), .PENABLE(VCC_net_1), .PWRITE(VCC_net_1), .PADDR({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .CLK0_PAD(GND_net_1), .CLK1_PAD(GND_net_1), .CLK2_PAD(
        GND_net_1), .CLK3_PAD(GND_net_1), .GL0(GL0_net), .GL1(), .GL2()
        , .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module my_hpms(
       CoreAHBLite_0_AHBmslave16_HRDATA,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA_0,
       req_dstreg_data_0_0,
       req_curr_state_RNI9FH21_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       cfdatain_d1_5,
       cfdatain_d1_2,
       cfdatain_d1_0,
       cfdatain_d1_20,
       cfdatain_d1_27,
       cfdatain_d1_26,
       cfdatain_d1_25,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       memwr_desc_int_m_9,
       memwr_desc_int_m_16,
       memwr_desc_int_m_15,
       memwr_desc_int_m_14,
       memwr_desc_int_m_17,
       memwr_desc_int_m_19,
       memwr_desc_int_m_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       cfdatain_o_0_iv_0_0_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_iv_0_7_0,
       masterDataInProg_0,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       my_hpms_top_0_COMM_BLK_INT,
       N_7894_i,
       N_8225,
       un2_cudata_wrdy_int_1_0,
       cfdatain_N_5,
       N_7903_0,
       g2_0_0_0,
       N_12_1,
       N_10_0_0,
       g2,
       un2_cudata_wrdy_int_9,
       g3,
       g0_0_2,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_1,
       cfdatain_o_iv_N_5_3_0,
       g0_0_0,
       g2_0,
       g0_0,
       cfrd_req_o,
       fmhwrite_d1,
       idle_trigger,
       cfwr_req_o,
       N_5111_i,
       cfrd_resp_o,
       N_7344,
       N_7928,
       cfdatain_o28,
       un1_cfdatain_o26_1_out,
       cfdatain_o27,
       cfdatain_N_8_mux_i_0,
       my_hpms_top_0_HPMS_READY,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       mchready_i,
       my_hpms_top_0_FIC32_0_CLK,
       DEVRST_N
    );
inout  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
output [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
input  [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
input  CoreAHBLite_0_AHBmslave16_HWDATA_0;
input  req_dstreg_data_0_0;
input  req_curr_state_RNI9FH21_0;
input  cfdatain_o_0_iv_0_a2_3_0_0;
input  cfdatain_d1_5;
input  cfdatain_d1_2;
input  cfdatain_d1_0;
input  cfdatain_d1_20;
input  cfdatain_d1_27;
input  cfdatain_d1_26;
input  cfdatain_d1_25;
input  cfdatain_d1_28;
input  cfdatain_d1_30;
input  cfdatain_d1_11;
input  memwr_desc_int_m_9;
input  memwr_desc_int_m_16;
input  memwr_desc_int_m_15;
input  memwr_desc_int_m_14;
input  memwr_desc_int_m_17;
input  memwr_desc_int_m_19;
input  memwr_desc_int_m_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_15;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_13;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_11;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_8;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_9;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_10;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_14;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_16;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_23;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_1;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_2;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_7;
input  cfdatain_o_0_iv_0_0_0;
input  cfdatain_o_0_iv_0_1_0;
input  cfdatain_o_iv_0_4_0;
input  cfdatain_o_iv_0_7_0;
output masterDataInProg_0;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output my_hpms_top_0_COMM_BLK_INT;
input  N_7894_i;
input  N_8225;
input  un2_cudata_wrdy_int_1_0;
input  cfdatain_N_5;
input  N_7903_0;
input  g2_0_0_0;
input  N_12_1;
input  N_10_0_0;
input  g2;
input  un2_cudata_wrdy_int_9;
input  g3;
input  g0_0_2;
input  cfdatain_o_iv_0_N_5_3_0;
input  g0_0_1;
input  cfdatain_o_iv_N_5_3_0;
input  g0_0_0;
input  g2_0;
input  g0_0;
input  cfrd_req_o;
input  fmhwrite_d1;
input  idle_trigger;
input  cfwr_req_o;
input  N_5111_i;
input  cfrd_resp_o;
input  N_7344;
input  N_7928;
input  cfdatain_o28;
input  un1_cfdatain_o26_1_out;
input  cfdatain_o27;
input  cfdatain_N_8_mux_i_0;
output my_hpms_top_0_HPMS_READY;
input  syssvc_blk_0_AHBL_MASTER_HWRITE;
output syssvc_blk_0_AHBL_MASTER_HRESP_0;
output mchready_i;
output my_hpms_top_0_FIC32_0_CLK;
input  DEVRST_N;

    wire SYSRESET_POR_net_1, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, LOCK, 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        CoreAHBLite_0_AHBmslave16_HRESP, 
        CoreAHBLite_0_AHBmslave16_HREADY, HREADY_M_pre37, 
        un1_masterAddrInProg_6_1_i, N_44_i, N_42_i, N_40_i, N_38_i, 
        N_46_i, N_36_i, CoreAHBLite_0_AHBmslave16_HWRITE, 
        my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N, 
        my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F, GND_net_1, VCC_net_1;
    
    my_hpms_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z5 CORERESETP_0 (
        .my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N(
        my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F(
        my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F), .SYSRESET_POR(
        SYSRESET_POR_net_1), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY));
    CoreAHBLite_Z4 CoreAHBLite_0 (.syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , nc0, 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] }), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .masterDataInProg_0(
        masterDataInProg_0), .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0), 
        .cfdatain_o_iv_0_4_0(cfdatain_o_iv_0_4_0), 
        .cfdatain_o_0_iv_0_1_0(cfdatain_o_0_iv_0_1_0), 
        .cfdatain_o_0_iv_0_0_0(cfdatain_o_0_iv_0_0_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), .memwr_desc_int_m_9(
        memwr_desc_int_m_9), .memwr_desc_int_m_16(memwr_desc_int_m_16), 
        .memwr_desc_int_m_15(memwr_desc_int_m_15), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_19(memwr_desc_int_m_19), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .cfdatain_d1_5(cfdatain_d1_5), 
        .cfdatain_d1_2(cfdatain_d1_2), .cfdatain_d1_0(cfdatain_d1_0), 
        .cfdatain_d1_20(cfdatain_d1_20), .cfdatain_d1_27(
        cfdatain_d1_27), .cfdatain_d1_26(cfdatain_d1_26), 
        .cfdatain_d1_25(cfdatain_d1_25), .cfdatain_d1_28(
        cfdatain_d1_28), .cfdatain_d1_30(cfdatain_d1_30), 
        .cfdatain_d1_11(cfdatain_d1_11), .cfdatain_o_0_iv_0_a2_3_0_0(
        cfdatain_o_0_iv_0_a2_3_0_0), .req_curr_state_RNI9FH21_0(
        req_curr_state_RNI9FH21_0), .req_dstreg_data_0_0(
        req_dstreg_data_0_0), .mchready_i(mchready_i), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), 
        .CoreAHBLite_0_AHBmslave16_HRESP(
        CoreAHBLite_0_AHBmslave16_HRESP), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_pre37(
        HREADY_M_pre37), .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .un1_masterAddrInProg_6_1_i(
        un1_masterAddrInProg_6_1_i), .N_44_i(N_44_i), .N_42_i(N_42_i), 
        .N_40_i(N_40_i), .N_38_i(N_38_i), .N_46_i(N_46_i), 
        .cfdatain_N_8_mux_i_0(cfdatain_N_8_mux_i_0), .N_36_i(N_36_i), 
        .cfdatain_o27(cfdatain_o27), .un1_cfdatain_o26_1_out(
        un1_cfdatain_o26_1_out), .cfdatain_o28(cfdatain_o28), .N_7928(
        N_7928), .N_7344(N_7344), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .cfrd_resp_o(cfrd_resp_o), 
        .N_5111_i(N_5111_i), .cfwr_req_o(cfwr_req_o), .idle_trigger(
        idle_trigger), .fmhwrite_d1(fmhwrite_d1), .cfrd_req_o(
        cfrd_req_o), .g0_0(g0_0), .g2_0(g2_0), .g0_0_0(g0_0_0), 
        .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), .g0_0_1(g0_0_1), 
        .cfdatain_o_iv_0_N_5_3_0(cfdatain_o_iv_0_N_5_3_0), .g0_0_2(
        g0_0_2), .g3(g3), .un2_cudata_wrdy_int_9(un2_cudata_wrdy_int_9)
        , .g2(g2), .N_10_0_0(N_10_0_0), .N_12_1(N_12_1), .g2_0_0_0(
        g2_0_0_0), .N_7903_0(N_7903_0), .cfdatain_N_5(cfdatain_N_5), 
        .un2_cudata_wrdy_int_1_0(un2_cudata_wrdy_int_1_0), .N_8225(
        N_8225), .N_7894_i(N_7894_i));
    VCC VCC (.Y(VCC_net_1));
    my_hpms_HPMS my_hpms_HPMS_0 (.CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        CoreAHBLite_0_AHBmslave16_HWDATA_0, 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] }), 
        .syssvc_blk_0_AHBL_MASTER_HRDATA({
        syssvc_blk_0_AHBL_MASTER_HRDATA[31], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[30], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[29], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[28], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[27], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[26], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[25], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[24], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[23], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[22], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[21], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[20], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[19], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[18], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[17], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[16], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[15], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[14], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[13], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[12], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[11], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[10], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[9], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[8], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[7], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[6], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[5], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[4], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[3], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[2], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[1], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HRDATA({
        CoreAHBLite_0_AHBmslave16_HRDATA[31], 
        CoreAHBLite_0_AHBmslave16_HRDATA[30], 
        CoreAHBLite_0_AHBmslave16_HRDATA[29], 
        CoreAHBLite_0_AHBmslave16_HRDATA[28], 
        CoreAHBLite_0_AHBmslave16_HRDATA[27], 
        CoreAHBLite_0_AHBmslave16_HRDATA[26], 
        CoreAHBLite_0_AHBmslave16_HRDATA[25], 
        CoreAHBLite_0_AHBmslave16_HRDATA[24], 
        CoreAHBLite_0_AHBmslave16_HRDATA[23], 
        CoreAHBLite_0_AHBmslave16_HRDATA[22], 
        CoreAHBLite_0_AHBmslave16_HRDATA[21], 
        CoreAHBLite_0_AHBmslave16_HRDATA[20], 
        CoreAHBLite_0_AHBmslave16_HRDATA[19], 
        CoreAHBLite_0_AHBmslave16_HRDATA[18], 
        CoreAHBLite_0_AHBmslave16_HRDATA[17], 
        CoreAHBLite_0_AHBmslave16_HRDATA[16], 
        CoreAHBLite_0_AHBmslave16_HRDATA[15], 
        CoreAHBLite_0_AHBmslave16_HRDATA[14], 
        CoreAHBLite_0_AHBmslave16_HRDATA[13], 
        CoreAHBLite_0_AHBmslave16_HRDATA[12], 
        CoreAHBLite_0_AHBmslave16_HRDATA[11], 
        CoreAHBLite_0_AHBmslave16_HRDATA[10], 
        CoreAHBLite_0_AHBmslave16_HRDATA[9], 
        CoreAHBLite_0_AHBmslave16_HRDATA[8], nc1, 
        CoreAHBLite_0_AHBmslave16_HRDATA[6], 
        CoreAHBLite_0_AHBmslave16_HRDATA[5], 
        CoreAHBLite_0_AHBmslave16_HRDATA[4], 
        CoreAHBLite_0_AHBmslave16_HRDATA[3], 
        CoreAHBLite_0_AHBmslave16_HRDATA[2], nc2, 
        CoreAHBLite_0_AHBmslave16_HRDATA[0]}), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), .LOCK(
        LOCK), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .N_36_i(N_36_i), .N_46_i(
        N_46_i), .un1_masterAddrInProg_6_1_i(
        un1_masterAddrInProg_6_1_i), .N_44_i(N_44_i), .N_42_i(N_42_i), 
        .N_40_i(N_40_i), .N_38_i(N_38_i), 
        .my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F(
        my_hpms_HPMS_TMP_0_MSS_RESET_N_M2F), 
        .CoreAHBLite_0_AHBmslave16_HRESP(
        CoreAHBLite_0_AHBmslave16_HRESP), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), 
        .my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N(
        my_hpms_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .my_hpms_top_0_COMM_BLK_INT(my_hpms_top_0_COMM_BLK_INT), 
        .HREADY_M_pre37(HREADY_M_pre37));
    my_hpms_CCC_0_FCCC CCC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), .LOCK(
        LOCK), .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK));
    GND GND (.Y(GND_net_1));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(SYSRESET_POR_net_1), 
        .DEVRST_N(DEVRST_N));
    
endmodule


module my_hpms_top(
       syssvc_blk_0_AHBL_MASTER_HADDR,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       CoreAHBLite_0_AHBmslave16_HRDATA,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       masterDataInProg_0,
       cfdatain_o_iv_0_7_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_0_iv_0_0_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       memwr_desc_int_m_9,
       memwr_desc_int_m_16,
       memwr_desc_int_m_15,
       memwr_desc_int_m_14,
       memwr_desc_int_m_17,
       memwr_desc_int_m_19,
       memwr_desc_int_m_0,
       cfdatain_d1_5,
       cfdatain_d1_2,
       cfdatain_d1_0,
       cfdatain_d1_20,
       cfdatain_d1_27,
       cfdatain_d1_26,
       cfdatain_d1_25,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_curr_state_RNI9FH21_0,
       req_dstreg_data_0_0,
       CoreAHBLite_0_AHBmslave16_HWDATA_0,
       DEVRST_N,
       my_hpms_top_0_FIC32_0_CLK,
       mchready_i,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       my_hpms_top_0_HPMS_READY,
       cfdatain_N_8_mux_i_0,
       cfdatain_o27,
       un1_cfdatain_o26_1_out,
       cfdatain_o28,
       N_7928,
       N_7344,
       cfrd_resp_o,
       N_5111_i,
       cfwr_req_o,
       idle_trigger,
       fmhwrite_d1,
       cfrd_req_o,
       g0_0,
       g2_0,
       g0_0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0_1,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_2,
       g3,
       un2_cudata_wrdy_int_9,
       g2,
       N_10_0_0,
       N_12_1,
       g2_0_0_0,
       N_7903_0,
       cfdatain_N_5,
       un2_cudata_wrdy_int_1_0,
       N_8225,
       N_7894_i,
       my_hpms_top_0_COMM_BLK_INT
    );
input  [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
output [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
inout  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
input  syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output masterDataInProg_0;
input  cfdatain_o_iv_0_7_0;
input  cfdatain_o_iv_0_4_0;
input  cfdatain_o_0_iv_0_1_0;
input  cfdatain_o_0_iv_0_0_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_15;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_13;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_11;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_8;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_9;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_10;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_14;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_16;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_23;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_0;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_1;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_2;
input  syssvc_blk_0_AHBL_MASTER_HWDATA_7;
input  memwr_desc_int_m_9;
input  memwr_desc_int_m_16;
input  memwr_desc_int_m_15;
input  memwr_desc_int_m_14;
input  memwr_desc_int_m_17;
input  memwr_desc_int_m_19;
input  memwr_desc_int_m_0;
input  cfdatain_d1_5;
input  cfdatain_d1_2;
input  cfdatain_d1_0;
input  cfdatain_d1_20;
input  cfdatain_d1_27;
input  cfdatain_d1_26;
input  cfdatain_d1_25;
input  cfdatain_d1_28;
input  cfdatain_d1_30;
input  cfdatain_d1_11;
input  cfdatain_o_0_iv_0_a2_3_0_0;
input  req_curr_state_RNI9FH21_0;
input  req_dstreg_data_0_0;
input  CoreAHBLite_0_AHBmslave16_HWDATA_0;
input  DEVRST_N;
output my_hpms_top_0_FIC32_0_CLK;
output mchready_i;
output syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  syssvc_blk_0_AHBL_MASTER_HWRITE;
output my_hpms_top_0_HPMS_READY;
input  cfdatain_N_8_mux_i_0;
input  cfdatain_o27;
input  un1_cfdatain_o26_1_out;
input  cfdatain_o28;
input  N_7928;
input  N_7344;
input  cfrd_resp_o;
input  N_5111_i;
input  cfwr_req_o;
input  idle_trigger;
input  fmhwrite_d1;
input  cfrd_req_o;
input  g0_0;
input  g2_0;
input  g0_0_0;
input  cfdatain_o_iv_N_5_3_0;
input  g0_0_1;
input  cfdatain_o_iv_0_N_5_3_0;
input  g0_0_2;
input  g3;
input  un2_cudata_wrdy_int_9;
input  g2;
input  N_10_0_0;
input  N_12_1;
input  g2_0_0_0;
input  N_7903_0;
input  cfdatain_N_5;
input  un2_cudata_wrdy_int_1_0;
input  N_8225;
input  N_7894_i;
output my_hpms_top_0_COMM_BLK_INT;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    my_hpms my_hpms_0 (.CoreAHBLite_0_AHBmslave16_HRDATA({
        CoreAHBLite_0_AHBmslave16_HRDATA[31], 
        CoreAHBLite_0_AHBmslave16_HRDATA[30], 
        CoreAHBLite_0_AHBmslave16_HRDATA[29], 
        CoreAHBLite_0_AHBmslave16_HRDATA[28], 
        CoreAHBLite_0_AHBmslave16_HRDATA[27], 
        CoreAHBLite_0_AHBmslave16_HRDATA[26], 
        CoreAHBLite_0_AHBmslave16_HRDATA[25], 
        CoreAHBLite_0_AHBmslave16_HRDATA[24], 
        CoreAHBLite_0_AHBmslave16_HRDATA[23], 
        CoreAHBLite_0_AHBmslave16_HRDATA[22], 
        CoreAHBLite_0_AHBmslave16_HRDATA[21], 
        CoreAHBLite_0_AHBmslave16_HRDATA[20], 
        CoreAHBLite_0_AHBmslave16_HRDATA[19], 
        CoreAHBLite_0_AHBmslave16_HRDATA[18], 
        CoreAHBLite_0_AHBmslave16_HRDATA[17], 
        CoreAHBLite_0_AHBmslave16_HRDATA[16], 
        CoreAHBLite_0_AHBmslave16_HRDATA[15], 
        CoreAHBLite_0_AHBmslave16_HRDATA[14], 
        CoreAHBLite_0_AHBmslave16_HRDATA[13], 
        CoreAHBLite_0_AHBmslave16_HRDATA[12], 
        CoreAHBLite_0_AHBmslave16_HRDATA[11], 
        CoreAHBLite_0_AHBmslave16_HRDATA[10], 
        CoreAHBLite_0_AHBmslave16_HRDATA[9], 
        CoreAHBLite_0_AHBmslave16_HRDATA[8], nc0, 
        CoreAHBLite_0_AHBmslave16_HRDATA[6], 
        CoreAHBLite_0_AHBmslave16_HRDATA[5], 
        CoreAHBLite_0_AHBmslave16_HRDATA[4], 
        CoreAHBLite_0_AHBmslave16_HRDATA[3], 
        CoreAHBLite_0_AHBmslave16_HRDATA[2], nc1, 
        CoreAHBLite_0_AHBmslave16_HRDATA[0]}), 
        .syssvc_blk_0_AHBL_MASTER_HRDATA({
        syssvc_blk_0_AHBL_MASTER_HRDATA[31], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[30], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[29], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[28], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[27], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[26], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[25], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[24], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[23], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[22], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[21], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[20], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[19], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[18], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[17], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[16], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[15], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[14], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[13], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[12], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[11], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[10], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[9], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[8], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[7], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[6], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[5], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[4], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[3], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[2], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[1], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]}), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA_0(
        CoreAHBLite_0_AHBmslave16_HWDATA_0), .req_dstreg_data_0_0(
        req_dstreg_data_0_0), .req_curr_state_RNI9FH21_0(
        req_curr_state_RNI9FH21_0), .cfdatain_o_0_iv_0_a2_3_0_0(
        cfdatain_o_0_iv_0_a2_3_0_0), .cfdatain_d1_5(cfdatain_d1_5), 
        .cfdatain_d1_2(cfdatain_d1_2), .cfdatain_d1_0(cfdatain_d1_0), 
        .cfdatain_d1_20(cfdatain_d1_20), .cfdatain_d1_27(
        cfdatain_d1_27), .cfdatain_d1_26(cfdatain_d1_26), 
        .cfdatain_d1_25(cfdatain_d1_25), .cfdatain_d1_28(
        cfdatain_d1_28), .cfdatain_d1_30(cfdatain_d1_30), 
        .cfdatain_d1_11(cfdatain_d1_11), .memwr_desc_int_m_9(
        memwr_desc_int_m_9), .memwr_desc_int_m_16(memwr_desc_int_m_16), 
        .memwr_desc_int_m_15(memwr_desc_int_m_15), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_19(memwr_desc_int_m_19), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), .cfdatain_o_0_iv_0_0_0(
        cfdatain_o_0_iv_0_0_0), .cfdatain_o_0_iv_0_1_0(
        cfdatain_o_0_iv_0_1_0), .cfdatain_o_iv_0_4_0(
        cfdatain_o_iv_0_4_0), .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0)
        , .masterDataInProg_0(masterDataInProg_0), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), 
        .my_hpms_top_0_COMM_BLK_INT(my_hpms_top_0_COMM_BLK_INT), 
        .N_7894_i(N_7894_i), .N_8225(N_8225), .un2_cudata_wrdy_int_1_0(
        un2_cudata_wrdy_int_1_0), .cfdatain_N_5(cfdatain_N_5), 
        .N_7903_0(N_7903_0), .g2_0_0_0(g2_0_0_0), .N_12_1(N_12_1), 
        .N_10_0_0(N_10_0_0), .g2(g2), .un2_cudata_wrdy_int_9(
        un2_cudata_wrdy_int_9), .g3(g3), .g0_0_2(g0_0_2), 
        .cfdatain_o_iv_0_N_5_3_0(cfdatain_o_iv_0_N_5_3_0), .g0_0_1(
        g0_0_1), .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), 
        .g0_0_0(g0_0_0), .g2_0(g2_0), .g0_0(g0_0), .cfrd_req_o(
        cfrd_req_o), .fmhwrite_d1(fmhwrite_d1), .idle_trigger(
        idle_trigger), .cfwr_req_o(cfwr_req_o), .N_5111_i(N_5111_i), 
        .cfrd_resp_o(cfrd_resp_o), .N_7344(N_7344), .N_7928(N_7928), 
        .cfdatain_o28(cfdatain_o28), .un1_cfdatain_o26_1_out(
        un1_cfdatain_o26_1_out), .cfdatain_o27(cfdatain_o27), 
        .cfdatain_N_8_mux_i_0(cfdatain_N_8_mux_i_0), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY), 
        .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .mchready_i(mchready_i), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .DEVRST_N(DEVRST_N));
    
endmodule


module CoreSysServices_FSMCtrl(
       cfburst_len_rd_o,
       cfburst_len_wr_o,
       cfdst_addr_o_iv,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       cfdst_addr_o_0_iv_0,
       cfsrc_addr_o_27,
       cfsrc_addr_o_11,
       cfsrc_addr_o_12,
       cfsrc_addr_o_10,
       cfsrc_addr_o_0,
       cfsrc_addr_o_14,
       cfsrc_addr_o_1,
       cfdst_addr_o_27,
       cfdst_addr_o_10,
       cfdst_addr_o_0,
       cfdst_addr_o_2,
       cfdst_addr_o_14,
       cfdst_addr_o_1,
       cfburst_len_wr_o_1_2_x_0,
       resp_curr_state_5,
       resp_curr_state_6,
       resp_curr_state_0,
       req_curr_state_0,
       curr_state_2,
       curr_state_0,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       N_7556_i,
       N_7888,
       N_7876,
       cfrd_resp_o,
       cfgrant_o,
       cfwr_req_o,
       cfrd_req_o,
       fctrans_done_o,
       N_7540_i,
       N_7929,
       cfburst_len_rd_o_1_sn_N_2,
       N_7931,
       N_7352_i,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       N_7920,
       fcbusreq_o,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       fmhwrite_d1,
       idle_trigger,
       mchready_i,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  [15:0] cfburst_len_rd_o;
input  [6:1] cfburst_len_wr_o;
input  [14:13] cfdst_addr_o_iv;
output [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
input  cfdst_addr_o_0_iv_0;
input  cfsrc_addr_o_27;
input  cfsrc_addr_o_11;
input  cfsrc_addr_o_12;
input  cfsrc_addr_o_10;
input  cfsrc_addr_o_0;
input  cfsrc_addr_o_14;
input  cfsrc_addr_o_1;
input  cfdst_addr_o_27;
input  cfdst_addr_o_10;
input  cfdst_addr_o_0;
input  cfdst_addr_o_2;
input  cfdst_addr_o_14;
input  cfdst_addr_o_1;
input  cfburst_len_wr_o_1_2_x_0;
input  resp_curr_state_5;
input  resp_curr_state_6;
input  resp_curr_state_0;
input  req_curr_state_0;
output curr_state_2;
output curr_state_0;
output syssvc_blk_0_AHBL_MASTER_HTRANS_0;
input  N_7556_i;
input  N_7888;
input  N_7876;
input  cfrd_resp_o;
input  cfgrant_o;
input  cfwr_req_o;
input  cfrd_req_o;
output fctrans_done_o;
input  N_7540_i;
input  N_7929;
input  cfburst_len_rd_o_1_sn_N_2;
input  N_7931;
input  N_7352_i;
input  syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  N_7920;
output fcbusreq_o;
output syssvc_blk_0_AHBL_MASTER_HWRITE;
output fmhwrite_d1;
output idle_trigger;
input  mchready_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire \curr_state_i_0[4] , \haddr_reg[25]_net_1 , VCC_net_1, 
        \haddr_reg_7[25]_net_1 , N_23, GND_net_1, 
        \haddr_reg[26]_net_1 , N_19_i, \haddr_reg[27]_net_1 , 
        \haddr_reg_7[27]_net_1 , \haddr_reg[28]_net_1 , N_102, 
        \haddr_reg[29]_net_1 , N_17_i, \haddr_reg[10]_net_1 , 
        \haddr_reg_7[10]_net_1 , \haddr_reg[11]_net_1 , 
        \haddr_reg_7[11]_net_1 , \haddr_reg[12]_net_1 , 
        \haddr_reg_7[12]_net_1 , \haddr_reg[13]_net_1 , 
        \haddr_reg_7[13]_net_1 , \haddr_reg[14]_net_1 , 
        \haddr_reg_7[14]_net_1 , \haddr_reg[15]_net_1 , 
        \haddr_reg_7[15]_net_1 , \haddr_reg[16]_net_1 , 
        \haddr_reg_7[16]_net_1 , \haddr_reg[17]_net_1 , 
        \haddr_reg_7[17]_net_1 , \haddr_reg[18]_net_1 , 
        \haddr_reg_7[18]_net_1 , \haddr_reg[19]_net_1 , 
        \haddr_reg_7[19]_net_1 , \haddr_reg[20]_net_1 , 
        \haddr_reg_7[20]_net_1 , \haddr_reg[21]_net_1 , 
        \haddr_reg_7[21]_net_1 , \haddr_reg[22]_net_1 , 
        \haddr_reg_7[22]_net_1 , \haddr_reg[23]_net_1 , 
        \haddr_reg_7[23]_net_1 , \haddr_reg[24]_net_1 , 
        \haddr_reg_7[24]_net_1 , \fmhaddr_o_8[27] , un1_fmhaddr_o20_i, 
        \fmhaddr_o_8[28] , N_103, N_112, \fmhaddr_o_8[31] , 
        \haddr_reg[0]_net_1 , \haddr_reg_7[0]_net_1 , 
        \haddr_reg[1]_net_1 , \haddr_reg_7[1]_net_1 , 
        \haddr_reg[2]_net_1 , \haddr_reg_7[2]_net_1 , 
        \haddr_reg[3]_net_1 , \haddr_reg_7[3]_net_1 , 
        \haddr_reg[4]_net_1 , \haddr_reg_7[4]_net_1 , 
        \haddr_reg[5]_net_1 , \haddr_reg_7[5]_net_1 , 
        \haddr_reg[6]_net_1 , \haddr_reg_7[6]_net_1 , 
        \haddr_reg[7]_net_1 , \haddr_reg_7[7]_net_1 , 
        \haddr_reg[8]_net_1 , \haddr_reg_7[8]_net_1 , 
        \haddr_reg[9]_net_1 , \haddr_reg_7[9]_net_1 , N_107, N_106, 
        N_105, \fmhaddr_o_8[15] , N_104, \fmhaddr_o_8[17] , 
        \fmhaddr_o_8[18] , \fmhaddr_o_8[19] , \fmhaddr_o_8[20] , 
        \fmhaddr_o_8[21] , \fmhaddr_o_8[22] , \fmhaddr_o_8[23] , 
        \fmhaddr_o_8[24] , \fmhaddr_o_8[25] , \fmhaddr_o_8[26] , N_110, 
        N_109, N_108, \fmhaddr_o_8[5] , \fmhaddr_o_8[6] , 
        \fmhaddr_o_8[7] , \fmhaddr_o_8[8] , \fmhaddr_o_8[9] , 
        \fmhaddr_o_8[10] , \fmhaddr_o_8[11] , fctrans_done_tmp_net_1, 
        fctrans_done_tmp5, fctrans_done_tmp_RNO_net_1, fmhaddr_o20_i_0, 
        cfrd_resp_d1_net_1, cfrd_resp_d1_23_net_1, cfrd_req_d1_net_1, 
        N_308_i, cfwr_req_d1_net_1, N_145_i, N_301_i, 
        \curr_state[1]_net_1 , N_296_i, \curr_state_ns[2] , 
        \curr_state[3]_net_1 , \curr_state_ns[3] , \curr_state_ns[4] , 
        \curr_state[5]_net_1 , \curr_state_ns[5] , 
        \curr_state[6]_net_1 , \curr_state_ns[6] , cfrd_req_d2_net_1, 
        cfrd_resp_d2_net_1, cfwr_req_d2_net_1, \word_count[0]_net_1 , 
        \word_count_lm[0] , N_27_i, \word_count[1]_net_1 , 
        \word_count_lm[1] , \word_count[2]_net_1 , \word_count_lm[2] , 
        \word_count[3]_net_1 , \word_count_lm[3] , 
        \word_count[4]_net_1 , \word_count_lm[4] , 
        \word_count[5]_net_1 , \word_count_lm[5] , 
        \word_count[6]_net_1 , \word_count_lm[6] , 
        \word_count[7]_net_1 , \word_count_lm[7] , 
        \word_count[8]_net_1 , \word_count_lm[8] , 
        \word_count[9]_net_1 , \word_count_lm[9] , 
        \word_count[10]_net_1 , \word_count_lm[10] , 
        \word_count[11]_net_1 , \word_count_lm[11] , 
        \word_count[12]_net_1 , \word_count_lm[12] , 
        \word_count[13]_net_1 , \word_count_lm[13] , 
        \word_count[14]_net_1 , \word_count_lm[14] , 
        \word_count[15]_net_1 , \word_count_lm[15] , 
        \word_count[16]_net_1 , \word_count_lm[16] , 
        \word_count[17]_net_1 , \word_count_lm[17] , 
        \word_count[18]_net_1 , \word_count_lm[18] , 
        \word_count[19]_net_1 , \word_count_lm[19] , 
        \word_count[20]_net_1 , \word_count_lm[20] , 
        \word_count[21]_net_1 , \word_count_lm[21] , 
        \word_count[22]_net_1 , \word_count_lm[22] , 
        \word_count[23]_net_1 , \word_count_lm[23] , 
        \word_count[24]_net_1 , \word_count_lm[24] , 
        \word_count[25]_net_1 , \word_count_lm[25] , 
        \word_count[26]_net_1 , \word_count_lm[26] , 
        \word_count[27]_net_1 , \word_count_lm[27] , 
        \word_count[28]_net_1 , \word_count_lm[28] , 
        \word_count[29]_net_1 , \word_count_lm[29] , 
        \word_count[30]_net_1 , \word_count_lm[30] , 
        \word_count[31]_net_1 , \word_count_lm[31] , 
        \word_count_cry[0]_net_1 , \word_count_cry_Y[0] , 
        \word_count_cry[1]_net_1 , \word_count_s[1] , 
        \word_count_cry[2]_net_1 , \word_count_s[2] , 
        \word_count_cry[3]_net_1 , \word_count_s[3] , 
        \word_count_cry[4]_net_1 , \word_count_s[4] , 
        \word_count_cry[5]_net_1 , \word_count_s[5] , 
        \word_count_cry[6]_net_1 , \word_count_s[6] , 
        \word_count_cry[7]_net_1 , \word_count_s[7] , 
        \word_count_cry[8]_net_1 , \word_count_s[8] , 
        \word_count_cry[9]_net_1 , \word_count_s[9] , 
        \word_count_cry[10]_net_1 , \word_count_s[10] , 
        \word_count_cry[11]_net_1 , \word_count_s[11] , 
        \word_count_cry[12]_net_1 , \word_count_s[12] , 
        \word_count_cry[13]_net_1 , \word_count_s[13] , 
        \word_count_cry[14]_net_1 , \word_count_s[14] , 
        \word_count_cry[15]_net_1 , \word_count_s[15] , 
        \word_count_cry[16]_net_1 , \word_count_s[16] , 
        \word_count_cry[17]_net_1 , \word_count_s[17] , 
        \word_count_cry[18]_net_1 , \word_count_s[18] , 
        \word_count_cry[19]_net_1 , \word_count_s[19] , 
        \word_count_cry[20]_net_1 , \word_count_s[20] , 
        \word_count_cry[21]_net_1 , \word_count_s[21] , 
        \word_count_cry[22]_net_1 , \word_count_s[22] , 
        \word_count_cry[23]_net_1 , \word_count_s[23] , 
        \word_count_cry[24]_net_1 , \word_count_s[24] , 
        \word_count_cry[25]_net_1 , \word_count_s[25] , 
        \word_count_cry[26]_net_1 , \word_count_s[26] , 
        \word_count_cry[27]_net_1 , \word_count_s[27] , 
        \word_count_cry[28]_net_1 , \word_count_s[28] , 
        \word_count_cry[29]_net_1 , \word_count_s[29] , 
        \word_count_s[31]_net_1 , \word_count_cry[30]_net_1 , 
        \word_count_s[30] , nextaddr_s_1_811_FCO, nextaddr_cry_1_net_1, 
        \nextaddr[1] , nextaddr_cry_2_net_1, \nextaddr[2] , 
        nextaddr_cry_3_net_1, \nextaddr[3] , nextaddr_cry_4_net_1, 
        \nextaddr[4] , nextaddr_cry_5_net_1, \nextaddr[5] , 
        nextaddr_cry_6_net_1, \nextaddr[6] , nextaddr_cry_7_net_1, 
        \nextaddr[7] , nextaddr_cry_8_net_1, \nextaddr[8] , 
        nextaddr_cry_9_net_1, \nextaddr[9] , nextaddr_cry_10_net_1, 
        \nextaddr[10] , nextaddr_cry_11_net_1, \nextaddr[11] , 
        nextaddr_cry_12_net_1, \nextaddr[12] , nextaddr_cry_13_net_1, 
        \nextaddr[13] , nextaddr_cry_14_net_1, \nextaddr[14] , 
        nextaddr_cry_15_net_1, \nextaddr[15] , nextaddr_cry_16_net_1, 
        \nextaddr[16] , nextaddr_cry_17_net_1, \nextaddr[17] , 
        nextaddr_cry_18_net_1, \nextaddr[18] , nextaddr_cry_19_net_1, 
        \nextaddr[19] , nextaddr_cry_20_net_1, \nextaddr[20] , 
        nextaddr_cry_21_net_1, \nextaddr[21] , nextaddr_cry_22_net_1, 
        \nextaddr[22] , nextaddr_cry_23_net_1, \nextaddr[23] , 
        nextaddr_cry_24_net_1, \nextaddr[24] , nextaddr_cry_25_net_1, 
        \nextaddr[25] , nextaddr_cry_26_net_1, \nextaddr[26] , 
        nextaddr_cry_27_net_1, \nextaddr[27] , \nextaddr[29] , 
        nextaddr_cry_28_net_1, \nextaddr[28] , 
        un1_cfcommaccess_active_1_1_net_1, 
        \word_count_lm_0_1_0[0]_net_1 , N_299, un1_cfwr_req_d1_i, 
        \haddr_reg_7_1_1[27]_net_1 , \fmhaddr_o_8_i_m2_1_1[29]_net_1 , 
        N_395, \fmhaddr_o_8_i_m2_1_1[13]_net_1 , 
        \haddr_reg_7_1_1[11]_net_1 , \fmhaddr_o_8_i_m2_1_1[14]_net_1 , 
        \word_count_lm_0_1_0[2]_net_1 , ahm_busreq_reg5_s1, 
        \word_count_lm_0_1_0[1]_net_1 , \haddr_reg_7_1_1[12]_net_1 , 
        \haddr_reg_7_1_1[10]_net_1 , \fmhaddr_o_8_i_m2_1_1[12]_net_1 , 
        \word_count_lm_0_1_0[3]_net_1 , 
        \fmhaddr_o_8_i_m2_1_1[2]_net_1 , \haddr_reg_7_1_1[0]_net_1 , 
        \fmhaddr_o_8_i_m2_1_1[4]_net_1 , \haddr_reg_7_1_1[2]_net_1 , 
        \haddr_reg_7_1_1[14]_net_1 , \word_count_lm_0_1_0[4]_net_1 , 
        \word_count_lm_0_1_0[5]_net_1 , \word_count_lm_0_1_0[6]_net_1 , 
        \fmhaddr_o_8_i_m2_1_1[3]_net_1 , 
        \fmhaddr_o_8_i_m2_1_1[16]_net_1 , \haddr_reg_7_1_1[1]_net_1 , 
        \haddr_reg_7_i_m2_1_1[28]_net_1 , 
        \fmhaddr_o_8_i_m2_1_1[30]_net_1 , N_304, word_m3_0_a2_1, 
        \curr_state_ns_i_a2_0_0[0]_net_1 , 
        fctrans_done_tmp5_0_a2_0_22_net_1, 
        fctrans_done_tmp5_0_a2_0_21_net_1, 
        fctrans_done_tmp5_0_a2_0_20_net_1, 
        fctrans_done_tmp5_0_a2_0_19_net_1, 
        fctrans_done_tmp5_0_a2_0_18_net_1, 
        fctrans_done_tmp5_0_a2_0_17_net_1, 
        fctrans_done_tmp5_0_a2_0_16_net_1, N_320, N_300, 
        fctrans_done_tmp5_0_a2_0_23_net_1, N_41, 
        fctrans_done_tmp5_0_a2_0_28_net_1, N_370, N_410, N_27_tz, 
        N_327, \curr_state_ns_i_a2_i_1[1]_net_1 ;
    
    CFG4 #( .INIT(16'h20FD) )  \fmhaddr_o_8_i_m2[12]  (.A(
        cfrd_resp_d2_net_1), .B(N_395), .C(cfsrc_addr_o_10), .D(
        \fmhaddr_o_8_i_m2_1_1[12]_net_1 ), .Y(N_107));
    CFG2 #( .INIT(4'h8) )  fctrans_done_o_inst_1 (.A(idle_trigger), .B(
        fctrans_done_tmp_net_1), .Y(fctrans_done_o));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[22]  (.A(VCC_net_1), 
        .B(\word_count[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[21]_net_1 ), .S(\word_count_s[22] ), .Y(), 
        .FCO(\word_count_cry[22]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \curr_state_ns_i_a2_i_a2[1]  (.A(
        \word_count[0]_net_1 ), .B(curr_state_2), .C(N_410), .Y(N_327));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[8]  (.A(
        \word_count_s[8] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), .D(
        cfburst_len_rd_o[8]), .Y(\word_count_lm[8] ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[31]  (.A(fcbusreq_o), .B(
        \word_count_s[31]_net_1 ), .Y(\word_count_lm[31] ));
    CFG3 #( .INIT(8'h47) )  \fmhaddr_o_8_i_m2[13]  (.A(
        cfdst_addr_o_iv[13]), .B(N_395), .C(
        \fmhaddr_o_8_i_m2_1_1[13]_net_1 ), .Y(N_106));
    SLE \curr_state[5]  (.D(\curr_state_ns[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\curr_state[5]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[25]  (.A(\nextaddr[25] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[25]_net_1 ));
    CFG3 #( .INIT(8'h35) )  \haddr_reg_7_1_1[2]  (.A(\nextaddr[2] ), 
        .B(N_7352_i), .C(cfrd_resp_d1_net_1), .Y(
        \haddr_reg_7_1_1[2]_net_1 ));
    CFG3 #( .INIT(8'hD1) )  \fmhaddr_o_8_i_m2[3]  (.A(
        \fmhaddr_o_8_i_m2_1_1[3]_net_1 ), .B(N_395), .C(cfdst_addr_o_1)
        , .Y(N_109));
    SLE \word_count[22]  (.D(\word_count_lm[22] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[22]_net_1 ));
    SLE \fmhaddr_o[11]  (.D(\fmhaddr_o_8[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[11]));
    CFG4 #( .INIT(16'hAA57) )  \word_count_lm_0[5]  (.A(
        ahm_busreq_reg5_s1), .B(N_7929), .C(cfburst_len_rd_o_1_sn_N_2), 
        .D(\word_count_lm_0_1_0[5]_net_1 ), .Y(\word_count_lm[5] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_8 (.A(VCC_net_1), .B(
        \haddr_reg[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_7_net_1), .S(\nextaddr[8] ), .Y(), .FCO(
        nextaddr_cry_8_net_1));
    CFG2 #( .INIT(4'hE) )  \curr_state_RNIPNMR[5]  (.A(curr_state_0), 
        .B(\curr_state[5]_net_1 ), .Y(fmhaddr_o20_i_0));
    CFG4 #( .INIT(16'hF7FF) )  un1_cfcommaccess_active_1 (.A(N_7876), 
        .B(N_7888), .C(un1_cfcommaccess_active_1_1_net_1), .D(N_7556_i)
        , .Y(N_370));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_19 (.A(
        \word_count[17]_net_1 ), .B(\word_count[16]_net_1 ), .C(
        \word_count[11]_net_1 ), .D(\word_count[10]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_19_net_1));
    SLE \word_count[5]  (.D(\word_count_lm[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[5]_net_1 ));
    SLE \haddr_reg[7]  (.D(\haddr_reg_7[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[7]_net_1 ));
    CFG2 #( .INIT(4'hE) )  un1_cfwr_req_d1 (.A(cfrd_req_d1_net_1), .B(
        cfwr_req_d1_net_1), .Y(un1_cfwr_req_d1_i));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[11]  (.A(N_395), .B(
        \nextaddr[9] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[11] ));
    SLE \word_count[24]  (.D(\word_count_lm[24] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[24]_net_1 ));
    SLE \fmhaddr_o[18]  (.D(\fmhaddr_o_8[18] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[18]));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[21]  (.A(\nextaddr[21] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[21]_net_1 ));
    SLE \word_count[7]  (.D(\word_count_lm[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[7]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[23]  (.A(fcbusreq_o), .B(
        \word_count_s[23] ), .Y(\word_count_lm[23] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[26]  (.A(VCC_net_1), 
        .B(\word_count[26]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[25]_net_1 ), .S(\word_count_s[26] ), .Y(), 
        .FCO(\word_count_cry[26]_net_1 ));
    CFG3 #( .INIT(8'h35) )  \haddr_reg_7_1_1[10]  (.A(\nextaddr[10] ), 
        .B(cfdst_addr_o_10), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7_1_1[10]_net_1 ));
    CFG4 #( .INIT(16'hAA57) )  \word_count_lm_0[4]  (.A(
        ahm_busreq_reg5_s1), .B(N_7931), .C(cfburst_len_rd_o_1_sn_N_2), 
        .D(\word_count_lm_0_1_0[4]_net_1 ), .Y(\word_count_lm[4] ));
    SLE \word_count[27]  (.D(\word_count_lm[27] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[27]_net_1 ));
    CFG3 #( .INIT(8'h72) )  \fmhaddr_o_8_i_m2_1_1[2]  (.A(
        cfrd_resp_d2_net_1), .B(cfsrc_addr_o_0), .C(
        \haddr_reg[0]_net_1 ), .Y(\fmhaddr_o_8_i_m2_1_1[2]_net_1 ));
    SLE \fmhaddr_o[24]  (.D(\fmhaddr_o_8[24] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[24]));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[18]  (.A(N_395), .B(
        \nextaddr[16] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[18] ));
    SLE cfrd_resp_d2 (.D(cfrd_resp_d1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfrd_resp_d2_net_1));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_7 (.A(VCC_net_1), .B(
        \haddr_reg[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_6_net_1), .S(\nextaddr[7] ), .Y(), .FCO(
        nextaddr_cry_7_net_1));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[9]  (.A(VCC_net_1), .B(
        \word_count[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[8]_net_1 ), .S(\word_count_s[9] ), .Y(), .FCO(
        \word_count_cry[9]_net_1 ));
    CFG3 #( .INIT(8'hE0) )  fcbusreq_o_0_0_0_a2_d (.A(cfrd_resp_o), .B(
        cfrd_req_o), .C(idle_trigger), .Y(ahm_busreq_reg5_s1));
    CFG3 #( .INIT(8'h1B) )  \haddr_reg_7_1_1[27]  (.A(
        cfrd_resp_d1_net_1), .B(\nextaddr[27] ), .C(cfsrc_addr_o_27), 
        .Y(\haddr_reg_7_1_1[27]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[23]  (.A(\nextaddr[23] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[23]_net_1 ));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[13]  (.A(
        \word_count_s[13] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[13]), .Y(\word_count_lm[13] ));
    SLE \haddr_reg[27]  (.D(\haddr_reg_7[27]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[27]_net_1 ));
    SLE \word_count[18]  (.D(\word_count_lm[18] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[18]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_22 (.A(
        \word_count[14]_net_1 ), .B(\word_count[9]_net_1 ), .C(
        \word_count[8]_net_1 ), .D(\word_count[3]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_22_net_1));
    SLE fctrans_done_tmp (.D(fctrans_done_tmp5), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(fctrans_done_tmp_RNO_net_1), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        fctrans_done_tmp_net_1));
    CFG4 #( .INIT(16'hAAA2) )  cfrd_resp_d2_RNI8LSO6 (.A(
        fmhaddr_o20_i_0), .B(N_299), .C(cfrd_resp_d2_net_1), .D(N_395), 
        .Y(un1_fmhaddr_o20_i));
    SLE cfrd_req_d1 (.D(\curr_state_i_0[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_308_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfrd_req_d1_net_1));
    CFG4 #( .INIT(16'h0100) )  fctrans_done_tmp5_0_a2_0_23 (.A(
        \word_count[21]_net_1 ), .B(\word_count[20]_net_1 ), .C(
        \word_count[15]_net_1 ), .D(fctrans_done_tmp5_0_a2_0_16_net_1), 
        .Y(fctrans_done_tmp5_0_a2_0_23_net_1));
    CFG4 #( .INIT(16'hEC0A) )  \curr_state_ns_0_iv_0[3]  (.A(
        \curr_state[3]_net_1 ), .B(curr_state_0), .C(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .D(mchready_i), .Y(
        \curr_state_ns[3] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_28 (.A(VCC_net_1), .B(
        \haddr_reg[28]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_27_net_1), .S(\nextaddr[28] ), .Y(), .FCO(
        nextaddr_cry_28_net_1));
    CFG3 #( .INIT(8'h35) )  \fmhaddr_o_8_i_m2_1_1[30]  (.A(
        \nextaddr[28] ), .B(N_7540_i), .C(cfrd_resp_d2_net_1), .Y(
        \fmhaddr_o_8_i_m2_1_1[30]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[7]  (.A(N_395), .B(
        \nextaddr[5] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[7] ));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[16]  (.A(
        cfrd_resp_d2_net_1), .B(\nextaddr[14] ), .C(cfsrc_addr_o_14), 
        .Y(\fmhaddr_o_8_i_m2_1_1[16]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[6]  (.A(N_395), .B(
        \nextaddr[4] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[6] ));
    SLE \haddr_reg[19]  (.D(\haddr_reg_7[19]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[19]_net_1 ));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[9]  (.A(
        \word_count_s[9] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), .D(
        cfburst_len_rd_o[9]), .Y(\word_count_lm[9] ));
    SLE \word_count[2]  (.D(\word_count_lm[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_5 (.A(VCC_net_1), .B(
        \haddr_reg[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_4_net_1), .S(\nextaddr[5] ), .Y(), .FCO(
        nextaddr_cry_5_net_1));
    CFG4 #( .INIT(16'h4F0B) )  \haddr_reg_7[14]  (.A(
        cfrd_resp_d1_net_1), .B(un1_cfwr_req_d1_i), .C(
        \haddr_reg_7_1_1[14]_net_1 ), .D(cfdst_addr_o_14), .Y(
        \haddr_reg_7[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_18 (.A(VCC_net_1), .B(
        \haddr_reg[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_17_net_1), .S(\nextaddr[18] ), .Y(), .FCO(
        nextaddr_cry_18_net_1));
    SLE \fmhaddr_o[22]  (.D(\fmhaddr_o_8[22] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[22]));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[28]  (.A(VCC_net_1), 
        .B(\word_count[28]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[27]_net_1 ), .S(\word_count_s[28] ), .Y(), 
        .FCO(\word_count_cry[28]_net_1 ));
    CFG4 #( .INIT(16'h2F0D) )  \haddr_reg_7[27]  (.A(un1_cfwr_req_d1_i)
        , .B(cfrd_resp_d1_net_1), .C(\haddr_reg_7_1_1[27]_net_1 ), .D(
        cfdst_addr_o_27), .Y(\haddr_reg_7[27]_net_1 ));
    CFG3 #( .INIT(8'h35) )  \fmhaddr_o_8_i_m2_1_1[4]  (.A(
        \nextaddr[2] ), .B(N_7352_i), .C(cfrd_resp_d2_net_1), .Y(
        \fmhaddr_o_8_i_m2_1_1[4]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[11]  (.A(VCC_net_1), 
        .B(\word_count[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[10]_net_1 ), .S(\word_count_s[11] ), .Y(), 
        .FCO(\word_count_cry[11]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[9]  (.A(N_395), .B(
        \nextaddr[7] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[9] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[24]  (.A(VCC_net_1), 
        .B(\word_count[24]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[23]_net_1 ), .S(\word_count_s[24] ), .Y(), 
        .FCO(\word_count_cry[24]_net_1 ));
    SLE \haddr_reg[16]  (.D(\haddr_reg_7[16]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[16]_net_1 ));
    SLE \haddr_reg[13]  (.D(\haddr_reg_7[13]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[13]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[21]  (.A(N_395), .B(
        \nextaddr[19] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[21] ));
    GND GND (.Y(GND_net_1));
    SLE \word_count[29]  (.D(\word_count_lm[29] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[29]_net_1 ));
    CFG3 #( .INIT(8'hD1) )  \fmhaddr_o_8_i_m2[29]  (.A(
        \fmhaddr_o_8_i_m2_1_1[29]_net_1 ), .B(N_395), .C(
        cfdst_addr_o_27), .Y(N_103));
    SLE fmhwrite_d1_inst_1 (.D(syssvc_blk_0_AHBL_MASTER_HWRITE), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(fmhwrite_d1));
    SLE \haddr_reg[1]  (.D(\haddr_reg_7[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[1]_net_1 ));
    CFG2 #( .INIT(4'hD) )  g0 (.A(mchready_i), .B(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(N_299));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[19]  (.A(N_395), .B(
        \nextaddr[17] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[19] ));
    CFG1 #( .INIT(2'h1) )  \curr_state_RNIDCRD[4]  (.A(curr_state_2), 
        .Y(\curr_state_i_0[4] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[7]  (.A(VCC_net_1), .B(
        \word_count[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[6]_net_1 ), .S(\word_count_s[7] ), .Y(), .FCO(
        \word_count_cry[7]_net_1 ));
    SLE \word_count[12]  (.D(\word_count_lm[12] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[12]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[28]  (.A(N_395), .B(
        \nextaddr[26] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[28] ));
    CFG4 #( .INIT(16'h04BF) )  \haddr_reg_7[12]  (.A(
        cfrd_resp_d1_net_1), .B(un1_cfwr_req_d1_i), .C(
        cfdst_addr_o_iv[14]), .D(\haddr_reg_7_1_1[12]_net_1 ), .Y(
        \haddr_reg_7[12]_net_1 ));
    CFG4 #( .INIT(16'hFF73) )  fctrans_done_tmp5_0_a2_0_RNI9MLN6 (.A(
        \word_count[0]_net_1 ), .B(fmhaddr_o20_i_0), .C(N_410), .D(
        N_299), .Y(N_27_tz));
    SLE \haddr_reg[12]  (.D(\haddr_reg_7[12]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[12]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[27]  (.A(fcbusreq_o), .B(
        \word_count_s[27] ), .Y(\word_count_lm[27] ));
    SLE \word_count[14]  (.D(\word_count_lm[14] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[14]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[5]  (.A(N_395), .B(
        \nextaddr[3] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[5] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[23]  (.A(VCC_net_1), 
        .B(\word_count[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[22]_net_1 ), .S(\word_count_s[23] ), .Y(), 
        .FCO(\word_count_cry[23]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[15]  (.A(VCC_net_1), 
        .B(\word_count[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[14]_net_1 ), .S(\word_count_s[15] ), .Y(), 
        .FCO(\word_count_cry[15]_net_1 ));
    SLE \word_count[17]  (.D(\word_count_lm[17] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[17]_net_1 ));
    SLE \word_count[20]  (.D(\word_count_lm[20] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[20]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[22]  (.A(fcbusreq_o), .B(
        \word_count_s[22] ), .Y(\word_count_lm[22] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[4]  (.A(VCC_net_1), .B(
        \word_count[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[3]_net_1 ), .S(\word_count_s[4] ), .Y(), .FCO(
        \word_count_cry[4]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[29]  (.A(
        cfrd_resp_d2_net_1), .B(\nextaddr[27] ), .C(cfsrc_addr_o_27), 
        .Y(\fmhaddr_o_8_i_m2_1_1[29]_net_1 ));
    CFG4 #( .INIT(16'hC5D5) )  \word_count_lm_0[1]  (.A(
        \word_count_lm_0_1_0[1]_net_1 ), .B(cfburst_len_rd_o[1]), .C(
        ahm_busreq_reg5_s1), .D(fcbusreq_o), .Y(\word_count_lm[1] ));
    SLE \word_count[31]  (.D(\word_count_lm[31] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[31]_net_1 ));
    SLE \word_count[9]  (.D(\word_count_lm[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[9]_net_1 ));
    SLE \fmhaddr_o[30]  (.D(N_112), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[30]));
    SLE \fmhaddr_o[19]  (.D(\fmhaddr_o_8[19] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[19]));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[17]  (.A(fcbusreq_o), .B(
        \word_count_s[17] ), .Y(\word_count_lm[17] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_22 (.A(VCC_net_1), .B(
        \haddr_reg[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_21_net_1), .S(\nextaddr[22] ), .Y(), .FCO(
        nextaddr_cry_22_net_1));
    CFG4 #( .INIT(16'h2165) )  \word_count_lm_0_1_0[5]  (.A(
        ahm_busreq_reg5_s1), .B(fcbusreq_o), .C(\word_count_s[5] ), .D(
        cfburst_len_wr_o[5]), .Y(\word_count_lm_0_1_0[5]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[17]  (.A(VCC_net_1), 
        .B(\word_count[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[16]_net_1 ), .S(\word_count_s[17] ), .Y(), 
        .FCO(\word_count_cry[17]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[18]  (.A(\nextaddr[18] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[18]_net_1 ));
    SLE \haddr_reg[5]  (.D(\haddr_reg_7[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[5]_net_1 ));
    CFG3 #( .INIT(8'h10) )  \curr_state_RNIQ5EK[0]  (.A(cfrd_req_o), 
        .B(cfwr_req_o), .C(idle_trigger), .Y(word_m3_0_a2_1));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_12 (.A(VCC_net_1), .B(
        \haddr_reg[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_11_net_1), .S(\nextaddr[12] ), .Y(), .FCO(
        nextaddr_cry_12_net_1));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[12]  (.A(
        \word_count_s[12] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[12]), .Y(\word_count_lm[12] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[5]  (.A(VCC_net_1), .B(
        \word_count[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[4]_net_1 ), .S(\word_count_s[5] ), .Y(), .FCO(
        \word_count_cry[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_s_29 (.A(VCC_net_1), .B(
        \haddr_reg[29]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_28_net_1), .S(\nextaddr[29] ), .Y(), .FCO());
    SLE cfrd_resp_d1 (.D(cfrd_resp_d1_23_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfrd_resp_d1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_s_1_811 (.A(VCC_net_1), .B(
        \haddr_reg[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(nextaddr_s_1_811_FCO));
    CFG3 #( .INIT(8'h27) )  \fmhaddr_o_8_i_m2[14]  (.A(N_395), .B(
        cfdst_addr_o_iv[14]), .C(\fmhaddr_o_8_i_m2_1_1[14]_net_1 ), .Y(
        N_105));
    VCC VCC (.Y(VCC_net_1));
    SLE \fmhaddr_o[16]  (.D(N_104), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[16]));
    SLE \fmhaddr_o[10]  (.D(\fmhaddr_o_8[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[10]));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[8]  (.A(VCC_net_1), .B(
        \word_count[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[7]_net_1 ), .S(\word_count_s[8] ), .Y(), .FCO(
        \word_count_cry[8]_net_1 ));
    SLE \curr_state[1]  (.D(N_296_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \curr_state[1]_net_1 ));
    CFG3 #( .INIT(8'h35) )  \haddr_reg_7_1_1[1]  (.A(\nextaddr[1] ), 
        .B(cfdst_addr_o_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7_1_1[1]_net_1 ));
    CFG3 #( .INIT(8'hC8) )  \curr_state_ns_i_a2_0_0[0]  (.A(
        \curr_state[3]_net_1 ), .B(syssvc_blk_0_AHBL_MASTER_HRESP_0), 
        .C(\curr_state[6]_net_1 ), .Y(
        \curr_state_ns_i_a2_0_0[0]_net_1 ));
    CFG4 #( .INIT(16'h3230) )  fmhwrite_o_0_f0_0_a2 (.A(idle_trigger), 
        .B(ahm_busreq_reg5_s1), .C(fmhwrite_d1), .D(cfwr_req_o), .Y(
        syssvc_blk_0_AHBL_MASTER_HWRITE));
    SLE \fmhaddr_o[21]  (.D(\fmhaddr_o_8[21] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[21]));
    SLE \haddr_reg[14]  (.D(\haddr_reg_7[14]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[14]_net_1 ));
    SLE \haddr_reg[29]  (.D(N_17_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_23), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \haddr_reg[29]_net_1 ));
    SLE \word_count[8]  (.D(\word_count_lm[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[8]_net_1 ));
    CFG3 #( .INIT(8'h47) )  \fmhaddr_o_8_i_m2[30]  (.A(
        cfdst_addr_o_0_iv_0), .B(N_395), .C(
        \fmhaddr_o_8_i_m2_1_1[30]_net_1 ), .Y(N_112));
    CFG3 #( .INIT(8'hD1) )  \haddr_reg_7[10]  (.A(
        \haddr_reg_7_1_1[10]_net_1 ), .B(cfrd_resp_d1_net_1), .C(
        cfsrc_addr_o_10), .Y(\haddr_reg_7[10]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[10]  (.A(VCC_net_1), 
        .B(\word_count[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[9]_net_1 ), .S(\word_count_s[10] ), .Y(), .FCO(
        \word_count_cry[10]_net_1 ));
    SLE \haddr_reg[11]  (.D(\haddr_reg_7[11]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[11]_net_1 ));
    SLE \word_count[19]  (.D(\word_count_lm[19] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[19]_net_1 ));
    SLE \fmhaddr_o[28]  (.D(\fmhaddr_o_8[28] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[28]));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_25 (.A(VCC_net_1), .B(
        \haddr_reg[25]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_24_net_1), .S(\nextaddr[25] ), .Y(), .FCO(
        nextaddr_cry_25_net_1));
    SLE \word_count[23]  (.D(\word_count_lm[23] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[23]_net_1 ));
    SLE \haddr_reg[26]  (.D(N_19_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_23), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \haddr_reg[26]_net_1 ));
    SLE \haddr_reg[23]  (.D(\haddr_reg_7[23]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[23]_net_1 ));
    SLE \fmhaddr_o[13]  (.D(N_106), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[13]));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[20]  (.A(fcbusreq_o), .B(
        \word_count_s[20] ), .Y(\word_count_lm[20] ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[4]  (.A(\nextaddr[4] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[4]_net_1 ));
    SLE \fmhaddr_o[17]  (.D(\fmhaddr_o_8[17] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[17]));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_15 (.A(VCC_net_1), .B(
        \haddr_reg[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_14_net_1), .S(\nextaddr[15] ), .Y(), .FCO(
        nextaddr_cry_15_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[23]  (.A(N_395), .B(
        \nextaddr[21] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[23] ));
    CFG4 #( .INIT(16'hF0FE) )  \curr_state_ns_1_iv_0[4]  (.A(
        \curr_state[6]_net_1 ), .B(\curr_state[3]_net_1 ), .C(N_304), 
        .D(N_299), .Y(\curr_state_ns[4] ));
    CFG2 #( .INIT(4'hE) )  fmhaddr_o_1_sqmuxa_i_o2_0 (.A(
        cfrd_req_d2_net_1), .B(cfwr_req_d2_net_1), .Y(N_395));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[3]  (.A(
        cfrd_resp_d2_net_1), .B(\nextaddr[1] ), .C(cfsrc_addr_o_1), .Y(
        \fmhaddr_o_8_i_m2_1_1[3]_net_1 ));
    SLE \fmhaddr_o[9]  (.D(\fmhaddr_o_8[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[9]));
    CFG4 #( .INIT(16'h2165) )  \word_count_lm_0_1_0[4]  (.A(
        ahm_busreq_reg5_s1), .B(fcbusreq_o), .C(\word_count_s[4] ), .D(
        cfburst_len_wr_o[4]), .Y(\word_count_lm_0_1_0[4]_net_1 ));
    CFG4 #( .INIT(16'hC5D5) )  \word_count_lm_0[3]  (.A(
        \word_count_lm_0_1_0[3]_net_1 ), .B(cfburst_len_rd_o[3]), .C(
        ahm_busreq_reg5_s1), .D(fcbusreq_o), .Y(\word_count_lm[3] ));
    CFG4 #( .INIT(16'hDF8F) )  \curr_state_RNO[0]  (.A(mchready_i), .B(
        N_327), .C(N_41), .D(\curr_state_ns_i_a2_0_0[0]_net_1 ), .Y(
        N_301_i));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[29]  (.A(VCC_net_1), 
        .B(\word_count[29]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[28]_net_1 ), .S(\word_count_s[29] ), .Y(), 
        .FCO(\word_count_cry[29]_net_1 ));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[10]  (.A(
        \word_count_s[10] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[10]), .Y(\word_count_lm[10] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_19 (.A(VCC_net_1), .B(
        \haddr_reg[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_18_net_1), .S(\nextaddr[19] ), .Y(), .FCO(
        nextaddr_cry_19_net_1));
    SLE \haddr_reg[22]  (.D(\haddr_reg_7[22]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[22]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \haddr_reg_7_1_1[11]  (.A(
        cfrd_resp_d1_net_1), .B(\nextaddr[11] ), .C(cfsrc_addr_o_11), 
        .Y(\haddr_reg_7_1_1[11]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[8]  (.A(\nextaddr[8] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[8]_net_1 ));
    CFG4 #( .INIT(16'hFFF8) )  fctrans_done_tmp_RNO (.A(idle_trigger), 
        .B(cfwr_req_o), .C(ahm_busreq_reg5_s1), .D(fctrans_done_tmp5), 
        .Y(fctrans_done_tmp_RNO_net_1));
    SLE \word_count[10]  (.D(\word_count_lm[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[10]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[3]  (.A(VCC_net_1), .B(
        \word_count[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[2]_net_1 ), .S(\word_count_s[3] ), .Y(), .FCO(
        \word_count_cry[3]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  fctrans_done_tmp5_0_a2_0 (.A(
        fctrans_done_tmp5_0_a2_0_18_net_1), .B(
        fctrans_done_tmp5_0_a2_0_17_net_1), .C(
        fctrans_done_tmp5_0_a2_0_28_net_1), .D(
        fctrans_done_tmp5_0_a2_0_23_net_1), .Y(N_410));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_21 (.A(VCC_net_1), .B(
        \haddr_reg[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_20_net_1), .S(\nextaddr[21] ), .Y(), .FCO(
        nextaddr_cry_21_net_1));
    CFG3 #( .INIT(8'h2E) )  \haddr_reg_7_1_1[0]  (.A(
        \haddr_reg[0]_net_1 ), .B(un1_cfwr_req_d1_i), .C(
        cfdst_addr_o_0), .Y(\haddr_reg_7_1_1[0]_net_1 ));
    CFG4 #( .INIT(16'hFE00) )  fcbusreq_o_0_0_0_a2 (.A(cfwr_req_o), .B(
        cfrd_req_o), .C(cfrd_resp_o), .D(idle_trigger), .Y(fcbusreq_o));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[19]  (.A(\nextaddr[19] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[19]_net_1 ));
    SLE \word_count[26]  (.D(\word_count_lm[26] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[26]_net_1 ));
    CFG3 #( .INIT(8'hD1) )  \haddr_reg_7[1]  (.A(
        \haddr_reg_7_1_1[1]_net_1 ), .B(cfrd_resp_d1_net_1), .C(
        cfsrc_addr_o_1), .Y(\haddr_reg_7[1]_net_1 ));
    SLE \haddr_reg[15]  (.D(\haddr_reg_7[15]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[15]_net_1 ));
    SLE \haddr_reg[10]  (.D(\haddr_reg_7[10]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_11 (.A(VCC_net_1), .B(
        \haddr_reg[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_10_net_1), .S(\nextaddr[11] ), .Y(), .FCO(
        nextaddr_cry_11_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[10]  (.A(N_395), .B(
        \nextaddr[8] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[10] ));
    SLE \fmhaddr_o[15]  (.D(\fmhaddr_o_8[15] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[15]));
    SLE \curr_state[4]  (.D(\curr_state_ns[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(curr_state_2));
    SLE cfwr_req_d1 (.D(\curr_state_i_0[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_145_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfwr_req_d1_net_1));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[3]  (.A(\nextaddr[3] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[3]_net_1 ));
    CFG4 #( .INIT(16'h50DC) )  \curr_state_ns_0_iv_0[5]  (.A(
        mchready_i), .B(N_320), .C(\curr_state[5]_net_1 ), .D(
        fmhwrite_d1), .Y(\curr_state_ns[5] ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[24]  (.A(\nextaddr[24] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[24]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[12]  (.A(VCC_net_1), 
        .B(\word_count[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[11]_net_1 ), .S(\word_count_s[12] ), .Y(), 
        .FCO(\word_count_cry[12]_net_1 ));
    CFG2 #( .INIT(4'hE) )  cfrd_req_d1_RNO (.A(curr_state_2), .B(
        cfrd_req_o), .Y(N_308_i));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[30]  (.A(fcbusreq_o), .B(
        \word_count_s[30] ), .Y(\word_count_lm[30] ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[9]  (.A(\nextaddr[9] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[9]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[6]  (.A(\nextaddr[6] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[6]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[2]  (.A(VCC_net_1), .B(
        \word_count[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[1]_net_1 ), .S(\word_count_s[2] ), .Y(), .FCO(
        \word_count_cry[2]_net_1 ));
    SLE \haddr_reg[18]  (.D(\haddr_reg_7[18]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[18]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_16 (.A(
        \word_count[25]_net_1 ), .B(\word_count[24]_net_1 ), .C(
        \word_count[19]_net_1 ), .D(\word_count[18]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_16_net_1));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_2 (.A(VCC_net_1), .B(
        \haddr_reg[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_1_net_1), .S(\nextaddr[2] ), .Y(), .FCO(
        nextaddr_cry_2_net_1));
    CFG3 #( .INIT(8'hF7) )  haddr_reg_1_sqmuxa_i_0_RNO (.A(mchready_i), 
        .B(fmhaddr_o20_i_0), .C(syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(
        N_300));
    CFG4 #( .INIT(16'hFEFF) )  \curr_state_ns_i_o3[0]  (.A(cfwr_req_o), 
        .B(cfrd_req_o), .C(cfrd_resp_o), .D(idle_trigger), .Y(N_41));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[13]  (.A(
        cfrd_resp_d2_net_1), .B(\nextaddr[11] ), .C(cfsrc_addr_o_11), 
        .Y(\fmhaddr_o_8_i_m2_1_1[13]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[26]  (.A(fcbusreq_o), .B(
        \word_count_s[26] ), .Y(\word_count_lm[26] ));
    SLE \haddr_reg[24]  (.D(\haddr_reg_7[24]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[24]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_1 (.A(VCC_net_1), .B(
        \haddr_reg[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_s_1_811_FCO), .S(\nextaddr[1] ), .Y(), .FCO(
        nextaddr_cry_1_net_1));
    SLE \fmhaddr_o[5]  (.D(\fmhaddr_o_8[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[5]));
    CFG4 #( .INIT(16'h0100) )  \curr_state_RNO[1]  (.A(
        \curr_state_ns_i_a2_i_1[1]_net_1 ), .B(N_304), .C(N_320), .D(
        N_41), .Y(N_296_i));
    SLE \word_count[13]  (.D(\word_count_lm[13] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[13]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[7]  (.A(\nextaddr[7] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[7]_net_1 ));
    SLE \haddr_reg[21]  (.D(\haddr_reg_7[21]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[21]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[22]  (.A(\nextaddr[22] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[22]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[14]  (.A(
        cfrd_resp_d2_net_1), .B(\nextaddr[12] ), .C(cfsrc_addr_o_12), 
        .Y(\fmhaddr_o_8_i_m2_1_1[14]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[16]  (.A(VCC_net_1), 
        .B(\word_count[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[15]_net_1 ), .S(\word_count_s[16] ), .Y(), 
        .FCO(\word_count_cry[16]_net_1 ));
    SLE \fmhaddr_o[4]  (.D(N_108), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[4]));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[0]  (.A(VCC_net_1), .B(
        \word_count[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(\word_count_cry_Y[0] ), .FCO(
        \word_count_cry[0]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_27 (.A(VCC_net_1), .B(
        \haddr_reg[27]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_26_net_1), .S(\nextaddr[27] ), .Y(), .FCO(
        nextaddr_cry_27_net_1));
    CFG4 #( .INIT(16'h8000) )  fctrans_done_tmp5_0_a2_0_28 (.A(
        fctrans_done_tmp5_0_a2_0_22_net_1), .B(
        fctrans_done_tmp5_0_a2_0_21_net_1), .C(
        fctrans_done_tmp5_0_a2_0_20_net_1), .D(
        fctrans_done_tmp5_0_a2_0_19_net_1), .Y(
        fctrans_done_tmp5_0_a2_0_28_net_1));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_3 (.A(VCC_net_1), .B(
        \haddr_reg[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_2_net_1), .S(\nextaddr[3] ), .Y(), .FCO(
        nextaddr_cry_3_net_1));
    SLE \fmhaddr_o[29]  (.D(N_103), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[29]));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[16]  (.A(fcbusreq_o), .B(
        \word_count_s[16] ), .Y(\word_count_lm[16] ));
    CFG4 #( .INIT(16'hE0CA) )  \curr_state_ns_0_0[6]  (.A(
        \curr_state[6]_net_1 ), .B(\curr_state[5]_net_1 ), .C(
        mchready_i), .D(syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(
        \curr_state_ns[6] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_17 (.A(VCC_net_1), .B(
        \haddr_reg[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_16_net_1), .S(\nextaddr[17] ), .Y(), .FCO(
        nextaddr_cry_17_net_1));
    SLE \fmhtrans_int[1]  (.D(fmhaddr_o20_i_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(mchready_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0));
    SLE \fmhaddr_o[2]  (.D(N_110), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[2]));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[20]  (.A(N_395), .B(
        \nextaddr[18] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[20] ));
    SLE \fmhaddr_o[7]  (.D(\fmhaddr_o_8[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[7]));
    CFG4 #( .INIT(16'hEFEE) )  haddr_reg_1_sqmuxa_i_0 (.A(
        un1_cfwr_req_d1_i), .B(cfrd_resp_d1_net_1), .C(N_300), .D(
        N_370), .Y(N_23));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[30]  (.A(VCC_net_1), 
        .B(\word_count[30]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[29]_net_1 ), .S(\word_count_s[30] ), .Y(), 
        .FCO(\word_count_cry[30]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[15]  (.A(\nextaddr[15] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[15]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[24]  (.A(N_395), .B(
        \nextaddr[22] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[24] ));
    SLE \fmhaddr_o[8]  (.D(\fmhaddr_o_8[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[8]));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[21]  (.A(VCC_net_1), 
        .B(\word_count[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[20]_net_1 ), .S(\word_count_s[21] ), .Y(), 
        .FCO(\word_count_cry[21]_net_1 ));
    SLE \haddr_reg[3]  (.D(\haddr_reg_7[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[3]_net_1 ));
    CFG3 #( .INIT(8'hD1) )  \fmhaddr_o_8_i_m2[2]  (.A(
        \fmhaddr_o_8_i_m2_1_1[2]_net_1 ), .B(N_395), .C(cfdst_addr_o_0)
        , .Y(N_110));
    SLE \fmhaddr_o[26]  (.D(\fmhaddr_o_8[26] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[26]));
    SLE \fmhaddr_o[20]  (.D(\fmhaddr_o_8[20] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[20]));
    CFG2 #( .INIT(4'h4) )  \curr_state_ns_1_iv_0_a2_0[4]  (.A(
        mchready_i), .B(curr_state_2), .Y(N_304));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[7]  (.A(
        \word_count_s[7] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), .D(
        cfburst_len_rd_o[7]), .Y(\word_count_lm[7] ));
    CFG3 #( .INIT(8'hB1) )  \fmhaddr_o_8_i_m2[16]  (.A(N_395), .B(
        \fmhaddr_o_8_i_m2_1_1[16]_net_1 ), .C(cfdst_addr_o_14), .Y(
        N_104));
    CFG3 #( .INIT(8'h35) )  \word_count_lm_0_1_0[1]  (.A(
        \word_count_s[1] ), .B(cfburst_len_wr_o[1]), .C(fcbusreq_o), 
        .Y(\word_count_lm_0_1_0[1]_net_1 ));
    SLE \word_count[16]  (.D(\word_count_lm[16] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_23 (.A(VCC_net_1), .B(
        \haddr_reg[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_22_net_1), .S(\nextaddr[23] ), .Y(), .FCO(
        nextaddr_cry_23_net_1));
    CFG4 #( .INIT(16'h0353) )  \word_count_lm_0_1_0[0]  (.A(
        cfburst_len_wr_o_1_2_x_0), .B(\word_count_cry_Y[0] ), .C(
        fcbusreq_o), .D(N_7920), .Y(\word_count_lm_0_1_0[0]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[24]  (.A(fcbusreq_o), .B(
        \word_count_s[24] ), .Y(\word_count_lm[24] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_6 (.A(VCC_net_1), .B(
        \haddr_reg[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_5_net_1), .S(\nextaddr[6] ), .Y(), .FCO(
        nextaddr_cry_6_net_1));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_RNO[29]  (.A(\nextaddr[29] ), 
        .B(cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(N_17_i));
    SLE \haddr_reg[25]  (.D(\haddr_reg_7[25]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[25]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[18]  (.A(VCC_net_1), 
        .B(\word_count[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[17]_net_1 ), .S(\word_count_s[18] ), .Y(), 
        .FCO(\word_count_cry[18]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_13 (.A(VCC_net_1), .B(
        \haddr_reg[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_12_net_1), .S(\nextaddr[13] ), .Y(), .FCO(
        nextaddr_cry_13_net_1));
    CFG4 #( .INIT(16'h02DF) )  \haddr_reg_7[11]  (.A(un1_cfwr_req_d1_i)
        , .B(cfrd_resp_d1_net_1), .C(cfdst_addr_o_iv[13]), .D(
        \haddr_reg_7_1_1[11]_net_1 ), .Y(\haddr_reg_7[11]_net_1 ));
    SLE \haddr_reg[20]  (.D(\haddr_reg_7[20]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[20]_net_1 ));
    SLE \word_count[21]  (.D(\word_count_lm[21] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[21]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[14]  (.A(VCC_net_1), 
        .B(\word_count[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[13]_net_1 ), .S(\word_count_s[14] ), .Y(), 
        .FCO(\word_count_cry[14]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[15]  (.A(N_395), .B(
        \nextaddr[13] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[15] ));
    SLE \word_count[6]  (.D(\word_count_lm[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[6]_net_1 ));
    SLE \fmhaddr_o[23]  (.D(\fmhaddr_o_8[23] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[23]));
    SLE \fmhaddr_o[27]  (.D(\fmhaddr_o_8[27] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[27]));
    SLE \word_count[25]  (.D(\word_count_lm[25] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[25]_net_1 ));
    SLE \haddr_reg[2]  (.D(\haddr_reg_7[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[2]_net_1 ));
    CFG4 #( .INIT(16'hC5D5) )  \word_count_lm_0[6]  (.A(
        \word_count_lm_0_1_0[6]_net_1 ), .B(cfburst_len_rd_o[6]), .C(
        ahm_busreq_reg5_s1), .D(fcbusreq_o), .Y(\word_count_lm[6] ));
    CFG3 #( .INIT(8'hD1) )  \haddr_reg_7[0]  (.A(
        \haddr_reg_7_1_1[0]_net_1 ), .B(cfrd_resp_d1_net_1), .C(
        cfsrc_addr_o_0), .Y(\haddr_reg_7[0]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[8]  (.A(N_395), .B(
        \nextaddr[6] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[8] ));
    SLE \fmhaddr_o[6]  (.D(\fmhaddr_o_8[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[6]));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[14]  (.A(
        \word_count_s[14] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[14]), .Y(\word_count_lm[14] ));
    SLE \haddr_reg[8]  (.D(\haddr_reg_7[8]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[8]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[25]  (.A(VCC_net_1), 
        .B(\word_count[25]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[24]_net_1 ), .S(\word_count_s[25] ), .Y(), 
        .FCO(\word_count_cry[25]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[20]  (.A(\nextaddr[20] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[20]_net_1 ));
    CFG3 #( .INIT(8'h35) )  \word_count_lm_0_1_0[2]  (.A(
        \word_count_s[2] ), .B(cfburst_len_wr_o[2]), .C(fcbusreq_o), 
        .Y(\word_count_lm_0_1_0[2]_net_1 ));
    SLE \curr_state[6]  (.D(\curr_state_ns[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\curr_state[6]_net_1 ));
    SLE \haddr_reg[28]  (.D(N_102), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(N_23), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \haddr_reg[28]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[13]  (.A(\nextaddr[13] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[13]_net_1 ));
    CFG4 #( .INIT(16'h4F0B) )  \haddr_reg_7[2]  (.A(cfrd_resp_d1_net_1)
        , .B(un1_cfwr_req_d1_i), .C(\haddr_reg_7_1_1[2]_net_1 ), .D(
        cfdst_addr_o_2), .Y(\haddr_reg_7[2]_net_1 ));
    SLE \fmhaddr_o[3]  (.D(N_109), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[3]));
    SLE \fmhaddr_o[14]  (.D(N_105), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[14]));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[25]  (.A(fcbusreq_o), .B(
        \word_count_s[25] ), .Y(\word_count_lm[25] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[27]  (.A(VCC_net_1), 
        .B(\word_count[27]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[26]_net_1 ), .S(\word_count_s[27] ), .Y(), 
        .FCO(\word_count_cry[27]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  fctrans_done_tmp5_0_a2 (.A(
        \word_count[0]_net_1 ), .B(fmhaddr_o20_i_0), .C(N_410), .D(
        N_299), .Y(fctrans_done_tmp5));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[13]  (.A(VCC_net_1), 
        .B(\word_count[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[12]_net_1 ), .S(\word_count_s[13] ), .Y(), 
        .FCO(\word_count_cry[13]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[5]  (.A(\nextaddr[5] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_4 (.A(VCC_net_1), .B(
        \haddr_reg[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_3_net_1), .S(\nextaddr[4] ), .Y(), .FCO(
        nextaddr_cry_4_net_1));
    SLE \curr_state[2]  (.D(\curr_state_ns[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(curr_state_0));
    CFG4 #( .INIT(16'hC5D5) )  \word_count_lm_0[2]  (.A(
        \word_count_lm_0_1_0[2]_net_1 ), .B(cfburst_len_rd_o[2]), .C(
        ahm_busreq_reg5_s1), .D(fcbusreq_o), .Y(\word_count_lm[2] ));
    CFG3 #( .INIT(8'h1B) )  \haddr_reg_7_1_1[12]  (.A(
        cfrd_resp_d1_net_1), .B(\nextaddr[12] ), .C(cfsrc_addr_o_12), 
        .Y(\haddr_reg_7_1_1[12]_net_1 ));
    CFG4 #( .INIT(16'hC5D5) )  \word_count_lm_0[0]  (.A(
        \word_count_lm_0_1_0[0]_net_1 ), .B(cfburst_len_rd_o[0]), .C(
        ahm_busreq_reg5_s1), .D(fcbusreq_o), .Y(\word_count_lm[0] ));
    CFG3 #( .INIT(8'h35) )  \word_count_lm_0_1_0[6]  (.A(
        \word_count_s[6] ), .B(cfburst_len_wr_o[6]), .C(fcbusreq_o), 
        .Y(\word_count_lm_0_1_0[6]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[17]  (.A(\nextaddr[17] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[17]_net_1 ));
    CFG4 #( .INIT(16'hE2FF) )  \curr_state_RNID09U7[0]  (.A(
        idle_trigger), .B(word_m3_0_a2_1), .C(cfrd_resp_o), .D(N_27_tz)
        , .Y(N_27_i));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_9 (.A(VCC_net_1), .B(
        \haddr_reg[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_8_net_1), .S(\nextaddr[9] ), .Y(), .FCO(
        nextaddr_cry_9_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[17]  (.A(N_395), .B(
        \nextaddr[15] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[17] ));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[15]  (.A(
        \word_count_s[15] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[15]), .Y(\word_count_lm[15] ));
    SLE \fmhaddr_o[25]  (.D(\fmhaddr_o_8[25] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[25]));
    SLE \word_count[4]  (.D(\word_count_lm[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[4]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  un1_cfcommaccess_active_1_1 (.A(
        req_curr_state_0), .B(resp_curr_state_5), .C(resp_curr_state_6)
        , .D(resp_curr_state_0), .Y(un1_cfcommaccess_active_1_1_net_1));
    SLE \haddr_reg[4]  (.D(\haddr_reg_7[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_24 (.A(VCC_net_1), .B(
        \haddr_reg[24]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_23_net_1), .S(\nextaddr[24] ), .Y(), .FCO(
        nextaddr_cry_24_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[25]  (.A(N_395), .B(
        \nextaddr[23] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[25] ));
    SLE cfrd_req_d2 (.D(cfrd_req_d1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfrd_req_d2_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[31]  (.A(N_395), .B(
        \nextaddr[29] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[31] ));
    SLE \fmhaddr_o[12]  (.D(N_107), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(un1_fmhaddr_o20_i), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(syssvc_blk_0_AHBL_MASTER_HADDR[12]));
    SLE \word_count[3]  (.D(\word_count_lm[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[3]_net_1 ));
    SLE cfwr_req_d2 (.D(cfwr_req_d1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfwr_req_d2_net_1));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[20]  (.A(VCC_net_1), 
        .B(\word_count[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[19]_net_1 ), .S(\word_count_s[20] ), .Y(), 
        .FCO(\word_count_cry[20]_net_1 ));
    SLE \word_count[30]  (.D(\word_count_lm[30] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[30]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_20 (.A(
        \word_count[13]_net_1 ), .B(\word_count[12]_net_1 ), .C(
        \word_count[7]_net_1 ), .D(\word_count[6]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_20_net_1));
    CFG3 #( .INIT(8'h80) )  curr_state_tr14_0_a2_0_a2_0 (.A(cfgrant_o), 
        .B(mchready_i), .C(\curr_state[1]_net_1 ), .Y(N_320));
    CFG4 #( .INIT(16'hD5C0) )  \curr_state_ns_0_iv_0[2]  (.A(
        mchready_i), .B(N_320), .C(fmhwrite_d1), .D(curr_state_0), .Y(
        \curr_state_ns[2] ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[29]  (.A(fcbusreq_o), .B(
        \word_count_s[29] ), .Y(\word_count_lm[29] ));
    SLE \haddr_reg[6]  (.D(\haddr_reg_7[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_14 (.A(VCC_net_1), .B(
        \haddr_reg[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_13_net_1), .S(\nextaddr[14] ), .Y(), .FCO(
        nextaddr_cry_14_net_1));
    CFG2 #( .INIT(4'hE) )  cfwr_req_d1_RNO (.A(cfwr_req_o), .B(
        curr_state_2), .Y(N_145_i));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[21]  (.A(fcbusreq_o), .B(
        \word_count_s[21] ), .Y(\word_count_lm[21] ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[1]  (.A(VCC_net_1), .B(
        \word_count[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[0]_net_1 ), .S(\word_count_s[1] ), .Y(), .FCO(
        \word_count_cry[1]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \fmhaddr_o_8_i_m2_1_1[12]  (.A(N_395), .B(
        \nextaddr[10] ), .C(cfdst_addr_o_10), .Y(
        \fmhaddr_o_8_i_m2_1_1[12]_net_1 ));
    SLE \word_count[0]  (.D(\word_count_lm[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[0]_net_1 ));
    CFG4 #( .INIT(16'h02DF) )  \haddr_reg_7_i_m2[28]  (.A(
        un1_cfwr_req_d1_i), .B(cfrd_resp_d1_net_1), .C(
        cfdst_addr_o_0_iv_0), .D(\haddr_reg_7_i_m2_1_1[28]_net_1 ), .Y(
        N_102));
    SLE \curr_state[0]  (.D(N_301_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(GND_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        idle_trigger));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[6]  (.A(VCC_net_1), .B(
        \word_count[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[5]_net_1 ), .S(\word_count_s[6] ), .Y(), .FCO(
        \word_count_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  \word_count_s[31]  (.A(VCC_net_1), .B(
        \word_count[31]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[30]_net_1 ), .S(\word_count_s[31]_net_1 ), .Y()
        , .FCO());
    CFG3 #( .INIT(8'h1B) )  \haddr_reg_7_1_1[14]  (.A(
        cfrd_resp_d1_net_1), .B(\nextaddr[14] ), .C(cfsrc_addr_o_14), 
        .Y(\haddr_reg_7_1_1[14]_net_1 ));
    SLE \haddr_reg[9]  (.D(\haddr_reg_7[9]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[9]_net_1 ));
    SLE \word_count[11]  (.D(\word_count_lm[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[11]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[28]  (.A(fcbusreq_o), .B(
        \word_count_s[28] ), .Y(\word_count_lm[28] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_20 (.A(VCC_net_1), .B(
        \haddr_reg[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_19_net_1), .S(\nextaddr[20] ), .Y(), .FCO(
        nextaddr_cry_20_net_1));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[19]  (.A(fcbusreq_o), .B(
        \word_count_s[19] ), .Y(\word_count_lm[19] ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_7[16]  (.A(\nextaddr[16] ), .B(
        cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(
        \haddr_reg_7[16]_net_1 ));
    SLE \haddr_reg[17]  (.D(\haddr_reg_7[17]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[17]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_21 (.A(
        \word_count[5]_net_1 ), .B(\word_count[4]_net_1 ), .C(
        \word_count[2]_net_1 ), .D(\word_count[1]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_21_net_1));
    SLE \word_count[15]  (.D(\word_count_lm[15] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[15]_net_1 ));
    CFG3 #( .INIT(8'hB1) )  \fmhaddr_o_8_i_m2[4]  (.A(N_395), .B(
        \fmhaddr_o_8_i_m2_1_1[4]_net_1 ), .C(cfdst_addr_o_2), .Y(N_108)
        );
    CFG3 #( .INIT(8'h32) )  cfrd_resp_d1_23 (.A(cfrd_resp_o), .B(
        curr_state_2), .C(cfrd_resp_d1_net_1), .Y(
        cfrd_resp_d1_23_net_1));
    CFG4 #( .INIT(16'hCA0A) )  \word_count_lm_0[11]  (.A(
        \word_count_s[11] ), .B(ahm_busreq_reg5_s1), .C(fcbusreq_o), 
        .D(cfburst_len_rd_o[11]), .Y(\word_count_lm[11] ));
    SLE \haddr_reg[0]  (.D(\haddr_reg_7[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_23), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\haddr_reg[0]_net_1 ));
    SLE \word_count[28]  (.D(\word_count_lm[28] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[28]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_26 (.A(VCC_net_1), .B(
        \haddr_reg[26]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_25_net_1), .S(\nextaddr[26] ), .Y(), .FCO(
        nextaddr_cry_26_net_1));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_17 (.A(
        \word_count[29]_net_1 ), .B(\word_count[28]_net_1 ), .C(
        \word_count[23]_net_1 ), .D(\word_count[22]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_17_net_1));
    SLE \curr_state[3]  (.D(\curr_state_ns[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\curr_state[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_10 (.A(VCC_net_1), .B(
        \haddr_reg[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_9_net_1), .S(\nextaddr[10] ), .Y(), .FCO(
        nextaddr_cry_10_net_1));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[22]  (.A(N_395), .B(
        \nextaddr[20] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[22] ));
    CFG4 #( .INIT(16'h0001) )  fctrans_done_tmp5_0_a2_0_18 (.A(
        \word_count[31]_net_1 ), .B(\word_count[30]_net_1 ), .C(
        \word_count[27]_net_1 ), .D(\word_count[26]_net_1 ), .Y(
        fctrans_done_tmp5_0_a2_0_18_net_1));
    SLE \word_count[1]  (.D(\word_count_lm[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_27_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\word_count[1]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[27]  (.A(N_395), .B(
        \nextaddr[25] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[27] ));
    ARI1 #( .INIT(20'h4AA00) )  nextaddr_cry_16 (.A(VCC_net_1), .B(
        \haddr_reg[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nextaddr_cry_15_net_1), .S(\nextaddr[16] ), .Y(), .FCO(
        nextaddr_cry_16_net_1));
    CFG2 #( .INIT(4'h4) )  \word_count_lm_0[18]  (.A(fcbusreq_o), .B(
        \word_count_s[18] ), .Y(\word_count_lm[18] ));
    CFG3 #( .INIT(8'h35) )  \haddr_reg_7_i_m2_1_1[28]  (.A(
        \nextaddr[28] ), .B(N_7540_i), .C(cfrd_resp_d1_net_1), .Y(
        \haddr_reg_7_i_m2_1_1[28]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \haddr_reg_RNO[26]  (.A(\nextaddr[26] ), 
        .B(cfrd_resp_d1_net_1), .C(un1_cfwr_req_d1_i), .Y(N_19_i));
    CFG3 #( .INIT(8'h35) )  \word_count_lm_0_1_0[3]  (.A(
        \word_count_s[3] ), .B(cfburst_len_wr_o[3]), .C(fcbusreq_o), 
        .Y(\word_count_lm_0_1_0[3]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  \word_count_cry[19]  (.A(VCC_net_1), 
        .B(\word_count[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \word_count_cry[18]_net_1 ), .S(\word_count_s[19] ), .Y(), 
        .FCO(\word_count_cry[19]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \fmhaddr_o_8_1_a2[26]  (.A(N_395), .B(
        \nextaddr[24] ), .C(cfrd_resp_d2_net_1), .Y(\fmhaddr_o_8[26] ));
    SLE \fmhaddr_o[31]  (.D(\fmhaddr_o_8[31] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fmhaddr_o20_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_AHBL_MASTER_HADDR[31]));
    CFG4 #( .INIT(16'hFFFE) )  \curr_state_ns_i_a2_i_1[1]  (.A(
        fmhaddr_o20_i_0), .B(N_327), .C(\curr_state[6]_net_1 ), .D(
        \curr_state[3]_net_1 ), .Y(\curr_state_ns_i_a2_i_1[1]_net_1 ));
    
endmodule


module CoreSysServices_CmdDec_Z7(
       cfdst_addr_o_iv,
       ucnrbg_handle_o,
       CoreAHBLite_0_AHBmslave16_HRDATA,
       uclatchcmd_o,
       cfburst_len_rd_o,
       cfburst_len_wr_o,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       cudata_r_o,
       CoreAHBLite_0_AHBmslave16_HWDATA_0,
       masterDataInProg_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_0_0,
       memwr_desc_int_m_9,
       memwr_desc_int_m_15,
       memwr_desc_int_m_16,
       memwr_desc_int_m_19,
       memwr_desc_int_m_17,
       memwr_desc_int_m_14,
       memwr_desc_int_m_0,
       curr_state_0,
       curr_state_2,
       req_curr_state_RNI9FH21_0,
       cfdst_addr_o_0_iv_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_dstreg_data_0_0,
       ucnrbg_length_o_0,
       cfburst_len_wr_o_1_2_x_0,
       cfdatain_o_iv_0_7_0,
       resp_curr_state_6,
       resp_curr_state_0,
       resp_curr_state_5,
       req_curr_state_0,
       cfsrc_addr_o_10,
       cfsrc_addr_o_11,
       cfsrc_addr_o_12,
       cfsrc_addr_o_14,
       cfsrc_addr_o_27,
       cfsrc_addr_o_0,
       cfsrc_addr_o_1,
       cfdst_addr_o_0,
       cfdst_addr_o_1,
       cfdst_addr_o_2,
       cfdst_addr_o_10,
       cfdst_addr_o_14,
       cfdst_addr_o_27,
       cfdatain_d1_25,
       cfdatain_d1_26,
       cfdatain_d1_27,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       cfdatain_d1_20,
       cfdatain_d1_0,
       cfdatain_d1_2,
       cfdatain_d1_5,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       cfdatain_N_8_mux_i_0,
       cfrd_resp_o,
       N_7929,
       N_7931,
       cfgrant_o,
       cfdatain_N_5,
       uctrig_o,
       N_7888,
       cfburst_len_rd_o_1_sn_N_2,
       N_7876,
       un1_cfdatain_o26_1_out,
       N_7344,
       N_7920,
       my_hpms_top_0_COMM_BLK_INT,
       idle_trigger,
       custatus_out_en,
       g2_0,
       g0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0_0,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_1,
       g3,
       g0_0_2,
       g2,
       N_10_0_0,
       N_7903_0,
       g2_0_0_0,
       N_12_1,
       N_8225,
       N_5111_i,
       N_7670,
       cfdatain_o27,
       un2_cudata_wrdy_int_9,
       N_7556_i,
       cfdatain_o28,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       mchready_i,
       un2_cudata_wrdy_int_1_0,
       N_7928,
       ucvalid_cmd_o,
       cfrd_req_o,
       fctrans_done_o,
       fcbusreq_o,
       CORESYSSERVICES_0_SERV_DATA_RVALID,
       cfwr_req_o,
       custatus_valid_o,
       RSTSYNC1,
       main_curr_state_5371_d,
       N_7894_i,
       N_7540_i,
       N_7352_i,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
output [14:13] cfdst_addr_o_iv;
input  [7:0] ucnrbg_handle_o;
input  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
input  [4:0] uclatchcmd_o;
output [15:0] cfburst_len_rd_o;
output [6:1] cfburst_len_wr_o;
input  [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
output [31:0] cudata_r_o;
output CoreAHBLite_0_AHBmslave16_HWDATA_0;
input  masterDataInProg_0;
output cfdatain_o_0_iv_0_1_0;
output cfdatain_o_iv_0_4_0;
output cfdatain_o_0_iv_0_0_0;
output memwr_desc_int_m_9;
output memwr_desc_int_m_15;
output memwr_desc_int_m_16;
output memwr_desc_int_m_19;
output memwr_desc_int_m_17;
output memwr_desc_int_m_14;
output memwr_desc_int_m_0;
input  curr_state_0;
input  curr_state_2;
output req_curr_state_RNI9FH21_0;
output cfdst_addr_o_0_iv_0;
output cfdatain_o_0_iv_0_a2_3_0_0;
output req_dstreg_data_0_0;
input  ucnrbg_length_o_0;
output cfburst_len_wr_o_1_2_x_0;
output cfdatain_o_iv_0_7_0;
output resp_curr_state_6;
output resp_curr_state_0;
output resp_curr_state_5;
output req_curr_state_0;
output cfsrc_addr_o_10;
output cfsrc_addr_o_11;
output cfsrc_addr_o_12;
output cfsrc_addr_o_14;
output cfsrc_addr_o_27;
output cfsrc_addr_o_0;
output cfsrc_addr_o_1;
output cfdst_addr_o_0;
output cfdst_addr_o_1;
output cfdst_addr_o_2;
output cfdst_addr_o_10;
output cfdst_addr_o_14;
output cfdst_addr_o_27;
output cfdatain_d1_25;
output cfdatain_d1_26;
output cfdatain_d1_27;
output cfdatain_d1_28;
output cfdatain_d1_30;
output cfdatain_d1_11;
output cfdatain_d1_20;
output cfdatain_d1_0;
output cfdatain_d1_2;
output cfdatain_d1_5;
output syssvc_blk_0_AHBL_MASTER_HWDATA_15;
output syssvc_blk_0_AHBL_MASTER_HWDATA_16;
output syssvc_blk_0_AHBL_MASTER_HWDATA_23;
output syssvc_blk_0_AHBL_MASTER_HWDATA_0;
output syssvc_blk_0_AHBL_MASTER_HWDATA_1;
output syssvc_blk_0_AHBL_MASTER_HWDATA_2;
output syssvc_blk_0_AHBL_MASTER_HWDATA_7;
output syssvc_blk_0_AHBL_MASTER_HWDATA_8;
output syssvc_blk_0_AHBL_MASTER_HWDATA_9;
output syssvc_blk_0_AHBL_MASTER_HWDATA_10;
output syssvc_blk_0_AHBL_MASTER_HWDATA_11;
output syssvc_blk_0_AHBL_MASTER_HWDATA_13;
output syssvc_blk_0_AHBL_MASTER_HWDATA_14;
output cfdatain_N_8_mux_i_0;
output cfrd_resp_o;
output N_7929;
output N_7931;
output cfgrant_o;
output cfdatain_N_5;
input  uctrig_o;
output N_7888;
output cfburst_len_rd_o_1_sn_N_2;
output N_7876;
output un1_cfdatain_o26_1_out;
output N_7344;
output N_7920;
input  my_hpms_top_0_COMM_BLK_INT;
input  idle_trigger;
output custatus_out_en;
output g2_0;
output g0_0;
output cfdatain_o_iv_N_5_3_0;
output g0_0_0;
output cfdatain_o_iv_0_N_5_3_0;
output g0_0_1;
output g3;
output g0_0_2;
output g2;
output N_10_0_0;
output N_7903_0;
output g2_0_0_0;
output N_12_1;
output N_8225;
output N_5111_i;
input  N_7670;
output cfdatain_o27;
output un2_cudata_wrdy_int_9;
output N_7556_i;
output cfdatain_o28;
input  syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  mchready_i;
output un2_cudata_wrdy_int_1_0;
output N_7928;
input  ucvalid_cmd_o;
output cfrd_req_o;
input  fctrans_done_o;
input  fcbusreq_o;
output CORESYSSERVICES_0_SERV_DATA_RVALID;
output cfwr_req_o;
output custatus_valid_o;
output RSTSYNC1;
output main_curr_state_5371_d;
output N_7894_i;
output N_7540_i;
output N_7352_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire VCC_net_1, GND_net_1, \burstlen_memwr_data_r[3]_net_1 , 
        \burstlen_memwr_data[3]_net_1 , 
        \burstlen_memwr_data_r[4]_net_1 , 
        \burstlen_memwr_data[4]_net_1 , \resp_srcreg_addr_d1[2]_net_1 , 
        \resp_srcreg_addr[2] , \resp_srcreg_addr_d1[3]_net_1 , 
        \resp_srcreg_addr[3] , \resp_srcreg_addr_d1[4]_net_1 , N_7379, 
        \resp_srcreg_data_d1[3]_net_1 , N_4185_i, N_4425_i, 
        \resp_srcreg_data_d1[4]_net_1 , \resp_srcreg_data_cnst[4] , 
        \resp_srcreg_addr_d1[13]_net_1 , N_4294_i, 
        \cfdatain_d1[23]_net_1 , \cfdatain_d1[24]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[25] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[26] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[27] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[28] , \cfdatain_d1[29]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[29] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[30] , \cfdatain_d1[31]_net_1 , 
        \memwr_data_addr_r[13]_net_1 , \memwr_data_addr_cnst[13] , 
        memwr_data_addr_3_sqmuxa, \memwr_data_addr_r[14]_net_1 , 
        memwr_data_addr_2_sqmuxa, \memwr_data_addr_r[29]_net_1 , 
        \memwr_data_addr_cnst[29] , \burstlen_memwr_data_r[0]_net_1 , 
        \burstlen_memwr_data[0]_net_1 , 
        \burstlen_memwr_data_r[2]_net_1 , 
        \burstlen_memwr_data[2]_net_1 , \cfdatain_d1[8]_net_1 , 
        \cfdatain_d1[9]_net_1 , \cfdatain_d1[10]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[11] , \cfdatain_d1[12]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[12] , \cfdatain_d1[13]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[13] , \cfdatain_d1[14]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[14] , \cfdatain_d1[15]_net_1 , 
        \cfdatain_d1[16]_net_1 , \cfdatain_d1[17]_net_1 , 
        \cfdatain_d1[18]_net_1 , \cfdatain_d1[19]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[20] , \cfdatain_d1[21]_net_1 , 
        \cfdatain_d1[22]_net_1 , \cfsrc_addr_d1[4]_net_1 , 
        \cfsrc_addr_d1[12]_net_1 , \cfsrc_addr_d1[13]_net_1 , 
        \cfsrc_addr_d1[14]_net_1 , \cfsrc_addr_d1[16]_net_1 , 
        \cfsrc_addr_d1[29]_net_1 , \cfsrc_addr_d1[30]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[0] , \cfdatain_d1[1]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[1] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[2] , \cfdatain_d1[3]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[3] , \cfdatain_d1[4]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[4] , 
        \cfdatain_d1_RNO[5]_net_1 , \cfdatain_d1[6]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[6] , \cfdatain_d1[7]_net_1 , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[7] , \cfdst_addr_d1[2]_net_1 , 
        \cfdst_addr_d1[3]_net_1 , \cfdst_addr_d1[4]_net_1 , 
        \cfdst_addr_d1[12]_net_1 , \cfdst_addr_d1[13]_net_1 , 
        \cfdst_addr_o_iv_i[13] , \cfdst_addr_d1[14]_net_1 , 
        \cfdst_addr_o_iv_i[14] , \cfdst_addr_d1[16]_net_1 , 
        \cfdst_addr_d1[29]_net_1 , \cfdst_addr_d1[30]_net_1 , 
        \cfdst_addr_o_0_iv_i[30] , \cfsrc_addr_d1[2]_net_1 , 
        \cfsrc_addr_d1[3]_net_1 , \burstlen_memrd_data_d1[5]_net_1 , 
        N_7917_i, \burstlen_memrd_data_d1[6]_net_1 , 
        \burstlen_memrd_data[6]_net_1 , 
        \burstlen_memrd_data_d1[7]_net_1 , 
        \burstlen_memrd_data[7]_net_1 , \cfburst_len_wr_d1[0]_net_1 , 
        \cfburst_len_wr_o[0] , \cfburst_len_wr_d1[1]_net_1 , 
        \cfburst_len_wr_d1[2]_net_1 , \cfburst_len_wr_d1[3]_net_1 , 
        \cfburst_len_wr_d1[4]_net_1 , \cfburst_len_wr_d1[5]_net_1 , 
        \cfburst_len_wr_d1[6]_net_1 , \cfburst_len_rd_d1[6]_net_1 , 
        \cfburst_len_rd_d1[7]_net_1 , \cfburst_len_rd_d1[8]_net_1 , 
        \cfburst_len_rd_d1[9]_net_1 , \cfburst_len_rd_d1[10]_net_1 , 
        \cfburst_len_rd_d1[11]_net_1 , \cfburst_len_rd_d1[12]_net_1 , 
        \cfburst_len_rd_d1[13]_net_1 , \cfburst_len_rd_d1[14]_net_1 , 
        \cfburst_len_rd_d1[15]_net_1 , 
        \burstlen_memrd_data_d1[0]_net_1 , \burstlen_memrd_data[0] , 
        \burstlen_memrd_data_d1[1]_net_1 , 
        \burstlen_memrd_data[1]_net_1 , 
        \burstlen_memrd_data_d1[2]_net_1 , 
        \burstlen_memrd_data[2]_net_1 , 
        \burstlen_memrd_data_d1[3]_net_1 , 
        \burstlen_memrd_data[3]_net_1 , 
        \burstlen_memrd_data_d1[4]_net_1 , N_7916_i, 
        \cfburst_len_rd_d1[0]_net_1 , \cfburst_len_rd_d1[1]_net_1 , 
        \cfburst_len_rd_d1[2]_net_1 , \cfburst_len_rd_d1[3]_net_1 , 
        \cfburst_len_rd_d1[4]_net_1 , N_7899_i, 
        \cfburst_len_rd_d1[5]_net_1 , N_7898_i, cucmd_error_net_1, 
        un1_main_curr_state_4_0_net_1, unreg_cmd_net_1, 
        unreg_cmd_1005_net_1, resp_data_done_net_1, 
        \resp_curr_state[4]_net_1 , N_4295_i, set_sent_options_r_net_1, 
        set_sent_options_r_1003_net_1, set_puf_getkcnum_net_1, 
        set_puf_getkcnum_1002_net_1, reset_puf_getkcnum_net_1, 
        un1_main_curr_state_1_0_net_1, txtokay_net_1, 
        txtokay_1000_net_1, rcvokay_net_1, rcvokay_999_net_1, 
        cmdrcv_net_1, cmdrcv_998_net_1, \main_curr_state[0]_net_1 , 
        \main_curr_state_ns[0] , \main_curr_state[1]_net_1 , N_8103_i, 
        \req_curr_state[23]_net_1 , \req_curr_state_ns_i_i[23]_net_1 , 
        \req_curr_state[24]_net_1 , \req_curr_state_ns_i_i[24]_net_1 , 
        \req_curr_state[25]_net_1 , N_5519_i, 
        \req_curr_state[26]_net_1 , \req_curr_state_ns[26] , 
        \req_curr_state[27]_net_1 , \req_curr_state_ns[27] , 
        \req_curr_state[28]_net_1 , \req_curr_state_ns[28] , 
        \req_curr_state[29]_net_1 , \req_curr_state_ns_i_i[29]_net_1 , 
        \req_curr_state[30]_net_1 , \req_curr_state_ns[30] , 
        \req_curr_state[31]_net_1 , \req_curr_state_ns_i_i[31]_net_1 , 
        \req_curr_state[32]_net_1 , \req_curr_state_ns[32] , 
        \req_curr_state[33]_net_1 , \req_curr_state_ns[33] , 
        \req_curr_state[34]_net_1 , N_5531_i, 
        \req_curr_state[35]_net_1 , \req_curr_state_ns[35] , 
        \req_curr_state[36]_net_1 , \req_curr_state_ns[36] , 
        \req_curr_state[8]_net_1 , \req_curr_state_ns[8] , 
        \req_curr_state[9]_net_1 , \req_curr_state_ns[9] , 
        \req_curr_state[10]_net_1 , \req_curr_state_ns[10] , 
        \req_curr_state[11]_net_1 , \req_curr_state_ns[11] , 
        \req_curr_state[12]_net_1 , \req_curr_state_ns[12] , 
        \req_curr_state[13]_net_1 , N_5501_i, 
        \req_curr_state[14]_net_1 , \req_curr_state_ns[14] , 
        \req_curr_state[15]_net_1 , \req_curr_state_ns[15] , 
        \req_curr_state[16]_net_1 , \req_curr_state_ns_i_i[16]_net_1 , 
        \req_curr_state[17]_net_1 , \req_curr_state_ns_i_i[17]_net_1 , 
        \req_curr_state[18]_net_1 , \req_curr_state_ns[18] , 
        \req_curr_state[19]_net_1 , \req_curr_state_ns_i_i[19]_net_1 , 
        \req_curr_state[20]_net_1 , \req_curr_state_ns[20] , 
        \req_curr_state[21]_net_1 , \req_curr_state_ns[21] , 
        \req_curr_state[22]_net_1 , \req_curr_state_ns[22] , N_5486_i, 
        \req_curr_state[1]_net_1 , \req_curr_state_ns[1] , 
        \req_curr_state[2]_net_1 , \req_curr_state_ns[2] , 
        \req_curr_state[3]_net_1 , \req_curr_state_ns[3] , 
        \req_curr_state[4]_net_1 , \req_curr_state_ns[4] , 
        \req_curr_state[5]_net_1 , N_5492_i, \req_curr_state[6]_net_1 , 
        \req_curr_state_ns[6] , \req_curr_state[7]_net_1 , 
        \req_curr_state_ns[7] , \resp_curr_state[21]_net_1 , N_4134_i, 
        \resp_curr_state[22]_net_1 , N_4136_i, 
        \resp_curr_state[23]_net_1 , \resp_curr_state_ns[23]_net_1 , 
        \resp_curr_state[24]_net_1 , \resp_curr_state_ns[24] , 
        \resp_curr_state[25]_net_1 , \resp_curr_state_ns[25] , 
        \resp_curr_state[26]_net_1 , N_4141_i, 
        \resp_curr_state[27]_net_1 , N_7483_i, 
        \resp_curr_state[28]_net_1 , 
        \resp_curr_state_ns_i_i[28]_net_1 , 
        \resp_curr_state[29]_net_1 , N_7521_i, 
        \resp_curr_state[30]_net_1 , \resp_curr_state_ns[30] , 
        N_4115_i, \resp_curr_state[7]_net_1 , 
        \resp_curr_state_ns[7]_net_1 , \resp_curr_state[8]_net_1 , 
        \resp_curr_state_ns[8]_net_1 , \resp_curr_state[9]_net_1 , 
        \resp_curr_state_ns[9] , \resp_curr_state[10]_net_1 , 
        \resp_curr_state_ns[10] , \resp_curr_state[11]_net_1 , 
        \resp_curr_state_ns[11] , \resp_curr_state[12]_net_1 , 
        \resp_curr_state_ns[12] , \resp_curr_state[13]_net_1 , 
        \resp_curr_state_ns[13]_net_1 , \resp_curr_state[14]_net_1 , 
        N_4124_i, \resp_curr_state[15]_net_1 , 
        \resp_curr_state[16]_net_1 , \resp_curr_state_ns[16]_net_1 , 
        \resp_curr_state[17]_net_1 , \resp_curr_state_ns[17] , 
        \resp_curr_state[18]_net_1 , \resp_curr_state_ns[18]_net_1 , 
        \resp_curr_state[19]_net_1 , N_4131_i, 
        \resp_curr_state[20]_net_1 , \resp_curr_state_ns[20] , 
        \resp_curr_state_ns[0] , \resp_curr_state[1]_net_1 , 
        \resp_curr_state_ns_i_i_a2[1]_net_1 , 
        \resp_curr_state[2]_net_1 , \resp_curr_state_ns[2] , 
        \resp_curr_state[3]_net_1 , \resp_curr_state_ns[3]_net_1 , 
        \resp_curr_state_ns[4] , \resp_curr_state_ns[5]_net_1 , 
        \resp_srcreg_data_d1[29]_net_1 , N_7484, 
        custatus_valid_o5_net_1, \resp_srcreg_data_d1[1]_net_1 , 
        N_7353_i, resp_phase_done_d1_net_1, resp_phase_done, 
        cmd_error_d1_net_1, cmd_error, resp_phase_done_pulse_net_1, 
        resp_phase_done_pulse_2_net_1, \resp_srcreg_addr_d1[16]_net_1 , 
        \resp_srcreg_addr[16] , N_7595_i, req_phase_done_d1_net_1, 
        resp_phase_active_d1_net_1, resp_phase_active_i_i_net_1, 
        resp_phase_active_pulse_net_1, resp_phase_active_pulse_2_net_1, 
        N_7350_i, fcbusreq_d1_net_1, fctrans_done_d1_net_1, 
        cudata_wrdy_d1_net_1, r_N_3_mux, N_5252_i, 
        \desc_datasel_cntr[0]_net_1 , \desc_datasel_cntr_s[0] , 
        N_7868_i, \desc_datasel_cntr[1]_net_1 , 
        \desc_datasel_cntr_s[1] , \desc_datasel_cntr[2]_net_1 , 
        \desc_datasel_cntr_s[2] , \desc_datasel_cntr[3]_net_1 , 
        \desc_datasel_cntr_s[3] , \desc_datasel_cntr[4]_net_1 , 
        \desc_datasel_cntr_s[4] , \desc_datasel_cntr[5]_net_1 , 
        \desc_datasel_cntr_s[5] , \desc_datasel_cntr[6]_net_1 , 
        \desc_datasel_cntr_s[6] , \desc_datasel_cntr[7]_net_1 , 
        \desc_datasel_cntr_s[7] , \desc_datasel_cntr[8]_net_1 , 
        \desc_datasel_cntr_s[8] , \desc_datasel_cntr[9]_net_1 , 
        \desc_datasel_cntr_s[9] , \desc_datasel_cntr[10]_net_1 , 
        \desc_datasel_cntr_s[10] , \desc_datasel_cntr[11]_net_1 , 
        \desc_datasel_cntr_s[11] , \desc_datasel_cntr[12]_net_1 , 
        \desc_datasel_cntr_s[12] , \desc_datasel_cntr[13]_net_1 , 
        \desc_datasel_cntr_s[13] , \desc_datasel_cntr[14]_net_1 , 
        \desc_datasel_cntr_s[14] , \desc_datasel_cntr[15]_net_1 , 
        \desc_datasel_cntr_s[15] , \desc_datasel_cntr[16]_net_1 , 
        \desc_datasel_cntr_s[16] , \desc_datasel_cntr[17]_net_1 , 
        \desc_datasel_cntr_s[17] , \desc_datasel_cntr[18]_net_1 , 
        \desc_datasel_cntr_s[18] , \desc_datasel_cntr[19]_net_1 , 
        \desc_datasel_cntr_s[19] , \desc_datasel_cntr[20]_net_1 , 
        \desc_datasel_cntr_s[20] , \desc_datasel_cntr[21]_net_1 , 
        \desc_datasel_cntr_s[21] , \desc_datasel_cntr[22]_net_1 , 
        \desc_datasel_cntr_s[22] , \desc_datasel_cntr[23]_net_1 , 
        \desc_datasel_cntr_s[23] , \desc_datasel_cntr[24]_net_1 , 
        \desc_datasel_cntr_s[24] , \desc_datasel_cntr[25]_net_1 , 
        \desc_datasel_cntr_s[25] , \desc_datasel_cntr[26]_net_1 , 
        \desc_datasel_cntr_s[26] , \desc_datasel_cntr[27]_net_1 , 
        \desc_datasel_cntr_s[27] , \desc_datasel_cntr[28]_net_1 , 
        \desc_datasel_cntr_s[28] , \desc_datasel_cntr[29]_net_1 , 
        \desc_datasel_cntr_s[29] , \desc_datasel_cntr[30]_net_1 , 
        \desc_datasel_cntr_s[30] , \desc_datasel_cntr[31]_net_1 , 
        \desc_datasel_cntr_s[31]_net_1 , desc_datasel_cntr_s_810_FCO, 
        \desc_datasel_cntr_cry[0]_net_1 , 
        \desc_datasel_cntr_cry[1]_net_1 , 
        \desc_datasel_cntr_cry[2]_net_1 , 
        \desc_datasel_cntr_cry[3]_net_1 , 
        \desc_datasel_cntr_cry[4]_net_1 , 
        \desc_datasel_cntr_cry[5]_net_1 , 
        \desc_datasel_cntr_cry[6]_net_1 , 
        \desc_datasel_cntr_cry[7]_net_1 , 
        \desc_datasel_cntr_cry[8]_net_1 , 
        \desc_datasel_cntr_cry[9]_net_1 , 
        \desc_datasel_cntr_cry[10]_net_1 , 
        \desc_datasel_cntr_cry[11]_net_1 , 
        \desc_datasel_cntr_cry[12]_net_1 , 
        \desc_datasel_cntr_cry[13]_net_1 , 
        \desc_datasel_cntr_cry[14]_net_1 , 
        \desc_datasel_cntr_cry[15]_net_1 , 
        \desc_datasel_cntr_cry[16]_net_1 , 
        \desc_datasel_cntr_cry[17]_net_1 , 
        \desc_datasel_cntr_cry[18]_net_1 , 
        \desc_datasel_cntr_cry[19]_net_1 , 
        \desc_datasel_cntr_cry[20]_net_1 , 
        \desc_datasel_cntr_cry[21]_net_1 , 
        \desc_datasel_cntr_cry[22]_net_1 , 
        \desc_datasel_cntr_cry[23]_net_1 , 
        \desc_datasel_cntr_cry[24]_net_1 , 
        \desc_datasel_cntr_cry[25]_net_1 , 
        \desc_datasel_cntr_cry[26]_net_1 , 
        \desc_datasel_cntr_cry[27]_net_1 , 
        \desc_datasel_cntr_cry[28]_net_1 , 
        \desc_datasel_cntr_cry[29]_net_1 , 
        \desc_datasel_cntr_cry[30]_net_1 , N_5305, N_4237, N_5301, 
        N_5157_i, N_4265, N_8105, N_5299_i, N_8108, N_7543_i, 
        memrd_data_addr_cnst_7ro, N_6101_2, N_7776, N_8065, 
        memwr_desc_5_sqmuxa_2_0, N_7943_2, 
        cfdatain_o_iv_0_7_N_4L6_net_1, N_7388, N_8052, do_mem_wr26_s8, 
        cfdatain_o_iv_0_7_N_5L9_net_1, memwr_desc_int34, 
        memwr_desc_int35, cfdatain_o_iv_0_7_N_6L11_net_1, N_7948, 
        \cfdatain_o_iv_0_a2_2_0[29]_net_1 , 
        cfdatain_o_iv_0_7_N_7L13_net_1, \cfdatain_o_iv_0_0[29]_net_1 , 
        cfdatain_o_iv_0_7_N_8L15_net_1, 
        \cfdatain_o_iv_0_o2_3_s_0[29]_net_1 , 
        \req_curr_state_RNIAQKD[35]_net_1 , 
        \resp_curr_state_RNI9SJA[16]_net_1 , 
        un2_cudata_wrdy_int_4_i_a2_0_0_net_1, 
        un2_cudata_wrdy_int_4_i_a2_0_0_RNI99IC1_net_1, N_7685_i, 
        m15_1_0, m15_2, m7, m15, m11, m7_1, m1, m15_0, N_8049, N_7477, 
        m15_1, N_7342, m7_1_0, cfburst_len_wr_o_1_2_250_tz_2, N_8056, 
        \cfburst_len_wr_o_1_2_a2_0_0[1]_net_1 , N_5293_i, 
        burstlen_memwr_desc36, do_mem_wr27_sx_net_1, do_mem_wr27_0_0, 
        do_mem_wr27_net_1, N_7683_i, N_7684_i, N_5292_i, N_7542_i, 
        cfdatain_o26_0_a2_sx_net_1, cfdatain_o26, cfdatain_o21, 
        un2_cudata_wrdy_int_4_i_0, cfdatain_o28_1_sx_net_1, 
        cfdatain_o29_0_a2_a0_0, cfdatain_o29_0_a2_a0_sx_net_1, 
        cfdatain_o29, un2_cudata_wrdy_int_9_sx_net_1, 
        cfdatain_o_iv_0_N_5L7_1_net_1, N_7700, 
        cfdatain_o_iv_0_N_5L7_net_1, N_7806, N_7544_i, N_7690, 
        req_dstreg_data20, g0_10_1, N_9_0_0, g2_0_1, 
        \req_dstreg_data_cnst_m[29]_net_1 , cfdatain_m4_e_0_1, 
        \memwr_desc_addr_i_RNICAN58[29]_net_1 , g0_12_1, N_7818, g0_4, 
        g0_5, g1_0_1_0, N_7_0, do_mem_wr25, N_4_0_0, g0_9_o3_0_0_net_1, 
        N_5331_i, N_5322_i, g1_0_0, \resp_srcreg_data_0[3] , 
        \req_dstreg_data_0_iv_0_0[3] , N_4374_i, g0_6_0, 
        cfdatain_o_iv_0_N_3_3_0, cfdatain_o_iv_0_N_2_5_0, g0_7_0, g2_1, 
        g2_0_0, N_5194_0, g1_0, \req_dstreg_data_cnst_0[4] , 
        \req_dstreg_data_0_iv_0_0[4] , cfdatain_o_iv_0_N_4L5_net_1, 
        \resp_srcreg_data_m[1] , N_5194, cfdatain_o_iv_N_2L1_net_1, 
        cfdatain_o_iv_N_3L3_net_1, cfdatain_o_iv_N_4L5_net_1, 
        cfdatain_o_iv_N_5L7_net_1, custatus_out_en_0_1_net_1, N_7355, 
        N_7796, \req_next_state_i_a12_3_1_0_i_o2_5_1_1[1]_net_1 , 
        \req_next_state_i_a12_3_1_0_i_a2_1_5[1]_net_1 , 
        \req_next_state_i_a12_3_1_0_i_o2_5[1] , N_7804, N_7481_i, 
        \cfburst_len_wr_o_1_2_1_1[1]_net_1 , 
        \cfburst_len_wr_o_1_2_1[1]_net_1 , N_5010_i, N_4863_i, 
        \cfburst_len_wr_o_1_2_a2_2_0[1]_net_1 , 
        un2_uclatchcmd_i_mux_16_i_2_net_1, 
        un2_uclatchcmd_i_mux_11_NE_net_1, N_8093_i_1, N_8093_i, 
        N_7341_i_1_0, N_7341_i, N_5354_i, 
        \req_curr_state_ns_0_0_1[18]_net_1 , N_7496, un1_m5_i_a3_0_3_1, 
        N_5757, un1_m5_i_a3_0_3, 
        burstlen_memrd_data_1_sqmuxa_1_0_a2_1_0, i3_mux, 
        burstlen_memwr_data_12_sqmuxa, 
        \burstlen_memwr_data_1[0]_net_1 , N_7351_i, 
        \burstlen_memwr_data_cnst[0] , burstlen_memrd_data_4_sqmuxa, 
        \cfburst_len_wr_o_1_1[3]_net_1 , N_6101, 
        \cfburst_len_wr_o_1_2_m2_1[0]_net_1 , 
        cfburst_len_wr_o_1_sn_N_3, datawr_reqd_0_a2_RNIGOICF_net_1, 
        resp_data_done_RNI74CL_net_1, 
        un1_req_curr_state_24_0_0_0_RNIULAK7_net_1, 
        un1_req_curr_state_24_i, N_7345, m20, N_4178_2, N_7545, N_7661, 
        N_5546, N_7560, N_5545, N_7584, N_7397, N_7386, 
        un1_burstlen_memwr_data130_1_i, N_4413_i, N_7426, 
        \req_dstreg_data_cnst[4] , N_7711_3, N_7707, N_7711_2, 
        \req_curr_state_ns_i_0_a2_2_2[13]_net_1 , N_7589, 
        cfdatain_m2_0_a2_0_0, \req_curr_state_ns_0_0_a2_0_0[20]_net_1 , 
        \cfsrc_addr_o_2_a2_1_0[3]_net_1 , 
        \req_next_state_i_a12_7_1[1]_net_1 , 
        \req_curr_state_ns_0_0_a3_0_0[36]_net_1 , 
        \req_curr_state_ns_0_0_a3_0_0[35]_net_1 , 
        burstlen_memrd_data_0_sqmuxa_3_0_a2_0_net_1, 
        \req_curr_state_ns_i_0_a2_1_0[13]_net_1 , 
        \resp_curr_state_ns_0_a3_0_0[10]_net_1 , 
        \resp_curr_state_ns_0_a2_0_0[25]_net_1 , do_mem_wr33_i_1_0, 
        do_mem_wr27_0_net_1, \memwr_desc_int_m_1[8] , N_4394_i, 
        \req_next_state_i_1_0_0_a2_c[5]_net_1 , 
        \req_next_state_i_a4_0_0_a3_0[1]_net_1 , do_mem_wr33, 
        \burstlen_memrd_data_0_RNO_1[0]_net_1 , 
        \req_next_state_i_a12_6_i_0[1]_net_1 , N_4395_i, N_4366_i, 
        main_next_state14, \resp_srcreg_addr[13]_net_1 , 
        \resp_srcreg_addr_d1_m[2]_net_1 , N_7455, N_7456, N_7462, 
        N_7380, N_7381, N_7515, N_7536, N_7556, N_7565, N_7708, N_7689, 
        N_7874, N_5310_2, N_105_i, N_8094, N_8119, N_7688, N_7469, 
        N_8106, N_5207_2, N_5158_i_0, N_5736, N_4418, N_4389_i, 
        cfrd_resp_o_0_sqmuxa_1, un1_burstlen_memwr_data132_1_i, 
        \burstlen_memwr_data_cnst[4] , N_6032, N_5, N_5668_1, N_5681_1, 
        N_7576_1, burstlen_memwr_data110, N_7550, N_7674, N_7662, 
        N_7470, N_8082, N_7465, N_7450, N_5332, 
        burstlen_memwr_desc34_2, N_7448, N_7790, N_8129_1, N_7801, 
        resp_next_state4_net_1, N_7351_1, N_47, memwr_desc_int33, 
        N_8069, N_7984, N_5174, burstlen_memrd_data_2_sqmuxa_1, N_6075, 
        burstlen_memrd_data_0_sqmuxa_3, N_8158, 
        \memwr_data_addr[14]_net_1 , unreg_cmd5_22_net_1, 
        unreg_cmd5_21_net_1, unreg_cmd5_20_net_1, unreg_cmd5_19_net_1, 
        unreg_cmd5_18_net_1, unreg_cmd5_17_net_1, unreg_cmd5_16_net_1, 
        unreg_cmd5_15_net_1, cfwr_req_d_i_a3_7_net_1, 
        cfwr_req_d_i_a3_6_net_1, cfwr_req_d_i_a3_5_net_1, 
        \req_curr_state_ns_0_0_a2_0_1[30]_net_1 , 
        burstlen_memrd_data_6_sqmuxa, burstlen_m3_0_a2_1, 
        \cfsrc_addr_o_2_a2_1_1[3]_net_1 , 
        \resp_curr_state_ns_a2_1[13]_net_1 , 
        \req_dstreg_addr_i_a4_1[2]_net_1 , 
        \req_next_state_i_a12_7_3[1]_net_1 , 
        cfrd_resp_o_i_i_a2_0_net_1, \req_curr_state_ns_0_0_a3_0_0[3] , 
        \cfburst_len_wr_o_1_0_1[3]_net_1 , do_mem_wr25_0_a2_1_net_1, 
        \req_curr_state_ns_0_0_0[22]_net_1 , 
        un1_burstlen_memwr_data130_1_0_a2_1_0_net_1, 
        un1_latchen_hrdata_int_6_i_a2_0_0_net_1, 
        do_mem_wr32_0_a2_1_net_1, un1_req_curr_state_21_0_a2_0_1_net_1, 
        un2_uclatchcmd_i_mux_11_NE_3_net_1, 
        un2_uclatchcmd_i_mux_11_NE_2_net_1, 
        un2_uclatchcmd_i_mux_11_NE_1_net_1, 
        un2_uclatchcmd_i_mux_11_NE_0_net_1, 
        burstlen_memrd_data_3_sqmuxa_1_net_1, 
        \req_curr_state_ns_i_0_a3_4_0[5]_net_1 , 
        \req_next_state_i_a12_3_1_0_i_a2_1_2[1]_net_1 , 
        \req_next_state_i_a12_3_1_0_i_a2_1_1[1]_net_1 , 
        \req_curr_state_ns_0_0_a2_1_1[22]_net_1 , 
        \resp_curr_state_ns_o2_10_a4_1[3]_net_1 , m2_e_20, m2_e_19, 
        m2_e_18, m2_e_17, m2_e_16, m2_e_15, m2_e_14, 
        \req_dstreg_data_cnst_m_i_a2_0_1[2]_net_1 , 
        un1_main_curr_state_2_0_a3_2_net_1, 
        un1_cfburst_len_wr_o13_i_a2_0_3_net_1, 
        un1_cfburst_len_wr_o13_i_a2_0_2_net_1, 
        \req_curr_state_ns_0_0_0[12]_net_1 , 
        un1_idle_trigger_4_i_a2_4_a4_0_a2_0_net_1, 
        \req_curr_state_ns_i_0_a2_1_1[5]_net_1 , 
        \req_curr_state_ns_0_0_a2_0_1[28]_net_1 , N_7794, N_7800, 
        do_mem_wr32, un1_do_mem_wr32_2_i, N_5733_i_0, cfdst_addr_o33, 
        burstlen_memwr_data_sn_N_6_mux, N_7439, N_5783, N_7798, 
        N_32_mux, \req_curr_state_ns_0_0_a2_1_2[22]_net_1 , 
        \req_dstreg_addr_i_a4_0[3]_net_1 , 
        un1_req_curr_state_24_0_a3_2_0_c_net_1, 
        un1_req_curr_state_24_0_0_0_net_1, un1_req_curr_state_21_i, 
        N_7821, N_7887, N_7480_i, N_7, N_8136_1, N_7995, N_5709_1_0_2, 
        N_5134_i_0, N_8088, N_5154, N_7656_1, burstlen_memwr_desc35_1, 
        N_7912, \ucnrbg_handle_i_m_2[3] , N_7365, N_108_i, N_7457, 
        N_8076, N_7792, N_7482_i, N_8064, burstlen_memrd_data_8_sqmuxa, 
        \burstlen_memrd_data_i_o2_0[4]_net_1 , 
        burstlen_memrd_data_3_sqmuxa_net_1, 
        \burstlen_memrd_data_i_o2_0[5]_net_1 , 
        \resp_curr_state_ns_i_0_0[26]_net_1 , 
        \req_next_state_i_1_0_0_a2_1_3[5]_net_1 , d_N_5, N_7566, 
        N_6076, burstlen_memrd_data_sn_N_6, N_6072, N_7658, 
        \resp_srcreg_data[3]_net_1 , \resp_curr_state_ns_0_0[0]_net_1 , 
        cfwr_req_d_i_a3_8_net_1, 
        \cfdst_addr_o_0_iv_0_a2_2_2[29]_net_1 , 
        \resp_curr_state_ns_0[8]_net_1 , 
        \resp_curr_state_ns_1[7]_net_1 , 
        \resp_curr_state_ns_0[7]_net_1 , 
        \resp_curr_state_ns_0_0[25]_net_1 , 
        \cfsrc_addr_o_2_0[14]_net_1 , 
        un1_req_curr_state_21_0_a2_2_net_1, 
        \req_next_state_i_a12_7_6[1]_net_1 , 
        \req_next_state_i_a12_7_5[1]_net_1 , 
        \req_curr_state_ns_i_0_1[25]_net_1 , 
        un1_req_curr_state_24_0_a3_2_1_3_net_1, 
        un1_req_curr_state_24_0_a3_2_1_2_net_1, 
        \cfdatain_o_0_iv_0_a2_1_3_1[2]_net_1 , 
        burstlen_memrd_data_8_sqmuxa_0_a2_1_net_1, 
        \main_curr_state_ns_0_0_0[0]_net_1 , 
        \req_curr_state_ns_i_0_a3_5_1[5]_net_1 , 
        \req_curr_state_ns_0_0_a3_1[3] , 
        un1_main_curr_state_2_0_a3_3_net_1, 
        \resp_curr_state_ns_3_i_1_0[3]_net_1 , cfdst_addr_o34, 
        cfdst_addr_o41_net_1, cfdst_addr_o42, N_8228, N_7372, N_7934, 
        N_7841, un1_do_mem_wr32_1_i, datawr_reqd, un1_fctrans_done_i_i, 
        N_7783, N_5753, cfgrant_req, N_7441, N_5345, 
        burstlen_memwr_desc34, \req_curr_state_ns_0_0_a3_1[1] , 
        \cfburst_len_wr_o_1_2_a2_3_3[0]_net_1 , N_7667, 
        \req_dstreg_data[6] , N_82_i, N_7780, N_7472, N_7906, N_7672, 
        N_7664, N_5562, N_7364, N_7362, N_7453, N_7446, N_7474, N_7919, 
        \cfdst_addr_o_iv_0[14]_net_1 , \cfburst_len_wr_o_1_2_a2_0[0] , 
        \resp_srcreg_data_m[4] , N_7687, burstlen_memwr_data_10_sqmuxa, 
        unreg_cmd5_29_net_1, unreg_cmd5_28_net_1, un1_m5_i_a3_0_2, 
        \cfdst_addr_o_iv_0_0[13]_net_1 , 
        \req_curr_state_ns_i_0_0[13]_net_1 , 
        un1_do_mem_wr32_2_0_0_0_net_1, un1_m1_e_0_0, 
        \req_curr_state_ns_i_0_a3_0_1[5] , 
        \req_next_state_i_a12_7_8[1]_net_1 , 
        \req_dstreg_data_0_iv_0[3]_net_1 , 
        \req_next_state_i_1_0_0_a2_1_2[5]_net_1 , 
        req_dstreg_data_2_sqmuxa_1_i_0_0_net_1, 
        \req_next_state_i_a12_3_4_2[1]_net_1 , 
        \req_curr_state_ns_0_0_a3_2[3]_net_1 , m2_e_25, m2_e_24, 
        N_7394, un1_req_curr_state_22_i_0, N_7891, N_7592, N_7531, 
        N_7577, resp_next_state102, burstlen_memwr_desc35, N_7434, 
        N_7433, N_7505, N_8077, N_7461, N_5193, 
        \resp_srcreg_addr_i_m[13] , N_5577, N_5697, N_7549, N_5133, 
        N_7436_2, N_7431, N_7430, m28, \cfdatain_o_iv_0[3]_net_1 , 
        cfburst_len_wr_o_1_2_250_tz_1, N_7722, N_5_0, 
        cfdatain_m4_0_a2_0, un1_m5_i_a3_0_4, 
        \cfdst_addr_o_iv_0_0[2]_net_1 , 
        \cfdst_addr_o_iv_0_0[16]_net_1 , 
        \cfdst_addr_o_iv_0_0[3]_net_1 , 
        \cfdst_addr_o_0_iv_0_1[29]_net_1 , cfrd_resp_o_i_i_0_net_1, 
        \cfsrc_addr_o_2_0[3]_net_1 , cfdatain_m1_0_a2_2_0, 
        un1_do_mem_wr32_2_0_0_1_net_1, 
        \req_curr_state_ns_i_0_1[5]_net_1 , un1_do_mem_wr32_1_0, 
        un1_latchen_hrdata_int_6_i_0_0_net_1, un1_m2_e_1, 
        \req_dstreg_data_0_iv_0[4]_net_1 , 
        un1_req_curr_state_24_0_a3_2_1_5_net_1, N_7421, 
        \req_next_state_i_a12_3_4[1]_net_1 , 
        \cfdatain_o_0_iv_0_a2_1_3[2]_net_1 , N_7627, N_7576, N_7503, 
        \resp_curr_state_ns_1_tz[3]_net_1 , 
        \resp_curr_state_ns_2[3]_net_1 , N_7506, 
        burstlen_memrd_data_1_sqmuxa_1, 
        \req_curr_state_ns_0_0_2[1]_net_1 , N_7488, N_7547, N_8080, 
        N_7963, N_7485, memwr_desc_5_sqmuxa, do_mem_wr27_s9, N_7445, 
        N_5300, N_8017_1, N_8084, m30_1, N_7492, unreg_cmd5_31_net_1, 
        un1_m5_i_a3_0_6, \cfdst_addr_o_iv_0_0[4]_net_1 , 
        \resp_curr_state_ns_0[3]_net_1 , 
        burstlen_memrd_data_1_sqmuxa_1_0_0_1_net_1, 
        \req_curr_state_ns_i_0_2[5]_net_1 , un1_do_mem_wr32_1_2_net_1, 
        \req_curr_state_ns_0_0_1[1]_net_1 , 
        \req_curr_state_ns_0_0_0[3]_net_1 , N_5709, N_5766, N_7640, 
        N_8002, memwr_desc_int46, memwr_desc_int47, N_23_mux, 
        set_sent_options_3_0_0_0_tz_net_1, N_7374, N_8000, N_8006_2, 
        N_7553, memwr_desc_int43, memwr_desc_int42, N_8079, N_7903, 
        N_8070, N_7974, N_4_0, memrd_data_addr_cnst_8ro, 
        cfdatain_m5_i_a3_0, un1_m5_i_a3_0_8, 
        \req_curr_state_ns_i_0_3[5]_net_1 , N_7498, N_7975, 
        \cfdatain_o_iv_1[4] , N_7563, N_7999, N_7447, 
        \cfdatain_o_0_iv_0_1[0] , \cfdatain_o_0_iv_0_0[2]_net_1 , 
        un1_m5_i_a3_0_9, \cfdatain_o_0_iv_0_2_0[13]_net_1 , 
        \cfdst_addr_o_iv_0_1[13]_net_1 , 
        \resp_curr_state_ns_2[8]_net_1 , 
        \resp_curr_state_ns_2_1[3]_net_1 , un1_N_5_mux_0, 
        cfdatain_o_iv_0_o2_2_out, N_4212, N_7965, N_8144, d_N_7, 
        \cfdatain_o_0_iv_0_1[2]_net_1 , un1_m5_i_a3_0_11, 
        \cfdatain_o_0_iv_0_2[13]_net_1 , N_7555, un1_m5_i_a3_0_12, 
        \cfdatain_o_0_iv_0_3_0[13] ;
    
    CFG3 #( .INIT(8'h72) )  \req_curr_state_ns_i_i[19]  (.A(
        \req_curr_state[19]_net_1 ), .B(fcbusreq_d1_net_1), .C(
        N_8136_1), .Y(\req_curr_state_ns_i_i[19]_net_1 ));
    CFG2 #( .INIT(4'h2) )  \cfsrc_addr_o_0_a2_1[13]  (.A(N_4413_i), .B(
        resp_curr_state_6), .Y(N_7456));
    CFG4 #( .INIT(16'hCE0A) )  un1_idle_trigger_4_i_a2_4_a4_0_o3 (.A(
        un1_idle_trigger_4_i_a2_4_a4_0_a2_0_net_1), .B(N_5345), .C(
        N_7670), .D(uclatchcmd_o[0]), .Y(N_7547));
    CFG4 #( .INIT(16'hFFFB) )  \req_dstreg_data_cnst_o4[4]  (.A(
        \req_curr_state[24]_net_1 ), .B(N_5194), .C(
        \req_curr_state[23]_net_1 ), .D(\req_curr_state[9]_net_1 ), .Y(
        \req_dstreg_data_cnst[4] ));
    SLE \cfdatain_d1[19]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[19]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[13]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[13]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[12]_net_1 ), .S(
        \desc_datasel_cntr_s[13] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[13]_net_1 ));
    CFG4 #( .INIT(16'h00E4) )  \cfsrc_addr_o_2_0[14]  (.A(N_4413_i), 
        .B(\resp_srcreg_addr[13]_net_1 ), .C(\cfsrc_addr_d1[14]_net_1 )
        , .D(resp_curr_state_6), .Y(\cfsrc_addr_o_2_0[14]_net_1 ));
    SLE \cfdatain_d1[22]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_14), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[22]_net_1 ));
    CFG4 #( .INIT(16'h33F5) )  \req_curr_state_RNI9FH21[10]  (.A(
        \req_curr_state[10]_net_1 ), .B(uclatchcmd_o[0]), .C(N_7806), 
        .D(N_7544_i), .Y(req_curr_state_RNI9FH21_0));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[22]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[22]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[21]_net_1 ), .S(
        \desc_datasel_cntr_s[22] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[22]_net_1 ));
    CFG4 #( .INIT(16'hCE0A) )  \resp_curr_state_ns[16]  (.A(
        \resp_curr_state[16]_net_1 ), .B(\resp_curr_state[17]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[16]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[16]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[16]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[15]_net_1 ), .S(
        \desc_datasel_cntr_s[16] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[16]_net_1 ));
    CFG4 #( .INIT(16'hDCCC) )  \cfdatain_o_0_iv_0[2]  (.A(
        un2_cudata_wrdy_int_9), .B(\cfdatain_o_0_iv_0_1[2]_net_1 ), .C(
        uclatchcmd_o[2]), .D(N_7544_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[2] ));
    CFG2 #( .INIT(4'h8) )  un1_main_curr_state_2_0_a3_2 (.A(N_7662), 
        .B(N_7674), .Y(un1_main_curr_state_2_0_a3_2_net_1));
    CFG4 #( .INIT(16'hBFFF) )  \req_curr_state_ns_i_o4[0]  (.A(
        req_phase_done_d1_net_1), .B(req_curr_state_0), .C(
        \main_curr_state[0]_net_1 ), .D(RSTSYNC1), .Y(N_5545));
    SLE fctrans_done_d1 (.D(fctrans_done_o), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(fctrans_done_d1_net_1));
    CFG4 #( .INIT(16'h0001) )  un1_cfburst_len_wr_o13_i_a2_0_3 (.A(
        \req_curr_state[26]_net_1 ), .B(\resp_curr_state[3]_net_1 ), 
        .C(RSTSYNC1), .D(\req_curr_state[5]_net_1 ), .Y(
        un1_cfburst_len_wr_o13_i_a2_0_3_net_1));
    CFG4 #( .INIT(16'hFEFF) )  \req_next_state_0_a12_0_i[0]  (.A(
        \req_curr_state[17]_net_1 ), .B(\req_curr_state[34]_net_1 ), 
        .C(N_5733_i_0), .D(fctrans_done_o), .Y(N_7783));
    CFG4 #( .INIT(16'h557F) )  cfwr_req_d_i_o2 (.A(txtokay_net_1), .B(
        mchready_i), .C(\req_curr_state[14]_net_1 ), .D(
        \req_curr_state[8]_net_1 ), .Y(N_7545));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[2]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[2]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[1]_net_1 ), .S(\desc_datasel_cntr_s[2] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[2]_net_1 ));
    CFG3 #( .INIT(8'h20) )  \cfdatain_o_0_iv_0_a2_1[23]  (.A(
        memwr_desc_int34), .B(N_7351_1), .C(cfdatain_o21), .Y(N_8064));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNIG1SL[28]  (.A(
        \desc_datasel_cntr[31]_net_1 ), .B(
        \desc_datasel_cntr[30]_net_1 ), .C(
        \desc_datasel_cntr[29]_net_1 ), .D(
        \desc_datasel_cntr[28]_net_1 ), .Y(m2_e_16));
    CFG4 #( .INIT(16'h8000) )  \cfsrc_addr_o_2_a2_0[12]  (.A(N_7685_i), 
        .B(N_7543_i), .C(N_32_mux), .D(N_7461), .Y(N_7421));
    CFG4 #( .INIT(16'hF8FF) )  \req_next_state_0_a12_0_i_RNIR74O[0]  (
        .A(fcbusreq_d1_net_1), .B(N_7800), .C(N_8136_1), .D(N_7783), 
        .Y(un1_m5_i_a3_0_4));
    CFG4 #( .INIT(16'h1000) )  \cfdst_addr_o_iv_0_a2[13]  (.A(
        memwr_data_addr_2_sqmuxa), .B(N_7556_i), .C(N_7351_1), .D(
        memwr_data_addr_3_sqmuxa), .Y(N_7934));
    CFG2 #( .INIT(4'hE) )  un1_burstlen_memwr_data132_1_0_o2 (.A(
        N_7543_i), .B(\req_curr_state[26]_net_1 ), .Y(N_7380));
    CFG4 #( .INIT(16'h0004) )  \req_next_state_i_a12_7_8[1]  (.A(
        \req_curr_state[7]_net_1 ), .B(N_7887), .C(N_7801), .D(N_7796), 
        .Y(\req_next_state_i_a12_7_8[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  cfdatain_o_iv_N_4L5 (.A(N_7894_i), .B(
        \cfdatain_d1[1]_net_1 ), .Y(cfdatain_o_iv_N_4L5_net_1));
    CFG4 #( .INIT(16'hCE0A) )  \req_curr_state_ns_0_0[21]  (.A(
        \req_curr_state[21]_net_1 ), .B(\req_curr_state[23]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \req_curr_state_ns[21] ));
    CFG3 #( .INIT(8'h31) )  \req_dstreg_data_cnst_m_RNIK7GT[29]  (.A(
        N_5111_i), .B(un2_cudata_wrdy_int_1_0), .C(
        \req_dstreg_data_cnst_m[29]_net_1 ), .Y(cfdatain_m4_e_0_1));
    CFG4 #( .INIT(16'h03AA) )  \resp_srcreg_data_d1_RNIMVLR[4]  (.A(
        \resp_srcreg_data_d1[4]_net_1 ), .B(
        \resp_curr_state[23]_net_1 ), .C(\resp_curr_state[21]_net_1 ), 
        .D(N_4425_i), .Y(g1_0));
    CFG3 #( .INIT(8'h80) )  burstlen_memrd_data_8_sqmuxa_0_a4 (.A(
        N_8049), .B(N_8052), .C(burstlen_memwr_desc34_2), .Y(N_8077));
    CFG4 #( .INIT(16'hAAEA) )  un2_cudata_wrdy_int_1_RNI88EK6 (.A(
        un2_cudata_wrdy_int_1_0), .B(
        un2_cudata_wrdy_int_4_i_a2_0_0_RNI99IC1_net_1), .C(mchready_i), 
        .D(syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(N_7894_i));
    SLE \cudata_r_o[24]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[24]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[24]));
    CFG2 #( .INIT(4'h8) )  
        \burstlen_memwr_data_cnst_4_2__burstlen_memwr_data_cnst_0_.m1  
        (.A(un1_burstlen_memwr_data130_1_i), .B(ucvalid_cmd_o), .Y(
        \burstlen_memwr_data_cnst[0] ));
    CFG2 #( .INIT(4'h8) )  do_mem_wr27_RNIFJBA (.A(do_mem_wr27_net_1), 
        .B(ucvalid_cmd_o), .Y(do_mem_wr27_s9));
    SLE set_puf_getkcnum (.D(set_puf_getkcnum_1002_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(set_puf_getkcnum_net_1));
    CFG3 #( .INIT(8'h04) )  \memrd_data_addr_cnst_8_0_.m13  (.A(
        N_5292_i), .B(N_5293_i), .C(N_7542_i), .Y(N_32_mux));
    CFG4 #( .INIT(16'h7250) )  \cfdatain_o_0_iv_0_RNO[0]  (.A(N_7894_i)
        , .B(N_8225), .C(cfdatain_d1_0), .D(cfdatain_m4_0_a2_0), .Y(
        \cfdatain_o_0_iv_0_1[0] ));
    CFG4 #( .INIT(16'hE000) )  \cfburst_len_wr_o_1_2_a2[1]  (.A(
        N_5354_i), .B(N_5293_i), .C(N_8080), .D(N_8076), .Y(N_8002));
    CFG2 #( .INIT(4'hD) )  un1_cutamper_fail_valid_8_i_a2_0_a2 (.A(
        N_4395_i), .B(\resp_curr_state[23]_net_1 ), .Y(N_4425_i));
    CFG4 #( .INIT(16'hFFBA) )  \resp_curr_state_ns[7]  (.A(
        \resp_curr_state_ns_1[7]_net_1 ), .B(N_7496), .C(
        \resp_curr_state[26]_net_1 ), .D(
        \resp_curr_state_ns_0[7]_net_1 ), .Y(
        \resp_curr_state_ns[7]_net_1 ));
    SLE \desc_datasel_cntr[14]  (.D(\desc_datasel_cntr_s[14] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[14]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \cfsrc_addr_o_2_a2_1_1[3]  (.A(
        do_mem_wr33_i_1_0), .B(\cfsrc_addr_o_2_a2_1_0[3]_net_1 ), .Y(
        \cfsrc_addr_o_2_a2_1_1[3]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \cfsrc_addr_o_2_a2_1[29]  (.A(do_mem_wr33), 
        .B(resp_curr_state_6), .C(N_8049), .Y(N_7461));
    CFG4 #( .INIT(16'hAEAA) )  \resp_curr_state_ns_0[7]  (.A(
        \resp_curr_state[27]_net_1 ), .B(\resp_curr_state[2]_net_1 ), 
        .C(rcvokay_net_1), .D(idle_trigger), .Y(
        \resp_curr_state_ns_0[7]_net_1 ));
    SLE custatus_valid_o_inst_1 (.D(custatus_valid_o5_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(custatus_valid_o));
    CFG4 #( .INIT(16'h0CAA) )  \resp_srcreg_data_d1_RNIOD0V[3]  (.A(
        \resp_srcreg_data_d1[3]_net_1 ), .B(
        \resp_curr_state[18]_net_1 ), .C(req_dstreg_data20), .D(
        N_4425_i), .Y(\resp_srcreg_data_0[3] ));
    CFG2 #( .INIT(4'h2) )  resp_phase_active_pulse_2 (.A(
        resp_phase_active_i_i_net_1), .B(resp_phase_active_d1_net_1), 
        .Y(resp_phase_active_pulse_2_net_1));
    CFG3 #( .INIT(8'h02) )  cfdatain_o26_0_a2 (.A(mchready_i), .B(
        cfdatain_o26_0_a2_sx_net_1), .C(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(cfdatain_o26));
    CFG4 #( .INIT(16'h0105) )  \req_curr_state_RNO[5]  (.A(N_7584), .B(
        \req_curr_state_ns_i_0_a3_0_1[5] ), .C(
        \req_curr_state_ns_i_0_3[5]_net_1 ), .D(N_7563), .Y(N_5492_i));
    SLE \cfdatain_d1[18]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[18]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[15]  (.A(
        \cfburst_len_rd_d1[15]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[15]));
    CFG2 #( .INIT(4'hD) )  N_5727_i_0_o2_0 (.A(N_5322_i), .B(
        uclatchcmd_o[1]), .Y(N_7790));
    CFG2 #( .INIT(4'h4) )  resp_phase_done_pulse_2 (.A(resp_phase_done)
        , .B(resp_phase_done_d1_net_1), .Y(
        resp_phase_done_pulse_2_net_1));
    CFG4 #( .INIT(16'h1000) )  cfdst_addr_o34_0_a3 (.A(
        \resp_curr_state[23]_net_1 ), .B(\req_curr_state[6]_net_1 ), 
        .C(N_7462), .D(\resp_curr_state[21]_net_1 ), .Y(cfdst_addr_o34)
        );
    SLE \req_curr_state[23]  (.D(\req_curr_state_ns_i_i[23]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[23]_net_1 )
        );
    CFG2 #( .INIT(4'h4) )  \resp_curr_state_ns_o2_10_a2_0_a2_0_a2[3]  
        (.A(uclatchcmd_o[2]), .B(uclatchcmd_o[4]), .Y(N_5332));
    CFG3 #( .INIT(8'hFE) )  \req_next_state_i_a12_3_1_0_i_o2_2[1]  (.A(
        \req_curr_state[10]_net_1 ), .B(\req_curr_state[9]_net_1 ), .C(
        \req_curr_state[6]_net_1 ), .Y(N_7794));
    CFG4 #( .INIT(16'hCECC) )  un1_do_mem_wr32_2_0_0_1 (.A(N_7457), .B(
        burstlen_memwr_desc35), .C(N_7542_i), .D(N_6101_2), .Y(
        un1_do_mem_wr32_2_0_0_1_net_1));
    CFG2 #( .INIT(4'h2) )  \resp_curr_state_ns_i_0_a2_0[26]  (.A(
        fctrans_done_o), .B(fcbusreq_d1_net_1), .Y(N_7536));
    CFG3 #( .INIT(8'h04) )  \cfburst_len_wr_o_1_2_a2_4[2]  (.A(
        N_7542_i), .B(N_5293_i), .C(N_5354_i), .Y(N_8088));
    CFG4 #( .INIT(16'hF1FB) )  \burstlen_memrd_data_i_o2_0[4]  (.A(
        ucvalid_cmd_o), .B(\burstlen_memrd_data_d1[4]_net_1 ), .C(
        burstlen_memrd_data_6_sqmuxa), .D(burstlen_memrd_data_8_sqmuxa)
        , .Y(\burstlen_memrd_data_i_o2_0[4]_net_1 ));
    SLE \cfdatain_d1[12]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[12] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[12]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \cfdatain_o_iv_0_a2_4_RNO_0[29]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[1]_net_1 )
        , .C(N_4_0), .D(\desc_datasel_cntr[2]_net_1 ), .Y(
        memwr_desc_int47));
    CFG4 #( .INIT(16'hFFFE) )  un1_cfdatain_o26 (.A(cfdatain_o28), .B(
        cfdatain_o27), .C(cfdatain_o29), .D(cfdatain_o26), .Y(N_8225));
    CFG3 #( .INIT(8'h08) )  \resp_curr_state_ns_a2_1[13]  (.A(
        \resp_curr_state[3]_net_1 ), .B(idle_trigger), .C(N_7469), .Y(
        \resp_curr_state_ns_a2_1[13]_net_1 ));
    CFG4 #( .INIT(16'hF5FD) )  \resp_srcreg_addr_0_iv[2]  (.A(N_4389_i)
        , .B(\resp_curr_state[4]_net_1 ), .C(
        \resp_srcreg_addr_d1_m[2]_net_1 ), .D(req_dstreg_data20), .Y(
        \resp_srcreg_addr[2] ));
    CFG2 #( .INIT(4'h4) )  \resp_srcreg_data_d1_RNO[3]  (.A(
        req_dstreg_data20), .B(\resp_curr_state[18]_net_1 ), .Y(
        N_4185_i));
    CFG4 #( .INIT(16'h88F8) )  \req_curr_state_ns_0_0[35]  (.A(
        \req_curr_state_ns_0_0_a3_0_0[35]_net_1 ), .B(N_5697), .C(
        \req_curr_state[35]_net_1 ), .D(fctrans_done_d1_net_1), .Y(
        \req_curr_state_ns[35] ));
    CFG2 #( .INIT(4'h1) )  un1_req_curr_state_21_0_a2_0_3 (.A(
        \resp_curr_state[16]_net_1 ), .B(\resp_curr_state[18]_net_1 ), 
        .Y(N_4394_i));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[30]  (.A(cfdatain_d1_30), 
        .B(memwr_desc_int_m_19), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[30] ));
    SLE \resp_curr_state[15]  (.D(\resp_curr_state[14]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[15]_net_1 ));
    CFG4 #( .INIT(16'hBA00) )  \cfdatain_o_iv_0_o2_3_s_0[29]  (.A(
        N_8079), .B(N_7894_i), .C(\cfdatain_d1[29]_net_1 ), .D(
        \cfdatain_o_iv_0_a2_2_0[29]_net_1 ), .Y(
        \cfdatain_o_iv_0_o2_3_s_0[29]_net_1 ));
    CFG3 #( .INIT(8'hB3) )  un1_latchen_hrdata_int_6_i_0_0 (.A(
        N_5331_i), .B(resp_next_state102), .C(N_7711_2), .Y(
        un1_latchen_hrdata_int_6_i_0_0_net_1));
    SLE cfwr_req_o_inst_1 (.D(N_7595_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfwr_req_o));
    CFG3 #( .INIT(8'h1B) )  \req_next_state_i_a12_3_1_0_i_o2_5_1_1[1]  
        (.A(\req_curr_state[12]_net_1 ), .B(N_7804), .C(
        fctrans_done_d1_net_1), .Y(
        \req_next_state_i_a12_3_1_0_i_o2_5_1_1[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \resp_curr_state_ns_0_a2_0_0[25]  (.A(
        cmdrcv_net_1), .B(\resp_curr_state[2]_net_1 ), .Y(
        \resp_curr_state_ns_0_a2_0_0[25]_net_1 ));
    SLE \resp_curr_state[27]  (.D(N_7483_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[27]_net_1 ));
    SLE unreg_cmd (.D(unreg_cmd_1005_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(unreg_cmd_net_1));
    CFG2 #( .INIT(4'h1) )  \resp_srcreg_data_cnst_a2[4]  (.A(
        \resp_curr_state[21]_net_1 ), .B(\resp_curr_state[23]_net_1 ), 
        .Y(\resp_srcreg_data_cnst[4] ));
    SLE \desc_datasel_cntr[27]  (.D(\desc_datasel_cntr_s[27] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[27]_net_1 ));
    SLE \resp_curr_state[28]  (.D(\resp_curr_state_ns_i_i[28]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[28]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_0_0_a3[7]  (.A(
        fctrans_done_o), .B(\req_curr_state[10]_net_1 ), .Y(N_8119));
    SLE cucmd_error (.D(main_curr_state_5371_d), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_main_curr_state_4_0_net_1), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cucmd_error_net_1));
    CFG4 #( .INIT(16'hA0EC) )  \req_curr_state_ns_0_0[2]  (.A(
        \req_curr_state[1]_net_1 ), .B(\req_curr_state[2]_net_1 ), .C(
        fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \req_curr_state_ns[2] ));
    CFG4 #( .INIT(16'hDDD5) )  req_dstreg_data_2_sqmuxa_1_i_0_0 (.A(
        \req_curr_state[12]_net_1 ), .B(N_7656_1), .C(N_5331_i), .D(
        N_5322_i), .Y(req_dstreg_data_2_sqmuxa_1_i_0_0_net_1));
    CFG4 #( .INIT(16'h0450) )  \cfburst_len_wr_o_1_2_o4[1]  (.A(
        N_7685_i), .B(N_7543_i), .C(N_5292_i), .D(N_5354_i), .Y(N_7906)
        );
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[21]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[21]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[20]_net_1 ), .S(
        \desc_datasel_cntr_s[21] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[21]_net_1 ));
    CFG4 #( .INIT(16'hFFDF) )  N_5727_i_0_o2 (.A(uclatchcmd_o[2]), .B(
        uclatchcmd_o[1]), .C(N_5322_i), .D(uclatchcmd_o[0]), .Y(N_7792)
        );
    CFG4 #( .INIT(16'h8000) )  \cfdatain_o_iv_0_0_RNO[29]  (.A(N_7450), 
        .B(N_8082), .C(N_7465), .D(N_8049), .Y(memwr_desc_5_sqmuxa));
    CFG2 #( .INIT(4'h7) )  burstlen_memwr_desc37_1_i_o2 (.A(N_7542_i), 
        .B(N_5293_i), .Y(N_7388));
    CFG4 #( .INIT(16'hECCC) )  burstlen_memrd_data_8_sqmuxa_0_0 (.A(
        burstlen_memrd_data_8_sqmuxa_0_a2_1_net_1), .B(N_8077), .C(
        N_7542_i), .D(N_8049), .Y(burstlen_memrd_data_8_sqmuxa));
    CFG3 #( .INIT(8'hB8) )  rcvokay_999 (.A(
        syssvc_blk_0_AHBL_MASTER_HRDATA[1]), .B(mchready_i), .C(
        rcvokay_net_1), .Y(rcvokay_999_net_1));
    CFG4 #( .INIT(16'h0007) )  \burstlen_memrd_data_d1_RNO[5]  (.A(
        do_mem_wr33), .B(ucvalid_cmd_o), .C(
        \burstlen_memrd_data_i_o2_0[5]_net_1 ), .D(
        burstlen_memrd_data_4_sqmuxa), .Y(N_7917_i));
    CFG3 #( .INIT(8'h23) )  cfdatain_o_iv_0_7_N_7L13 (.A(
        cfdatain_o_iv_0_7_N_5L9_net_1), .B(N_7948), .C(
        \cfdatain_o_iv_0_a2_2_0[29]_net_1 ), .Y(
        cfdatain_o_iv_0_7_N_7L13_net_1));
    SLE \cfburst_len_wr_d1[4]  (.D(cfburst_len_wr_o[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[4]_net_1 ));
    CFG3 #( .INIT(8'h54) )  cmd_error_f0_0_a3 (.A(resp_curr_state_0), 
        .B(N_7482_i), .C(cmd_error_d1_net_1), .Y(cmd_error));
    CFG4 #( .INIT(16'hFF80) )  \req_curr_state_ns_0_0[18]  (.A(
        \req_curr_state[8]_net_1 ), .B(txtokay_net_1), .C(idle_trigger)
        , .D(\req_curr_state_ns_0_0_1[18]_net_1 ), .Y(
        \req_curr_state_ns[18] ));
    SLE \cfdatain_d1[23]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[23]_net_1 ));
    CFG2 #( .INIT(4'hD) )  \memwr_data_addr_cnst_0_0[13]  (.A(N_7351_1)
        , .B(memwr_data_addr_2_sqmuxa), .Y(\memwr_data_addr_cnst[13] ));
    CFG4 #( .INIT(16'hBA30) )  \req_curr_state_ns_0_0_0[12]  (.A(
        \req_curr_state[21]_net_1 ), .B(fctrans_done_d1_net_1), .C(
        \req_curr_state[12]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_0_0_0[12]_net_1 ));
    CFG2 #( .INIT(4'h7) )  cfrd_resp_o_i_i_o2_2 (.A(idle_trigger), .B(
        \resp_curr_state[4]_net_1 ), .Y(N_7381));
    SLE \cfburst_len_wr_d1[2]  (.D(cfburst_len_wr_o[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[2]_net_1 ));
    CFG4 #( .INIT(16'h0010) )  unreg_cmd5_22 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[0]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[10]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[5]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[9]), .Y(unreg_cmd5_22_net_1));
    CFG4 #( .INIT(16'h1000) )  \resp_curr_state_ns_o2_10_a4[3]  (.A(
        set_puf_getkcnum_net_1), .B(uclatchcmd_o[1]), .C(
        \resp_curr_state_ns_o2_10_a4_1[3]_net_1 ), .D(N_5134_i_0), .Y(
        N_5305));
    CFG4 #( .INIT(16'h8000) )  burstlen_memwr_desc35_0_a2 (.A(N_5354_i)
        , .B(burstlen_memwr_desc35_1), .C(N_7465), .D(N_7450), .Y(
        burstlen_memwr_desc35));
    CFG4 #( .INIT(16'hFFF8) )  \cfburst_len_wr_o_1_2[2]  (.A(N_8006_2), 
        .B(N_5), .C(N_8000), .D(N_7999), .Y(cfburst_len_wr_o[2]));
    CFG3 #( .INIT(8'h80) )  burstlen_memrd_data_3_sqmuxa_1 (.A(
        N_7542_i), .B(ucvalid_cmd_o), .C(N_5354_i), .Y(
        burstlen_memrd_data_3_sqmuxa_1_net_1));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_6_sqmuxa_0_a2 (.A(
        ucnrbg_length_o_0), .B(N_7455), .C(N_8082), .D(N_7453), .Y(
        burstlen_memrd_data_6_sqmuxa));
    CFG4 #( .INIT(16'h0197) )  \memrd_data_addr_cnst_8_0_.m28  (.A(
        N_5293_i), .B(N_5292_i), .C(N_7542_i), .D(N_5354_i), .Y(m28));
    CFG2 #( .INIT(4'h4) )  \resp_srcreg_addr_d1_m[2]  (.A(N_4294_i), 
        .B(\resp_srcreg_addr_d1[2]_net_1 ), .Y(
        \resp_srcreg_addr_d1_m[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_RNIU89T[11]  (.A(N_7544_i), 
        .B(N_7670), .Y(N_4_0_0));
    CFG4 #( .INIT(16'h20EC) )  \resp_curr_state_RNO[6]  (.A(
        resp_curr_state_5), .B(resp_curr_state_6), .C(
        fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(N_4115_i));
    SLE \memwr_data_addr_r[29]  (.D(\memwr_data_addr_cnst[29] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(memwr_data_addr_3_sqmuxa), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \memwr_data_addr_r[29]_net_1 ));
    CFG4 #( .INIT(16'hE0F0) )  \req_curr_state_RNO[34]  (.A(
        \req_curr_state[35]_net_1 ), .B(\req_curr_state[34]_net_1 ), 
        .C(N_7566), .D(N_5697), .Y(N_5531_i));
    SLE \req_curr_state[17]  (.D(\req_curr_state_ns_i_i[17]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[17]_net_1 )
        );
    CFG3 #( .INIT(8'h20) )  \burstlen_memrd_data[6]  (.A(N_6075), .B(
        burstlen_memrd_data_6_sqmuxa), .C(burstlen_memrd_data_sn_N_6), 
        .Y(\burstlen_memrd_data[6]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  un1_req_phase_done_d1_1_i_a4_0_a3 (.A(
        uclatchcmd_o[3]), .B(N_5345), .C(uclatchcmd_o[1]), .D(
        uclatchcmd_o[0]), .Y(N_5299_i));
    CFG4 #( .INIT(16'h0200) )  un1_req_curr_state_21_0_a2_2 (.A(
        N_5310_2), .B(\req_curr_state[12]_net_1 ), .C(N_7801), .D(
        N_4394_i), .Y(un1_req_curr_state_21_0_a2_2_net_1));
    CFG2 #( .INIT(4'hE) )  set_puf_getkcnum_RNI98OP (.A(
        set_puf_getkcnum_net_1), .B(uclatchcmd_o[4]), .Y(N_5292_i));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[11]  (.A(
        \cfburst_len_rd_d1[11]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[11]));
    SLE \cudata_r_o[3]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[3]));
    CFG4 #( .INIT(16'h2000) )  \memwr_desc_0_a2_0[317]  (.A(N_7448), 
        .B(N_7388), .C(N_7450), .D(N_8049), .Y(N_7431));
    CFG4 #( .INIT(16'h3133) )  un1_do_mem_wr32_1_0_0 (.A(N_7457), .B(
        burstlen_memwr_desc35), .C(N_7542_i), .D(N_6101_2), .Y(
        un1_do_mem_wr32_1_0));
    SLE reset_puf_getkcnum (.D(main_curr_state_5371_d), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_main_curr_state_1_0_net_1), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        reset_puf_getkcnum_net_1));
    SLE \burstlen_memwr_data_r[4]  (.D(\burstlen_memwr_data[4]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memwr_data_r[4]_net_1 ));
    SLE \req_curr_state[24]  (.D(\req_curr_state_ns_i_i[24]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[24]_net_1 )
        );
    CFG4 #( .INIT(16'hA2A0) )  cfrd_resp_o_i_i_a2_4 (.A(N_8049), .B(
        N_7543_i), .C(N_7445), .D(N_7362), .Y(N_7447));
    CFG4 #( .INIT(16'hF9F1) )  \memrd_data_addr_cnst_8_0_.m15  (.A(
        N_7685_i), .B(m15_1_0), .C(m15_2), .D(m7), .Y(m15));
    SLE \cfburst_len_wr_d1[3]  (.D(cfburst_len_wr_o[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \desc_datasel_cntr_RNIEC7I5[2]  (.A(
        memwr_desc_int34), .B(ucvalid_cmd_o), .Y(g1_0_1_0));
    CFG4 #( .INIT(16'hC0EA) )  \resp_curr_state_ns[13]  (.A(
        \resp_curr_state[13]_net_1 ), .B(
        \resp_curr_state_ns_a2_1[13]_net_1 ), .C(N_4212), .D(
        mchready_i), .Y(\resp_curr_state_ns[13]_net_1 ));
    CFG3 #( .INIT(8'hCE) )  \resp_curr_state_ns_0[17]  (.A(
        \resp_curr_state[17]_net_1 ), .B(\resp_curr_state[1]_net_1 ), 
        .C(fcbusreq_d1_net_1), .Y(\resp_curr_state_ns[17] ));
    SLE \desc_datasel_cntr[25]  (.D(\desc_datasel_cntr_s[25] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[25]_net_1 ));
    CFG4 #( .INIT(16'h13FF) )  \req_next_state_i_a12_0_1_i[1]  (.A(
        rcvokay_net_1), .B(txtokay_net_1), .C(cmdrcv_net_1), .D(
        idle_trigger), .Y(N_7780));
    CFG4 #( .INIT(16'hFFF8) )  \req_next_state_i_1_0_0_a2_1[5]  (.A(
        N_7790), .B(\req_curr_state[4]_net_1 ), .C(
        \req_next_state_i_1_0_0_a2_1_3[5]_net_1 ), .D(
        \req_next_state_i_1_0_0_a2_1_2[5]_net_1 ), .Y(N_5709));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_0_0_a3_0_0[35]  (.A(
        fcbusreq_d1_net_1), .B(\req_curr_state[22]_net_1 ), .Y(
        \req_curr_state_ns_0_0_a3_0_0[35]_net_1 ));
    SLE \resp_srcreg_addr_d1[4]  (.D(N_7379), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_addr_d1[4]_net_1 ));
    CFG4 #( .INIT(16'hF3F1) )  \resp_curr_state_ns_2_1[3]  (.A(N_7722), 
        .B(N_7688), .C(\resp_curr_state_ns_0[3]_net_1 ), .D(
        \resp_curr_state_ns_1_tz[3]_net_1 ), .Y(
        \resp_curr_state_ns_2_1[3]_net_1 ));
    CFG4 #( .INIT(16'h5551) )  \req_curr_state_RNO[25]  (.A(
        \req_curr_state_ns_i_0_1[25]_net_1 ), .B(N_5697), .C(
        \req_curr_state[34]_net_1 ), .D(\req_curr_state[25]_net_1 ), 
        .Y(N_5519_i));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[20]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[20]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[19]_net_1 ), .S(
        \desc_datasel_cntr_s[20] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[20]_net_1 ));
    CFG3 #( .INIT(8'hEA) )  \cfsrc_addr_o_2[14]  (.A(
        \cfsrc_addr_o_2_0[14]_net_1 ), .B(memrd_data_addr_cnst_7ro), 
        .C(N_7461), .Y(cfsrc_addr_o_12));
    CFG4 #( .INIT(16'h53F3) )  \cfburst_len_wr_o_1_2_m2_1[0]  (.A(
        N_4863_i), .B(\cfburst_len_wr_d1[0]_net_1 ), .C(N_7481_i), .D(
        N_5010_i), .Y(\cfburst_len_wr_o_1_2_m2_1[0]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  un1_resp_curr_state_8_i_a2_0_a2 (.A(
        \resp_curr_state[4]_net_1 ), .B(\resp_curr_state[3]_net_1 ), 
        .C(N_4389_i), .D(N_7515), .Y(N_4413_i));
    CFG4 #( .INIT(16'h22F2) )  \req_curr_state_ns_0_0[20]  (.A(
        \req_curr_state_ns_0_0_a2_0_0[20]_net_1 ), .B(N_5207_2), .C(
        \req_curr_state[20]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[20] ));
    SLE \desc_datasel_cntr[18]  (.D(\desc_datasel_cntr_s[18] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[18]_net_1 ));
    SLE \cfsrc_addr_d1[2]  (.D(cfsrc_addr_o_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[2]_net_1 ));
    CFG2 #( .INIT(4'h1) )  cfdatain_o_iv_0_7_N_6L11 (.A(
        memwr_desc_int34), .B(memwr_desc_int35), .Y(
        cfdatain_o_iv_0_7_N_6L11_net_1));
    CFG4 #( .INIT(16'h0040) )  un2_cudata_wrdy_int_1_RNIQFD2C (.A(
        un2_cudata_wrdy_int_1_0), .B(N_9_0_0), .C(N_7894_i), .D(N_8225)
        , .Y(N_10_0_0));
    SLE \cudata_r_o[5]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[5]));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[13]  (.A(
        \cfburst_len_rd_d1[13]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[13]));
    CFG4 #( .INIT(16'hF808) )  \burstlen_memwr_data[4]  (.A(
        burstlen_memwr_data_12_sqmuxa), .B(
        \burstlen_memwr_data_r[4]_net_1 ), .C(
        burstlen_memwr_data_sn_N_6_mux), .D(
        \burstlen_memwr_data_cnst[4] ), .Y(
        \burstlen_memwr_data[4]_net_1 ));
    CFG3 #( .INIT(8'h10) )  \cfburst_len_wr_o_1_2_a2_2[2]  (.A(
        N_7685_i), .B(N_7543_i), .C(N_7542_i), .Y(N_8076));
    CFG4 #( .INIT(16'h0302) )  \req_curr_state_RNIKNN74[24]  (.A(
        \req_curr_state[24]_net_1 ), .B(N_7806), .C(N_7544_i), .D(
        g2_0_1), .Y(g0_10_1));
    CFG4 #( .INIT(16'hECA0) )  \req_curr_state_ns_0[8]  (.A(
        \req_curr_state[17]_net_1 ), .B(\req_curr_state[8]_net_1 ), .C(
        fcbusreq_d1_net_1), .D(N_7780), .Y(\req_curr_state_ns[8] ));
    CFG2 #( .INIT(4'hE) )  \resp_srcreg_addr[13]  (.A(N_4294_i), .B(
        \resp_srcreg_addr_d1[13]_net_1 ), .Y(
        \resp_srcreg_addr[13]_net_1 ));
    SLE \cudata_r_o[30]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[30]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[30]));
    CFG3 #( .INIT(8'h02) )  cfdatain_o29_0_a2_a0 (.A(mchready_i), .B(
        cfdatain_o29_0_a2_a0_sx_net_1), .C(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(cfdatain_o29));
    SLE \cfsrc_addr_d1[4]  (.D(N_7352_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[4]_net_1 ));
    CFG4 #( .INIT(16'h0040) )  \req_curr_state_ns_0_0_a3_3[1]  (.A(
        N_5545), .B(N_7662), .C(N_7672), .D(N_7550), .Y(N_7577));
    CFG4 #( .INIT(16'h4000) )  un1_burstlen_memwr_data130_1_0_a2_0 (.A(
        N_5354_i), .B(burstlen_memwr_desc35_1), .C(N_7455), .D(N_7450), 
        .Y(N_7397));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[8]  (.A(
        \cfburst_len_rd_d1[8]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[8]));
    CFG2 #( .INIT(4'h1) )  \req_curr_state_RNI9LS7_0[27]  (.A(
        \req_curr_state[4]_net_1 ), .B(\req_curr_state[27]_net_1 ), .Y(
        N_7556_i));
    CFG4 #( .INIT(16'h0800) )  un1_fctrans_done_i_0_a2 (.A(
        set_puf_getkcnum_net_1), .B(fctrans_done_o), .C(
        reset_puf_getkcnum_net_1), .D(resp_curr_state_0), .Y(
        un1_fctrans_done_i_i));
    SLE \req_curr_state[12]  (.D(\req_curr_state_ns[12] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[12]_net_1 )
        );
    CFG2 #( .INIT(4'h7) )  \req_next_state_i_a12_6_i_0[1]  (.A(
        fctrans_done_o), .B(\req_curr_state[2]_net_1 ), .Y(
        \req_next_state_i_a12_6_i_0[1]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \req_curr_state_ns_0_0_a2_0_1[28]  (.A(
        txtokay_net_1), .B(idle_trigger), .C(\req_curr_state[8]_net_1 )
        , .Y(\req_curr_state_ns_0_0_a2_0_1[28]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \req_curr_state_ns_0_0_0[3]  (.A(N_7672)
        , .B(\req_curr_state_ns_0_0_a3_2[3]_net_1 ), .C(
        \req_curr_state[3]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_0_0_0[3]_net_1 ));
    CFG3 #( .INIT(8'h7D) )  g0_9_o3_0_0 (.A(uclatchcmd_o[2]), .B(
        uclatchcmd_o[0]), .C(uclatchcmd_o[1]), .Y(g0_9_o3_0_0_net_1));
    CFG4 #( .INIT(16'h8F88) )  \cfdatain_o_0_iv_0_o2[5]  (.A(
        memwr_desc_int35), .B(do_mem_wr26_s8), .C(N_7351_1), .D(
        memwr_desc_int34), .Y(N_7903));
    CFG4 #( .INIT(16'h0400) )  \req_next_state_i_a12_3_4[1]  (.A(
        N_7801), .B(\req_next_state_i_a12_3_4_2[1]_net_1 ), .C(
        \req_curr_state[7]_net_1 ), .D(N_7887), .Y(
        \req_next_state_i_a12_3_4[1]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[14]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[14]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[13]_net_1 ), .S(
        \desc_datasel_cntr_s[14] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[14]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \cfdatain_o_0_iv_0[13]  (.A(N_5111_i), 
        .B(N_7345), .C(\cfdatain_o_0_iv_0_2[13]_net_1 ), .D(
        un2_cudata_wrdy_int_9), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[13] ));
    CFG4 #( .INIT(16'hACA0) )  \burstlen_memwr_data[2]  (.A(
        burstlen_memwr_data_10_sqmuxa), .B(
        \burstlen_memwr_data_r[2]_net_1 ), .C(
        burstlen_memwr_data_sn_N_6_mux), .D(
        burstlen_memwr_data_12_sqmuxa), .Y(
        \burstlen_memwr_data[2]_net_1 ));
    CFG4 #( .INIT(16'hFEFC) )  \req_curr_state_ns_0_0[7]  (.A(
        \req_curr_state[7]_net_1 ), .B(\req_curr_state[32]_net_1 ), .C(
        N_8119), .D(N_7689), .Y(\req_curr_state_ns[7] ));
    SLE \cfburst_len_rd_d1[10]  (.D(cfburst_len_rd_o[10]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[10]_net_1 ));
    CFG4 #( .INIT(16'h3310) )  cfrd_resp_o_i_i_a2_8 (.A(N_5354_i), .B(
        N_7685_i), .C(N_108_i), .D(N_7441), .Y(N_7445));
    SLE \resp_curr_state[8]  (.D(\resp_curr_state_ns[8]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[8]_net_1 )
        );
    SLE \desc_datasel_cntr[6]  (.D(\desc_datasel_cntr_s[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[6]_net_1 ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[10]  (.A(
        \cfdatain_d1[10]_net_1 ), .B(ucnrbg_handle_o[2]), .C(N_8070), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_2));
    CFG4 #( .INIT(16'hFBF0) )  \cfdst_addr_o_iv_0[3]  (.A(N_7690), .B(
        \req_dstreg_addr_i_a4_0[3]_net_1 ), .C(
        \cfdst_addr_o_iv_0_0[3]_net_1 ), .D(un1_req_curr_state_22_i_0), 
        .Y(cfdst_addr_o_1));
    CFG4 #( .INIT(16'hFEFA) )  \req_curr_state_RNIQGJK[10]  (.A(
        \req_curr_state[10]_net_1 ), .B(\req_curr_state[11]_net_1 ), 
        .C(\req_curr_state[25]_net_1 ), .D(set_puf_getkcnum_net_1), .Y(
        g2_1));
    CFG4 #( .INIT(16'hAE0C) )  \req_curr_state_ns_0_0[27]  (.A(
        \req_curr_state[26]_net_1 ), .B(\req_curr_state[27]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[27] ));
    GND GND (.Y(GND_net_1));
    SLE resp_phase_active_pulse (.D(resp_phase_active_pulse_2_net_1), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        resp_phase_active_pulse_net_1));
    CFG2 #( .INIT(4'hE) )  \req_dstreg_data_cnst_o4_i_o2[1]  (.A(
        \req_curr_state[25]_net_1 ), .B(\req_curr_state[10]_net_1 ), 
        .Y(N_7690));
    SLE \cfdatain_d1[13]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[13] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[13]_net_1 ));
    SLE \resp_curr_state[29]  (.D(N_7521_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[29]_net_1 ));
    CFG3 #( .INIT(8'hDF) )  \memwr_desc_addr_i_0[13]  (.A(
        memrd_data_addr_cnst_7ro), .B(N_7543_i), .C(N_8049), .Y(N_7345)
        );
    CFG3 #( .INIT(8'h32) )  datawr_reqd_0_a2_RNIGOICF (.A(datawr_reqd), 
        .B(un1_m5_i_a3_0_12), .C(\req_next_state_i_a12_6_i_0[1]_net_1 )
        , .Y(datawr_reqd_0_a2_RNIGOICF_net_1));
    CFG4 #( .INIT(16'hAB03) )  \memrd_data_addr_cnst_8_0_.m7  (.A(m7_1)
        , .B(N_7685_i), .C(m7_1_0), .D(m1), .Y(m7));
    CFG4 #( .INIT(16'hCC8C) )  cudata_wrdy_d1_RNI2JKU (.A(
        \req_curr_state[5]_net_1 ), .B(cudata_wrdy_d1_net_1), .C(
        burstlen_memwr_data110), .D(\req_curr_state[2]_net_1 ), .Y(
        cfdatain_o21));
    CFG2 #( .INIT(4'h7) )  burstlen_memwr_data_6_sqmuxa_i_0_1 (.A(
        do_mem_wr25), .B(ucvalid_cmd_o), .Y(N_7351_1));
    CFG3 #( .INIT(8'h02) )  cfdatain_o28_1 (.A(mchready_i), .B(
        cfdatain_o28_1_sx_net_1), .C(syssvc_blk_0_AHBL_MASTER_HRESP_0), 
        .Y(cfdatain_o28));
    CFG3 #( .INIT(8'hF8) )  \req_next_state_i_1_0_0_2[5]  (.A(
        fctrans_done_d1_net_1), .B(\req_curr_state[25]_net_1 ), .C(
        req_curr_state_0), .Y(N_5709_1_0_2));
    CFG3 #( .INIT(8'h90) )  un1_uchprior_flushreq_i_2_i_0_o3 (.A(
        reset_puf_getkcnum_net_1), .B(set_puf_getkcnum_net_1), .C(
        resp_phase_done_pulse_net_1), .Y(N_8105));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[0]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[0]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        desc_datasel_cntr_s_810_FCO), .S(\desc_datasel_cntr_s[0] ), .Y(
        ), .FCO(\desc_datasel_cntr_cry[0]_net_1 ));
    CFG4 #( .INIT(16'h00E4) )  \cfsrc_addr_o_0[13]  (.A(N_4413_i), .B(
        \resp_srcreg_addr[13]_net_1 ), .C(\cfsrc_addr_d1[13]_net_1 ), 
        .D(resp_curr_state_6), .Y(cfsrc_addr_o_11));
    SLE \cfburst_len_rd_d1[9]  (.D(cfburst_len_rd_o[9]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[9]_net_1 ));
    CFG4 #( .INIT(16'hFF80) )  \req_curr_state_ns_0_0[22]  (.A(
        \req_curr_state_ns_0_0_a2_1_1[22]_net_1 ), .B(
        \req_curr_state_ns_0_0_a2_1_2[22]_net_1 ), .C(N_7711_2), .D(
        \req_curr_state_ns_0_0_0[22]_net_1 ), .Y(
        \req_curr_state_ns[22] ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[17]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[17]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[16]_net_1 ), .S(
        \desc_datasel_cntr_s[17] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[17]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \req_curr_state_ns_0_a3_0_2_i_o2[30]  (.A(
        mchready_i), .B(\req_curr_state[14]_net_1 ), .Y(N_5207_2));
    CFG4 #( .INIT(16'h8000) )  do_mem_wr27_RNIRD9V6 (.A(
        memwr_desc_int34), .B(do_mem_wr27_s9), .C(ucnrbg_handle_o[3]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_0));
    CFG4 #( .INIT(16'h3B33) )  \cfburst_len_wr_o_1_2_m2[0]  (.A(
        N_7481_i), .B(\cfburst_len_wr_o_1_2_m2_1[0]_net_1 ), .C(
        cfburst_len_wr_o_1_sn_N_3), .D(\burstlen_memwr_data[0]_net_1 ), 
        .Y(N_7920));
    CFG3 #( .INIT(8'hF2) )  \req_curr_state_ns_0_0[26]  (.A(
        \req_curr_state[26]_net_1 ), .B(fcbusreq_d1_net_1), .C(N_7627), 
        .Y(\req_curr_state_ns[26] ));
    CFG4 #( .INIT(16'h0004) )  \req_next_state_0_a12_1_a2[0]  (.A(
        \req_curr_state[34]_net_1 ), .B(N_7806), .C(
        \req_curr_state[17]_net_1 ), .D(fctrans_done_d1_net_1), .Y(
        N_5753));
    SLE \cfdatain_d1[3]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[3] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[3]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  
        burstlen_memwr_data_6_sqmuxa_i_0_1_RNI13Q47 (.A(
        ucnrbg_handle_o[4]), .B(cfdatain_o21), .C(memwr_desc_int34), 
        .D(N_7351_1), .Y(memwr_desc_int_m_9));
    CFG4 #( .INIT(16'h5073) )  \cfdst_addr_o_iv_0[14]  (.A(
        \cfdst_addr_d1[14]_net_1 ), .B(N_7556_i), .C(
        un1_req_curr_state_21_i), .D(\memwr_data_addr[14]_net_1 ), .Y(
        \cfdst_addr_o_iv_0[14]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \cfdatain_o_iv_0_a2_1_2[29]  (.A(
        cfdatain_o21), .B(ucvalid_cmd_o), .Y(N_7943_2));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_1_sqmuxa_1_0_a2_1 (
        .A(burstlen_memrd_data_1_sqmuxa_1_0_a2_1_0), .B(N_7542_i), .C(
        N_8049), .D(N_7448), .Y(N_7434));
    CFG4 #( .INIT(16'hFF02) )  \req_curr_state_ns_i_0_0[13]  (.A(
        \req_curr_state_ns_i_0_a2_1_0[13]_net_1 ), .B(
        \req_curr_state[31]_net_1 ), .C(N_7689), .D(N_7708), .Y(
        \req_curr_state_ns_i_0_0[13]_net_1 ));
    CFG4 #( .INIT(16'hE0F0) )  \cfdatain_o_iv_0_0[29]  (.A(
        memwr_desc_5_sqmuxa), .B(memwr_data_addr_2_sqmuxa), .C(N_8069), 
        .D(N_7351_1), .Y(\cfdatain_o_iv_0_0[29]_net_1 ));
    SLE \resp_curr_state[23]  (.D(\resp_curr_state_ns[23]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[23]_net_1 ));
    CFG3 #( .INIT(8'hAE) )  \req_curr_state_ns_i_0_o3_0[5]  (.A(N_7553)
        , .B(\req_curr_state_ns_i_0_a2_1_1[5]_net_1 ), .C(N_7550), .Y(
        N_7563));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_0_iv_0_a2_0_1[31]  (.A(
        cfdatain_o21), .B(do_mem_wr26_s8), .C(memwr_desc_int35), .Y(
        N_8017_1));
    CFG2 #( .INIT(4'h4) )  \resp_curr_state_ns_0_a3_0_0[10]  (.A(
        cmdrcv_net_1), .B(\resp_curr_state[2]_net_1 ), .Y(
        \resp_curr_state_ns_0_a3_0_0[10]_net_1 ));
    CFG4 #( .INIT(16'hCE0A) )  \req_curr_state_ns_0_0_0[22]  (.A(
        \req_curr_state[22]_net_1 ), .B(\req_curr_state[24]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \req_curr_state_ns_0_0_0[22]_net_1 ));
    CFG2 #( .INIT(4'h1) )  burstlen_memwr_desc35_0_a2_0 (.A(N_7543_i), 
        .B(N_5292_i), .Y(N_7450));
    CFG2 #( .INIT(4'h2) )  cfcommaccess_active_0_a4_0_a2_1 (.A(
        burstlen_memwr_data110), .B(\req_curr_state[5]_net_1 ), .Y(
        N_7888));
    CFG3 #( .INIT(8'h08) )  cfrd_resp_o_i_i_a2_0_2 (.A(rcvokay_net_1), 
        .B(idle_trigger), .C(N_4389_i), .Y(cfrd_resp_o_i_i_a2_0_net_1));
    CFG3 #( .INIT(8'h04) )  \req_curr_state_ns_i_0_a2_0[5]  (.A(N_7670)
        , .B(N_7662), .C(N_7550), .Y(N_7667));
    CFG4 #( .INIT(16'hFF08) )  \cfdatain_o_0_iv_0_1[2]  (.A(
        cfdatain_m5_i_a3_0), .B(N_7894_i), .C(N_8225), .D(
        \cfdatain_o_0_iv_0_0[2]_net_1 ), .Y(
        \cfdatain_o_0_iv_0_1[2]_net_1 ));
    CFG3 #( .INIT(8'hC5) )  \resp_curr_state_ns_o2_2_0_m2[3]  (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[4]), .C(uclatchcmd_o[0]), .Y(
        N_5174));
    CFG4 #( .INIT(16'h0400) )  unreg_cmd5_20 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[13]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[3]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[12]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[6]), .Y(unreg_cmd5_20_net_1));
    CFG4 #( .INIT(16'hF1FD) )  \resp_curr_state_ns_i_0_0[26]  (.A(
        \resp_curr_state[26]_net_1 ), .B(\resp_curr_state[25]_net_1 ), 
        .C(N_7536), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns_i_0_0[26]_net_1 ));
    SLE \cfdatain_d1[1]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[1] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[1]_net_1 ));
    CFG4 #( .INIT(16'hFDF0) )  \cfdst_addr_o_iv_0[4]  (.A(
        \req_dstreg_addr_i_a4_0[3]_net_1 ), .B(N_7806), .C(
        \cfdst_addr_o_iv_0_0[4]_net_1 ), .D(un1_req_curr_state_22_i_0), 
        .Y(cfdst_addr_o_2));
    CFG4 #( .INIT(16'h0020) )  \req_curr_state_ns_i_0_a3_5_1[5]  (.A(
        uclatchcmd_o[2]), .B(\req_curr_state[5]_net_1 ), .C(N_7576_1), 
        .D(uclatchcmd_o[0]), .Y(
        \req_curr_state_ns_i_0_a3_5_1[5]_net_1 ));
    SLE \cudata_r_o[28]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[28]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[28]));
    SLE \desc_datasel_cntr[11]  (.D(\desc_datasel_cntr_s[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[11]_net_1 ));
    CFG4 #( .INIT(16'hF0F1) )  \cfdatain_o_0_iv_0[14]  (.A(N_5111_i), 
        .B(N_7928), .C(cfdatain_o_0_iv_0_1_0), .D(
        un2_cudata_wrdy_int_9), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[14] ));
    SLE \resp_curr_state[2]  (.D(\resp_curr_state_ns[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[2]_net_1 )
        );
    CFG2 #( .INIT(4'hE) )  un1_cfdatain_o26_1_s (.A(cfdatain_o26), .B(
        cfdatain_o29), .Y(un1_cfdatain_o26_1_out));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_i_i_a3_0_1[23]  (.A(
        fcbusreq_d1_net_1), .B(\req_curr_state[20]_net_1 ), .Y(
        N_8129_1));
    CFG4 #( .INIT(16'hFFAB) )  \cfdatain_o_iv_0[7]  (.A(
        cfdatain_o_iv_0_N_4L5_net_1), .B(cfdatain_o_iv_0_N_5L7_net_1), 
        .C(un2_cudata_wrdy_int_9), .D(\resp_srcreg_data_m[1] ), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[7] ));
    SLE \desc_datasel_cntr[7]  (.D(\desc_datasel_cntr_s[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[7]_net_1 ));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_0_iv_0_a2_3_0[0]  (.A(
        req_dstreg_data20), .B(ucnrbg_handle_o[0]), .C(
        \req_curr_state[12]_net_1 ), .Y(cfdatain_o_0_iv_0_a2_3_0_0));
    CFG4 #( .INIT(16'h8000) )  un1_idle_trigger_4_i_2_0_a2_0 (.A(
        uclatchcmd_o[4]), .B(uclatchcmd_o[1]), .C(uclatchcmd_o[0]), .D(
        N_5134_i_0), .Y(N_7531));
    CFG4 #( .INIT(16'h2272) )  \resp_curr_state_RNO[19]  (.A(
        \resp_curr_state[19]_net_1 ), .B(fcbusreq_d1_net_1), .C(
        fctrans_done_o), .D(N_4265), .Y(N_4131_i));
    CFG4 #( .INIT(16'hE000) )  \resp_srcreg_data_d1_RNICTIS[1]  (.A(
        \resp_curr_state[21]_net_1 ), .B(
        \resp_srcreg_data_d1[1]_net_1 ), .C(N_8225), .D(N_4374_i), .Y(
        \resp_srcreg_data_m[1] ));
    SLE \cfburst_len_wr_d1[1]  (.D(cfburst_len_wr_o[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[1]_net_1 ));
    CFG2 #( .INIT(4'h1) )  cfrd_resp_o_i_a2_5 (.A(
        \resp_curr_state[7]_net_1 ), .B(\resp_curr_state[8]_net_1 ), 
        .Y(N_4418));
    CFG4 #( .INIT(16'hECA0) )  \resp_curr_state_ns_1[7]  (.A(
        \resp_curr_state[7]_net_1 ), .B(\resp_curr_state[21]_net_1 ), 
        .C(N_7689), .D(fctrans_done_o), .Y(
        \resp_curr_state_ns_1[7]_net_1 ));
    SLE \burstlen_memrd_data_d1[4]  (.D(N_7916_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \req_next_state_i_1_0_0_a2_c[5]  (.A(
        uclatchcmd_o[2]), .B(\req_curr_state[4]_net_1 ), .Y(
        \req_next_state_i_1_0_0_a2_c[5]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  txtokay_1000 (.A(
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]), .B(mchready_i), .C(
        txtokay_net_1), .Y(txtokay_1000_net_1));
    CFG2 #( .INIT(4'h2) )  \burstlen_memwr_desc_3_0_.m4  (.A(N_7543_i), 
        .B(N_7685_i), .Y(N_5));
    CFG3 #( .INIT(8'h47) )  \cfburst_len_wr_o_1_1[3]  (.A(N_5010_i), 
        .B(N_7481_i), .C(\cfburst_len_wr_d1[3]_net_1 ), .Y(
        \cfburst_len_wr_o_1_1[3]_net_1 ));
    SLE \cfsrc_addr_d1[14]  (.D(cfsrc_addr_o_12), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[14]_net_1 ));
    SLE \resp_srcreg_addr_d1[16]  (.D(\resp_srcreg_addr[16] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_addr_d1[16]_net_1 ));
    CFG4 #( .INIT(16'hFFBA) )  burstlen_memrd_data_1_sqmuxa_1_0_0_1 (
        .A(N_7434), .B(ucnrbg_length_o_0), .C(do_mem_wr26_s8), .D(
        N_7433), .Y(burstlen_memrd_data_1_sqmuxa_1_0_0_1_net_1));
    SLE \req_curr_state[20]  (.D(\req_curr_state_ns[20] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[20]_net_1 )
        );
    CFG4 #( .INIT(16'h0001) )  unreg_cmd5_16 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[25]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[31]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[24]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[21]), .Y(unreg_cmd5_16_net_1));
    CFG2 #( .INIT(4'hE) )  set_puf_getkcnum_RNI65OP (.A(
        set_puf_getkcnum_net_1), .B(uclatchcmd_o[1]), .Y(N_5354_i));
    CFG3 #( .INIT(8'h01) )  \req_dstreg_addr_i_a4_1[2]  (.A(
        \req_curr_state[35]_net_1 ), .B(\req_curr_state[8]_net_1 ), .C(
        \req_curr_state[14]_net_1 ), .Y(
        \req_dstreg_addr_i_a4_1[2]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  burstlen_memwr_desc36_0_a2 (.A(N_7543_i)
        , .B(N_5293_i), .C(memwr_desc_5_sqmuxa_2_0), .D(m1), .Y(
        burstlen_memwr_desc36));
    CFG2 #( .INIT(4'h2) )  un1_burstlen_memwr_data130_1_0_a2_2 (.A(
        N_7685_i), .B(N_7542_i), .Y(N_7455));
    CFG2 #( .INIT(4'h8) )  un1_idle_trigger_4_i_2_0_a2 (.A(N_7485), .B(
        uclatchcmd_o[2]), .Y(N_4178_2));
    CFG3 #( .INIT(8'h5D) )  \cfdst_addr_o_0_iv_0[30]  (.A(N_7462), .B(
        un1_req_curr_state_21_i), .C(\cfdst_addr_d1[30]_net_1 ), .Y(
        cfdst_addr_o_0_iv_0));
    CFG4 #( .INIT(16'h0001) )  \req_dstreg_data_cnst_m[29]  (.A(N_7690)
        , .B(N_7806), .C(N_7544_i), .D(\req_dstreg_data_cnst[4] ), .Y(
        \req_dstreg_data_cnst_m[29]_net_1 ));
    SLE \burstlen_memrd_data_d1[6]  (.D(\burstlen_memrd_data[6]_net_1 )
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[6]_net_1 ));
    SLE set_sent_options_r (.D(set_sent_options_r_1003_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(set_sent_options_r_net_1));
    CFG4 #( .INIT(16'hAEAA) )  \resp_curr_state_ns_0[25]  (.A(
        \resp_curr_state_ns_0_0[25]_net_1 ), .B(
        \resp_curr_state[26]_net_1 ), .C(N_7488), .D(N_7536), .Y(
        \resp_curr_state_ns[25] ));
    SLE \cudata_r_o[4]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[4]));
    SLE \cfburst_len_rd_d1[13]  (.D(cfburst_len_rd_o[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[13]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[12]  (.A(
        \cfburst_len_rd_d1[12]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[12]));
    CFG2 #( .INIT(4'hD) )  \req_curr_state_ns_i_0_o3_0[25]  (.A(
        \req_curr_state[25]_net_1 ), .B(fctrans_done_d1_net_1), .Y(
        N_7565));
    CFG4 #( .INIT(16'h099F) )  \memrd_data_addr_cnst_8_0_.m11  (.A(
        N_5293_i), .B(N_5292_i), .C(N_7542_i), .D(N_5354_i), .Y(m11));
    SLE \resp_curr_state[22]  (.D(N_4136_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[22]_net_1 ));
    CFG3 #( .INIT(8'h51) )  \cfsrc_addr_o_i[30]  (.A(resp_curr_state_6)
        , .B(N_4413_i), .C(\cfsrc_addr_d1[30]_net_1 ), .Y(N_7540_i));
    CFG3 #( .INIT(8'hC8) )  \cfburst_len_wr_o_1_2_x[0]  (.A(
        cfburst_len_wr_o_1_2_250_tz_2), .B(N_8056), .C(
        \cfburst_len_wr_o_1_2_a2_0_0[1]_net_1 ), .Y(
        cfburst_len_wr_o_1_2_x_0));
    SLE \cfburst_len_rd_d1[14]  (.D(cfburst_len_rd_o[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[14]_net_1 ));
    SLE \cudata_r_o[7]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[7]));
    CFG4 #( .INIT(16'h0070) )  \cfburst_len_wr_o_1_2_a2_0_2[0]  (.A(
        N_7685_i), .B(N_5292_i), .C(N_8065), .D(N_7543_i), .Y(
        \cfburst_len_wr_o_1_2_a2_0[0] ));
    CFG4 #( .INIT(16'h88F8) )  \resp_curr_state_ns_0[10]  (.A(
        \resp_curr_state_ns_0_a3_0_0[10]_net_1 ), .B(N_5158_i_0), .C(
        \resp_curr_state[10]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[10] ));
    CFG2 #( .INIT(4'h2) )  \req_curr_state_ns_0_a2_9_1[1]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[1]), .Y(N_5668_1));
    SLE \cudata_r_o[16]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[16]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[16]));
    CFG4 #( .INIT(16'h0ACE) )  \resp_curr_state_ns_0[9]  (.A(
        \resp_curr_state[9]_net_1 ), .B(\resp_curr_state[7]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(N_7689), .Y(\resp_curr_state_ns[9] ));
    SLE \cudata_r_o[13]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[13]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[13]));
    CFG3 #( .INIT(8'h01) )  burstlen_memwr_data_sn_m4 (.A(
        burstlen_memwr_data_12_sqmuxa), .B(N_7351_i), .C(
        burstlen_memrd_data_4_sqmuxa), .Y(
        burstlen_memwr_data_sn_N_6_mux));
    SLE \cfburst_len_wr_d1[5]  (.D(cfburst_len_wr_o[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[5]_net_1 ));
    CFG4 #( .INIT(16'h7BDE) )  un2_uclatchcmd_i_mux_11_NE_0 (.A(
        cudata_r_o[7]), .B(cudata_r_o[6]), .C(N_7683_i), .D(N_7684_i), 
        .Y(un2_uclatchcmd_i_mux_11_NE_0_net_1));
    CFG4 #( .INIT(16'h0800) )  \memrd_data_addr_cnst_8_0_.m16  (.A(
        N_7685_i), .B(m1), .C(N_5292_i), .D(N_5293_i), .Y(
        memrd_data_addr_cnst_7ro));
    CFG4 #( .INIT(16'h0001) )  unreg_cmd5_19 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[28]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[18]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[22]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[15]), .Y(unreg_cmd5_19_net_1));
    CFG3 #( .INIT(8'h20) )  \memwr_desc_addr_i_a2[29]  (.A(N_7542_i), 
        .B(N_7543_i), .C(N_7457), .Y(N_7477));
    CFG3 #( .INIT(8'hFE) )  \resp_curr_state_ns_i_i2_5_0_o2_0[28]  (.A(
        uclatchcmd_o[4]), .B(uclatchcmd_o[2]), .C(uclatchcmd_o[0]), .Y(
        N_5154));
    CFG3 #( .INIT(8'h20) )  \burstlen_memrd_data[2]  (.A(N_8158), .B(
        burstlen_memrd_data_6_sqmuxa), .C(burstlen_memrd_data_sn_N_6), 
        .Y(\burstlen_memrd_data[2]_net_1 ));
    CFG4 #( .INIT(16'hCE0A) )  \cfdst_addr_o_iv_0_1[13]  (.A(
        un1_req_curr_state_21_i), .B(N_7345), .C(
        \cfdst_addr_d1[13]_net_1 ), .D(\req_curr_state[2]_net_1 ), .Y(
        \cfdst_addr_o_iv_0_1[13]_net_1 ));
    CFG4 #( .INIT(16'h0100) )  \req_dstreg_data_cnst_m_i_a2_0_1[2]  (
        .A(uclatchcmd_o[1]), .B(\req_curr_state[24]_net_1 ), .C(
        uclatchcmd_o[0]), .D(uclatchcmd_o[2]), .Y(
        \req_dstreg_data_cnst_m_i_a2_0_1[2]_net_1 ));
    CFG4 #( .INIT(16'h0007) )  \cfdst_addr_d1_RNO[14]  (.A(N_7928), .B(
        \req_curr_state[2]_net_1 ), .C(\resp_srcreg_addr_i_m[13] ), .D(
        \cfdst_addr_o_iv_0[14]_net_1 ), .Y(\cfdst_addr_o_iv_i[14] ));
    CFG2 #( .INIT(4'hE) )  \req_curr_state_ns_0_0_o3[1]  (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[1]), .Y(N_7550));
    CFG4 #( .INIT(16'hF8F0) )  req_dstreg_data_2_sqmuxa_1_i_0 (.A(
        N_5134_i_0), .B(uclatchcmd_o[1]), .C(
        req_dstreg_data_2_sqmuxa_1_i_0_0_net_1), .D(N_5133), .Y(
        N_5111_i));
    CFG4 #( .INIT(16'hFAFC) )  
        \req_next_state_i_a12_3_1_0_i_o2_RNIJBV71[1]  (.A(N_7796), .B(
        \req_curr_state[29]_net_1 ), .C(un1_m5_i_a3_0_4), .D(
        fctrans_done_o), .Y(un1_m5_i_a3_0_6));
    CFG3 #( .INIT(8'h02) )  un1_latchen_hrdata_int_2_0_i_a2_0_a3 (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[4]), .C(N_7670), .Y(N_5331_i)
        );
    SLE \resp_curr_state[21]  (.D(N_4134_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[21]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  cfdst_addr_o42_0_a2 (.A(
        \resp_curr_state[16]_net_1 ), .B(\resp_curr_state[18]_net_1 ), 
        .C(N_7891), .D(N_7874), .Y(cfdst_addr_o42));
    CFG4 #( .INIT(16'h0001) )  cfdatain_o26_0_a2_sx_RNO (.A(
        \req_curr_state[6]_net_1 ), .B(\req_curr_state[24]_net_1 ), .C(
        \req_curr_state[23]_net_1 ), .D(\req_curr_state[9]_net_1 ), .Y(
        N_7776));
    CFG4 #( .INIT(16'h7727) )  \burstlen_memwr_data_1[0]  (.A(N_7351_i)
        , .B(ucnrbg_length_o_0), .C(\burstlen_memwr_data_cnst[0] ), .D(
        burstlen_memrd_data_4_sqmuxa), .Y(
        \burstlen_memwr_data_1[0]_net_1 ));
    CFG3 #( .INIT(8'h1F) )  un1_cfburst_len_wr_o14_i_0 (.A(
        \req_curr_state[26]_net_1 ), .B(\req_curr_state[3]_net_1 ), .C(
        idle_trigger), .Y(N_5010_i));
    CFG2 #( .INIT(4'h7) )  \req_dstreg_data_cnst_i_o4[3]  (.A(
        set_puf_getkcnum_net_1), .B(\req_curr_state[11]_net_1 ), .Y(
        N_5194));
    SLE \desc_datasel_cntr[22]  (.D(\desc_datasel_cntr_s[22] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[22]_net_1 ));
    SLE \desc_datasel_cntr[29]  (.D(\desc_datasel_cntr_s[29] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[29]_net_1 ));
    CFG4 #( .INIT(16'h0800) )  un1_latchen_hrdata_int_6_i_a2_0_0 (.A(
        N_5292_i), .B(N_5293_i), .C(N_5354_i), .D(N_7543_i), .Y(
        un1_latchen_hrdata_int_6_i_a2_0_0_net_1));
    SLE \cfsrc_addr_d1[16]  (.D(cfsrc_addr_o_14), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[16]_net_1 ));
    CFG4 #( .INIT(16'h2320) )  \cfsrc_addr_o_i[4]  (.A(
        \cfsrc_addr_d1[4]_net_1 ), .B(resp_curr_state_6), .C(N_4413_i), 
        .D(N_7379), .Y(N_7352_i));
    SLE \req_curr_state[28]  (.D(\req_curr_state_ns[28] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[28]_net_1 )
        );
    SLE \req_curr_state[25]  (.D(N_5519_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[25]_net_1 )
        );
    CFG3 #( .INIT(8'h01) )  \req_next_state_i_a12_7_1_0_a2_0[1]  (.A(
        \req_curr_state[24]_net_1 ), .B(\req_curr_state[14]_net_1 ), 
        .C(\req_curr_state[35]_net_1 ), .Y(N_7887));
    CFG3 #( .INIT(8'h04) )  \req_curr_state_ns_0_0_a2_0_1[30]  (.A(
        txtokay_net_1), .B(idle_trigger), .C(N_5736), .Y(
        \req_curr_state_ns_0_0_a2_0_1[30]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[4]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[4]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[3]_net_1 ), .S(\desc_datasel_cntr_s[4] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[4]_net_1 ));
    CFG3 #( .INIT(8'hAE) )  \cfdst_addr_o_iv_0[16]  (.A(
        \cfdst_addr_o_iv_0_0[16]_net_1 ), .B(un1_req_curr_state_22_i_0)
        , .C(\req_curr_state[6]_net_1 ), .Y(cfdst_addr_o_14));
    CFG4 #( .INIT(16'h0040) )  un2_cudata_wrdy_int_1_RNIKTPC6 (.A(
        un2_cudata_wrdy_int_1_0), .B(g0_5), .C(mchready_i), .D(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(cfdatain_o27));
    CFG4 #( .INIT(16'h0200) )  cfrd_resp_o_i_i_a2_9 (.A(N_5293_i), .B(
        N_5292_i), .C(N_7542_i), .D(N_5354_i), .Y(N_7439));
    SLE \desc_datasel_cntr[8]  (.D(\desc_datasel_cntr_s[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[8]_net_1 ));
    CFG3 #( .INIT(8'h80) )  \resp_curr_state_ns_o2_10_a4_1[3]  (.A(
        uclatchcmd_o[3]), .B(N_5332), .C(uclatchcmd_o[0]), .Y(
        \resp_curr_state_ns_o2_10_a4_1[3]_net_1 ));
    SLE \cfsrc_addr_d1[29]  (.D(cfsrc_addr_o_27), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[29]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[9]  (.A(
        \cfburst_len_rd_d1[9]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[9]));
    CFG3 #( .INIT(8'h80) )  \req_curr_state_ns_0_0_a2_1_1[22]  (.A(
        uclatchcmd_o[3]), .B(idle_trigger), .C(
        \req_curr_state[11]_net_1 ), .Y(
        \req_curr_state_ns_0_0_a2_1_1[22]_net_1 ));
    CFG4 #( .INIT(16'hA0B0) )  \cfdatain_o_0_iv_0_2_RNIJSSF1[13]  (.A(
        \cfdatain_o_0_iv_0_2[13]_net_1 ), .B(N_5111_i), .C(
        \cfdatain_o_0_iv_0_3_0[13] ), .D(un2_cudata_wrdy_int_9), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA_0));
    SLE \req_curr_state[33]  (.D(\req_curr_state_ns[33] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[33]_net_1 )
        );
    CFG2 #( .INIT(4'h1) )  \req_dstreg_addr_i_a4_2_0_a2_0_a2[3]  (.A(
        \req_curr_state[31]_net_1 ), .B(\req_curr_state[29]_net_1 ), 
        .Y(N_5310_2));
    SLE \req_curr_state[7]  (.D(\req_curr_state_ns[7] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[7]_net_1 ));
    SLE \cfburst_len_rd_d1[12]  (.D(cfburst_len_rd_o[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[12]_net_1 ));
    CFG3 #( .INIT(8'hB3) )  un1_main_curr_state_1_0 (.A(
        set_puf_getkcnum_net_1), .B(main_curr_state_5371_d), .C(
        \req_curr_state[34]_net_1 ), .Y(un1_main_curr_state_1_0_net_1));
    SLE \resp_curr_state[3]  (.D(\resp_curr_state_ns[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[3]_net_1 )
        );
    CFG4 #( .INIT(16'h4000) )  \burstlen_memrd_data_2_RNO[3]  (.A(
        N_7685_i), .B(N_5293_i), .C(N_7341_i_1_0), .D(N_8049), .Y(
        N_7341_i));
    CFG4 #( .INIT(16'h2000) )  un1_burstlen_memwr_data132_1_0_a2 (.A(
        N_7380), .B(N_7542_i), .C(N_7457), .D(N_6101_2), .Y(
        un1_burstlen_memwr_data132_1_i));
    CFG4 #( .INIT(16'hFFEA) )  \req_next_state_i_a12_7_RNIJ97FC[1]  (
        .A(un1_m5_i_a3_0_9), .B(mchready_i), .C(un1_m1_e_0_0), .D(
        un1_m5_i_a3_0_8), .Y(un1_m5_i_a3_0_11));
    CFG3 #( .INIT(8'h10) )  \cfburst_len_wr_o_1_2_a2_4[1]  (.A(
        N_5354_i), .B(N_7685_i), .C(N_5292_i), .Y(N_8052));
    SLE \desc_datasel_cntr[1]  (.D(\desc_datasel_cntr_s[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[1]_net_1 ));
    CFG3 #( .INIT(8'h07) )  burstlen_memrd_data_sn_m5 (.A(
        ucvalid_cmd_o), .B(do_mem_wr33), .C(
        burstlen_memrd_data_4_sqmuxa), .Y(burstlen_memrd_data_sn_N_6));
    CFG4 #( .INIT(16'h0001) )  unreg_cmd5_17 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[26]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[23]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[20]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[30]), .Y(unreg_cmd5_17_net_1));
    CFG4 #( .INIT(16'h1050) )  rcvokay_RNIHO7Q (.A(txtokay_net_1), .B(
        cmdrcv_net_1), .C(\req_curr_state[8]_net_1 ), .D(rcvokay_net_1)
        , .Y(un1_m5_i_a3_0_3_1));
    CFG4 #( .INIT(16'h7FFF) )  \cfdst_addr_o_iv_2_0_o4[14]  (.A(
        N_7543_i), .B(ucvalid_cmd_o), .C(memrd_data_addr_cnst_7ro), .D(
        N_6101_2), .Y(N_7928));
    CFG3 #( .INIT(8'h02) )  \req_curr_state_ns_0_0_a2_2_1[3]  (.A(
        uclatchcmd_o[2]), .B(uclatchcmd_o[0]), .C(uclatchcmd_o[1]), .Y(
        N_7656_1));
    SLE \cfdatain_d1[25]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[25] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_25));
    CFG3 #( .INIT(8'hFE) )  un2_cudata_wrdy_int_9_sx (.A(
        un2_cudata_wrdy_int_1_0), .B(cfdatain_o29), .C(cfdatain_o27), 
        .Y(un2_cudata_wrdy_int_9_sx_net_1));
    CFG4 #( .INIT(16'hCCEF) )  
        un1_latchen_hrdata_int_2_0_i_a2_0_a3_RNI2D2H3 (.A(
        uclatchcmd_o[0]), .B(g0_9_o3_0_0_net_1), .C(N_5331_i), .D(
        N_5322_i), .Y(N_7_0));
    CFG2 #( .INIT(4'h4) )  un1_main_curr_state_2_0_a2 (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[4]), .Y(N_7662));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[25]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[25]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[24]_net_1 ), .S(
        \desc_datasel_cntr_s[25] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[25]_net_1 ));
    CFG2 #( .INIT(4'h1) )  cfdatain_o28_1_RNI1G5Q6 (.A(cfdatain_o27), 
        .B(cfdatain_o28), .Y(cfdatain_m2_0_a2_0_0));
    CFG3 #( .INIT(8'hF8) )  \cfsrc_addr_o_2[12]  (.A(
        \cfsrc_addr_d1[12]_net_1 ), .B(N_7456), .C(N_7421), .Y(
        cfsrc_addr_o_10));
    CFG2 #( .INIT(4'h1) )  \req_curr_state_ns_i_0_a2_1_0[13]  (.A(
        \req_curr_state[11]_net_1 ), .B(\req_curr_state[33]_net_1 ), 
        .Y(\req_curr_state_ns_i_0_a2_1_0[13]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  \req_curr_state_ns_0_0_a3_2[1]  (.A(
        N_5545), .B(N_7664), .C(N_7576_1), .D(N_5562), .Y(N_7576));
    CFG4 #( .INIT(16'h0008) )  \cfburst_len_wr_o_1_2_a2_3[2]  (.A(
        N_8049), .B(cfburst_len_wr_o_1_sn_N_3), .C(N_4863_i), .D(
        N_5292_i), .Y(N_8080));
    CFG4 #( .INIT(16'h220F) )  \burstlen_memrd_data[7]  (.A(N_6076), 
        .B(burstlen_memrd_data_6_sqmuxa), .C(
        burstlen_memrd_data_4_sqmuxa), .D(burstlen_memrd_data_sn_N_6), 
        .Y(\burstlen_memrd_data[7]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  un1_req_curr_state_21_0_a2_0 (.A(
        un1_req_curr_state_21_0_a2_0_1_net_1), .B(N_7462), .C(
        \resp_curr_state[23]_net_1 ), .D(N_7794), .Y(N_7891));
    SLE \resp_curr_state[10]  (.D(\resp_curr_state_ns[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[10]_net_1 ));
    CFG4 #( .INIT(16'h555D) )  \req_dstreg_addr_i_o2[2]  (.A(
        \req_curr_state[12]_net_1 ), .B(uclatchcmd_o[2]), .C(N_105_i), 
        .D(N_7821), .Y(N_5193));
    CFG4 #( .INIT(16'h8000) )  unreg_cmd5_29 (.A(unreg_cmd5_18_net_1), 
        .B(unreg_cmd5_17_net_1), .C(unreg_cmd5_19_net_1), .D(
        unreg_cmd5_20_net_1), .Y(unreg_cmd5_29_net_1));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0_0[12]  (.A(
        \cfdatain_d1[12]_net_1 ), .B(ucnrbg_handle_o[4]), .C(N_8070), 
        .D(N_7894_i), .Y(cfdatain_o_0_iv_0_0_0));
    SLE \resp_srcreg_addr_d1[13]  (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_4294_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_addr_d1[13]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[29]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[29]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[28]_net_1 ), .S(
        \desc_datasel_cntr_s[29] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[29]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  \cfdatain_o_iv_0_a2_10_RNO[29]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[1]_net_1 )
        , .C(N_4_0), .D(\desc_datasel_cntr[2]_net_1 ), .Y(
        memwr_desc_int43));
    SLE \cfburst_len_rd_d1[1]  (.D(cfburst_len_rd_o[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[1]_net_1 ));
    SLE \cfburst_len_rd_d1[2]  (.D(cfburst_len_rd_o[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[2]_net_1 ));
    CFG4 #( .INIT(16'h7DBE) )  un2_uclatchcmd_i_mux_11_NE_2 (.A(
        cudata_r_o[4]), .B(cudata_r_o[0]), .C(N_7543_i), .D(N_5292_i), 
        .Y(un2_uclatchcmd_i_mux_11_NE_2_net_1));
    CFG4 #( .INIT(16'hF0F1) )  \cfdatain_o_0_iv_0[12]  (.A(N_5111_i), 
        .B(N_7344), .C(cfdatain_o_0_iv_0_0_0), .D(
        un2_cudata_wrdy_int_9), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[12] ));
    SLE \resp_curr_state[16]  (.D(\resp_curr_state_ns[16]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[16]_net_1 ));
    SLE \desc_datasel_cntr[9]  (.D(\desc_datasel_cntr_s[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[9]_net_1 ));
    CFG2 #( .INIT(4'h2) )  un2_custatus_out_en2_4_i_a2 (.A(N_4394_i), 
        .B(\resp_curr_state[23]_net_1 ), .Y(N_4374_i));
    CFG3 #( .INIT(8'h80) )  un1_req_curr_state_21_0_a2 (.A(N_7891), .B(
        N_7887), .C(un1_req_curr_state_21_0_a2_2_net_1), .Y(
        un1_req_curr_state_21_i));
    CFG4 #( .INIT(16'hAAFC) )  \req_next_state_i_1_0_0_a2_1_3[5]  (.A(
        \req_curr_state[27]_net_1 ), .B(\req_curr_state[4]_net_1 ), .C(
        \req_curr_state[6]_net_1 ), .D(fctrans_done_o), .Y(
        \req_next_state_i_1_0_0_a2_1_3[5]_net_1 ));
    CFG2 #( .INIT(4'hD) )  \resp_curr_state_ns_i_0_o2[26]  (.A(
        N_8093_i), .B(un2_uclatchcmd_i_mux_11_NE_net_1), .Y(N_7488));
    SLE \cfdst_addr_d1[14]  (.D(\cfdst_addr_o_iv_i[14] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[14]_net_1 ));
    SLE \cudata_r_o[1]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[1]));
    CFG4 #( .INIT(16'hFFAE) )  \cfdatain_o_0_iv_0_2[13]  (.A(N_7974), 
        .B(\cfdatain_d1[13]_net_1 ), .C(N_7894_i), .D(
        \cfdatain_o_0_iv_0_2_0[13]_net_1 ), .Y(
        \cfdatain_o_0_iv_0_2[13]_net_1 ));
    CFG4 #( .INIT(16'hFFF8) )  
        \cfburst_len_wr_o_1_2_a2_3_3_RNISLKV4[0]  (.A(N_5), .B(N_8088), 
        .C(\cfburst_len_wr_o_1_2_a2_3_3[0]_net_1 ), .D(
        cfburst_len_wr_o_1_2_250_tz_1), .Y(
        cfburst_len_wr_o_1_2_250_tz_2));
    CFG2 #( .INIT(4'h8) )  \resp_curr_state_ns_i_i_a2[1]  (.A(
        resp_next_state4_net_1), .B(resp_curr_state_0), .Y(
        \resp_curr_state_ns_i_i_a2[1]_net_1 ));
    SLE \desc_datasel_cntr[10]  (.D(\desc_datasel_cntr_s[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[10]_net_1 ));
    CFG4 #( .INIT(16'h70F0) )  un2_cudata_wrdy_int_4_i_a2_0_0_RNI99IC1 
        (.A(\resp_curr_state_RNI9SJA[16]_net_1 ), .B(
        un2_cudata_wrdy_int_4_i_a2_0_0_net_1), .C(curr_state_0), .D(
        \req_curr_state_RNIAQKD[35]_net_1 ), .Y(
        un2_cudata_wrdy_int_4_i_a2_0_0_RNI99IC1_net_1));
    SLE \cudata_r_o[15]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[15]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[15]));
    CFG3 #( .INIT(8'hBA) )  \cfdatain_o_0_iv_0[0]  (.A(
        \cfdatain_o_0_iv_0_1[0] ), .B(un2_cudata_wrdy_int_9), .C(
        cfdatain_o_0_iv_0_a2_3_0_0), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[0] ));
    CFG4 #( .INIT(16'h0302) )  \req_curr_state_ns_i_0_a3[5]  (.A(
        N_5546), .B(\req_curr_state[5]_net_1 ), .C(N_7560), .D(N_5545), 
        .Y(N_7584));
    CFG2 #( .INIT(4'hD) )  \req_curr_state_ns_0_o4[14]  (.A(mchready_i)
        , .B(N_7780), .Y(N_5577));
    CFG4 #( .INIT(16'hC400) )  \memwr_desc_addr_i_RNICAN58[29]  (.A(
        N_7342), .B(N_7894_i), .C(\req_dstreg_data_cnst_m[29]_net_1 ), 
        .D(cfdatain_m4_e_0_1), .Y(
        \memwr_desc_addr_i_RNICAN58[29]_net_1 ));
    CFG4 #( .INIT(16'hC0CA) )  
        \req_dstreg_addr_i_a4_0_a2_0_i_o2_RNIBTUC1[4]  (.A(g1_0_0), .B(
        uclatchcmd_o[3]), .C(N_7544_i), .D(N_7806), .Y(
        \req_dstreg_data_0_iv_0_0[3] ));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNIQL5N2[16]  (.A(
        m2_e_19), .B(m2_e_18), .C(m2_e_17), .D(m2_e_16), .Y(m2_e_25));
    CFG4 #( .INIT(16'h0400) )  cudata_rvalid_o_RNO (.A(N_7470), .B(
        mchready_i), .C(cucmd_error_net_1), .D(curr_state_2), .Y(
        N_7350_i));
    CFG4 #( .INIT(16'h00E4) )  \cfsrc_addr_o_2_0[3]  (.A(N_4413_i), .B(
        \resp_srcreg_addr[3] ), .C(\cfsrc_addr_d1[3]_net_1 ), .D(
        resp_curr_state_6), .Y(\cfsrc_addr_o_2_0[3]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \cfdst_addr_o_iv_0_0[16]  (.A(
        un1_req_curr_state_21_i), .B(N_8228), .C(
        \cfdst_addr_d1[16]_net_1 ), .D(\resp_srcreg_addr[16] ), .Y(
        \cfdst_addr_o_iv_0_0[16]_net_1 ));
    CFG4 #( .INIT(16'h2220) )  cfdatain_o_iv_0_7_N_8L15 (.A(
        cfdatain_o_iv_0_7_N_7L13_net_1), .B(
        \cfdatain_o_iv_0_0[29]_net_1 ), .C(
        cfdatain_o_iv_0_7_N_4L6_net_1), .D(
        cfdatain_o_iv_0_7_N_6L11_net_1), .Y(
        cfdatain_o_iv_0_7_N_8L15_net_1));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[23]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[23]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[22]_net_1 ), .S(
        \desc_datasel_cntr_s[23] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[23]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  un2_uclatchcmd_i_mux_16_i_2_RNIBE0Q1 (
        .A(un2_uclatchcmd_i_mux_16_i_2_net_1), .B(
        un2_uclatchcmd_i_mux_11_NE_net_1), .C(cudata_r_o[7]), .D(
        N_8093_i_1), .Y(N_8093_i));
    SLE \cudata_r_o[20]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[20]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[20]));
    SLE \req_curr_state[21]  (.D(\req_curr_state_ns[21] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[21]_net_1 )
        );
    CFG2 #( .INIT(4'h7) )  \req_curr_state_ns_0_o4_i_o2_i_o2[7]  (.A(
        idle_trigger), .B(my_hpms_top_0_COMM_BLK_INT), .Y(N_7689));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[26]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[26]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[25]_net_1 ), .S(
        \desc_datasel_cntr_s[26] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[26]_net_1 ));
    CFG2 #( .INIT(4'h8) )  un1_cfburst_len_wr_o14_i_0_RNIMPCJ1 (.A(
        N_7481_i), .B(N_5010_i), .Y(cfburst_len_wr_o_1_sn_N_3));
    CFG4 #( .INIT(16'h0001) )  \req_curr_state_RNI4H0G[6]  (.A(
        \req_curr_state[6]_net_1 ), .B(\req_curr_state[9]_net_1 ), .C(
        \resp_curr_state[23]_net_1 ), .D(\req_curr_state[24]_net_1 ), 
        .Y(g0_4));
    SLE \desc_datasel_cntr[31]  (.D(\desc_datasel_cntr_s[31]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[31]_net_1 ));
    SLE \resp_curr_state[25]  (.D(\resp_curr_state_ns[25] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[25]_net_1 ));
    CFG4 #( .INIT(16'h04C4) )  \main_curr_state_RNO[1]  (.A(
        un1_fctrans_done_i_i), .B(N_8108), .C(
        \main_curr_state[0]_net_1 ), .D(main_next_state14), .Y(
        N_8103_i));
    CFG4 #( .INIT(16'h0100) )  un1_req_curr_state_24_0_a3_2_1_2 (.A(
        \req_curr_state[27]_net_1 ), .B(\req_curr_state[9]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(N_7711_3), .Y(
        un1_req_curr_state_24_0_a3_2_1_2_net_1));
    SLE \req_curr_state[34]  (.D(N_5531_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[34]_net_1 )
        );
    CFG2 #( .INIT(4'h8) )  \cfburst_len_wr_o_1_2_a2_0_0[1]  (.A(
        burstlen_memwr_desc34_2), .B(N_7906), .Y(
        \cfburst_len_wr_o_1_2_a2_0_0[1]_net_1 ));
    CFG4 #( .INIT(16'hFEF0) )  
        \req_next_state_i_a4_0_0_a3_0_RNI5RMPE[1]  (.A(
        \req_next_state_i_a4_0_0_a3_0[1]_net_1 ), .B(
        \req_curr_state[29]_net_1 ), .C(un1_m5_i_a3_0_11), .D(N_8093_i)
        , .Y(un1_m5_i_a3_0_12));
    CFG4 #( .INIT(16'h4000) )  memwr_data_addr_2_sqmuxa_0_a2 (.A(
        N_5292_i), .B(N_7685_i), .C(N_8049), .D(N_8065), .Y(
        memwr_data_addr_2_sqmuxa));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_1_sqmuxa_1_0_a2_0 (
        .A(N_5293_i), .B(N_7543_i), .C(N_8052), .D(N_7474), .Y(N_7433));
    CFG4 #( .INIT(16'h202F) )  \memrd_data_addr_cnst_8_0_.m7_1_0  (.A(
        N_5354_i), .B(N_7542_i), .C(
        burstlen_memrd_data_1_sqmuxa_1_0_a2_1_0), .D(i3_mux), .Y(
        m7_1_0));
    CFG4 #( .INIT(16'hAA30) )  \cfburst_len_rd_o_1[1]  (.A(
        \burstlen_memrd_data[1]_net_1 ), .B(un1_req_curr_state_24_i), 
        .C(\cfburst_len_rd_d1[1]_net_1 ), .D(cfrd_resp_o_0_sqmuxa_1), 
        .Y(cfburst_len_rd_o[1]));
    SLE \resp_curr_state[9]  (.D(\resp_curr_state_ns[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[9]_net_1 )
        );
    CFG4 #( .INIT(16'hFEEE) )  un1_burstlen_memwr_data130_1_0_o2 (.A(
        do_mem_wr27_net_1), .B(burstlen_memwr_desc36), .C(N_7364), .D(
        un1_burstlen_memwr_data130_1_0_a2_1_0_net_1), .Y(N_7386));
    CFG4 #( .INIT(16'h0007) )  \req_curr_state_RNO[13]  (.A(
        \req_curr_state_ns_i_0_a2_2_2[13]_net_1 ), .B(
        \req_curr_state_ns_0_0_a2_1_2[22]_net_1 ), .C(N_7707), .D(
        \req_curr_state_ns_i_0_0[13]_net_1 ), .Y(N_5501_i));
    CFG4 #( .INIT(16'h0200) )  \burstlen_memrd_data[1]  (.A(
        \burstlen_memrd_data_d1[1]_net_1 ), .B(ucvalid_cmd_o), .C(
        burstlen_memrd_data_6_sqmuxa), .D(burstlen_memrd_data_sn_N_6), 
        .Y(\burstlen_memrd_data[1]_net_1 ));
    SLE \cfdatain_d1[15]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_7), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[15]_net_1 ));
    CFG3 #( .INIT(8'h01) )  \req_next_state_i_a12_3_1_0_i_a2_1_1[1]  (
        .A(\req_curr_state[19]_net_1 ), .B(\req_curr_state[16]_net_1 ), 
        .C(\req_curr_state[12]_net_1 ), .Y(
        \req_next_state_i_a12_3_1_0_i_a2_1_1[1]_net_1 ));
    CFG4 #( .INIT(16'h2010) )  un1_idle_trigger_4_i_a2_4_a4_0_a2_0 (.A(
        uclatchcmd_o[2]), .B(uclatchcmd_o[4]), .C(uclatchcmd_o[3]), .D(
        uclatchcmd_o[0]), .Y(un1_idle_trigger_4_i_a2_4_a4_0_a2_0_net_1)
        );
    CFG3 #( .INIT(8'h80) )  \req_curr_state_ns_0_a3_0_a2[32]  (.A(
        fctrans_done_o), .B(N_8093_i), .C(\req_curr_state[29]_net_1 ), 
        .Y(\req_curr_state_ns[32] ));
    CFG4 #( .INIT(16'hA0EC) )  \resp_curr_state_ns_0[24]  (.A(
        \resp_curr_state[23]_net_1 ), .B(\resp_curr_state[24]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[24] ));
    SLE \req_curr_state[29]  (.D(\req_curr_state_ns_i_i[29]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[29]_net_1 )
        );
    CFG4 #( .INIT(16'h5F1F) )  \cudata_r_o_RNIU2461[2]  (.A(
        cudata_r_o[3]), .B(cudata_r_o[2]), .C(cudata_r_o[5]), .D(
        cudata_r_o[4]), .Y(N_8093_i_1));
    CFG2 #( .INIT(4'h1) )  un1_cfburst_len_wr_o14_i_0_a2 (.A(
        \req_curr_state[3]_net_1 ), .B(\req_curr_state[26]_net_1 ), .Y(
        burstlen_memwr_data110));
    SLE \cudata_r_o[0]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[0]));
    SLE \burstlen_memrd_data_d1[1]  (.D(\burstlen_memrd_data[1]_net_1 )
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[1]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \cfdatain_o_0_iv_0_RNO_0[0]  (.A(
        un2_cudata_wrdy_int_1_0), .B(req_curr_state_RNI9FH21_0), .Y(
        cfdatain_m4_0_a2_0));
    CFG2 #( .INIT(4'h1) )  burstlen_memwr_desc34_2_0_a4 (.A(N_7542_i), 
        .B(N_5293_i), .Y(burstlen_memwr_desc34_2));
    CFG2 #( .INIT(4'h6) )  \req_dstreg_data_cnst_i_a2_2_i_x2[2]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[1]), .Y(N_105_i));
    CFG4 #( .INIT(16'hF888) )  \cfdst_addr_o_0_iv_0_1[29]  (.A(
        \cfdst_addr_o_0_iv_0_a2_2_2[29]_net_1 ), .B(
        un1_do_mem_wr32_2_i), .C(\cfdst_addr_d1[29]_net_1 ), .D(
        un1_req_curr_state_21_i), .Y(\cfdst_addr_o_0_iv_0_1[29]_net_1 )
        );
    SLE cfrd_req_o_inst_1 (.D(N_5252_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfrd_req_o));
    CFG3 #( .INIT(8'hD8) )  \burstlen_memrd_data_2[2]  (.A(
        ucvalid_cmd_o), .B(burstlen_memrd_data_0_sqmuxa_3), .C(
        \burstlen_memrd_data_d1[2]_net_1 ), .Y(N_8158));
    CFG3 #( .INIT(8'h08) )  \burstlen_memrd_data[3]  (.A(N_6072), .B(
        burstlen_memrd_data_sn_N_6), .C(burstlen_memrd_data_6_sqmuxa), 
        .Y(\burstlen_memrd_data[3]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  do_mem_wr25_0_a2 (.A(N_7542_i), .B(
        N_5292_i), .C(do_mem_wr25_0_a2_1_net_1), .D(N_6101_2), .Y(
        do_mem_wr25));
    CFG2 #( .INIT(4'h2) )  un1_resp_curr_state_15_i_a2 (.A(N_4394_i), 
        .B(\resp_curr_state[21]_net_1 ), .Y(N_4395_i));
    SLE \cudata_r_o[27]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[27]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[27]));
    SLE \cfdatain_d1[30]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[30] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_30));
    CFG3 #( .INIT(8'h04) )  \resp_curr_state_ns_2[3]  (.A(N_7670), .B(
        N_5681_1), .C(N_7688), .Y(\resp_curr_state_ns_2[3]_net_1 ));
    CFG4 #( .INIT(16'hA0E4) )  \req_curr_state_ns_i_i[29]  (.A(
        \req_curr_state[28]_net_1 ), .B(\req_curr_state[29]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \req_curr_state_ns_i_i[29]_net_1 ));
    CFG4 #( .INIT(16'hF7FF) )  cfdatain_o28_1_sx (.A(
        \resp_curr_state[16]_net_1 ), .B(curr_state_0), .C(
        cfdatain_o21), .D(un2_cudata_wrdy_int_4_i_0), .Y(
        cfdatain_o28_1_sx_net_1));
    CFG2 #( .INIT(4'h2) )  cfrd_resp_o_i_i_a2_1_RNIO1KON (.A(
        un1_req_curr_state_24_i), .B(cfrd_resp_o_0_sqmuxa_1), .Y(
        cfburst_len_rd_o_1_sn_N_2));
    SLE \cfdatain_d1[4]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[4] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[4]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNI2HPL[20]  (.A(
        \desc_datasel_cntr[23]_net_1 ), .B(
        \desc_datasel_cntr[22]_net_1 ), .C(
        \desc_datasel_cntr[21]_net_1 ), .D(
        \desc_datasel_cntr[20]_net_1 ), .Y(m2_e_18));
    CFG2 #( .INIT(4'h6) )  \burstlen_memwr_desc_3_0_.m37  (.A(N_5354_i)
        , .B(N_5293_i), .Y(N_47));
    CFG4 #( .INIT(16'hA0E4) )  \req_dstreg_data_0_iv_0[4]  (.A(
        N_7544_i), .B(\req_dstreg_data_cnst[4] ), .C(uclatchcmd_o[4]), 
        .D(N_7806), .Y(\req_dstreg_data_0_iv_0[4]_net_1 ));
    SLE \cfdst_addr_d1[13]  (.D(\cfdst_addr_o_iv_i[13] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[13]_net_1 ));
    CFG4 #( .INIT(16'hAE0C) )  \resp_curr_state_ns_0[2]  (.A(
        \resp_curr_state[9]_net_1 ), .B(\resp_curr_state[2]_net_1 ), 
        .C(idle_trigger), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[2] ));
    CFG4 #( .INIT(16'hAE0C) )  \req_curr_state_ns_0_0[4]  (.A(
        \req_curr_state[3]_net_1 ), .B(\req_curr_state[4]_net_1 ), .C(
        fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[4] ));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNI77GA8[1]  (.A(
        do_mem_wr26_s8), .B(memwr_desc_int35), .C(ucnrbg_handle_o[3]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_16));
    CFG4 #( .INIT(16'h5F4E) )  un1_req_curr_state_24_0_0_0_RNIULAK7 (
        .A(un1_N_5_mux_0), .B(un1_req_curr_state_24_0_0_0_net_1), .C(
        datawr_reqd), .D(d_N_7), .Y(
        un1_req_curr_state_24_0_0_0_RNIULAK7_net_1));
    CFG4 #( .INIT(16'h8000) )  \resp_curr_state_ns_i_i_a2_0[28]  (.A(
        N_5158_i_0), .B(resp_next_state102), .C(
        \resp_curr_state[20]_net_1 ), .D(cmdrcv_net_1), .Y(N_7503));
    CFG3 #( .INIT(8'h01) )  burstlen_memwr_desc35_0_a2_1_0 (.A(
        N_7683_i), .B(N_7684_i), .C(N_5293_i), .Y(
        burstlen_memwr_desc35_1));
    SLE \cudata_r_o[11]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[11]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[11]));
    CFG4 #( .INIT(16'hFF80) )  
        req_dstreg_data20_0_a2_0_a2_0_a3_RNI2K3K1 (.A(
        \req_curr_state[12]_net_1 ), .B(ucnrbg_handle_o[6]), .C(
        req_dstreg_data20), .D(N_4_0_0), .Y(req_dstreg_data_0_0));
    CFG2 #( .INIT(4'h8) )  \cfdatain_o_0_iv_0_a2_5[13]  (.A(
        memwr_desc_int34), .B(do_mem_wr26_s8), .Y(N_8084));
    CFG2 #( .INIT(4'h7) )  \memwr_desc_addr_i[12]  (.A(m20), .B(N_8049)
        , .Y(N_7344));
    SLE \cfsrc_addr_d1[3]  (.D(cfsrc_addr_o_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[3]_net_1 ));
    SLE \cudata_r_o[12]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[12]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[12]));
    CFG3 #( .INIT(8'h51) )  \resp_next_state_2_.m3_e  (.A(N_7480_i), 
        .B(unreg_cmd_net_1), .C(idle_trigger), .Y(N_7));
    CFG3 #( .INIT(8'hE0) )  \resp_srcreg_data_d1_RNIU0SE_0[1]  (.A(
        \resp_srcreg_data_d1[1]_net_1 ), .B(
        \resp_curr_state[21]_net_1 ), .C(N_4374_i), .Y(g0_7_0));
    CFG4 #( .INIT(16'hFFFE) )  un1_do_mem_wr32_2_0_0 (.A(N_7386), .B(
        un1_do_mem_wr32_2_0_0_1_net_1), .C(do_mem_wr25), .D(
        un1_do_mem_wr32_2_0_0_0_net_1), .Y(un1_do_mem_wr32_2_i));
    SLE \cfdatain_d1[26]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[26] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_26));
    CFG3 #( .INIT(8'hF2) )  \resp_curr_state_ns[5]  (.A(
        resp_curr_state_5), .B(fcbusreq_d1_net_1), .C(
        cfrd_resp_o_0_sqmuxa_1), .Y(\resp_curr_state_ns[5]_net_1 ));
    CFG4 #( .INIT(16'hCE0A) )  \req_curr_state_ns_0_0[9]  (.A(
        \req_curr_state[9]_net_1 ), .B(\req_curr_state[15]_net_1 ), .C(
        fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[9] ));
    CFG4 #( .INIT(16'hFFFE) )  un2_uclatchcmd_i_mux_11_NE (.A(
        un2_uclatchcmd_i_mux_11_NE_2_net_1), .B(
        un2_uclatchcmd_i_mux_11_NE_0_net_1), .C(
        un2_uclatchcmd_i_mux_11_NE_1_net_1), .D(
        un2_uclatchcmd_i_mux_11_NE_3_net_1), .Y(
        un2_uclatchcmd_i_mux_11_NE_net_1));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_0_0_a2_0_0[20]  (.A(
        idle_trigger), .B(txtokay_net_1), .Y(
        \req_curr_state_ns_0_0_a2_0_0[20]_net_1 ));
    CFG4 #( .INIT(16'hEEFE) )  \req_curr_state_ns_0_0_1[1]  (.A(N_7577)
        , .B(\req_curr_state_ns_0_0_2[1]_net_1 ), .C(
        \req_curr_state[1]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_0_0_1[1]_net_1 ));
    CFG2 #( .INIT(4'h2) )  burstlen_memrd_data_0_sqmuxa_3_0_a2_0_0 (.A(
        N_7543_i), .B(N_5292_i), .Y(
        burstlen_memrd_data_0_sqmuxa_3_0_a2_0_net_1));
    CFG4 #( .INIT(16'hC888) )  set_puf_getkcnum_1002 (.A(
        set_puf_getkcnum_net_1), .B(main_curr_state_5371_d), .C(
        un1_main_curr_state_2_0_a3_3_net_1), .D(
        un1_main_curr_state_2_0_a3_2_net_1), .Y(
        set_puf_getkcnum_1002_net_1));
    CFG2 #( .INIT(4'h7) )  cfburst_len_wr_o13_i_0 (.A(idle_trigger), 
        .B(\req_curr_state[1]_net_1 ), .Y(N_4863_i));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_0_iv_0_a2_2[12]  (.A(
        do_mem_wr27_s9), .B(cfdatain_o21), .C(memwr_desc_int34), .Y(
        N_8070));
    CFG4 #( .INIT(16'hECA0) )  \cfdst_addr_o_iv_0_0[4]  (.A(
        \cfdst_addr_d1[4]_net_1 ), .B(N_7379), .C(
        un1_req_curr_state_21_i), .D(N_8228), .Y(
        \cfdst_addr_o_iv_0_0[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  resp_next_state65_i_o2_i_a2 (.A(
        fctrans_done_o), .B(unreg_cmd_net_1), .Y(N_7469));
    CFG3 #( .INIT(8'h20) )  custatus_valid_o5 (.A(mchready_i), .B(
        N_5_0), .C(\resp_curr_state[3]_net_1 ), .Y(
        custatus_valid_o5_net_1));
    SLE cudata_rvalid_o (.D(N_7350_i), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_DATA_RVALID));
    CFG4 #( .INIT(16'hFFDC) )  un1_burstlen_memwr_data130_1_0_0 (.A(
        ucnrbg_length_o_0), .B(N_7397), .C(do_mem_wr25), .D(N_7386), 
        .Y(un1_burstlen_memwr_data130_1_i));
    SLE \cfdatain_d1[20]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[20] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_20));
    CFG4 #( .INIT(16'hFFFE) )  \resp_curr_state_ns_i_o2[19]  (.A(
        N_5305), .B(N_4237), .C(N_5301), .D(N_5157_i), .Y(N_4265));
    CFG2 #( .INIT(4'h8) )  cudata_wrdy_d1_RNIUAH51 (.A(cfdatain_o21), 
        .B(ucnrbg_length_o_0), .Y(g2_0_0_0));
    CFG4 #( .INIT(16'hEEE2) )  \burstlen_memwr_data[3]  (.A(N_6032), 
        .B(burstlen_memwr_data_sn_N_6_mux), .C(
        burstlen_memwr_data_10_sqmuxa), .D(
        \burstlen_memwr_data_cnst[4] ), .Y(
        \burstlen_memwr_data[3]_net_1 ));
    CFG3 #( .INIT(8'h80) )  \req_curr_state_ns_i_i_a3_0_1[19]  (.A(
        my_hpms_top_0_COMM_BLK_INT), .B(\req_curr_state[13]_net_1 ), 
        .C(idle_trigger), .Y(N_8136_1));
    CFG3 #( .INIT(8'hC9) )  \memrd_data_addr_cnst_8_0_.m4x  (.A(
        N_7542_i), .B(N_5293_i), .C(N_5354_i), .Y(i3_mux));
    CFG3 #( .INIT(8'hF2) )  \resp_curr_state_ns_0[12]  (.A(
        \resp_curr_state[12]_net_1 ), .B(fcbusreq_d1_net_1), .C(N_7640)
        , .Y(\resp_curr_state_ns[12] ));
    CFG4 #( .INIT(16'hF8FA) )  \cfdatain_o_0_iv_0_2_0[13]  (.A(N_8069), 
        .B(do_mem_wr27_s9), .C(N_7975), .D(N_7351_1), .Y(
        \cfdatain_o_0_iv_0_2_0[13]_net_1 ));
    CFG3 #( .INIT(8'h73) )  un1_req_curr_state_24_0_a3_2_0_c (.A(
        uclatchcmd_o[0]), .B(\req_curr_state[12]_net_1 ), .C(
        uclatchcmd_o[2]), .Y(un1_req_curr_state_24_0_a3_2_0_c_net_1));
    CFG4 #( .INIT(16'h0100) )  \req_curr_state_ns_i_0_a2_1_1[5]  (.A(
        req_curr_state_0), .B(uclatchcmd_o[2]), .C(uclatchcmd_o[0]), 
        .D(uclatchcmd_o[3]), .Y(
        \req_curr_state_ns_i_0_a2_1_1[5]_net_1 ));
    CFG4 #( .INIT(16'h00DF) )  cfdatain_o_iv_0_7_N_5L9 (.A(N_6101_2), 
        .B(N_7388), .C(N_8052), .D(do_mem_wr26_s8), .Y(
        cfdatain_o_iv_0_7_N_5L9_net_1));
    CFG4 #( .INIT(16'h000E) )  cfrd_resp_o_i_i_a2_1 (.A(N_7446), .B(
        N_7447), .C(cucmd_error_net_1), .D(N_7381), .Y(
        cfrd_resp_o_0_sqmuxa_1));
    CFG4 #( .INIT(16'hF1F0) )  un1_idle_trigger_4_i_2_0_o2 (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[1]), .C(N_7531), .D(N_5322_i)
        , .Y(N_7485));
    SLE \burstlen_memrd_data_d1[5]  (.D(N_7917_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[5]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_4_sqmuxa_0_a2_2 (.A(
        N_7465), .B(N_7450), .C(ucvalid_cmd_o), .D(N_6101_2), .Y(
        N_7436_2));
    CFG2 #( .INIT(4'hB) )  un2_cudata_wrdy_int_1 (.A(cfdatain_o21), .B(
        N_7556_i), .Y(un2_cudata_wrdy_int_1_0));
    CFG2 #( .INIT(4'h8) )  \cfdatain_o_iv_0_a2_6[29]  (.A(
        memwr_desc_int33), .B(cfdatain_o21), .Y(N_8069));
    CFG2 #( .INIT(4'h2) )  set_puf_getkcnum_RNI54OP (.A(
        uclatchcmd_o[0]), .B(set_puf_getkcnum_net_1), .Y(N_7543_i));
    CFG4 #( .INIT(16'hFFFB) )  \req_curr_state_RNISR3P[23]  (.A(
        \req_curr_state[24]_net_1 ), .B(N_5194_0), .C(
        \req_curr_state[23]_net_1 ), .D(\req_curr_state[9]_net_1 ), .Y(
        \req_dstreg_data_cnst_0[4] ));
    SLE \req_curr_state[26]  (.D(\req_curr_state_ns[26] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[26]_net_1 )
        );
    SLE \desc_datasel_cntr[13]  (.D(\desc_datasel_cntr_s[13] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[13]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  cmdrcv_998 (.A(mchready_i), .B(
        cmdrcv_net_1), .C(syssvc_blk_0_AHBL_MASTER_HRDATA[7]), .Y(
        cmdrcv_998_net_1));
    CFG4 #( .INIT(16'h0A0E) )  \cfdatain_o_iv_RNO_0[4]  (.A(
        \req_dstreg_data_0_iv_0[4]_net_1 ), .B(ucnrbg_handle_o[4]), .C(
        un2_cudata_wrdy_int_9), .D(N_7700), .Y(\cfdatain_o_iv_1[4] ));
    SLE \cudata_r_o[19]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[19]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[19]));
    CFG2 #( .INIT(4'hB) )  un1_req_phase_done_d1_1_i_o4 (.A(
        \req_curr_state[25]_net_1 ), .B(req_phase_done_d1_net_1), .Y(
        main_next_state14));
    CFG4 #( .INIT(16'h0ACE) )  \req_curr_state_ns_0_0_1[18]  (.A(
        \req_curr_state[29]_net_1 ), .B(\req_curr_state[18]_net_1 ), 
        .C(N_7496), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_0_0_1[18]_net_1 ));
    SLE \req_curr_state[2]  (.D(\req_curr_state_ns[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[2]_net_1 ));
    CFG4 #( .INIT(16'h0200) )  burstlen_memrd_data_2_sqmuxa_1_0_a2_0 (
        .A(ucvalid_cmd_o), .B(N_5292_i), .C(N_7543_i), .D(N_6101_2), 
        .Y(N_7453));
    SLE \desc_datasel_cntr[24]  (.D(\desc_datasel_cntr_s[24] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[24]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_2_sqmuxa_1_0_a2 (.A(
        N_8049), .B(N_7448), .C(N_7450), .D(burstlen_memwr_desc34_2), 
        .Y(burstlen_memrd_data_2_sqmuxa_1));
    CFG3 #( .INIT(8'hE0) )  \resp_srcreg_data_d1_RNO[1]  (.A(
        \resp_srcreg_data_d1[1]_net_1 ), .B(
        \resp_curr_state[21]_net_1 ), .C(N_4374_i), .Y(N_7353_i));
    CFG2 #( .INIT(4'h4) )  \memrd_data_addr_cnst_8_0_.m1  (.A(N_7542_i)
        , .B(N_5354_i), .Y(m1));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_i_0_a3_2[5]  (.A(
        fcbusreq_d1_net_1), .B(\req_curr_state[5]_net_1 ), .Y(N_7589));
    CFG3 #( .INIT(8'h40) )  do_mem_wr27 (.A(do_mem_wr27_sx_net_1), .B(
        N_7685_i), .C(do_mem_wr27_0_0), .Y(do_mem_wr27_net_1));
    CFG4 #( .INIT(16'hAADC) )  un2_uclatchcmd_i_mux_16_i_2 (.A(
        cudata_r_o[6]), .B(cudata_r_o[1]), .C(cudata_r_o[0]), .D(
        N_8094), .Y(un2_uclatchcmd_i_mux_16_i_2_net_1));
    CFG3 #( .INIT(8'h14) )  \burstlen_memwr_desc_3_0_.m11_i_o4  (.A(
        N_7685_i), .B(N_7543_i), .C(N_7542_i), .Y(N_7919));
    SLE \memwr_data_addr_r[13]  (.D(\memwr_data_addr_cnst[13] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(memwr_data_addr_3_sqmuxa), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \memwr_data_addr_r[13]_net_1 ));
    CFG4 #( .INIT(16'h00E4) )  \cfburst_len_wr_o_1[4]  (.A(N_7481_i), 
        .B(\cfburst_len_wr_d1[4]_net_1 ), .C(
        \burstlen_memwr_data[4]_net_1 ), .D(cfburst_len_wr_o_1_sn_N_3), 
        .Y(cfburst_len_wr_o[4]));
    SLE \resp_srcreg_data_d1[3]  (.D(N_4185_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_4425_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_data_d1[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  desc_datasel_cntr_s_810 (.A(VCC_net_1), 
        .B(\req_curr_state[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(VCC_net_1), .S(), .Y(), .FCO(desc_datasel_cntr_s_810_FCO));
    SLE \cfdatain_d1[9]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[9]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  unreg_cmd5_31 (.A(unreg_cmd5_21_net_1), 
        .B(unreg_cmd5_22_net_1), .C(unreg_cmd5_28_net_1), .D(
        unreg_cmd5_29_net_1), .Y(unreg_cmd5_31_net_1));
    CFG4 #( .INIT(16'h0400) )  un1_do_mem_wr32_1 (.A(N_7386), .B(
        un1_do_mem_wr32_1_2_net_1), .C(do_mem_wr25), .D(
        un1_do_mem_wr32_1_0), .Y(un1_do_mem_wr32_1_i));
    SLE \cfdatain_d1[5]  (.D(\cfdatain_d1_RNO[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7894_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_5));
    CFG4 #( .INIT(16'h2000) )  \desc_datasel_cntr_RNITBQV4[0]  (.A(
        \desc_datasel_cntr[0]_net_1 ), .B(\desc_datasel_cntr[1]_net_1 )
        , .C(m2_e_24), .D(m2_e_25), .Y(N_23_mux));
    CFG4 #( .INIT(16'h4000) )  burstlen_memwr_data_12_sqmuxa_0_a2 (.A(
        N_7543_i), .B(burstlen_memwr_data110), .C(N_7457), .D(N_7474), 
        .Y(burstlen_memwr_data_12_sqmuxa));
    CFG4 #( .INIT(16'hFFF4) )  custatus_out_en_0 (.A(
        reset_puf_getkcnum_net_1), .B(custatus_out_en_0_1_net_1), .C(
        \req_curr_state[32]_net_1 ), .D(\req_curr_state[33]_net_1 ), 
        .Y(custatus_out_en));
    SLE \cudata_r_o[6]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[6]));
    CFG4 #( .INIT(16'h7FFF) )  cfwr_req_o_RNO (.A(
        cfwr_req_d_i_a3_8_net_1), .B(N_7555), .C(
        cfwr_req_d_i_a3_7_net_1), .D(cfwr_req_d_i_a3_6_net_1), .Y(
        N_7595_i));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_0_o4_0[1]  (.A(
        ucvalid_cmd_o), .B(set_puf_getkcnum_net_1), .Y(N_5546));
    SLE \cfdatain_d1[16]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_8), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[16]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \memrd_data_addr_cnst_8_0_.m23_e  (.A(
        N_5293_i), .B(N_5292_i), .Y(do_mem_wr33_i_1_0));
    CFG3 #( .INIT(8'h01) )  un1_cfburst_len_wr_o13_i_a2_0_2 (.A(
        \resp_curr_state[26]_net_1 ), .B(\resp_curr_state[1]_net_1 ), 
        .C(\req_curr_state[3]_net_1 ), .Y(
        un1_cfburst_len_wr_o13_i_a2_0_2_net_1));
    CFG4 #( .INIT(16'h2D1E) )  \resp_curr_state_ns_1_0_x2[3]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[3]), .C(uclatchcmd_o[1]), .D(
        uclatchcmd_o[2]), .Y(N_82_i));
    CFG2 #( .INIT(4'h7) )  \req_next_state_i_o2_5[1]  (.A(cmdrcv_net_1)
        , .B(rcvokay_net_1), .Y(N_5736));
    SLE \req_curr_state[30]  (.D(\req_curr_state_ns[30] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[30]_net_1 )
        );
    CFG3 #( .INIT(8'hB0) )  resp_phase_active_i_i (.A(N_8105), .B(
        un1_fctrans_done_i_i), .C(\main_curr_state[1]_net_1 ), .Y(
        resp_phase_active_i_i_net_1));
    SLE \cudata_r_o[14]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[14]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[14]));
    CFG4 #( .INIT(16'h0040) )  cmd_error_1_sqmuxa_0_a2_i_a2_RNIG1QP2 (
        .A(N_7515), .B(fctrans_done_o), .C(
        un2_uclatchcmd_i_mux_11_NE_net_1), .D(N_8093_i), .Y(N_7482_i));
    CFG3 #( .INIT(8'h04) )  \cfsrc_addr_o_2_a2_0[2]  (.A(N_4413_i), .B(
        \resp_srcreg_addr[2] ), .C(resp_curr_state_6), .Y(N_7426));
    CFG4 #( .INIT(16'hCFEF) )  \resp_srcreg_addr_0_iv[3]  (.A(
        \resp_srcreg_addr_d1[3]_net_1 ), .B(
        \resp_curr_state[21]_net_1 ), .C(N_7515), .D(N_4294_i), .Y(
        \resp_srcreg_addr[3] ));
    SLE \resp_curr_state[5]  (.D(\resp_curr_state_ns[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_curr_state_5));
    CFG2 #( .INIT(4'h1) )  \req_curr_state_ns_i_0_a2_0_0[13]  (.A(
        \req_curr_state[33]_net_1 ), .B(\req_curr_state[13]_net_1 ), 
        .Y(N_7711_3));
    CFG4 #( .INIT(16'hFFF1) )  cfgrant_o_inst_1 (.A(resp_curr_state_0), 
        .B(\resp_curr_state[1]_net_1 ), .C(cfgrant_req), .D(RSTSYNC1), 
        .Y(cfgrant_o));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_ns_0_0_a3_0_0[36]  (.A(
        \req_curr_state[12]_net_1 ), .B(fctrans_done_d1_net_1), .Y(
        \req_curr_state_ns_0_0_a3_0_0[36]_net_1 ));
    SLE \cfburst_len_wr_d1[0]  (.D(\cfburst_len_wr_o[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[0]_net_1 ));
    CFG4 #( .INIT(16'hC4C0) )  cfrd_resp_o_i_i_a2_3 (.A(
        set_puf_getkcnum_net_1), .B(ucvalid_cmd_o), .C(do_mem_wr25), 
        .D(do_mem_wr32), .Y(N_7446));
    CFG4 #( .INIT(16'hFCF8) )  \cfburst_len_wr_o_1_2[0]  (.A(
        \cfburst_len_wr_o_1_2_a2_0_0[1]_net_1 ), .B(N_8056), .C(N_7920)
        , .D(cfburst_len_wr_o_1_2_250_tz_2), .Y(\cfburst_len_wr_o[0] ));
    CFG2 #( .INIT(4'h1) )  cfcommaccess_active_0_a4_0_a2_0 (.A(
        \req_curr_state[2]_net_1 ), .B(\req_curr_state[1]_net_1 ), .Y(
        N_7876));
    CFG4 #( .INIT(16'h7BDE) )  un2_uclatchcmd_i_mux_11_NE_3 (.A(
        cudata_r_o[3]), .B(cudata_r_o[1]), .C(N_5293_i), .D(N_5354_i), 
        .Y(un2_uclatchcmd_i_mux_11_NE_3_net_1));
    SLE \desc_datasel_cntr[30]  (.D(\desc_datasel_cntr_s[30] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[30]_net_1 ));
    SLE \resp_curr_state[1]  (.D(\resp_curr_state_ns_i_i_a2[1]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[1]_net_1 )
        );
    CFG4 #( .INIT(16'h0001) )  un1_req_curr_state_24_0_0_0_RNIRNEM (.A(
        \req_curr_state[3]_net_1 ), .B(
        un1_req_curr_state_24_0_0_0_net_1), .C(N_7796), .D(
        \req_next_state_i_a12_6_i_0[1]_net_1 ), .Y(un1_m2_e_1));
    SLE \cfdatain_d1[10]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_2), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[10]_net_1 ));
    CFG3 #( .INIT(8'h51) )  \cfburst_len_rd_d1_RNO[5]  (.A(N_7929), .B(
        un1_req_curr_state_24_i), .C(cfrd_resp_o_0_sqmuxa_1), .Y(
        N_7898_i));
    SLE \cfburst_len_wr_d1[6]  (.D(cfburst_len_wr_o[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_wr_d1[6]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \burstlen_memrd_data_2[6]  (.A(
        ucvalid_cmd_o), .B(burstlen_memrd_data_2_sqmuxa_1), .C(
        \burstlen_memrd_data_d1[6]_net_1 ), .Y(N_6075));
    CFG3 #( .INIT(8'h20) )  un1_latchen_hrdata_int_4_0_i_a2_0_a2 (.A(
        N_7670), .B(uclatchcmd_o[3]), .C(N_5332), .Y(N_5345));
    CFG3 #( .INIT(8'h80) )  do_mem_wr27_0 (.A(N_5293_i), .B(N_5354_i), 
        .C(N_7543_i), .Y(do_mem_wr27_0_0));
    SLE \burstlen_memwr_data_r[3]  (.D(\burstlen_memwr_data[3]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memwr_data_r[3]_net_1 ));
    CFG4 #( .INIT(16'hAA30) )  \cfburst_len_rd_o_1[3]  (.A(
        \burstlen_memrd_data[3]_net_1 ), .B(un1_req_curr_state_24_i), 
        .C(\cfburst_len_rd_d1[3]_net_1 ), .D(cfrd_resp_o_0_sqmuxa_1), 
        .Y(cfburst_len_rd_o[3]));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[24]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[24]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[23]_net_1 ), .S(
        \desc_datasel_cntr_s[24] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[24]_net_1 ));
    CFG4 #( .INIT(16'hCCCD) )  \cfdst_addr_o_iv_0_0[13]  (.A(
        memwr_data_addr_3_sqmuxa), .B(N_7934), .C(
        \memwr_data_addr_r[13]_net_1 ), .D(N_7556_i), .Y(
        \cfdst_addr_o_iv_0_0[13]_net_1 ));
    CFG4 #( .INIT(16'hFFF4) )  \req_curr_state_ns_0_0[1]  (.A(N_5545), 
        .B(N_5546), .C(\req_curr_state_ns_0_0_1[1]_net_1 ), .D(N_7576), 
        .Y(\req_curr_state_ns[1] ));
    CFG4 #( .INIT(16'h5F7F) )  \resp_curr_state_ns_1_tz[3]  (.A(
        idle_trigger), .B(\resp_curr_state_ns_3_i_1_0[3]_net_1 ), .C(
        N_82_i), .D(N_5345), .Y(\resp_curr_state_ns_1_tz[3]_net_1 ));
    CFG4 #( .INIT(16'hFF20) )  \req_curr_state_ns_i_0_3[5]  (.A(
        \req_curr_state[4]_net_1 ), .B(uclatchcmd_o[2]), .C(N_7667), 
        .D(\req_curr_state_ns_i_0_2[5]_net_1 ), .Y(
        \req_curr_state_ns_i_0_3[5]_net_1 ));
    SLE \desc_datasel_cntr[16]  (.D(\desc_datasel_cntr_s[16] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[16]_net_1 ));
    CFG2 #( .INIT(4'h1) )  burstlen_memrd_data77_4 (.A(N_7684_i), .B(
        N_7683_i), .Y(N_6101_2));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_s[31]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[31]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[30]_net_1 ), .S(
        \desc_datasel_cntr_s[31]_net_1 ), .Y(), .FCO());
    CFG4 #( .INIT(16'h8000) )  do_mem_wr33_0_a2 (.A(N_5354_i), .B(
        N_7543_i), .C(do_mem_wr33_i_1_0), .D(N_7472), .Y(do_mem_wr33));
    CFG3 #( .INIT(8'h01) )  \cfdatain_o_0_iv_0_a2_1_3_1[2]  (.A(N_7806)
        , .B(N_7544_i), .C(N_7818), .Y(
        \cfdatain_o_0_iv_0_a2_1_3_1[2]_net_1 ));
    SLE \memwr_data_addr_r[14]  (.D(memwr_data_addr_2_sqmuxa), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(memwr_data_addr_3_sqmuxa), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \memwr_data_addr_r[14]_net_1 ));
    CFG3 #( .INIT(8'hF8) )  \req_curr_state_ns_0_0[11]  (.A(
        \req_curr_state[18]_net_1 ), .B(fcbusreq_d1_net_1), .C(N_7708), 
        .Y(\req_curr_state_ns[11] ));
    CFG4 #( .INIT(16'h7FFF) )  memwr_data_addr_3_sqmuxa_0_a2 (.A(
        N_8049), .B(burstlen_memwr_data110), .C(
        burstlen_memwr_desc34_2), .D(N_8052), .Y(
        memwr_data_addr_3_sqmuxa));
    SLE \resp_srcreg_data_d1[4]  (.D(\resp_srcreg_data_cnst[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_4425_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_data_d1[4]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \resp_curr_state_RNI47M5[2]  (.A(
        \resp_curr_state[2]_net_1 ), .B(\resp_curr_state[20]_net_1 ), 
        .Y(N_4389_i));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNII1QL[24]  (.A(
        \desc_datasel_cntr[27]_net_1 ), .B(
        \desc_datasel_cntr[26]_net_1 ), .C(
        \desc_datasel_cntr[25]_net_1 ), .D(
        \desc_datasel_cntr[24]_net_1 ), .Y(m2_e_17));
    CFG3 #( .INIT(8'h80) )  do_mem_wr25_0_a2_RNIAPKQ (.A(
        ucnrbg_length_o_0), .B(ucvalid_cmd_o), .C(do_mem_wr25), .Y(
        N_7351_i));
    CFG4 #( .INIT(16'hDCFF) )  \cfdatain_o_iv_0_7[29]  (.A(N_7894_i), 
        .B(\cfdatain_o_iv_0_o2_3_s_0[29]_net_1 ), .C(
        \cfdatain_d1[29]_net_1 ), .D(cfdatain_o_iv_0_7_N_8L15_net_1), 
        .Y(cfdatain_o_iv_0_7_0));
    CFG4 #( .INIT(16'hECCC) )  
        req_dstreg_data20_0_a2_0_a2_0_a3_RNI4E3F2 (.A(
        req_dstreg_data20), .B(\req_dstreg_data_0_iv_0_0[4] ), .C(
        ucnrbg_handle_o[4]), .D(\req_curr_state[12]_net_1 ), .Y(g2_0));
    SLE \cfdatain_d1[27]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[27] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_27));
    CFG4 #( .INIT(16'hDDDF) )  \memwr_desc_addr_i[29]  (.A(N_8049), .B(
        N_7477), .C(m15_1), .D(m15), .Y(N_7342));
    SLE cmd_error_d1 (.D(cmd_error), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cmd_error_d1_net_1));
    CFG4 #( .INIT(16'h0020) )  cfdst_addr_o33_0_a3 (.A(
        \resp_curr_state[23]_net_1 ), .B(\req_curr_state[6]_net_1 ), 
        .C(N_7556_i), .D(\req_curr_state[2]_net_1 ), .Y(cfdst_addr_o33)
        );
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[25]  (.A(cfdatain_d1_25), 
        .B(memwr_desc_int_m_14), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[25] ));
    CFG4 #( .INIT(16'hFFAE) )  \cfdatain_o_0_iv_0_1[14]  (.A(N_7963), 
        .B(\cfdatain_d1[14]_net_1 ), .C(N_7894_i), .D(N_7965), .Y(
        cfdatain_o_0_iv_0_1_0));
    CFG3 #( .INIT(8'h04) )  cfgrant_req_0_a4_0_a2 (.A(
        \req_curr_state[1]_net_1 ), .B(N_7888), .C(req_curr_state_0), 
        .Y(cfgrant_req));
    CFG4 #( .INIT(16'h8000) )  
        un1_burstlen_memwr_data130_1_0_a2_2_RNIRCIL1 (.A(N_7450), .B(
        N_8082), .C(N_7455), .D(N_8049), .Y(do_mem_wr26_s8));
    CFG3 #( .INIT(8'hEC) )  \resp_curr_state_ns_0[3]  (.A(
        fcbusreq_d1_net_1), .B(\resp_curr_state_ns_2[3]_net_1 ), .C(
        \resp_curr_state[10]_net_1 ), .Y(
        \resp_curr_state_ns_0[3]_net_1 ));
    CFG4 #( .INIT(16'h5155) )  \resp_curr_state_RNO[26]  (.A(
        \resp_curr_state_ns_i_0_0[26]_net_1 ), .B(N_7488), .C(
        \resp_curr_state[25]_net_1 ), .D(fctrans_done_o), .Y(N_4141_i));
    CFG4 #( .INIT(16'hF2F0) )  
        \cfburst_len_wr_o_1_2_a2_0_2_RNIGJIR2[0]  (.A(N_47), .B(
        N_5292_i), .C(\cfburst_len_wr_o_1_2_a2_0[0] ), .D(N_8076), .Y(
        cfburst_len_wr_o_1_2_250_tz_1));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[27]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[27]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[26]_net_1 ), .S(
        \desc_datasel_cntr_s[27] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[27]_net_1 ));
    CFG4 #( .INIT(16'hCCCE) )  \resp_curr_state_ns[3]  (.A(N_4212), .B(
        \resp_curr_state_ns_2_1[3]_net_1 ), .C(idle_trigger), .D(
        N_4237), .Y(\resp_curr_state_ns[3]_net_1 ));
    SLE \req_curr_state[4]  (.D(\req_curr_state_ns[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[4]_net_1 ));
    CFG4 #( .INIT(16'h5101) )  \burstlen_memrd_data_0[0]  (.A(
        burstlen_memrd_data_4_sqmuxa), .B(d_N_5), .C(
        burstlen_m3_0_a2_1), .D(burstlen_memrd_data_1_sqmuxa_1), .Y(
        \burstlen_memrd_data[0] ));
    CFG2 #( .INIT(4'h1) )  \resp_curr_state_ns_o2_10_o2_i_a3[3]  (.A(
        uclatchcmd_o[3]), .B(N_7670), .Y(N_5134_i_0));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_0_iv_0_a2[14]  (.A(
        memwr_data_addr_2_sqmuxa), .B(cfdatain_o21), .C(
        memwr_desc_int33), .Y(N_7963));
    CFG4 #( .INIT(16'hAA30) )  \cfburst_len_rd_o_1[6]  (.A(
        \burstlen_memrd_data[6]_net_1 ), .B(un1_req_curr_state_24_i), 
        .C(\cfburst_len_rd_d1[6]_net_1 ), .D(cfrd_resp_o_0_sqmuxa_1), 
        .Y(cfburst_len_rd_o[6]));
    CFG4 #( .INIT(16'h0100) )  datawr_reqd_0_a2 (.A(do_mem_wr32), .B(
        un1_do_mem_wr32_1_i), .C(set_puf_getkcnum_net_1), .D(
        ucvalid_cmd_o), .Y(datawr_reqd));
    CFG3 #( .INIT(8'hFE) )  \req_next_state_i_a12_3_1_0_i_o2_0[1]  (.A(
        \req_curr_state[28]_net_1 ), .B(\req_curr_state[18]_net_1 ), 
        .C(\req_curr_state[3]_net_1 ), .Y(N_7800));
    CFG3 #( .INIT(8'hFE) )  \cfdatain_o_iv_0_o4_0[29]  (.A(
        memwr_desc_int34), .B(memwr_desc_int33), .C(memwr_desc_int35), 
        .Y(N_7912));
    CFG4 #( .INIT(16'h00E4) )  \cfburst_len_wr_o_1_2_a2_0[2]  (.A(
        N_7481_i), .B(\cfburst_len_wr_d1[2]_net_1 ), .C(
        \burstlen_memwr_data[2]_net_1 ), .D(cfburst_len_wr_o_1_sn_N_3), 
        .Y(N_8000));
    CFG4 #( .INIT(16'hEFEE) )  
        \req_next_state_0_a12_3_0_a2_RNIET561[0]  (.A(
        un1_m5_i_a3_0_3_1), .B(N_5757), .C(my_hpms_top_0_COMM_BLK_INT), 
        .D(\req_curr_state[7]_net_1 ), .Y(un1_m5_i_a3_0_3));
    SLE \asynchevent_curr_state[0]  (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(RSTSYNC1));
    SLE \req_curr_state[35]  (.D(\req_curr_state_ns[35] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[35]_net_1 )
        );
    SLE \req_curr_state[1]  (.D(\req_curr_state_ns[1] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[1]_net_1 ));
    SLE txtokay (.D(txtokay_1000_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(txtokay_net_1));
    CFG3 #( .INIT(8'hFE) )  \resp_curr_state_ns_o2_10[3]  (.A(N_5301), 
        .B(N_5305), .C(N_5157_i), .Y(N_4212));
    CFG3 #( .INIT(8'hFD) )  \cfdatain_o_iv_0[29]  (.A(
        cfdatain_N_8_mux_i_0), .B(cfdatain_o_iv_0_7_0), .C(
        cfdatain_o_iv_0_4_0), .Y(\syssvc_blk_0_AHBL_MASTER_HWDATA[29] )
        );
    SLE \desc_datasel_cntr[3]  (.D(\desc_datasel_cntr_s[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[3]_net_1 ));
    CFG4 #( .INIT(16'h3350) )  \main_curr_state_ns_0_i_m3[1]  (.A(
        N_8105), .B(N_5299_i), .C(\main_curr_state[1]_net_1 ), .D(
        \main_curr_state[0]_net_1 ), .Y(N_8108));
    SLE \desc_datasel_cntr[28]  (.D(\desc_datasel_cntr_s[28] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[28]_net_1 ));
    CFG2 #( .INIT(4'hE) )  resp_data_done_RNO (.A(
        \resp_curr_state[4]_net_1 ), .B(resp_curr_state_0), .Y(
        N_4295_i));
    CFG4 #( .INIT(16'hC4EE) )  set_sent_options_r_1003 (.A(
        \req_curr_state[12]_net_1 ), .B(set_sent_options_r_net_1), .C(
        set_sent_options_3_0_0_0_tz_net_1), .D(N_7792), .Y(
        set_sent_options_r_1003_net_1));
    SLE \req_curr_state[3]  (.D(\req_curr_state_ns[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[3]_net_1 ));
    SLE \resp_srcreg_data_d1[1]  (.D(N_7353_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_data_d1[1]_net_1 ));
    CFG3 #( .INIT(8'h23) )  \resp_srcreg_addr_f0_0_a3[16]  (.A(
        \resp_srcreg_addr_d1[16]_net_1 ), .B(
        \resp_curr_state[23]_net_1 ), .C(N_4366_i), .Y(
        \resp_srcreg_addr[16] ));
    CFG2 #( .INIT(4'hB) )  \resp_curr_state_ns_3_i_o2[3]  (.A(
        fctrans_done_o), .B(\resp_curr_state[3]_net_1 ), .Y(N_7688));
    CFG4 #( .INIT(16'hFFBF) )  \resp_curr_state_ns_i_i2_5_0_o2[28]  (
        .A(uclatchcmd_o[3]), .B(uclatchcmd_o[1]), .C(N_5134_i_0), .D(
        N_5154), .Y(resp_next_state102));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[5]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[5]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[4]_net_1 ), .S(\desc_datasel_cntr_s[5] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[5]_net_1 ));
    CFG3 #( .INIT(8'h31) )  cfdatain_o_iv_N_2L1 (.A(N_5194), .B(N_7806)
        , .C(N_7690), .Y(cfdatain_o_iv_N_2L1_net_1));
    CFG4 #( .INIT(16'hFF40) )  burstlen_memrd_data_4_sqmuxa_0_0 (.A(
        N_5293_i), .B(N_5354_i), .C(N_7436_2), .D(N_7430), .Y(
        burstlen_memrd_data_4_sqmuxa));
    CFG2 #( .INIT(4'h2) )  \resp_srcreg_addr_RNI06BM[13]  (.A(N_8228), 
        .B(\resp_srcreg_addr[13]_net_1 ), .Y(
        \resp_srcreg_addr_i_m[13] ));
    SLE \cfsrc_addr_d1[13]  (.D(cfsrc_addr_o_11), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[13]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  
        \req_next_state_i_a12_3_1_0_i_a2_1_5[1]  (.A(N_7876), .B(
        \req_next_state_i_a12_3_1_0_i_a2_1_2[1]_net_1 ), .C(
        burstlen_memwr_data110), .D(
        \req_next_state_i_a12_3_1_0_i_a2_1_1[1]_net_1 ), .Y(
        \req_next_state_i_a12_3_1_0_i_a2_1_5[1]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  \req_next_state_i_a12_7_5[1]  (.A(
        \req_next_state_i_a12_7_1[1]_net_1 ), .B(N_7711_3), .C(
        \req_curr_state[29]_net_1 ), .D(\req_curr_state[26]_net_1 ), 
        .Y(\req_next_state_i_a12_7_5[1]_net_1 ));
    CFG4 #( .INIT(16'hFF32) )  \req_next_state_0_a12_1_a2_RNI4MR31[0]  
        (.A(\req_curr_state[7]_net_1 ), .B(idle_trigger), .C(N_7801), 
        .D(N_5753), .Y(un1_m5_i_a3_0_2));
    CFG4 #( .INIT(16'hB380) )  \memrd_data_addr_cnst_8_0_.m20  (.A(
        N_7685_i), .B(N_7543_i), .C(N_32_mux), .D(
        memrd_data_addr_cnst_7ro), .Y(m20));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[18]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[18]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[17]_net_1 ), .S(
        \desc_datasel_cntr_s[18] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[18]_net_1 ));
    CFG3 #( .INIT(8'h0B) )  \req_dstreg_data_cnst_i_a2_2_i_a2[2]  (.A(
        uclatchcmd_o[0]), .B(N_5331_i), .C(N_5322_i), .Y(N_7821));
    CFG4 #( .INIT(16'h8F0F) )  \resp_curr_state_ns_o2_10_o4_0[3]  (.A(
        N_5134_i_0), .B(uclatchcmd_o[1]), .C(N_7792), .D(N_5133), .Y(
        N_5157_i));
    CFG2 #( .INIT(4'h4) )  \req_curr_state_ns_i_0_a2_0[13]  (.A(
        idle_trigger), .B(\req_curr_state[11]_net_1 ), .Y(N_7708));
    SLE \req_curr_state[27]  (.D(\req_curr_state_ns[27] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[27]_net_1 )
        );
    SLE \cfdst_addr_d1[3]  (.D(cfdst_addr_o_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[3]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  cfwr_req_d_i_a3_7 (.A(
        \req_curr_state[1]_net_1 ), .B(\req_curr_state[34]_net_1 ), .C(
        \req_curr_state[16]_net_1 ), .D(\req_curr_state[22]_net_1 ), 
        .Y(cfwr_req_d_i_a3_7_net_1));
    CFG2 #( .INIT(4'h8) )  \burstlen_memrd_data_0_RNO_1[0]  (.A(
        do_mem_wr33), .B(ucvalid_cmd_o), .Y(
        \burstlen_memrd_data_0_RNO_1[0]_net_1 ));
    CFG4 #( .INIT(16'h88C0) )  \req_curr_state_ns_0_0_a2[3]  (.A(
        uclatchcmd_o[3]), .B(N_7674), .C(uclatchcmd_o[1]), .D(
        uclatchcmd_o[0]), .Y(N_7658));
    CFG4 #( .INIT(16'h0800) )  un1_latchen_hrdata_int_6_i_a2_1 (.A(
        uclatchcmd_o[3]), .B(N_5345), .C(uclatchcmd_o[1]), .D(
        uclatchcmd_o[0]), .Y(N_7506));
    CFG4 #( .INIT(16'hFF20) )  \req_curr_state_ns_i_0_2[5]  (.A(N_7664)
        , .B(N_7560), .C(\req_curr_state_ns_i_0_a3_5_1[5]_net_1 ), .D(
        \req_curr_state_ns_i_0_1[5]_net_1 ), .Y(
        \req_curr_state_ns_i_0_2[5]_net_1 ));
    CFG4 #( .INIT(16'h73F3) )  
        un1_cfburst_len_wr_o13_i_a2_0_2_RNIFQND1 (.A(
        un1_cfburst_len_wr_o13_i_a2_0_3_net_1), .B(N_4863_i), .C(
        idle_trigger), .D(un1_cfburst_len_wr_o13_i_a2_0_2_net_1), .Y(
        N_7481_i));
    CFG3 #( .INIT(8'hF4) )  \req_curr_state_ns_0_0[6]  (.A(
        fctrans_done_o), .B(\req_curr_state[6]_net_1 ), .C(N_7589), .Y(
        \req_curr_state_ns[6] ));
    CFG4 #( .INIT(16'h0222) )  \cfdatain_o_0_iv_0_a2_1_3[2]  (.A(
        \cfdatain_o_0_iv_0_a2_1_3_1[2]_net_1 ), .B(N_7841), .C(
        \req_dstreg_data_cnst_m_i_a2_0_1[2]_net_1 ), .D(N_5331_i), .Y(
        \cfdatain_o_0_iv_0_a2_1_3[2]_net_1 ));
    CFG4 #( .INIT(16'hFFEF) )  un2_cudata_wrdy_int_9_inst_1 (.A(
        cfdatain_o26), .B(cfdatain_o28), .C(N_7894_i), .D(
        un2_cudata_wrdy_int_9_sx_net_1), .Y(un2_cudata_wrdy_int_9));
    SLE \burstlen_memwr_data_r[2]  (.D(\burstlen_memwr_data[2]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memwr_data_r[2]_net_1 ));
    CFG4 #( .INIT(16'h4440) )  \req_curr_state_ns_0_0_2[1]  (.A(N_5545)
        , .B(N_7664), .C(N_7658), .D(\req_curr_state_ns_0_0_a3_1[1] ), 
        .Y(\req_curr_state_ns_0_0_2[1]_net_1 ));
    CFG4 #( .INIT(16'hFFF8) )  \cfsrc_addr_o_2[2]  (.A(N_7456), .B(
        \cfsrc_addr_d1[2]_net_1 ), .C(N_7426), .D(N_7421), .Y(
        cfsrc_addr_o_0));
    SLE \req_curr_state[9]  (.D(\req_curr_state_ns[9] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[9]_net_1 ));
    SLE \cfdatain_d1[17]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_9), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[17]_net_1 ));
    CFG4 #( .INIT(16'hC0EA) )  \resp_curr_state_ns_0[20]  (.A(
        \resp_curr_state[20]_net_1 ), .B(\resp_curr_state[11]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(idle_trigger), .Y(
        \resp_curr_state_ns[20] ));
    CFG4 #( .INIT(16'hFEFA) )  cfrd_resp_o_i_i (.A(
        cfrd_resp_o_i_i_0_net_1), .B(cfrd_resp_o_i_i_a2_0_net_1), .C(
        cfrd_resp_o_0_sqmuxa_1), .D(N_7374), .Y(cfrd_resp_o));
    CFG3 #( .INIT(8'hC4) )  cfdatain_o_iv_0_N_5L7 (.A(
        ucnrbg_handle_o[7]), .B(cfdatain_o_iv_0_N_5L7_1_net_1), .C(
        N_7700), .Y(cfdatain_o_iv_0_N_5L7_net_1));
    CFG4 #( .INIT(16'hA0EC) )  \resp_curr_state_ns[23]  (.A(
        \resp_curr_state[22]_net_1 ), .B(\resp_curr_state[23]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \resp_curr_state_ns[23]_net_1 ));
    CFG3 #( .INIT(8'hFE) )  cfrd_resp_o_i_i_o2_0 (.A(cmdrcv_net_1), .B(
        resp_next_state102), .C(\resp_curr_state[2]_net_1 ), .Y(N_7374)
        );
    CFG2 #( .INIT(4'h8) )  \resp_curr_state_RNO[14]  (.A(mchready_i), 
        .B(\resp_curr_state[13]_net_1 ), .Y(N_4124_i));
    CFG2 #( .INIT(4'h2) )  set_puf_getkcnum_RNI87OP_0 (.A(
        uclatchcmd_o[3]), .B(set_puf_getkcnum_net_1), .Y(N_7685_i));
    CFG3 #( .INIT(8'h04) )  \req_curr_state_ns_0_0_a2_1_3[22]  (.A(
        N_7670), .B(uclatchcmd_o[3]), .C(uclatchcmd_o[4]), .Y(
        \req_curr_state_ns_0_0_a2_1_2[22]_net_1 ));
    CFG4 #( .INIT(16'h0020) )  \req_curr_state_ns_0_0_a3_1_0[3]  (.A(
        \req_curr_state[2]_net_1 ), .B(set_puf_getkcnum_net_1), .C(
        fctrans_done_o), .D(N_7550), .Y(
        \req_curr_state_ns_0_0_a3_1[3] ));
    SLE \req_curr_state[13]  (.D(N_5501_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[13]_net_1 )
        );
    CFG4 #( .INIT(16'h0007) )  \burstlen_memrd_data_d1_RNO[4]  (.A(
        ucvalid_cmd_o), .B(do_mem_wr33), .C(
        \burstlen_memrd_data_i_o2_0[4]_net_1 ), .D(
        burstlen_memrd_data_4_sqmuxa), .Y(N_7916_i));
    CFG4 #( .INIT(16'hF888) )  \cfsrc_addr_o_2[29]  (.A(N_7456), .B(
        \cfsrc_addr_d1[29]_net_1 ), .C(memrd_data_addr_cnst_8ro), .D(
        N_7461), .Y(cfsrc_addr_o_27));
    CFG4 #( .INIT(16'hCC80) )  \cfdatain_o_0_iv_0_a2_1[14]  (.A(
        do_mem_wr27_s9), .B(\memwr_desc_int_m_1[8] ), .C(
        ucnrbg_handle_o[6]), .D(do_mem_wr26_s8), .Y(N_7965));
    CFG2 #( .INIT(4'h8) )  resp_next_state4 (.A(RSTSYNC1), .B(
        resp_phase_active_pulse_net_1), .Y(resp_next_state4_net_1));
    SLE rcvokay (.D(rcvokay_999_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK)
        , .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(rcvokay_net_1));
    CFG2 #( .INIT(4'h2) )  \req_curr_state_ns_0_0_a2_2[1]  (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[2]), .Y(N_7674));
    CFG4 #( .INIT(16'hEFAF) )  \resp_curr_state_ns_0[0]  (.A(
        \resp_curr_state_ns_0_0[0]_net_1 ), .B(
        \resp_curr_state[3]_net_1 ), .C(N_7355), .D(N_7469), .Y(
        \resp_curr_state_ns[0] ));
    CFG2 #( .INIT(4'h1) )  burstlen_memrd_data_0_sqmuxa_3_0_a2_0 (.A(
        N_7685_i), .B(N_5354_i), .Y(N_7448));
    CFG4 #( .INIT(16'h0040) )  \desc_datasel_cntr_RNICBR95[1]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[1]_net_1 )
        , .C(N_4_0), .D(\desc_datasel_cntr[2]_net_1 ), .Y(
        memwr_desc_int35));
    CFG4 #( .INIT(16'h7F00) )  
        req_dstreg_data20_0_a2_0_a2_0_a3_RNISSIA2 (.A(
        \req_curr_state[12]_net_1 ), .B(ucnrbg_handle_o[1]), .C(
        req_dstreg_data20), .D(g2_0_0), .Y(cfdatain_o_iv_N_5_3_0));
    CFG4 #( .INIT(16'h44F4) )  \req_curr_state_ns_0_0[28]  (.A(N_5736), 
        .B(\req_curr_state_ns_0_0_a2_0_1[28]_net_1 ), .C(
        \req_curr_state[28]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[28] ));
    CFG4 #( .INIT(16'hDC50) )  \resp_curr_state_ns_0_0[0]  (.A(
        resp_next_state4_net_1), .B(fctrans_done_o), .C(
        resp_curr_state_0), .D(resp_curr_state_6), .Y(
        \resp_curr_state_ns_0_0[0]_net_1 ));
    CFG4 #( .INIT(16'h0010) )  un1_do_mem_wr32_2_0_a2_0 (.A(N_5354_i), 
        .B(N_7685_i), .C(N_5292_i), .D(N_5293_i), .Y(N_7457));
    CFG3 #( .INIT(8'hBA) )  un1_custatus_out_en2_0_0_o2_0 (.A(N_8144), 
        .B(\resp_curr_state[15]_net_1 ), .C(N_7381), .Y(N_7355));
    CFG3 #( .INIT(8'h46) )  \req_curr_state_ns_0_o4_2[1]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[3]), .C(uclatchcmd_o[2]), .Y(
        N_5562));
    SLE \desc_datasel_cntr[4]  (.D(\desc_datasel_cntr_s[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[4]_net_1 ));
    CFG4 #( .INIT(16'hA0EC) )  \resp_curr_state_RNO[29]  (.A(
        \resp_curr_state[28]_net_1 ), .B(\resp_curr_state[29]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(N_7521_i));
    SLE \req_curr_state[22]  (.D(\req_curr_state_ns[22] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[22]_net_1 )
        );
    CFG2 #( .INIT(4'h4) )  cfdatain_o_iv_N_3L3 (.A(N_7700), .B(
        ucnrbg_handle_o[1]), .Y(cfdatain_o_iv_N_3L3_net_1));
    SLE \cudata_r_o[9]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[9]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[9]));
    CFG4 #( .INIT(16'h0008) )  un1_latchen_hrdata_int_6_i_a2_0 (.A(
        N_6101_2), .B(un1_latchen_hrdata_int_6_i_a2_0_0_net_1), .C(
        N_7542_i), .D(N_7685_i), .Y(N_7505));
    CFG4 #( .INIT(16'h7BDE) )  un2_uclatchcmd_i_mux_11_NE_1 (.A(
        cudata_r_o[2]), .B(cudata_r_o[5]), .C(N_7542_i), .D(N_7685_i), 
        .Y(un2_uclatchcmd_i_mux_11_NE_1_net_1));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_iv_0_a2_2_0[29]  (.A(
        memwr_desc_int33), .B(ucvalid_cmd_o), .C(cfdatain_o21), .Y(
        \cfdatain_o_iv_0_a2_2_0[29]_net_1 ));
    SLE \req_curr_state[31]  (.D(\req_curr_state_ns_i_i[31]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[31]_net_1 )
        );
    CFG4 #( .INIT(16'h0001) )  un1_burstlen_memwr_data130_1_0_a2_1_0 (
        .A(N_7683_i), .B(N_7684_i), .C(N_5292_i), .D(N_7543_i), .Y(
        un1_burstlen_memwr_data130_1_0_a2_1_0_net_1));
    SLE \resp_curr_state[0]  (.D(\resp_curr_state_ns[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_curr_state_0));
    CFG2 #( .INIT(4'h8) )  un1_resp_curr_state_10_i_a2 (.A(N_4413_i), 
        .B(N_4395_i), .Y(N_4366_i));
    CFG4 #( .INIT(16'h0008) )  un1_req_curr_state_24_0_a3_2_1_3 (.A(
        N_7874), .B(un1_req_curr_state_24_0_a3_2_0_c_net_1), .C(
        \req_curr_state[31]_net_1 ), .D(\req_curr_state[11]_net_1 ), 
        .Y(un1_req_curr_state_24_0_a3_2_1_3_net_1));
    CFG3 #( .INIT(8'hBA) )  \req_curr_state_ns_0_0_o3[3]  (.A(N_7658), 
        .B(uclatchcmd_o[3]), .C(N_7549), .Y(N_7553));
    CFG4 #( .INIT(16'h8000) )  \cfburst_len_wr_o_1_0[3]  (.A(N_7919), 
        .B(N_47), .C(\cfburst_len_wr_o_1_0_1[3]_net_1 ), .D(N_6101_2), 
        .Y(N_6101));
    CFG4 #( .INIT(16'hFFAE) )  \req_curr_state_ns_i_0_1[5]  (.A(N_7589)
        , .B(N_7560), .C(fctrans_done_o), .D(N_7592), .Y(
        \req_curr_state_ns_i_0_1[5]_net_1 ));
    CFG4 #( .INIT(16'hA0C0) )  \cfdatain_o_iv_RNO[4]  (.A(
        \resp_srcreg_data_cnst[4] ), .B(\resp_srcreg_data_d1[4]_net_1 )
        , .C(N_8225), .D(N_4425_i), .Y(\resp_srcreg_data_m[4] ));
    SLE \resp_srcreg_addr_d1[2]  (.D(\resp_srcreg_addr[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_addr_d1[2]_net_1 ));
    CFG2 #( .INIT(4'hE) )  \req_curr_state_ns_i_0_o3[5]  (.A(N_7556), 
        .B(\req_curr_state[2]_net_1 ), .Y(N_7560));
    CFG2 #( .INIT(4'h8) )  \req_next_state_i_a4_0_0_a3_0[1]  (.A(
        fctrans_done_o), .B(\req_curr_state[31]_net_1 ), .Y(
        \req_next_state_i_a4_0_0_a3_0[1]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  \resp_srcreg_addr_1_f0_i_o2[4]  (.A(
        \resp_curr_state[21]_net_1 ), .B(N_4389_i), .C(N_7372), .D(
        N_4374_i), .Y(N_7379));
    CFG3 #( .INIT(8'hEA) )  \resp_curr_state_ns_0[8]  (.A(
        \resp_curr_state[30]_net_1 ), .B(\resp_curr_state[8]_net_1 ), 
        .C(N_7689), .Y(\resp_curr_state_ns_0[8]_net_1 ));
    CFG4 #( .INIT(16'hCE0A) )  \req_curr_state_ns_0_0[10]  (.A(
        \req_curr_state[10]_net_1 ), .B(\req_curr_state[16]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[10] ));
    SLE \desc_datasel_cntr[2]  (.D(\desc_datasel_cntr_s[2] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \req_next_state_i_a4_0_0_a3[1]  (.A(
        N_8093_i), .B(\req_next_state_i_a4_0_0_a3_0[1]_net_1 ), .Y(
        \req_curr_state_ns[33] ));
    CFG2 #( .INIT(4'h7) )  req_dstreg_data_1_sqmuxa_1_0_a4_i_o2 (.A(
        req_dstreg_data20), .B(\req_curr_state[12]_net_1 ), .Y(N_7700));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[28]  (.A(cfdatain_d1_28), 
        .B(memwr_desc_int_m_17), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[28] ));
    CFG4 #( .INIT(16'h8000) )  burstlen_memwr_desc34_0_a2 (.A(N_7543_i)
        , .B(N_5354_i), .C(memwr_desc_5_sqmuxa_2_0), .D(
        burstlen_memwr_desc34_2), .Y(burstlen_memwr_desc34));
    SLE \resp_curr_state[20]  (.D(\resp_curr_state_ns[20] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[20]_net_1 ));
    SLE \cfdatain_d1[0]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[0] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_0));
    CFG2 #( .INIT(4'h1) )  cudata_rvalid_o_2_i_a2 (.A(
        resp_curr_state_6), .B(resp_curr_state_5), .Y(N_7470));
    SLE \cfdst_addr_d1[12]  (.D(cfdst_addr_o_10), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[12]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  \req_next_state_i_a12_3_1_0_i_o2[1]  (
        .A(\req_curr_state[27]_net_1 ), .B(\req_curr_state[10]_net_1 ), 
        .C(\req_curr_state[9]_net_1 ), .D(\req_curr_state[6]_net_1 ), 
        .Y(N_7796));
    CFG4 #( .INIT(16'hFCFE) )  \cfdst_addr_o_0_iv_0[29]  (.A(
        \req_curr_state[2]_net_1 ), .B(N_7995), .C(
        \cfdst_addr_o_0_iv_0_1[29]_net_1 ), .D(N_7342), .Y(
        cfdst_addr_o_27));
    CFG2 #( .INIT(4'h2) )  \req_curr_state_RNI1LBC[2]  (.A(N_7556_i), 
        .B(\req_curr_state[2]_net_1 ), .Y(N_7462));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[10]  (.A(
        \cfburst_len_rd_d1[10]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[10]));
    CFG4 #( .INIT(16'h8C00) )  \req_next_state_i_o2_5_RNI9ID51[1]  (.A(
        txtokay_net_1), .B(\req_curr_state[14]_net_1 ), .C(N_5736), .D(
        idle_trigger), .Y(un1_m1_e_0_0));
    CFG4 #( .INIT(16'hEEE4) )  \burstlen_memrd_data_2[7]  (.A(
        ucvalid_cmd_o), .B(\burstlen_memrd_data_d1[7]_net_1 ), .C(
        burstlen_memrd_data_2_sqmuxa_1), .D(
        burstlen_memrd_data_3_sqmuxa_net_1), .Y(N_6076));
    SLE \resp_curr_state[26]  (.D(N_4141_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[26]_net_1 ));
    SLE \cfdst_addr_d1[16]  (.D(cfdst_addr_o_14), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[16]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \memrd_data_addr_cnst_8_0_.m4_e  (.A(
        N_5293_i), .B(N_5292_i), .Y(
        burstlen_memrd_data_1_sqmuxa_1_0_a2_1_0));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNI6HLL[12]  (.A(
        \desc_datasel_cntr[15]_net_1 ), .B(
        \desc_datasel_cntr[14]_net_1 ), .C(
        \desc_datasel_cntr[13]_net_1 ), .D(
        \desc_datasel_cntr[12]_net_1 ), .Y(m2_e_20));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[1]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[1]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[0]_net_1 ), .S(\desc_datasel_cntr_s[1] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[1]_net_1 ));
    SLE \desc_datasel_cntr[21]  (.D(\desc_datasel_cntr_s[21] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[21]_net_1 ));
    CFG4 #( .INIT(16'hBBBA) )  \cfdatain_o_iv[3]  (.A(
        \cfdatain_o_iv_0[3]_net_1 ), .B(un2_cudata_wrdy_int_9), .C(
        \req_dstreg_data_0_iv_0[3]_net_1 ), .D(
        \ucnrbg_handle_i_m_2[3] ), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[3] ));
    SLE \req_curr_state[6]  (.D(\req_curr_state_ns[6] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[6]_net_1 ));
    CFG4 #( .INIT(16'h0010) )  \desc_datasel_cntr_RNICBR95_0[1]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[1]_net_1 )
        , .C(N_4_0), .D(\desc_datasel_cntr[2]_net_1 ), .Y(
        memwr_desc_int33));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNI55GA8[1]  (.A(
        do_mem_wr26_s8), .B(memwr_desc_int35), .C(ucnrbg_handle_o[1]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_14));
    CFG4 #( .INIT(16'hFEFF) )  \req_next_state_i_1_0_0_a2_1_2[5]  (.A(
        \req_curr_state[3]_net_1 ), .B(
        \req_next_state_i_1_0_0_a2_c[5]_net_1 ), .C(N_5709_1_0_2), .D(
        N_7876), .Y(\req_next_state_i_1_0_0_a2_1_2[5]_net_1 ));
    CFG3 #( .INIT(8'h10) )  do_mem_wr32_0_a2_1 (.A(N_7685_i), .B(
        N_7543_i), .C(N_5292_i), .Y(do_mem_wr32_0_a2_1_net_1));
    CFG2 #( .INIT(4'hE) )  \req_next_state_i_a12_3_1_0_i_o2_4[1]  (.A(
        \req_curr_state[11]_net_1 ), .B(\req_curr_state[8]_net_1 ), .Y(
        N_7801));
    CFG3 #( .INIT(8'h40) )  \cfdatain_o_iv_0_a2_5[29]  (.A(N_7542_i), 
        .B(N_5293_i), .C(N_5354_i), .Y(N_8065));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_RNIDSFK3[23]  (.A(N_7_0), 
        .B(\req_curr_state[23]_net_1 ), .Y(g2_0_1));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[16]  (.A(
        \cfdatain_d1[16]_net_1 ), .B(ucnrbg_handle_o[0]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_8));
    CFG4 #( .INIT(16'hAE0C) )  \resp_curr_state_ns_0[4]  (.A(
        \resp_curr_state[12]_net_1 ), .B(\resp_curr_state[4]_net_1 ), 
        .C(idle_trigger), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[4] ));
    CFG4 #( .INIT(16'hC5F5) )  \cfburst_len_rd_o_1_i_m2[4]  (.A(
        \cfburst_len_rd_d1[4]_net_1 ), .B(
        \burstlen_memrd_data_i_o2_0[4]_net_1 ), .C(
        cfrd_resp_o_0_sqmuxa_1), .D(burstlen_memrd_data_sn_N_6), .Y(
        N_7931));
    CFG4 #( .INIT(16'h0800) )  \req_next_state_i_a12_3_4_RNICNPU3[1]  
        (.A(\req_next_state_i_a12_3_4[1]_net_1 ), .B(N_7792), .C(
        \req_next_state_i_a12_3_1_0_i_o2_5[1] ), .D(un1_m2_e_1), .Y(
        un1_N_5_mux_0));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[12]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[12]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[11]_net_1 ), .S(
        \desc_datasel_cntr_s[12] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[12]_net_1 ));
    CFG4 #( .INIT(16'hEEE2) )  \burstlen_memrd_data_2[3]  (.A(
        \burstlen_memrd_data_d1[3]_net_1 ), .B(ucvalid_cmd_o), .C(
        N_7341_i), .D(burstlen_memrd_data_8_sqmuxa), .Y(N_6072));
    CFG4 #( .INIT(16'h3BBB) )  
        un1_req_curr_state_24_0_a3_2_1_5_RNIHR6E2 (.A(
        un1_req_curr_state_24_0_a3_2_1_5_net_1), .B(N_5709), .C(
        \req_curr_state[12]_net_1 ), .D(N_7790), .Y(un1_m5_i_a3_0_8));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_RNI6LPD[11]  (.A(
        set_puf_getkcnum_net_1), .B(\req_curr_state[11]_net_1 ), .Y(
        g1_0_0));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[9]  (.A(
        \cfdatain_d1[9]_net_1 ), .B(ucnrbg_handle_o[1]), .C(N_8070), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_1));
    CFG4 #( .INIT(16'hEAAA) )  
        req_dstreg_data20_0_a2_0_a2_0_a3_RNIC5P32 (.A(
        \req_dstreg_data_0_iv_0_0[3] ), .B(req_dstreg_data20), .C(
        ucnrbg_handle_o[3]), .D(\req_curr_state[12]_net_1 ), .Y(g3));
    CFG3 #( .INIT(8'h04) )  \cfdst_addr_o_0_iv_0_a2_1[29]  (.A(
        memwr_data_addr_3_sqmuxa), .B(\memwr_data_addr_r[29]_net_1 ), 
        .C(N_7556_i), .Y(N_7995));
    CFG4 #( .INIT(16'hCE0A) )  \resp_curr_state_ns[18]  (.A(
        \resp_curr_state[18]_net_1 ), .B(\resp_curr_state[19]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns[18]_net_1 ));
    SLE \desc_datasel_cntr[17]  (.D(\desc_datasel_cntr_s[17] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[17]_net_1 ));
    SLE \req_curr_state[14]  (.D(\req_curr_state_ns[14] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[14]_net_1 )
        );
    CFG4 #( .INIT(16'h0400) )  \cfburst_len_wr_o_1_2_a2_3_3[0]  (.A(
        N_7685_i), .B(do_mem_wr33_i_1_0), .C(N_5354_i), .D(N_7542_i), 
        .Y(\cfburst_len_wr_o_1_2_a2_3_3[0]_net_1 ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[23]  (.A(
        \cfdatain_d1[23]_net_1 ), .B(ucnrbg_handle_o[7]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_15));
    CFG4 #( .INIT(16'h3F35) )  
        \req_dstreg_addr_i_a4_0_a2_0_i_o2_RNITMOJ1[4]  (.A(g2_1), .B(
        uclatchcmd_o[1]), .C(N_7544_i), .D(N_7806), .Y(g2_0_0));
    SLE \burstlen_memrd_data_d1[7]  (.D(\burstlen_memrd_data[7]_net_1 )
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[7]_net_1 ));
    SLE \main_curr_state[0]  (.D(\main_curr_state_ns[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\main_curr_state[0]_net_1 )
        );
    SLE \resp_curr_state[4]  (.D(\resp_curr_state_ns[4] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[4]_net_1 )
        );
    SLE \cfburst_len_rd_d1[8]  (.D(cfburst_len_rd_o[8]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[8]_net_1 ));
    SLE \resp_srcreg_addr_d1[3]  (.D(\resp_srcreg_addr[3] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_addr_d1[3]_net_1 ));
    CFG3 #( .INIT(8'hF4) )  resp_data_done_RNI74CL (.A(
        resp_data_done_net_1), .B(\resp_curr_state[1]_net_1 ), .C(
        \req_curr_state[5]_net_1 ), .Y(resp_data_done_RNI74CL_net_1));
    SLE \resp_curr_state[14]  (.D(N_4124_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[14]_net_1 ));
    CFG4 #( .INIT(16'hE0C0) )  \cfdatain_o_iv_0_4[29]  (.A(N_7912), .B(
        cfdatain_o_iv_0_o2_2_out), .C(cfdatain_o21), .D(N_8077), .Y(
        cfdatain_o_iv_0_4_0));
    CFG3 #( .INIT(8'hEA) )  \req_curr_state_ns_0_0[12]  (.A(
        \req_curr_state_ns_0_0_0[12]_net_1 ), .B(
        set_sent_options_r_net_1), .C(N_8129_1), .Y(
        \req_curr_state_ns[12] ));
    CFG3 #( .INIT(8'h40) )  \desc_datasel_cntr_RNINTPQ4[0]  (.A(
        \desc_datasel_cntr[0]_net_1 ), .B(m2_e_24), .C(m2_e_25), .Y(
        N_4_0));
    CFG4 #( .INIT(16'h2000) )  \req_next_state_i_a12_7[1]  (.A(
        \req_next_state_i_a12_7_8[1]_net_1 ), .B(N_7792), .C(
        \req_next_state_i_a12_7_5[1]_net_1 ), .D(
        \req_next_state_i_a12_7_6[1]_net_1 ), .Y(N_5766));
    CFG2 #( .INIT(4'h2) )  \req_curr_state_ns_0_a2_4_1[1]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[2]), .Y(N_5681_1));
    SLE \cfdst_addr_d1[4]  (.D(cfdst_addr_o_2), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[4]_net_1 ));
    SLE \cudata_r_o[18]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[18]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[18]));
    CFG4 #( .INIT(16'h0305) )  \burstlen_memrd_data_0_RNO[0]  (.A(
        \burstlen_memrd_data_d1[0]_net_1 ), .B(ucnrbg_length_o_0), .C(
        \burstlen_memrd_data_0_RNO_1[0]_net_1 ), .D(
        burstlen_memrd_data_6_sqmuxa), .Y(d_N_5));
    CFG3 #( .INIT(8'h10) )  \memrd_data_addr_cnst_8_0_.m15_0  (.A(
        N_7685_i), .B(N_7543_i), .C(m7), .Y(m15_1));
    CFG3 #( .INIT(8'h10) )  \desc_datasel_cntr_RNICBR95[2]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[2]_net_1 )
        , .C(N_23_mux), .Y(memwr_desc_int34));
    CFG3 #( .INIT(8'hE0) )  \resp_srcreg_data_d1_RNIU0SE[1]  (.A(
        \resp_srcreg_data_d1[1]_net_1 ), .B(
        \resp_curr_state[21]_net_1 ), .C(N_4374_i), .Y(g0_6_0));
    CFG2 #( .INIT(4'h1) )  cfrd_resp_o_i_a2_4_0_a4_0_a2 (.A(
        resp_next_state102), .B(cmdrcv_net_1), .Y(N_5300));
    CFG4 #( .INIT(16'h0207) )  \req_curr_state_RNIC6US1[10]  (.A(
        N_7544_i), .B(N_7670), .C(cfdatain_o_iv_0_N_3_3_0), .D(
        cfdatain_o_iv_0_N_2_5_0), .Y(cfdatain_o_iv_0_N_5_3_0));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[8]  (.A(
        \cfdatain_d1[8]_net_1 ), .B(ucnrbg_handle_o[0]), .C(N_8070), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_0));
    CFG2 #( .INIT(4'hE) )  \req_dstreg_addr_i_a4_0_a2_0_i_o2[4]  (.A(
        \req_curr_state[12]_net_1 ), .B(\req_curr_state[35]_net_1 ), 
        .Y(N_7806));
    CFG4 #( .INIT(16'h0001) )  \req_next_state_i_a12_7_3[1]  (.A(
        \req_curr_state[30]_net_1 ), .B(\req_curr_state[36]_net_1 ), 
        .C(\req_curr_state[22]_net_1 ), .D(\req_curr_state[16]_net_1 ), 
        .Y(\req_next_state_i_a12_7_3[1]_net_1 ));
    CFG4 #( .INIT(16'h0004) )  \req_next_state_i_a2_1_0_a2_0_a2[1]  (
        .A(\req_curr_state[26]_net_1 ), .B(fcbusreq_d1_net_1), .C(
        \req_curr_state[15]_net_1 ), .D(\req_curr_state[1]_net_1 ), .Y(
        N_5783));
    CFG4 #( .INIT(16'hA0E4) )  
        \req_dstreg_addr_i_a4_0_a2_0_i_o2_RNI259O1[4]  (.A(N_7544_i), 
        .B(\req_dstreg_data_cnst_0[4] ), .C(uclatchcmd_o[4]), .D(
        N_7806), .Y(\req_dstreg_data_0_iv_0_0[4] ));
    CFG2 #( .INIT(4'h4) )  \req_curr_state_RNI6LPD_1[11]  (.A(
        set_puf_getkcnum_net_1), .B(\req_curr_state[11]_net_1 ), .Y(
        N_7544_i));
    CFG4 #( .INIT(16'hFFFE) )  cfrd_req_o_RNO (.A(
        \req_curr_state[30]_net_1 ), .B(\req_curr_state[28]_net_1 ), 
        .C(\req_curr_state[17]_net_1 ), .D(\req_curr_state[19]_net_1 ), 
        .Y(N_5252_i));
    CFG2 #( .INIT(4'h4) )  \cfdatain_o_0_iv_0_a2_0[2]  (.A(N_7894_i), 
        .B(cfdatain_d1_2), .Y(N_7984));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_0_iv_0_a2_3[13]  (.A(
        cfdatain_o21), .B(do_mem_wr26_s8), .C(memwr_desc_int34), .Y(
        N_7974));
    CFG3 #( .INIT(8'hB8) )  \resp_curr_state_ns_a2_i_m2[27]  (.A(
        \resp_curr_state[26]_net_1 ), .B(
        un2_uclatchcmd_i_mux_11_NE_net_1), .C(
        \resp_curr_state[29]_net_1 ), .Y(N_7492));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNI8URK[8]  (.A(
        \desc_datasel_cntr[11]_net_1 ), .B(
        \desc_datasel_cntr[10]_net_1 ), .C(
        \desc_datasel_cntr[9]_net_1 ), .D(\desc_datasel_cntr[8]_net_1 )
        , .Y(m2_e_14));
    CFG4 #( .INIT(16'hAA30) )  \cfburst_len_rd_o_1[7]  (.A(
        \burstlen_memrd_data[7]_net_1 ), .B(un1_req_curr_state_24_i), 
        .C(\cfburst_len_rd_d1[7]_net_1 ), .D(cfrd_resp_o_0_sqmuxa_1), 
        .Y(cfburst_len_rd_o[7]));
    CFG4 #( .INIT(16'hEAC0) )  do_mem_wr25_0_a2_RNI151TC (.A(
        do_mem_wr26_s8), .B(do_mem_wr25), .C(g1_0_1_0), .D(
        memwr_desc_int35), .Y(N_7903_0));
    CFG4 #( .INIT(16'h2000) )  \memrd_data_addr_cnst_8_0_.m15_1  (.A(
        N_7685_i), .B(N_7543_i), .C(m7_1), .D(m1), .Y(m15_0));
    SLE \desc_datasel_cntr[15]  (.D(\desc_datasel_cntr_s[15] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[15]_net_1 ));
    SLE \cudata_r_o[8]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[8]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[8]));
    CFG3 #( .INIT(8'h08) )  un1_idle_trigger_4_i_a2_4_a4_0_a3 (.A(
        uclatchcmd_o[3]), .B(N_7547), .C(uclatchcmd_o[1]), .Y(N_5301));
    CFG3 #( .INIT(8'hE4) )  \memwr_data_addr[14]  (.A(
        memwr_data_addr_3_sqmuxa), .B(\memwr_data_addr_r[14]_net_1 ), 
        .C(memwr_data_addr_2_sqmuxa), .Y(\memwr_data_addr[14]_net_1 ));
    CFG4 #( .INIT(16'hDC50) )  \cfdatain_d1_RNIH34D8[4]  (.A(N_7894_i), 
        .B(N_8225), .C(\cfdatain_d1[4]_net_1 ), .D(g1_0), .Y(g0_0));
    CFG4 #( .INIT(16'h22F2) )  \req_curr_state_ns_0_0[30]  (.A(
        \req_curr_state_ns_0_0_a2_0_1[30]_net_1 ), .B(N_5207_2), .C(
        \req_curr_state[30]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[30] ));
    CFG4 #( .INIT(16'h2000) )  \req_curr_state_ns_i_0_a2_2_2[13]  (.A(
        uclatchcmd_o[3]), .B(\req_curr_state[31]_net_1 ), .C(N_7711_2), 
        .D(N_7711_3), .Y(\req_curr_state_ns_i_0_a2_2_2[13]_net_1 ));
    SLE \burstlen_memrd_data_d1[3]  (.D(\burstlen_memrd_data[3]_net_1 )
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[3]_net_1 ));
    SLE \req_curr_state[36]  (.D(\req_curr_state_ns[36] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[36]_net_1 )
        );
    SLE \cfdatain_d1[2]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[2] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_2));
    CFG4 #( .INIT(16'hFFAB) )  \cfdatain_o_iv[1]  (.A(
        cfdatain_o_iv_N_4L5_net_1), .B(cfdatain_o_iv_N_5L7_net_1), .C(
        un2_cudata_wrdy_int_9), .D(\resp_srcreg_data_m[1] ), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[1] ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[18]  (.A(
        \cfdatain_d1[18]_net_1 ), .B(ucnrbg_handle_o[2]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_10));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_iv_RNO[3]  (.A(
        req_dstreg_data20), .B(ucnrbg_handle_o[3]), .C(
        \req_curr_state[12]_net_1 ), .Y(\ucnrbg_handle_i_m_2[3] ));
    CFG4 #( .INIT(16'h8000) )  \cfdatain_o_iv_0_o2_2_s_RNO[29]  (.A(
        ucnrbg_handle_o[5]), .B(N_7455), .C(N_8082), .D(N_7453), .Y(
        cfdatain_m1_0_a2_2_0));
    SLE \cudata_r_o[2]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[2]));
    CFG4 #( .INIT(16'hF044) )  \main_curr_state_ns_0_0_0[0]  (.A(
        \main_curr_state[1]_net_1 ), .B(uctrig_o), .C(
        main_next_state14), .D(\main_curr_state[0]_net_1 ), .Y(
        \main_curr_state_ns_0_0_0[0]_net_1 ));
    CFG4 #( .INIT(16'hE222) )  \cfburst_len_wr_o_1_2_1[1]  (.A(
        \cfburst_len_wr_d1[1]_net_1 ), .B(N_7481_i), .C(N_8049), .D(
        \cfburst_len_wr_o_1_2_1_1[1]_net_1 ), .Y(
        \cfburst_len_wr_o_1_2_1[1]_net_1 ));
    SLE resp_data_done (.D(\resp_curr_state[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_4295_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_data_done_net_1));
    CFG3 #( .INIT(8'h8B) )  \burstlen_memwr_data[0]  (.A(
        \burstlen_memwr_data_r[0]_net_1 ), .B(
        burstlen_memwr_data_12_sqmuxa), .C(
        \burstlen_memwr_data_1[0]_net_1 ), .Y(
        \burstlen_memwr_data[0]_net_1 ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[17]  (.A(
        \cfdatain_d1[17]_net_1 ), .B(ucnrbg_handle_o[1]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_9));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[24]  (.A(
        \cfdatain_d1[24]_net_1 ), .B(ucnrbg_handle_o[0]), .C(N_8017_1), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_16));
    SLE \req_curr_state[8]  (.D(\req_curr_state_ns[8] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[8]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  do_mem_wr25_0_a2_1 (.A(N_7685_i), .B(
        N_7543_i), .C(N_5293_i), .D(N_5354_i), .Y(
        do_mem_wr25_0_a2_1_net_1));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNIAB2K[4]  (.A(
        \desc_datasel_cntr[7]_net_1 ), .B(\desc_datasel_cntr[6]_net_1 )
        , .C(\desc_datasel_cntr[5]_net_1 ), .D(
        \desc_datasel_cntr[4]_net_1 ), .Y(m2_e_15));
    CFG4 #( .INIT(16'hF8F0) )  \cfdatain_o_0_iv_0_0[2]  (.A(
        cfdatain_o21), .B(ucnrbg_length_o_0), .C(N_7984), .D(N_7903), 
        .Y(\cfdatain_o_0_iv_0_0[2]_net_1 ));
    CFG3 #( .INIT(8'h01) )  \cfdst_addr_d1_RNO[13]  (.A(
        \resp_srcreg_addr_i_m[13] ), .B(
        \cfdst_addr_o_iv_0_0[13]_net_1 ), .C(
        \cfdst_addr_o_iv_0_1[13]_net_1 ), .Y(\cfdst_addr_o_iv_i[13] ));
    CFG2 #( .INIT(4'h8) )  \cfdatain_o_0_iv_0_a2_1_0[14]  (.A(
        memwr_desc_int34), .B(cfdatain_o21), .Y(
        \memwr_desc_int_m_1[8] ));
    CFG3 #( .INIT(8'hFE) )  \cfdst_addr_o_iv_0[13]  (.A(
        \resp_srcreg_addr_i_m[13] ), .B(
        \cfdst_addr_o_iv_0_0[13]_net_1 ), .C(
        \cfdst_addr_o_iv_0_1[13]_net_1 ), .Y(cfdst_addr_o_iv[13]));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[31]  (.A(
        \cfdatain_d1[31]_net_1 ), .B(ucnrbg_handle_o[7]), .C(N_8017_1), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_23));
    CFG3 #( .INIT(8'h80) )  \resp_curr_state_RNO[27]  (.A(N_7492), .B(
        N_8093_i), .C(fctrans_done_o), .Y(N_7483_i));
    CFG4 #( .INIT(16'hC0EA) )  \req_dstreg_data_0_iv_0[6]  (.A(
        ucnrbg_handle_o[6]), .B(N_7670), .C(N_7544_i), .D(N_7700), .Y(
        \req_dstreg_data[6] ));
    CFG4 #( .INIT(16'hFFF8) )  \cfburst_len_wr_o_1_2[1]  (.A(N_8006_2), 
        .B(do_mem_wr27_0_net_1), .C(\cfburst_len_wr_o_1_2_1[1]_net_1 ), 
        .D(N_8002), .Y(cfburst_len_wr_o[1]));
    CFG4 #( .INIT(16'h0100) )  \req_next_state_0_a12_3_0_a2[0]  (.A(
        \req_curr_state[34]_net_1 ), .B(\req_curr_state[17]_net_1 ), 
        .C(idle_trigger), .D(\req_curr_state[11]_net_1 ), .Y(N_5757));
    CFG3 #( .INIT(8'hBA) )  \resp_curr_state_ns[8]  (.A(
        \resp_curr_state_ns_2[8]_net_1 ), .B(N_7496), .C(
        \resp_curr_state[29]_net_1 ), .Y(\resp_curr_state_ns[8]_net_1 )
        );
    SLE \resp_curr_state[7]  (.D(\resp_curr_state_ns[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\resp_curr_state[7]_net_1 )
        );
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[11]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[11]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[10]_net_1 ), .S(
        \desc_datasel_cntr_s[11] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[11]_net_1 ));
    CFG2 #( .INIT(4'h8) )  
        \burstlen_memwr_data_cnst_4_2__burstlen_memwr_data_cnst_0_.m3  
        (.A(un1_burstlen_memwr_data132_1_i), .B(ucvalid_cmd_o), .Y(
        \burstlen_memwr_data_cnst[4] ));
    SLE \cudata_r_o[31]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[31]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[31]));
    CFG4 #( .INIT(16'h0F27) )  un1_cfdatain_o26_1_s_RNI0JRCF (.A(
        cfdatain_m2_0_a2_0_0), .B(
        \memwr_desc_addr_i_RNICAN58[29]_net_1 ), .C(N_7484), .D(
        un1_cfdatain_o26_1_out), .Y(cfdatain_N_8_mux_i_0));
    CFG3 #( .INIT(8'h04) )  un1_cfdst_addr_o33_RNI58SR (.A(N_8228), .B(
        N_7462), .C(un1_req_curr_state_21_i), .Y(
        un1_req_curr_state_22_i_0));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNI88GA8[1]  (.A(
        do_mem_wr26_s8), .B(memwr_desc_int35), .C(ucnrbg_handle_o[4]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_17));
    CFG4 #( .INIT(16'hF8F0) )  set_sent_options_3_0_0_0_tz (.A(
        N_5134_i_0), .B(uclatchcmd_o[1]), .C(req_dstreg_data20), .D(
        N_5133), .Y(set_sent_options_3_0_0_0_tz_net_1));
    CFG2 #( .INIT(4'h1) )  \req_next_state_i_a12_7_3_i_i3_i_a2_0[1]  (
        .A(\req_curr_state[24]_net_1 ), .B(\req_curr_state[35]_net_1 ), 
        .Y(N_7874));
    CFG3 #( .INIT(8'h01) )  \cfdatain_d1_RNO[5]  (.A(
        un2_cudata_wrdy_int_1_0), .B(cfdatain_N_5), .C(N_8225), .Y(
        \cfdatain_d1_RNO[5]_net_1 ));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[11]  (.A(cfdatain_d1_11), 
        .B(memwr_desc_int_m_0), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[11] ));
    SLE \burstlen_memrd_data_d1[0]  (.D(\burstlen_memrd_data[0] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[0]_net_1 ));
    CFG4 #( .INIT(16'hF900) )  \resp_curr_state_ns_2_i_a2[3]  (.A(
        uclatchcmd_o[4]), .B(uclatchcmd_o[2]), .C(uclatchcmd_o[0]), .D(
        N_7687), .Y(N_7722));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hFF1D) )  \burstlen_memrd_data_i_o2_0[5]  (.A(
        \burstlen_memrd_data_d1[5]_net_1 ), .B(ucvalid_cmd_o), .C(
        burstlen_memrd_data_3_sqmuxa_net_1), .D(
        burstlen_memrd_data_6_sqmuxa), .Y(
        \burstlen_memrd_data_i_o2_0[5]_net_1 ));
    CFG4 #( .INIT(16'hCE02) )  \resp_curr_state_RNO[21]  (.A(
        \resp_curr_state[21]_net_1 ), .B(\resp_curr_state[24]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(N_4134_i));
    CFG4 #( .INIT(16'h0001) )  cfwr_req_d_i_a3_6 (.A(
        \req_curr_state[3]_net_1 ), .B(\resp_curr_state[23]_net_1 ), 
        .C(\req_curr_state[36]_net_1 ), .D(\req_curr_state[15]_net_1 ), 
        .Y(cfwr_req_d_i_a3_6_net_1));
    CFG4 #( .INIT(16'hDC50) )  \cfdatain_d1_RNIM1A08[1]  (.A(N_7894_i), 
        .B(N_8225), .C(\cfdatain_d1[1]_net_1 ), .D(g0_7_0), .Y(g0_0_0));
    SLE \req_curr_state[5]  (.D(N_5492_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[5]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[9]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[9]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[8]_net_1 ), .S(\desc_datasel_cntr_s[9] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[9]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  \req_next_state_i_a12_3_4_2[1]  (.A(
        N_7711_3), .B(N_5310_2), .C(N_7800), .D(N_7796), .Y(
        \req_next_state_i_a12_3_4_2[1]_net_1 ));
    CFG2 #( .INIT(4'hE) )  un1_do_mem_wr32_2_0_0_0 (.A(do_mem_wr32), 
        .B(burstlen_memwr_desc34), .Y(un1_do_mem_wr32_2_0_0_0_net_1));
    CFG4 #( .INIT(16'hFFFE) )  un1_cfdst_addr_o33 (.A(cfdst_addr_o33), 
        .B(cfdst_addr_o34), .C(cfdst_addr_o41_net_1), .D(
        cfdst_addr_o42), .Y(N_8228));
    CFG2 #( .INIT(4'hE) )  \req_next_state_i_a12_3_1_0_i_o2_7[1]  (.A(
        N_7798), .B(\req_curr_state[2]_net_1 ), .Y(N_7804));
    CFG3 #( .INIT(8'h09) )  \req_curr_state_ns_0_0_a2_1_2[22]  (.A(
        uclatchcmd_o[2]), .B(uclatchcmd_o[0]), .C(uclatchcmd_o[1]), .Y(
        N_7711_2));
    CFG3 #( .INIT(8'h10) )  cfwr_req_d_i_a3_8 (.A(
        \req_curr_state[26]_net_1 ), .B(\req_curr_state[5]_net_1 ), .C(
        cfwr_req_d_i_a3_5_net_1), .Y(cfwr_req_d_i_a3_8_net_1));
    CFG3 #( .INIT(8'h01) )  \resp_curr_state_RNI9SJA[16]  (.A(
        \resp_curr_state[18]_net_1 ), .B(\resp_curr_state[16]_net_1 ), 
        .C(\req_curr_state[12]_net_1 ), .Y(
        \resp_curr_state_RNI9SJA[16]_net_1 ));
    CFG3 #( .INIT(8'h80) )  req_dstreg_data20_0_a2_0_a2_0_a3_RNI5CQM (
        .A(req_dstreg_data20), .B(ucnrbg_handle_o[7]), .C(
        \req_curr_state[12]_net_1 ), .Y(cfdatain_o_iv_0_N_3_3_0));
    CFG4 #( .INIT(16'hFFF8) )  \cfdst_addr_o_iv[14]  (.A(N_7928), .B(
        \req_curr_state[2]_net_1 ), .C(\resp_srcreg_addr_i_m[13] ), .D(
        \cfdst_addr_o_iv_0[14]_net_1 ), .Y(cfdst_addr_o_iv[14]));
    CFG4 #( .INIT(16'hC080) )  \cfdatain_o_iv_0_a2_4[29]  (.A(
        memwr_desc_int46), .B(burstlen_memwr_desc35), .C(N_7943_2), .D(
        memwr_desc_int47), .Y(N_7948));
    SLE resp_phase_done_pulse (.D(resp_phase_done_pulse_2_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        resp_phase_done_pulse_net_1));
    CFG2 #( .INIT(4'h4) )  cfdatain_o_iv_0_N_4L5 (.A(N_7894_i), .B(
        \cfdatain_d1[7]_net_1 ), .Y(cfdatain_o_iv_0_N_4L5_net_1));
    CFG4 #( .INIT(16'h0400) )  \req_dstreg_data_cnst_m_i_a2[2]  (.A(
        \req_curr_state[24]_net_1 ), .B(uclatchcmd_o[2]), .C(N_105_i), 
        .D(N_5322_i), .Y(N_7841));
    CFG2 #( .INIT(4'h4) )  \req_curr_state_ns_0_0_a3_2_1[1]  (.A(
        uclatchcmd_o[3]), .B(uclatchcmd_o[1]), .Y(N_7576_1));
    CFG4 #( .INIT(16'h88F8) )  \req_curr_state_ns_0_0[36]  (.A(
        \req_curr_state_ns_0_0_a3_0_0[36]_net_1 ), .B(N_5697), .C(
        \req_curr_state[36]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[36] ));
    SLE \cfburst_len_rd_d1[7]  (.D(cfburst_len_rd_o[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[7]_net_1 ));
    CFG4 #( .INIT(16'h4048) )  \req_curr_state_ns_0_0_a3_2[3]  (.A(
        uclatchcmd_o[3]), .B(\req_curr_state_ns_0_0_a3_1[3] ), .C(
        uclatchcmd_o[4]), .D(uclatchcmd_o[0]), .Y(
        \req_curr_state_ns_0_0_a3_2[3]_net_1 ));
    CFG4 #( .INIT(16'h04AE) )  \req_curr_state_ns_i_i[17]  (.A(
        \req_curr_state[17]_net_1 ), .B(\req_curr_state[7]_net_1 ), .C(
        N_7689), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_i_i[17]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \cfdatain_o_0_iv_0_a2_4[13]  (.A(
        memwr_desc_int34), .B(do_mem_wr27_s9), .C(ucnrbg_handle_o[5]), 
        .D(cfdatain_o21), .Y(N_7975));
    CFG3 #( .INIT(8'h20) )  unreg_cmd5_15 (.A(
        \resp_curr_state[3]_net_1 ), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[19]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[4]), .Y(unreg_cmd5_15_net_1));
    CFG4 #( .INIT(16'hFCA8) )  \cfdatain_o_iv_0_a2_10[29]  (.A(
        memwr_desc_int43), .B(N_7431), .C(N_7430), .D(memwr_desc_int42)
        , .Y(N_8079));
    CFG4 #( .INIT(16'hDC50) )  \cfdatain_o_iv_0[3]  (.A(N_7894_i), .B(
        N_8225), .C(\cfdatain_d1[3]_net_1 ), .D(
        \resp_srcreg_data[3]_net_1 ), .Y(\cfdatain_o_iv_0[3]_net_1 ));
    CFG4 #( .INIT(16'h8801) )  req_dstreg_data_2_sqmuxa_1_i_o2_0 (.A(
        uclatchcmd_o[2]), .B(uclatchcmd_o[4]), .C(uclatchcmd_o[3]), .D(
        uclatchcmd_o[0]), .Y(N_5133));
    CFG2 #( .INIT(4'hB) )  cmd_error_1_sqmuxa_0_a2_i_o2 (.A(N_8093_i), 
        .B(fctrans_done_o), .Y(N_7496));
    SLE cudata_wrdy_d1 (.D(r_N_3_mux), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cudata_wrdy_d1_net_1));
    CFG3 #( .INIT(8'hA2) )  \cfdst_addr_d1_RNO[30]  (.A(N_7462), .B(
        un1_req_curr_state_21_i), .C(\cfdst_addr_d1[30]_net_1 ), .Y(
        \cfdst_addr_o_0_iv_i[30] ));
    CFG3 #( .INIT(8'hF2) )  burstlen_memrd_data_1_sqmuxa_1_0_o2_0 (.A(
        do_mem_wr32), .B(set_puf_getkcnum_net_1), .C(do_mem_wr25), .Y(
        N_7365));
    SLE \cfburst_len_rd_d1[15]  (.D(cfburst_len_rd_o[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[15]_net_1 ));
    CFG2 #( .INIT(4'hB) )  un2_uclatchcmd_i_mux_16_i_o4 (.A(
        cudata_r_o[4]), .B(cudata_r_o[5]), .Y(N_8094));
    CFG2 #( .INIT(4'h8) )  \burstlen_memwr_data_2[3]  (.A(
        burstlen_memwr_data_12_sqmuxa), .B(
        \burstlen_memwr_data_r[3]_net_1 ), .Y(N_6032));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[10]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[10]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[9]_net_1 ), .S(
        \desc_datasel_cntr_s[10] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[10]_net_1 ));
    SLE \desc_datasel_cntr[20]  (.D(\desc_datasel_cntr_s[20] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[20]_net_1 ));
    SLE \cfdst_addr_d1[29]  (.D(cfdst_addr_o_27), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[29]_net_1 ));
    SLE \cfdatain_d1[31]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[31]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \cfdatain_d1_RNIF9N37[6]  (.A(N_7894_i), .B(
        \cfdatain_d1[6]_net_1 ), .Y(g2));
    CFG4 #( .INIT(16'h0020) )  un1_main_curr_state_2_0_a3_3 (.A(
        \resp_curr_state[14]_net_1 ), .B(reset_puf_getkcnum_net_1), .C(
        N_5668_1), .D(N_7670), .Y(un1_main_curr_state_2_0_a3_3_net_1));
    CFG4 #( .INIT(16'hFFFE) )  \req_next_state_0_a2_1_0_o2[0]  (.A(
        \req_curr_state[34]_net_1 ), .B(fcbusreq_d1_net_1), .C(
        \req_curr_state[22]_net_1 ), .D(\req_curr_state[17]_net_1 ), 
        .Y(N_7798));
    CFG3 #( .INIT(8'h10) )  \req_curr_state_ns_0_0_a2_1[1]  (.A(N_7670)
        , .B(uclatchcmd_o[2]), .C(ucvalid_cmd_o), .Y(N_7672));
    SLE \req_curr_state[10]  (.D(\req_curr_state_ns[10] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[10]_net_1 )
        );
    CFG3 #( .INIT(8'hF4) )  un1_req_curr_state_24_0_0_0 (.A(
        resp_data_done_net_1), .B(\resp_curr_state[1]_net_1 ), .C(
        \req_curr_state[5]_net_1 ), .Y(
        un1_req_curr_state_24_0_0_0_net_1));
    CFG2 #( .INIT(4'h8) )  req_dstreg_data20_0_a2_0_a2_0_a3 (.A(
        N_5331_i), .B(N_7656_1), .Y(req_dstreg_data20));
    CFG4 #( .INIT(16'hF0F7) )  cfwr_req_d_i_o3 (.A(txtokay_net_1), .B(
        \req_curr_state[8]_net_1 ), .C(N_7661), .D(idle_trigger), .Y(
        N_7555));
    CFG4 #( .INIT(16'hDC50) )  \cfdatain_d1_RNIIGEG8[3]  (.A(N_7894_i), 
        .B(N_8225), .C(\cfdatain_d1[3]_net_1 ), .D(
        \resp_srcreg_data_0[3] ), .Y(g0_0_2));
    CFG4 #( .INIT(16'h0001) )  cfwr_req_d_i_a3_5 (.A(
        \req_curr_state[18]_net_1 ), .B(\req_curr_state[21]_net_1 ), 
        .C(\resp_curr_state[16]_net_1 ), .D(\resp_curr_state[1]_net_1 )
        , .Y(cfwr_req_d_i_a3_5_net_1));
    SLE \burstlen_memwr_data_r[0]  (.D(\burstlen_memwr_data[0]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memwr_data_r[0]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNI66GA8[1]  (.A(
        do_mem_wr26_s8), .B(memwr_desc_int35), .C(ucnrbg_handle_o[2]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_15));
    CFG4 #( .INIT(16'h1420) )  \req_curr_state_ns_0_0_o2[3]  (.A(
        uclatchcmd_o[0]), .B(uclatchcmd_o[3]), .C(uclatchcmd_o[1]), .D(
        uclatchcmd_o[2]), .Y(N_7549));
    CFG2 #( .INIT(4'h8) )  \memwr_desc_0_a2[317]  (.A(
        burstlen_memwr_desc34), .B(ucvalid_cmd_o), .Y(N_7430));
    CFG4 #( .INIT(16'h7222) )  custatus_out_en_0_1 (.A(
        set_puf_getkcnum_net_1), .B(N_7355), .C(
        resp_phase_done_pulse_net_1), .D(\main_curr_state[1]_net_1 ), 
        .Y(custatus_out_en_0_1_net_1));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_0_sqmuxa_3_0_a2 (.A(
        N_7448), .B(burstlen_memrd_data_0_sqmuxa_3_0_a2_0_net_1), .C(
        burstlen_memwr_desc34_2), .D(N_8049), .Y(
        burstlen_memrd_data_0_sqmuxa_3));
    SLE \resp_curr_state[17]  (.D(\resp_curr_state_ns[17] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[17]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[3]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[3]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[2]_net_1 ), .S(\desc_datasel_cntr_s[3] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[3]_net_1 ));
    SLE \cfdst_addr_d1[30]  (.D(\cfdst_addr_o_0_iv_i[30] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[30]_net_1 ));
    SLE \resp_curr_state[30]  (.D(\resp_curr_state_ns[30] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[30]_net_1 ));
    CFG2 #( .INIT(4'h1) )  cmd_error_1_sqmuxa_0_a2_i_a2 (.A(
        \resp_curr_state[26]_net_1 ), .B(\resp_curr_state[29]_net_1 ), 
        .Y(N_7515));
    CFG4 #( .INIT(16'hA0E4) )  \req_curr_state_ns_i_i[16]  (.A(
        \req_curr_state[9]_net_1 ), .B(\req_curr_state[16]_net_1 ), .C(
        fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_i_i[16]_net_1 ));
    SLE \resp_curr_state[18]  (.D(\resp_curr_state_ns[18]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[18]_net_1 ));
    CFG4 #( .INIT(16'hA020) )  \resp_curr_state_ns_3_0_a2[8]  (.A(
        \resp_curr_state[20]_net_1 ), .B(rcvokay_net_1), .C(
        idle_trigger), .D(N_5300), .Y(N_7498));
    CFG3 #( .INIT(8'h20) )  \cfdatain_o_iv_0_a2_10_RNO_0[29]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[2]_net_1 )
        , .C(N_23_mux), .Y(memwr_desc_int42));
    SLE \cudata_r_o[26]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[26]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[26]));
    SLE req_phase_done_d1 (.D(\req_curr_state[25]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(req_phase_done_d1_net_1));
    CFG2 #( .INIT(4'h1) )  \req_curr_state_RNINVQ6[23]  (.A(
        \req_curr_state[24]_net_1 ), .B(\req_curr_state[23]_net_1 ), 
        .Y(N_7818));
    SLE \cudata_r_o[23]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[23]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[23]));
    CFG2 #( .INIT(4'hB) )  un1_resp_curr_state_4_i_a2 (.A(N_4425_i), 
        .B(N_4413_i), .Y(N_4294_i));
    CFG4 #( .INIT(16'hFFB0) )  cfrd_resp_o_i_i_o2_4 (.A(N_5293_i), .B(
        N_5292_i), .C(N_7465), .D(N_7439), .Y(N_7362));
    CFG2 #( .INIT(4'h4) )  set_puf_getkcnum_RNIMTSP_0 (.A(
        set_puf_getkcnum_net_1), .B(N_7670), .Y(N_7683_i));
    CFG4 #( .INIT(16'h0207) )  cfdatain_o_iv_N_5L7 (.A(N_7544_i), .B(
        uclatchcmd_o[1]), .C(cfdatain_o_iv_N_3L3_net_1), .D(
        cfdatain_o_iv_N_2L1_net_1), .Y(cfdatain_o_iv_N_5L7_net_1));
    SLE \cfburst_len_rd_d1[5]  (.D(N_7898_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[5]_net_1 ));
    CFG4 #( .INIT(16'hBFFF) )  cfdatain_o_iv_0_7_N_4L6 (.A(N_7543_i), 
        .B(N_8065), .C(memwr_desc_5_sqmuxa_2_0), .D(N_7943_2), .Y(
        cfdatain_o_iv_0_7_N_4L6_net_1));
    CFG4 #( .INIT(16'hD591) )  \cfburst_len_wr_o_1[3]  (.A(
        \cfburst_len_wr_o_1_1[3]_net_1 ), .B(N_7481_i), .C(
        \burstlen_memwr_data[3]_net_1 ), .D(N_6101), .Y(
        cfburst_len_wr_o[3]));
    SLE \burstlen_memrd_data_d1[2]  (.D(\burstlen_memrd_data[2]_net_1 )
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \burstlen_memrd_data_d1[2]_net_1 ));
    CFG4 #( .INIT(16'hC0CA) )  \req_curr_state_ns_i_0_m3[34]  (.A(
        \req_curr_state[34]_net_1 ), .B(fctrans_done_d1_net_1), .C(
        N_7806), .D(fcbusreq_d1_net_1), .Y(N_7566));
    SLE resp_phase_active_d1 (.D(resp_phase_active_i_i_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_phase_active_d1_net_1)
        );
    SLE \cfdatain_d1[6]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[6] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[6]_net_1 ));
    SLE \cfdatain_d1[21]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[21]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  \req_curr_state_ns_i_0_a3_4[5]  (.A(
        N_7662), .B(\req_curr_state_ns_i_0_a3_4_0[5]_net_1 ), .C(
        N_7672), .D(N_7550), .Y(N_7592));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[20]  (.A(cfdatain_d1_20), 
        .B(memwr_desc_int_m_9), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[20] ));
    CFG3 #( .INIT(8'h01) )  \req_next_state_0_a12_0_i_RNO[0]  (.A(
        \req_curr_state[27]_net_1 ), .B(\req_curr_state[9]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .Y(N_5733_i_0));
    CFG4 #( .INIT(16'hB3A0) )  \cfdst_addr_o_0_iv_0[12]  (.A(
        un1_req_curr_state_21_i), .B(N_7344), .C(
        \cfdst_addr_d1[12]_net_1 ), .D(\req_curr_state[2]_net_1 ), .Y(
        cfdst_addr_o_10));
    CFG4 #( .INIT(16'hFF7F) )  cfdatain_o29_0_a2_a0_sx (.A(
        cfdatain_o29_0_a2_a0_0), .B(N_7556_i), .C(
        un2_cudata_wrdy_int_4_i_a2_0_0_net_1), .D(cfdatain_o21), .Y(
        cfdatain_o29_0_a2_a0_sx_net_1));
    CFG2 #( .INIT(4'h8) )  \req_curr_state_RNO[0]  (.A(N_5545), .B(
        N_5709_1_0_2), .Y(N_5486_i));
    SLE \cudata_r_o[10]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[10]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[10]));
    CFG4 #( .INIT(16'h20EC) )  \resp_curr_state_RNO[22]  (.A(
        \resp_curr_state[16]_net_1 ), .B(\resp_curr_state[22]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(N_4136_i));
    CFG2 #( .INIT(4'h1) )  \req_next_state_i_a12_7_1[1]  (.A(
        \req_curr_state[31]_net_1 ), .B(\req_curr_state[19]_net_1 ), 
        .Y(\req_next_state_i_a12_7_1[1]_net_1 ));
    CFG3 #( .INIT(8'h01) )  \req_curr_state_ns_i_0_a3_4_0[5]  (.A(
        \req_curr_state[5]_net_1 ), .B(set_puf_getkcnum_net_1), .C(
        \req_curr_state[27]_net_1 ), .Y(
        \req_curr_state_ns_i_0_a3_4_0[5]_net_1 ));
    SLE \cfdatain_d1[24]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[24]_net_1 ));
    CFG4 #( .INIT(16'h0ACE) )  \resp_curr_state_ns_0[11]  (.A(
        \resp_curr_state[11]_net_1 ), .B(\resp_curr_state[8]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(N_7689), .Y(\resp_curr_state_ns[11] )
        );
    CFG4 #( .INIT(16'h0001) )  do_mem_wr33_0_a2_0_0_a2 (.A(N_7684_i), 
        .B(N_7683_i), .C(N_7685_i), .D(N_7542_i), .Y(N_7472));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[6]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[6]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[5]_net_1 ), .S(\desc_datasel_cntr_s[6] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[6]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  \req_next_state_i_a12_7_RNI03AM3[1]  (
        .A(N_5766), .B(un1_m5_i_a3_0_6), .C(un1_m5_i_a3_0_3), .D(
        un1_m5_i_a3_0_2), .Y(un1_m5_i_a3_0_9));
    CFG4 #( .INIT(16'hC5F5) )  \cfburst_len_rd_o_1_i_m2[5]  (.A(
        \cfburst_len_rd_d1[5]_net_1 ), .B(
        \burstlen_memrd_data_i_o2_0[5]_net_1 ), .C(
        cfrd_resp_o_0_sqmuxa_1), .D(burstlen_memrd_data_sn_N_6), .Y(
        N_7929));
    CFG2 #( .INIT(4'h2) )  \req_dstreg_addr_i_a4_0[3]  (.A(N_5310_2), 
        .B(\req_curr_state[11]_net_1 ), .Y(
        \req_dstreg_addr_i_a4_0[3]_net_1 ));
    SLE \req_curr_state[18]  (.D(\req_curr_state_ns[18] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[18]_net_1 )
        );
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[7]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[7]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[6]_net_1 ), .S(\desc_datasel_cntr_s[7] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[7]_net_1 ));
    CFG4 #( .INIT(16'hAA30) )  \cfburst_len_rd_o_1[2]  (.A(
        \burstlen_memrd_data[2]_net_1 ), .B(un1_req_curr_state_24_i), 
        .C(\cfburst_len_rd_d1[2]_net_1 ), .D(cfrd_resp_o_0_sqmuxa_1), 
        .Y(cfburst_len_rd_o[2]));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[15]  (.A(
        \cfdatain_d1[15]_net_1 ), .B(ucnrbg_handle_o[7]), .C(N_8070), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_7));
    CFG4 #( .INIT(16'h2000) )  \req_curr_state_RNILUT41[23]  (.A(
        curr_state_0), .B(\req_curr_state[23]_net_1 ), .C(g0_4), .D(
        \resp_curr_state[21]_net_1 ), .Y(g0_5));
    SLE \req_curr_state[15]  (.D(\req_curr_state_ns[15] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[15]_net_1 )
        );
    CFG4 #( .INIT(16'hCE02) )  \req_curr_state_ns_i_i[24]  (.A(
        \req_curr_state[24]_net_1 ), .B(\req_curr_state[36]_net_1 ), 
        .C(fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_i_i[24]_net_1 ));
    CFG4 #( .INIT(16'h00E4) )  \cfsrc_addr_o_0[16]  (.A(N_4413_i), .B(
        \resp_srcreg_addr[16] ), .C(\cfsrc_addr_d1[16]_net_1 ), .D(
        resp_curr_state_6), .Y(cfsrc_addr_o_14));
    CFG3 #( .INIT(8'hE0) )  \resp_srcreg_data_f0_i[29]  (.A(
        \resp_srcreg_data_d1[29]_net_1 ), .B(
        \resp_curr_state[23]_net_1 ), .C(N_4395_i), .Y(N_7484));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[21]  (.A(
        \cfdatain_d1[21]_net_1 ), .B(ucnrbg_handle_o[5]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_13));
    CFG3 #( .INIT(8'h51) )  \cfburst_len_rd_d1_RNO[4]  (.A(N_7931), .B(
        un1_req_curr_state_24_i), .C(cfrd_resp_o_0_sqmuxa_1), .Y(
        N_7899_i));
    CFG4 #( .INIT(16'hF8F0) )  \cfsrc_addr_o_2[3]  (.A(
        \cfsrc_addr_o_2_a2_1_1[3]_net_1 ), .B(m1), .C(
        \cfsrc_addr_o_2_0[3]_net_1 ), .D(N_7461), .Y(cfsrc_addr_o_1));
    CFG4 #( .INIT(16'h0001) )  \req_curr_state_RNIAQKD[35]  (.A(
        \req_curr_state[11]_net_1 ), .B(\req_curr_state[25]_net_1 ), 
        .C(\req_curr_state[35]_net_1 ), .D(\req_curr_state[10]_net_1 ), 
        .Y(\req_curr_state_RNIAQKD[35]_net_1 ));
    CFG2 #( .INIT(4'hE) )  set_puf_getkcnum_RNI87OP (.A(
        uclatchcmd_o[3]), .B(set_puf_getkcnum_net_1), .Y(N_5293_i));
    CFG3 #( .INIT(8'h40) )  \memwr_data_addr_cnst_0_a2_0_a2[29]  (.A(
        do_mem_wr32), .B(un1_do_mem_wr32_2_i), .C(ucvalid_cmd_o), .Y(
        \memwr_data_addr_cnst[29] ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[22]  (.A(
        \cfdatain_d1[22]_net_1 ), .B(ucnrbg_handle_o[6]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_14));
    SLE \cfburst_len_rd_d1[4]  (.D(N_7899_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[4]_net_1 ));
    CFG4 #( .INIT(16'h2080) )  \resp_curr_state_ns_0_a3[12]  (.A(
        N_5158_i_0), .B(resp_next_state102), .C(
        \resp_curr_state[20]_net_1 ), .D(cmdrcv_net_1), .Y(N_7640));
    CFG3 #( .INIT(8'h80) )  \cfdatain_o_iv_0_a2_4_RNO[29]  (.A(
        \desc_datasel_cntr[3]_net_1 ), .B(\desc_datasel_cntr[2]_net_1 )
        , .C(N_23_mux), .Y(memwr_desc_int46));
    CFG3 #( .INIT(8'h40) )  \memrd_data_addr_cnst_8_0_.m30_2  (.A(
        N_7685_i), .B(N_7543_i), .C(m28), .Y(m30_1));
    CFG4 #( .INIT(16'hB000) )  un1_req_curr_state_24_0_a3_2_1_5 (.A(
        N_5783), .B(N_7798), .C(un1_req_curr_state_24_0_a3_2_1_2_net_1)
        , .D(un1_req_curr_state_24_0_a3_2_1_3_net_1), .Y(
        un1_req_curr_state_24_0_a3_2_1_5_net_1));
    CFG4 #( .INIT(16'h2220) )  \cfburst_len_wr_o_1_2_1_1[1]  (.A(
        N_5010_i), .B(N_4863_i), .C(
        \cfburst_len_wr_o_1_2_a2_0_0[1]_net_1 ), .D(
        \cfburst_len_wr_o_1_2_a2_2_0[1]_net_1 ), .Y(
        \cfburst_len_wr_o_1_2_1_1[1]_net_1 ));
    CFG4 #( .INIT(16'hF0F8) )  cfrd_resp_o_i_i_0 (.A(idle_trigger), .B(
        my_hpms_top_0_COMM_BLK_INT), .C(N_7394), .D(N_4418), .Y(
        cfrd_resp_o_i_i_0_net_1));
    CFG3 #( .INIT(8'h20) )  burstlen_memrd_data_8_sqmuxa_0_a2_1 (.A(
        N_5293_i), .B(N_7543_i), .C(N_8052), .Y(
        burstlen_memrd_data_8_sqmuxa_0_a2_1_net_1));
    SLE \cfdatain_d1[7]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[7] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[7]_net_1 ));
    CFG4 #( .INIT(16'h10FE) )  \req_curr_state_ns_i_0_1[25]  (.A(
        \req_curr_state[34]_net_1 ), .B(\req_curr_state[22]_net_1 ), 
        .C(N_7565), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns_i_0_1[25]_net_1 ));
    SLE \cfburst_len_rd_d1[0]  (.D(cfburst_len_rd_o[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[0]_net_1 ));
    CFG3 #( .INIT(8'hA2) )  \cfdatain_o_0_iv_0_2_RNIL22N[13]  (.A(
        masterDataInProg_0), .B(N_7345), .C(
        \cfdatain_o_0_iv_0_2[13]_net_1 ), .Y(
        \cfdatain_o_0_iv_0_3_0[13] ));
    CFG3 #( .INIT(8'h02) )  \cfburst_len_rd_o_1[14]  (.A(
        \cfburst_len_rd_d1[14]_net_1 ), .B(cfrd_resp_o_0_sqmuxa_1), .C(
        un1_req_curr_state_24_i), .Y(cfburst_len_rd_o[14]));
    SLE \req_curr_state[32]  (.D(\req_curr_state_ns[32] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[32]_net_1 )
        );
    CFG4 #( .INIT(16'h0100) )  
        \req_next_state_i_a12_3_1_0_i_a2_1_2[1]  (.A(
        \req_curr_state[36]_net_1 ), .B(\req_curr_state[30]_net_1 ), 
        .C(\req_curr_state[15]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_next_state_i_a12_3_1_0_i_a2_1_2[1]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \cfsrc_addr_o_2_a2_1_0[3]  (.A(N_7543_i), 
        .B(N_7685_i), .Y(\cfsrc_addr_o_2_a2_1_0[3]_net_1 ));
    CFG3 #( .INIT(8'h32) )  \req_curr_state_RNI9HQ8[10]  (.A(
        \req_curr_state[25]_net_1 ), .B(N_7806), .C(
        \req_curr_state[10]_net_1 ), .Y(cfdatain_o_iv_0_N_2_5_0));
    SLE \cudata_r_o[17]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[17]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[17]));
    SLE cmdrcv (.D(cmdrcv_998_net_1), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        cmdrcv_net_1));
    CFG4 #( .INIT(16'h44F4) )  unreg_cmd_1005 (.A(resp_curr_state_0), 
        .B(unreg_cmd_net_1), .C(unreg_cmd5_31_net_1), .D(N_5_0), .Y(
        unreg_cmd_1005_net_1));
    SLE \desc_datasel_cntr[12]  (.D(\desc_datasel_cntr_s[12] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[12]_net_1 ));
    SLE \desc_datasel_cntr[19]  (.D(\desc_datasel_cntr_s[19] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[19]_net_1 ));
    SLE \resp_curr_state[19]  (.D(N_4131_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[19]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \desc_datasel_cntr_RNIM1ML[16]  (.A(
        \desc_datasel_cntr[19]_net_1 ), .B(
        \desc_datasel_cntr[18]_net_1 ), .C(
        \desc_datasel_cntr[17]_net_1 ), .D(
        \desc_datasel_cntr[16]_net_1 ), .Y(m2_e_19));
    CFG2 #( .INIT(4'h8) )  do_mem_wr27_1_0_0_a2_0 (.A(N_5354_i), .B(
        N_5293_i), .Y(N_8082));
    CFG4 #( .INIT(16'h0040) )  \req_curr_state_ns_0_0_a3_1_0[1]  (.A(
        uclatchcmd_o[3]), .B(N_7550), .C(uclatchcmd_o[2]), .D(
        uclatchcmd_o[0]), .Y(\req_curr_state_ns_0_0_a3_1[1] ));
    CFG3 #( .INIT(8'h93) )  cfrd_resp_o_i_i_x2_0 (.A(N_5292_i), .B(
        N_5293_i), .C(N_7542_i), .Y(N_108_i));
    SLE \cfdst_addr_d1[2]  (.D(cfdst_addr_o_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdst_addr_d1[2]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  \memrd_data_addr_cnst_8_0_.m30  (.A(
        m30_1), .B(m15_2), .C(m15_0), .D(m15_1), .Y(
        memrd_data_addr_cnst_8ro));
    SLE \cfdatain_d1[11]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[11] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_11));
    CFG3 #( .INIT(8'hCA) )  un1_req_curr_state_24_0_0_0_RNILI9MN (.A(
        datawr_reqd_0_a2_RNIGOICF_net_1), .B(
        resp_data_done_RNI74CL_net_1), .C(
        un1_req_curr_state_24_0_0_0_RNIULAK7_net_1), .Y(
        un1_req_curr_state_24_i));
    SLE \main_curr_state[1]  (.D(N_8103_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\main_curr_state[1]_net_1 )
        );
    CFG3 #( .INIT(8'h01) )  un1_do_mem_wr32_1_2 (.A(N_7397), .B(
        burstlen_memwr_desc34), .C(do_mem_wr32), .Y(
        un1_do_mem_wr32_1_2_net_1));
    CFG4 #( .INIT(16'hFEEE) )  \resp_curr_state_ns_2[8]  (.A(
        \resp_curr_state_ns_0[8]_net_1 ), .B(N_7498), .C(
        \resp_curr_state[18]_net_1 ), .D(fctrans_done_o), .Y(
        \resp_curr_state_ns_2[8]_net_1 ));
    CFG3 #( .INIT(8'h40) )  cfdatain_o29_0_a2_a0_0_0 (.A(
        \resp_curr_state[16]_net_1 ), .B(curr_state_0), .C(
        \resp_curr_state[18]_net_1 ), .Y(cfdatain_o29_0_a2_a0_0));
    SLE \desc_datasel_cntr[23]  (.D(\desc_datasel_cntr_s[23] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[23]_net_1 ));
    CFG4 #( .INIT(16'h0480) )  un1_burstlen_memwr_data130_1_0_o2_1 (.A(
        N_5354_i), .B(N_5293_i), .C(N_7685_i), .D(N_7542_i), .Y(N_7364)
        );
    CFG2 #( .INIT(4'hD) )  cudata_wrdy_d1_RNIELLD (.A(
        \req_curr_state[2]_net_1 ), .B(cudata_wrdy_d1_net_1), .Y(
        N_7868_i));
    CFG4 #( .INIT(16'hAAFC) )  \cfburst_len_rd_o_1[0]  (.A(
        \burstlen_memrd_data[0] ), .B(\cfburst_len_rd_d1[0]_net_1 ), 
        .C(un1_req_curr_state_24_i), .D(cfrd_resp_o_0_sqmuxa_1), .Y(
        cfburst_len_rd_o[0]));
    CFG2 #( .INIT(4'h8) )  rcvokay_RNIJ4UH (.A(idle_trigger), .B(
        rcvokay_net_1), .Y(N_5158_i_0));
    CFG3 #( .INIT(8'h08) )  \memrd_data_addr_cnst_8_0_.m7_2  (.A(
        N_5293_i), .B(N_7685_i), .C(N_5292_i), .Y(m7_1));
    CFG4 #( .INIT(16'h0001) )  un1_latchen_hrdata_int_6_i_0_0_RNI2TOU 
        (.A(un1_latchen_hrdata_int_6_i_0_0_net_1), .B(N_7506), .C(
        N_4178_2), .D(N_7505), .Y(N_7480_i));
    CFG4 #( .INIT(16'hDC50) )  \cfdatain_d1_RNIS7A08[7]  (.A(N_7894_i), 
        .B(N_8225), .C(\cfdatain_d1[7]_net_1 ), .D(g0_6_0), .Y(g0_0_1));
    CFG4 #( .INIT(16'hF7FF) )  cfdatain_o26_0_a2_sx (.A(
        \resp_curr_state[23]_net_1 ), .B(curr_state_0), .C(
        un2_cudata_wrdy_int_1_0), .D(N_7776), .Y(
        cfdatain_o26_0_a2_sx_net_1));
    SLE \cfdatain_d1[14]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[14] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[14]_net_1 ));
    CFG4 #( .INIT(16'hFCF8) )  burstlen_memrd_data_1_sqmuxa_1_0_0 (.A(
        do_mem_wr27_net_1), .B(ucvalid_cmd_o), .C(
        burstlen_memrd_data_1_sqmuxa_1_0_0_1_net_1), .D(N_7365), .Y(
        burstlen_memrd_data_1_sqmuxa_1));
    CFG3 #( .INIT(8'hB0) )  un2_cudata_wrdy_int_4_i_0_0 (.A(
        un2_cudata_wrdy_int_4_i_a2_0_0_net_1), .B(curr_state_0), .C(
        N_7556_i), .Y(un2_cudata_wrdy_int_4_i_0));
    SLE \cudata_r_o[25]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[25]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[25]));
    CFG4 #( .INIT(16'h0ACE) )  \cfdatain_o_0_iv_0[6]  (.A(
        \cfdatain_d1[6]_net_1 ), .B(\req_dstreg_data[6] ), .C(N_7894_i)
        , .D(un2_cudata_wrdy_int_9), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[6] ));
    CFG4 #( .INIT(16'hFF70) )  \cfdst_addr_o_iv_0[2]  (.A(
        \req_dstreg_addr_i_a4_1[2]_net_1 ), .B(N_5193), .C(
        un1_req_curr_state_22_i_0), .D(\cfdst_addr_o_iv_0_0[2]_net_1 ), 
        .Y(cfdst_addr_o_0));
    CFG4 #( .INIT(16'hFEFF) )  \resp_srcreg_addr_1_f0_i_o2_1[4]  (.A(
        \resp_srcreg_addr_d1[4]_net_1 ), .B(\resp_curr_state[3]_net_1 )
        , .C(\resp_curr_state[4]_net_1 ), .D(N_7515), .Y(N_7372));
    CFG4 #( .INIT(16'h1B0A) )  \req_curr_state_ns_i_i[23]  (.A(
        \req_curr_state[23]_net_1 ), .B(set_sent_options_r_net_1), .C(
        fctrans_done_o), .D(N_8129_1), .Y(
        \req_curr_state_ns_i_i[23]_net_1 ));
    CFG4 #( .INIT(16'hFF04) )  \main_curr_state_ns_0_0[0]  (.A(N_8106), 
        .B(un1_fctrans_done_i_i), .C(\main_curr_state[0]_net_1 ), .D(
        \main_curr_state_ns_0_0_0[0]_net_1 ), .Y(
        \main_curr_state_ns[0] ));
    CFG4 #( .INIT(16'h4000) )  burstlen_memwr_data_10_sqmuxa_0_a2 (.A(
        N_7543_i), .B(\req_curr_state[3]_net_1 ), .C(N_7457), .D(
        N_7474), .Y(burstlen_memwr_data_10_sqmuxa));
    CFG4 #( .INIT(16'hFF80) )  \req_curr_state_ns_0_0[3]  (.A(N_7664), 
        .B(\req_curr_state_ns_0_0_a3_0_0[3] ), .C(N_7553), .D(
        \req_curr_state_ns_0_0_0[3]_net_1 ), .Y(\req_curr_state_ns[3] )
        );
    CFG3 #( .INIT(8'h80) )  \cfburst_len_wr_o_1_2_a2_4[0]  (.A(N_8049), 
        .B(N_5010_i), .C(N_7481_i), .Y(N_8056));
    CFG4 #( .INIT(16'h0008) )  \cfburst_len_wr_o_1_2_a2_3_2[1]  (.A(
        N_8088), .B(N_8056), .C(N_4863_i), .D(N_5292_i), .Y(N_8006_2));
    CFG4 #( .INIT(16'h0800) )  \req_next_state_i_a12_7_6[1]  (.A(
        \req_next_state_i_a12_7_3[1]_net_1 ), .B(N_7876), .C(
        \req_curr_state[15]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \req_next_state_i_a12_7_6[1]_net_1 ));
    CFG3 #( .INIT(8'h02) )  \burstlen_memrd_data_0_RNO_0[0]  (.A(
        ucvalid_cmd_o), .B(do_mem_wr33), .C(
        burstlen_memrd_data_6_sqmuxa), .Y(burstlen_m3_0_a2_1));
    CFG4 #( .INIT(16'h0A0E) )  \cfdatain_o_0_iv_0_1_RNO[2]  (.A(
        \cfdatain_o_0_iv_0_a2_1_3[2]_net_1 ), .B(ucnrbg_handle_o[2]), 
        .C(un2_cudata_wrdy_int_1_0), .D(N_7700), .Y(cfdatain_m5_i_a3_0)
        );
    SLE \resp_curr_state[13]  (.D(\resp_curr_state_ns[13]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[13]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \cfburst_len_wr_o_1_2_a2_3_0[1]  (.A(
        N_7543_i), .B(N_7685_i), .Y(do_mem_wr27_0_net_1));
    SLE \req_curr_state[11]  (.D(\req_curr_state_ns[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[11]_net_1 )
        );
    SLE fcbusreq_d1 (.D(fcbusreq_o), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        fcbusreq_d1_net_1));
    CFG4 #( .INIT(16'h0001) )  unreg_cmd5_18 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[17]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[16]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[27]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[29]), .Y(unreg_cmd5_18_net_1));
    CFG2 #( .INIT(4'h4) )  \cfburst_len_wr_o_1[6]  (.A(N_7481_i), .B(
        \cfburst_len_wr_d1[6]_net_1 ), .Y(cfburst_len_wr_o[6]));
    CFG4 #( .INIT(16'h0004) )  unreg_cmd5_21 (.A(
        CoreAHBLite_0_AHBmslave16_HRDATA[8]), .B(
        CoreAHBLite_0_AHBmslave16_HRDATA[2]), .C(
        CoreAHBLite_0_AHBmslave16_HRDATA[14]), .D(
        CoreAHBLite_0_AHBmslave16_HRDATA[11]), .Y(unreg_cmd5_21_net_1));
    CFG4 #( .INIT(16'hEEFE) )  \cfdatain_o_iv[4]  (.A(
        \resp_srcreg_data_m[4] ), .B(\cfdatain_o_iv_1[4] ), .C(
        \cfdatain_d1[4]_net_1 ), .D(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[4] ));
    CFG3 #( .INIT(8'h80) )  cfdst_addr_o41 (.A(N_7891), .B(
        \resp_curr_state[16]_net_1 ), .C(N_7874), .Y(
        cfdst_addr_o41_net_1));
    CFG4 #( .INIT(16'h0001) )  burstlen_memrd_data77_2_0_0_a2 (.A(
        N_7684_i), .B(N_7683_i), .C(N_7685_i), .D(N_5292_i), .Y(
        memwr_desc_5_sqmuxa_2_0));
    CFG4 #( .INIT(16'hD010) )  \req_next_state_i_a12_3_4_RNI5EMD3[1]  
        (.A(N_7804), .B(N_7792), .C(
        \req_next_state_i_a12_3_4[1]_net_1 ), .D(
        \req_next_state_i_a12_3_1_0_i_o2_5[1] ), .Y(d_N_7));
    CFG4 #( .INIT(16'h088C) )  cfrd_resp_o_i_i_a2_0 (.A(
        \resp_curr_state[4]_net_1 ), .B(idle_trigger), .C(N_4418), .D(
        N_4389_i), .Y(N_7394));
    CFG4 #( .INIT(16'hF888) )  \cfdst_addr_o_iv_0_0[2]  (.A(
        \cfdst_addr_d1[2]_net_1 ), .B(un1_req_curr_state_21_i), .C(
        N_8228), .D(\resp_srcreg_addr[2] ), .Y(
        \cfdst_addr_o_iv_0_0[2]_net_1 ));
    CFG4 #( .INIT(16'h0100) )  \req_curr_state_ns_i_0_a3_0_1_0[5]  (.A(
        \req_curr_state[5]_net_1 ), .B(set_puf_getkcnum_net_1), .C(
        N_7556), .D(N_7664), .Y(\req_curr_state_ns_i_0_a3_0_1[5] ));
    CFG2 #( .INIT(4'h4) )  \cfburst_len_wr_o_1[5]  (.A(N_7481_i), .B(
        \cfburst_len_wr_d1[5]_net_1 ), .Y(cfburst_len_wr_o[5]));
    CFG4 #( .INIT(16'hFF80) )  
        req_dstreg_data20_0_a2_0_a2_0_a3_RNIKUHU4 (.A(
        ucnrbg_handle_o[2]), .B(\req_curr_state[12]_net_1 ), .C(
        req_dstreg_data20), .D(g0_10_1), .Y(N_9_0_0));
    CFG3 #( .INIT(8'h20) )  \req_curr_state_ns_i_a2_0_a3[25]  (.A(
        uclatchcmd_o[2]), .B(uclatchcmd_o[0]), .C(N_7667), .Y(N_5697));
    CFG4 #( .INIT(16'hF888) )  \cfdst_addr_o_iv_0_0[3]  (.A(
        un1_req_curr_state_21_i), .B(\cfdst_addr_d1[3]_net_1 ), .C(
        N_8228), .D(\resp_srcreg_addr[3] ), .Y(
        \cfdst_addr_o_iv_0_0[3]_net_1 ));
    CFG2 #( .INIT(4'h2) )  set_puf_getkcnum_RNI76OP (.A(
        uclatchcmd_o[2]), .B(set_puf_getkcnum_net_1), .Y(N_7542_i));
    CFG4 #( .INIT(16'h54FF) )  un1_main_curr_state_4_0 (.A(
        resp_curr_state_0), .B(cmd_error_d1_net_1), .C(N_7482_i), .D(
        main_curr_state_5371_d), .Y(un1_main_curr_state_4_0_net_1));
    CFG3 #( .INIT(8'h37) )  \memrd_data_addr_cnst_8_0_.m15_1_0  (.A(
        N_7685_i), .B(N_7543_i), .C(m11), .Y(m15_1_0));
    CFG4 #( .INIT(16'h5510) )  
        \req_next_state_i_a12_3_1_0_i_o2_5_1[1]  (.A(N_7796), .B(
        \req_curr_state[3]_net_1 ), .C(
        \req_next_state_i_a12_3_1_0_i_o2_5_1_1[1]_net_1 ), .D(
        \req_next_state_i_a12_3_1_0_i_a2_1_5[1]_net_1 ), .Y(
        \req_next_state_i_a12_3_1_0_i_o2_5[1] ));
    CFG3 #( .INIT(8'h80) )  \desc_datasel_cntr_RNIOQJU1[4]  (.A(
        m2_e_20), .B(m2_e_15), .C(m2_e_14), .Y(m2_e_24));
    CFG3 #( .INIT(8'h80) )  \cfburst_len_wr_o_1_2_a2[2]  (.A(N_8080), 
        .B(N_5354_i), .C(N_8076), .Y(N_7999));
    CFG4 #( .INIT(16'hF0E0) )  cfwr_req_d_i_a2_0 (.A(N_4178_2), .B(
        N_4237), .C(N_7545), .D(N_5301), .Y(N_7661));
    CFG4 #( .INIT(16'h3F15) )  
        req_dstreg_data_1_sqmuxa_1_0_a4_i_o2_RNIDEKG1 (.A(
        ucnrbg_handle_o[5]), .B(uclatchcmd_o[3]), .C(N_7544_i), .D(
        N_7700), .Y(cfdatain_N_5));
    SLE \cfsrc_addr_d1[12]  (.D(cfsrc_addr_o_10), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[12]_net_1 ));
    CFG4 #( .INIT(16'hFFF8) )  \cfdatain_o_iv_0_o2_2_s[29]  (.A(
        memwr_desc_int35), .B(cfdatain_m1_0_a2_2_0), .C(N_8084), .D(
        N_8079), .Y(cfdatain_o_iv_0_o2_2_out));
    CFG4 #( .INIT(16'h3010) )  \req_curr_state_ns_i_0_a2[13]  (.A(
        \req_curr_state[31]_net_1 ), .B(\req_curr_state[11]_net_1 ), 
        .C(N_7711_3), .D(N_7496), .Y(N_7707));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[28]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[28]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[27]_net_1 ), .S(
        \desc_datasel_cntr_s[28] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[28]_net_1 ));
    CFG4 #( .INIT(16'h2154) )  \burstlen_memrd_data_2_RNO_0[3]  (.A(
        N_5292_i), .B(N_5354_i), .C(N_7542_i), .D(N_7543_i), .Y(
        N_7341_i_1_0));
    SLE \req_curr_state[19]  (.D(\req_curr_state_ns_i_i[19]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[19]_net_1 )
        );
    CFG4 #( .INIT(16'h0002) )  burstlen_memwr_data_12_sqmuxa_0_a2_1 (
        .A(ucvalid_cmd_o), .B(N_7683_i), .C(N_7684_i), .D(N_7542_i), 
        .Y(N_7474));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[8]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[8]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[7]_net_1 ), .S(\desc_datasel_cntr_s[8] )
        , .Y(), .FCO(\desc_datasel_cntr_cry[8]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \cfburst_len_wr_o_1_0_1[3]  (.A(N_5292_i), 
        .B(ucvalid_cmd_o), .C(N_4863_i), .Y(
        \cfburst_len_wr_o_1_0_1[3]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \resp_curr_state_ns_0_0[25]  (.A(
        \resp_curr_state_ns_0_a2_0_0[25]_net_1 ), .B(N_5158_i_0), .C(
        \resp_curr_state[25]_net_1 ), .D(fcbusreq_d1_net_1), .Y(
        \resp_curr_state_ns_0_0[25]_net_1 ));
    CFG4 #( .INIT(16'hC0EA) )  \cfdatain_o_0_iv_0[19]  (.A(
        \cfdatain_d1[19]_net_1 ), .B(ucnrbg_handle_o[3]), .C(N_8064), 
        .D(N_7894_i), .Y(syssvc_blk_0_AHBL_MASTER_HWDATA_11));
    CFG3 #( .INIT(8'h04) )  \req_curr_state_ns_i_0_a2[5]  (.A(N_7670), 
        .B(ucvalid_cmd_o), .C(uclatchcmd_o[4]), .Y(N_7664));
    SLE \desc_datasel_cntr[26]  (.D(\desc_datasel_cntr_s[26] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[26]_net_1 ));
    CFG3 #( .INIT(8'h01) )  un1_req_curr_state_21_0_a2_0_1 (.A(
        \req_curr_state[25]_net_1 ), .B(\req_curr_state[23]_net_1 ), 
        .C(\resp_curr_state[21]_net_1 ), .Y(
        un1_req_curr_state_21_0_a2_0_1_net_1));
    SLE \cfdatain_d1[29]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[29] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[29]_net_1 ));
    CFG2 #( .INIT(4'h2) )  un2_cudata_wrdy_int_1_RNIOK4M6 (.A(N_7894_i)
        , .B(un2_cudata_wrdy_int_1_0), .Y(g0_12_1));
    CFG3 #( .INIT(8'h08) )  cudata_wrdy_d1_RNO (.A(mchready_i), .B(
        curr_state_0), .C(syssvc_blk_0_AHBL_MASTER_HRESP_0), .Y(
        r_N_3_mux));
    CFG4 #( .INIT(16'h4000) )  \req_curr_state_ns_0_0_a3_0[26]  (.A(
        uclatchcmd_o[2]), .B(\req_curr_state[4]_net_1 ), .C(N_7667), 
        .D(fctrans_done_o), .Y(N_7627));
    CFG2 #( .INIT(4'hD) )  un1_idle_trigger_4_i_o2 (.A(
        \resp_curr_state[3]_net_1 ), .B(unreg_cmd_net_1), .Y(N_4237));
    CFG3 #( .INIT(8'h40) )  \req_curr_state_ns_0_0_a3_0_2[3]  (.A(
        set_puf_getkcnum_net_1), .B(\req_curr_state[2]_net_1 ), .C(
        fctrans_done_o), .Y(\req_curr_state_ns_0_0_a3_0_0[3] ));
    CFG3 #( .INIT(8'h02) )  memwr_data_addr_2_sqmuxa_0_a2_0 (.A(
        ucvalid_cmd_o), .B(N_7683_i), .C(N_7684_i), .Y(N_8049));
    SLE \cfdatain_d1[8]  (.D(syssvc_blk_0_AHBL_MASTER_HWDATA_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfdatain_d1[8]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \req_curr_state_RNI6LPD_0[11]  (.A(
        set_puf_getkcnum_net_1), .B(\req_curr_state[11]_net_1 ), .Y(
        N_5194_0));
    CFG3 #( .INIT(8'h04) )  req_m1_e (.A(uclatchcmd_o[3]), .B(
        uclatchcmd_o[4]), .C(N_7670), .Y(N_5322_i));
    SLE \resp_srcreg_data_d1[29]  (.D(N_7484), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_srcreg_data_d1[29]_net_1 ));
    CFG4 #( .INIT(16'h0040) )  \cfdst_addr_o_0_iv_0_a2_2_2[29]  (.A(
        do_mem_wr32), .B(memwr_data_addr_3_sqmuxa), .C(ucvalid_cmd_o), 
        .D(N_7556_i), .Y(\cfdst_addr_o_0_iv_0_a2_2_2[29]_net_1 ));
    CFG4 #( .INIT(16'hA0E4) )  \req_curr_state_ns_i_i[31]  (.A(
        \req_curr_state[30]_net_1 ), .B(\req_curr_state[31]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(fctrans_done_o), .Y(
        \req_curr_state_ns_i_i[31]_net_1 ));
    SLE \cfburst_len_rd_d1[3]  (.D(cfburst_len_rd_o[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[3]_net_1 ));
    SLE \cudata_r_o[21]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[21]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[21]));
    CFG3 #( .INIT(8'hDC) )  \resp_curr_state_ns_2_i_o2[3]  (.A(N_7670), 
        .B(uclatchcmd_o[3]), .C(N_5174), .Y(N_7687));
    SLE \cfburst_len_rd_d1[6]  (.D(cfburst_len_rd_o[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[6]_net_1 ));
    SLE \resp_curr_state[12]  (.D(\resp_curr_state_ns[12] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[12]_net_1 ));
    CFG4 #( .INIT(16'hC0D1) )  \req_dstreg_data_0_iv_0[3]  (.A(N_7806), 
        .B(N_7544_i), .C(uclatchcmd_o[3]), .D(N_5194), .Y(
        \req_dstreg_data_0_iv_0[3]_net_1 ));
    CFG4 #( .INIT(16'hEFAF) )  resp_phase_done_0_0 (.A(
        resp_curr_state_6), .B(\resp_curr_state[3]_net_1 ), .C(N_7355), 
        .D(N_7469), .Y(resp_phase_done));
    SLE \cudata_r_o[22]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[22]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[22]));
    CFG4 #( .INIT(16'h8000) )  \desc_datasel_cntr_RNIAAGA8[1]  (.A(
        do_mem_wr26_s8), .B(memwr_desc_int35), .C(ucnrbg_handle_o[6]), 
        .D(cfdatain_o21), .Y(memwr_desc_int_m_19));
    CFG4 #( .INIT(16'hFFFE) )  do_mem_wr27_sx (.A(N_7683_i), .B(
        N_7684_i), .C(N_5292_i), .D(N_7542_i), .Y(do_mem_wr27_sx_net_1)
        );
    CFG4 #( .INIT(16'h2000) )  do_mem_wr32_0_a2 (.A(
        do_mem_wr32_0_a2_1_net_1), .B(N_7542_i), .C(N_8082), .D(
        N_6101_2), .Y(do_mem_wr32));
    SLE \desc_datasel_cntr[5]  (.D(\desc_datasel_cntr_s[5] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[5]_net_1 ));
    SLE \resp_curr_state[24]  (.D(\resp_curr_state_ns[24] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[24]_net_1 ));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[27]  (.A(cfdatain_d1_27), 
        .B(memwr_desc_int_m_16), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[27] ));
    CFG3 #( .INIT(8'h15) )  \resp_curr_state_ns_3_i_1_0[3]  (.A(N_7670)
        , .B(uclatchcmd_o[3]), .C(uclatchcmd_o[4]), .Y(
        \resp_curr_state_ns_3_i_1_0[3]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \resp_curr_state_ns_a2_0_a2[30]  (.A(
        fctrans_done_o), .B(\resp_curr_state[29]_net_1 ), .C(N_8093_i), 
        .D(un2_uclatchcmd_i_mux_11_NE_net_1), .Y(
        \resp_curr_state_ns[30] ));
    CFG4 #( .INIT(16'h6070) )  \cfburst_len_wr_o_1_2_a2_2_0[1]  (.A(
        N_7685_i), .B(N_5292_i), .C(N_8065), .D(N_7543_i), .Y(
        \cfburst_len_wr_o_1_2_a2_2_0[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  set_puf_getkcnum_RNIMTSP (.A(
        set_puf_getkcnum_net_1), .B(N_7670), .Y(N_7684_i));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[15]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[15]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[14]_net_1 ), .S(
        \desc_datasel_cntr_s[15] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[15]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \req_curr_state_ns_0[14]  (.A(
        \req_curr_state[19]_net_1 ), .B(\req_curr_state[14]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(N_5577), .Y(\req_curr_state_ns[14] ));
    SLE \desc_datasel_cntr[0]  (.D(\desc_datasel_cntr_s[0] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(N_7868_i), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \desc_datasel_cntr[0]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  unreg_cmd5_28 (.A(
        syssvc_blk_0_AHBL_MASTER_HRDATA[7]), .B(unreg_cmd5_16_net_1), 
        .C(unreg_cmd5_15_net_1), .D(syssvc_blk_0_AHBL_MASTER_HRDATA[1])
        , .Y(unreg_cmd5_28_net_1));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[30]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[30]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[29]_net_1 ), .S(
        \desc_datasel_cntr_s[30] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[30]_net_1 ));
    CFG2 #( .INIT(4'h4) )  burstlen_memwr_desc35_0_a2_1 (.A(N_7685_i), 
        .B(N_7542_i), .Y(N_7465));
    CFG4 #( .INIT(16'h0080) )  un1_cfdatain_o26_RNIL2018 (.A(N_7544_i), 
        .B(uclatchcmd_o[2]), .C(g0_12_1), .D(N_8225), .Y(N_12_1));
    CFG2 #( .INIT(4'hB) )  resp_phase_active_i_i_o2 (.A(N_8105), .B(
        \main_curr_state[1]_net_1 ), .Y(N_8106));
    CFG3 #( .INIT(8'h80) )  \memrd_data_addr_cnst_8_0_.m15_3  (.A(
        N_7685_i), .B(N_7543_i), .C(N_32_mux), .Y(m15_2));
    SLE \req_curr_state[0]  (.D(N_5486_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(req_curr_state_0));
    SLE \cfburst_len_rd_d1[11]  (.D(cfburst_len_rd_o[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \cfburst_len_rd_d1[11]_net_1 ));
    CFG4 #( .INIT(16'h2E3F) )  cfdatain_o_iv_0_N_5L7_1 (.A(N_7806), .B(
        N_7544_i), .C(N_7670), .D(N_7690), .Y(
        cfdatain_o_iv_0_N_5L7_1_net_1));
    CFG4 #( .INIT(16'h8000) )  burstlen_memrd_data_3_sqmuxa (.A(
        N_6101_2), .B(burstlen_memrd_data_3_sqmuxa_1_net_1), .C(
        \cfsrc_addr_o_2_a2_1_0[3]_net_1 ), .D(do_mem_wr33_i_1_0), .Y(
        burstlen_memrd_data_3_sqmuxa_net_1));
    CFG3 #( .INIT(8'hCE) )  \cfdatain_o_0_iv[26]  (.A(cfdatain_d1_26), 
        .B(memwr_desc_int_m_15), .C(N_7894_i), .Y(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[26] ));
    ARI1 #( .INIT(20'h48800) )  \desc_datasel_cntr_cry[19]  (.A(
        VCC_net_1), .B(\desc_datasel_cntr[19]_net_1 ), .C(
        \req_curr_state[2]_net_1 ), .D(GND_net_1), .FCI(
        \desc_datasel_cntr_cry[18]_net_1 ), .S(
        \desc_datasel_cntr_s[19] ), .Y(), .FCO(
        \desc_datasel_cntr_cry[19]_net_1 ));
    CFG4 #( .INIT(16'h0E02) )  \resp_next_state_2_.m4  (.A(
        fctrans_done_o), .B(N_7), .C(\resp_curr_state[14]_net_1 ), .D(
        idle_trigger), .Y(N_5_0));
    SLE \cfdatain_d1[28]  (.D(\syssvc_blk_0_AHBL_MASTER_HWDATA[28] ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cfdatain_d1_28));
    SLE resp_phase_done_d1 (.D(resp_phase_done), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_phase_done_d1_net_1));
    CFG4 #( .INIT(16'h0008) )  un2_cudata_wrdy_int_4_i_a2_0_0 (.A(
        N_7818), .B(\resp_srcreg_data_cnst[4] ), .C(
        \req_curr_state[9]_net_1 ), .D(\req_curr_state[6]_net_1 ), .Y(
        un2_cudata_wrdy_int_4_i_a2_0_0_net_1));
    CFG2 #( .INIT(4'hE) )  main_curr_state_s0_0_a3 (.A(
        \main_curr_state[0]_net_1 ), .B(\main_curr_state[1]_net_1 ), 
        .Y(main_curr_state_5371_d));
    SLE \resp_curr_state[11]  (.D(\resp_curr_state_ns[11] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \resp_curr_state[11]_net_1 ));
    SLE \resp_curr_state[6]  (.D(N_4115_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(resp_curr_state_6));
    CFG2 #( .INIT(4'hE) )  \req_curr_state_RNI9LS7[27]  (.A(
        \req_curr_state[4]_net_1 ), .B(\req_curr_state[27]_net_1 ), .Y(
        N_7556));
    CFG4 #( .INIT(16'hA0EC) )  \req_curr_state_ns_0_0[15]  (.A(
        \req_curr_state[6]_net_1 ), .B(\req_curr_state[15]_net_1 ), .C(
        fctrans_done_o), .D(fcbusreq_d1_net_1), .Y(
        \req_curr_state_ns[15] ));
    SLE \cudata_r_o[29]  (.D(syssvc_blk_0_AHBL_MASTER_HRDATA[29]), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(cudata_r_o[29]));
    SLE \cfsrc_addr_d1[30]  (.D(N_7540_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\cfsrc_addr_d1[30]_net_1 ));
    CFG4 #( .INIT(16'h1110) )  un1_custatus_out_en2_0_0_o2_0_a3_0 (.A(
        cucmd_error_net_1), .B(\resp_curr_state[15]_net_1 ), .C(N_7447)
        , .D(N_7446), .Y(N_8144));
    CFG4 #( .INIT(16'h0CAA) )  \resp_srcreg_data[3]  (.A(
        \resp_srcreg_data_d1[3]_net_1 ), .B(
        \resp_curr_state[18]_net_1 ), .C(req_dstreg_data20), .D(
        N_4425_i), .Y(\resp_srcreg_data[3]_net_1 ));
    CFG4 #( .INIT(16'hFF02) )  \resp_curr_state_ns_i_i[28]  (.A(
        \resp_curr_state[28]_net_1 ), .B(\resp_curr_state[20]_net_1 ), 
        .C(fcbusreq_d1_net_1), .D(N_7503), .Y(
        \resp_curr_state_ns_i_i[28]_net_1 ));
    CFG4 #( .INIT(16'h2010) )  cfrd_resp_o_i_i_a2_11 (.A(N_5292_i), .B(
        N_7542_i), .C(N_7543_i), .D(N_8082), .Y(N_7441));
    SLE \req_curr_state[16]  (.D(\req_curr_state_ns_i_i[16]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\req_curr_state[16]_net_1 )
        );
    
endmodule


module CoreSysServices_UserIF_Z6(
       CORESYSSERVICES_0_SERV_DATA_R,
       cudata_r_o,
       CORESYSSERVICES_0_SERV_STATUS_RESP,
       uclatchcmd_o,
       my_sysservice_state_0_SERV_NRBG_HANDLE,
       ucnrbg_handle_o,
       my_sysservice_state_0_SERV_CMDBYTE_REQ,
       ucnrbg_length_o_0,
       main_curr_state_5371_d,
       CORESYSSERVICES_0_SERV_DATA_RVALID,
       N_7670,
       uctrig_o,
       CORESYSSERVICES_0_SERV_STATUS_VALID,
       ucvalid_cmd_o,
       custatus_out_en,
       my_sysservice_state_0_SERV_ENABLE_REQ,
       custatus_valid_o,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY,
       CORESYSSERVICES_0_SERV_BUSY
    );
output [31:0] CORESYSSERVICES_0_SERV_DATA_R;
input  [31:0] cudata_r_o;
output [7:0] CORESYSSERVICES_0_SERV_STATUS_RESP;
output [4:0] uclatchcmd_o;
input  [7:0] my_sysservice_state_0_SERV_NRBG_HANDLE;
output [7:0] ucnrbg_handle_o;
input  [4:0] my_sysservice_state_0_SERV_CMDBYTE_REQ;
output ucnrbg_length_o_0;
input  main_curr_state_5371_d;
input  CORESYSSERVICES_0_SERV_DATA_RVALID;
output N_7670;
output uctrig_o;
output CORESYSSERVICES_0_SERV_STATUS_VALID;
output ucvalid_cmd_o;
input  custatus_out_en;
input  my_sysservice_state_0_SERV_ENABLE_REQ;
input  custatus_valid_o;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;
output CORESYSSERVICES_0_SERV_BUSY;

    wire CORESYSSERVICES_0_SERV_BUSY_i, \ustatus_resp_lat[0]_net_1 , 
        VCC_net_1, GND_net_1, \ustatus_resp_lat[1]_net_1 , 
        \ustatus_resp_lat[2]_net_1 , \ustatus_resp_lat[3]_net_1 , 
        \ustatus_resp_lat[4]_net_1 , \ustatus_resp_lat[5]_net_1 , 
        \ustatus_resp_lat[6]_net_1 , \ustatus_resp_lat[7]_net_1 , 
        \ucmdbyte_req_d1[0]_net_1 , \ucmdbyte_req_d1[1]_net_1 , 
        \ucmdbyte_req_d1[2]_net_1 , \ucmdbyte_req_d1[4]_net_1 , 
        new_serv_d1_net_1, ustatus_valid_lat_net_1, 
        un1_custatus_valid_i_net_1, ureq_enable_d1_net_1, 
        ureq_enable_d2_net_1, un1_ureq_enable_i_net_1, 
        ubusy_int5_net_1, ustatus_valid_o_3_net_1, uctrig_o_3_net_1, 
        udata_r_sel1, udata_r_sel1_0_a2_3_net_1;
    
    SLE \ustatus_resp_lat[3]  (.D(cudata_r_o[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[3]_net_1 ));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNICDOG (.A(udata_r_sel1), 
        .B(cudata_r_o[28]), .Y(CORESYSSERVICES_0_SERV_DATA_R[28]));
    SLE \ucmdbyte_req_d1[3]  (.D(VCC_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_length_o_0));
    SLE ubusy_int (.D(ubusy_int5_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_BUSY));
    SLE \ustatus_resp_lat[7]  (.D(cudata_r_o[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[7]_net_1 ));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI33NG (.A(udata_r_sel1), 
        .B(cudata_r_o[10]), .Y(CORESYSSERVICES_0_SERV_DATA_R[10]));
    SLE \ucnrbg_handle_o[5]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[5]));
    SLE \ustatus_resp_lat[1]  (.D(cudata_r_o[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI66NG (.A(udata_r_sel1), 
        .B(cudata_r_o[13]), .Y(CORESYSSERVICES_0_SERV_DATA_R[13]));
    SLE \ustatus_resp_o[6]  (.D(\ustatus_resp_lat[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[6]));
    SLE \ustatus_resp_lat[5]  (.D(cudata_r_o[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[5]_net_1 ));
    SLE \uclatchcmd_o[3]  (.D(ucnrbg_length_o_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uclatchcmd_o[3]));
    SLE \ustatus_resp_lat[0]  (.D(cudata_r_o[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[0]_net_1 ));
    SLE \ustatus_resp_o[3]  (.D(\ustatus_resp_lat[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[3]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIBBNG (.A(udata_r_sel1), 
        .B(cudata_r_o[18]), .Y(CORESYSSERVICES_0_SERV_DATA_R[18]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIDEOG (.A(udata_r_sel1), 
        .B(cudata_r_o[29]), .Y(CORESYSSERVICES_0_SERV_DATA_R[29]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI88NG (.A(udata_r_sel1), 
        .B(cudata_r_o[15]), .Y(CORESYSSERVICES_0_SERV_DATA_R[15]));
    SLE ucvalid_cmd_o_inst_1 (.D(my_sysservice_state_0_SERV_ENABLE_REQ)
        , .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(
        CORESYSSERVICES_0_SERV_BUSY_i), .ALn(my_hpms_top_0_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(ucvalid_cmd_o));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI45OG (.A(udata_r_sel1), 
        .B(cudata_r_o[20]), .Y(CORESYSSERVICES_0_SERV_DATA_R[20]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[7]  (.A(cudata_r_o[23]), .B(
        cudata_r_o[7]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[7]));
    SLE \ustatus_resp_lat[4]  (.D(cudata_r_o[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[4]_net_1 ));
    SLE \ucmdbyte_req_d1[1]  (.D(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\ucmdbyte_req_d1[1]_net_1 )
        );
    SLE \uclatchcmd_o[0]  (.D(\ucmdbyte_req_d1[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uclatchcmd_o[0]));
    CFG4 #( .INIT(16'hFFFE) )  ubusy_int5 (.A(
        my_sysservice_state_0_SERV_ENABLE_REQ), .B(
        main_curr_state_5371_d), .C(ureq_enable_d2_net_1), .D(
        ureq_enable_d1_net_1), .Y(ubusy_int5_net_1));
    SLE ureq_enable_d1 (.D(my_sysservice_state_0_SERV_ENABLE_REQ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ureq_enable_d1_net_1));
    CFG3 #( .INIT(8'h40) )  udata_r_sel1_0_a2 (.A(uclatchcmd_o[4]), .B(
        uclatchcmd_o[3]), .C(udata_r_sel1_0_a2_3_net_1), .Y(
        udata_r_sel1));
    SLE \ucnrbg_handle_o[1]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[1]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[3]  (.A(cudata_r_o[19]), .B(
        cudata_r_o[3]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[3]));
    VCC VCC (.Y(VCC_net_1));
    SLE \uclatchcmd_o[4]  (.D(\ucmdbyte_req_d1[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uclatchcmd_o[4]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI56OG (.A(udata_r_sel1), 
        .B(cudata_r_o[21]), .Y(CORESYSSERVICES_0_SERV_DATA_R[21]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI89OG (.A(udata_r_sel1), 
        .B(cudata_r_o[24]), .Y(CORESYSSERVICES_0_SERV_DATA_R[24]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI78OG (.A(udata_r_sel1), 
        .B(cudata_r_o[23]), .Y(CORESYSSERVICES_0_SERV_DATA_R[23]));
    CFG2 #( .INIT(4'h8) )  uctrig_o_3 (.A(ucvalid_cmd_o), .B(
        new_serv_d1_net_1), .Y(uctrig_o_3_net_1));
    SLE \ustatus_resp_o[2]  (.D(\ustatus_resp_lat[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[2]));
    SLE \ustatus_resp_lat[2]  (.D(cudata_r_o[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[2]_net_1 ));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI9AOG (.A(udata_r_sel1), 
        .B(cudata_r_o[25]), .Y(CORESYSSERVICES_0_SERV_DATA_R[25]));
    SLE \ucmdbyte_req_d1[4]  (.D(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\ucmdbyte_req_d1[4]_net_1 )
        );
    CFG1 #( .INIT(2'h1) )  ucvalid_cmd_o_RNO (.A(
        CORESYSSERVICES_0_SERV_BUSY), .Y(CORESYSSERVICES_0_SERV_BUSY_i)
        );
    SLE \ucnrbg_handle_o[0]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[0]));
    SLE \uclatchcmd_o[2]  (.D(\ucmdbyte_req_d1[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uclatchcmd_o[2]));
    CFG2 #( .INIT(4'h2) )  un1_ureq_enable_i (.A(
        my_sysservice_state_0_SERV_ENABLE_REQ), .B(
        CORESYSSERVICES_0_SERV_BUSY), .Y(un1_ureq_enable_i_net_1));
    SLE uctrig_o_inst_1 (.D(uctrig_o_3_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uctrig_o));
    SLE \ucnrbg_handle_o[7]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[7]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI77NG (.A(udata_r_sel1), 
        .B(cudata_r_o[14]), .Y(CORESYSSERVICES_0_SERV_DATA_R[14]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[1]  (.A(cudata_r_o[17]), .B(
        cudata_r_o[1]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[1]));
    SLE \ustatus_resp_lat[6]  (.D(cudata_r_o[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_valid_o), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ustatus_resp_lat[6]_net_1 ));
    SLE \ucnrbg_handle_o[3]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[3]));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI57PG (.A(udata_r_sel1), 
        .B(cudata_r_o[30]), .Y(CORESYSSERVICES_0_SERV_DATA_R[30]));
    SLE \ustatus_resp_o[7]  (.D(\ustatus_resp_lat[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[7]));
    SLE \uclatchcmd_o[1]  (.D(\ucmdbyte_req_d1[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(uclatchcmd_o[1]));
    SLE \ustatus_resp_o[5]  (.D(\ustatus_resp_lat[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[5]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI44NG (.A(udata_r_sel1), 
        .B(cudata_r_o[11]), .Y(CORESYSSERVICES_0_SERV_DATA_R[11]));
    SLE new_serv_d1 (.D(un1_ureq_enable_i_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(new_serv_d1_net_1));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[5]  (.A(cudata_r_o[21]), .B(
        cudata_r_o[5]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[5]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI67OG (.A(udata_r_sel1), 
        .B(cudata_r_o[22]), .Y(CORESYSSERVICES_0_SERV_DATA_R[22]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[0]  (.A(cudata_r_o[16]), .B(
        cudata_r_o[0]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[0]));
    SLE ustatus_valid_o (.D(ustatus_valid_o_3_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_VALID));
    SLE \ucmdbyte_req_d1[2]  (.D(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\ucmdbyte_req_d1[2]_net_1 )
        );
    SLE \ustatus_resp_o[0]  (.D(\ustatus_resp_lat[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[0]));
    SLE \ustatus_resp_o[4]  (.D(\ustatus_resp_lat[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[4]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI68PG (.A(udata_r_sel1), 
        .B(cudata_r_o[31]), .Y(CORESYSSERVICES_0_SERV_DATA_R[31]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIRHQF (.A(udata_r_sel1), 
        .B(cudata_r_o[9]), .Y(CORESYSSERVICES_0_SERV_DATA_R[9]));
    SLE \ustatus_resp_o[1]  (.D(\ustatus_resp_lat[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(custatus_out_en), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORESYSSERVICES_0_SERV_STATUS_RESP[1]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIQGQF (.A(udata_r_sel1), 
        .B(cudata_r_o[8]), .Y(CORESYSSERVICES_0_SERV_DATA_R[8]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIAANG (.A(udata_r_sel1), 
        .B(cudata_r_o[17]), .Y(CORESYSSERVICES_0_SERV_DATA_R[17]));
    SLE \ucnrbg_handle_o[4]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[4]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNICCNG (.A(udata_r_sel1), 
        .B(cudata_r_o[19]), .Y(CORESYSSERVICES_0_SERV_DATA_R[19]));
    SLE \ucnrbg_handle_o[6]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[6]));
    CFG2 #( .INIT(4'hD) )  un1_custatus_valid_i (.A(
        CORESYSSERVICES_0_SERV_BUSY), .B(custatus_valid_o), .Y(
        un1_custatus_valid_i_net_1));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[6]  (.A(cudata_r_o[22]), .B(
        cudata_r_o[6]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[6]));
    CFG4 #( .INIT(16'h0200) )  udata_r_sel1_0_a2_3 (.A(
        CORESYSSERVICES_0_SERV_DATA_RVALID), .B(uclatchcmd_o[1]), .C(
        uclatchcmd_o[2]), .D(uclatchcmd_o[0]), .Y(
        udata_r_sel1_0_a2_3_net_1));
    SLE \uclatchcmd_o_fast[4]  (.D(\ucmdbyte_req_d1[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(new_serv_d1_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(N_7670));
    CFG2 #( .INIT(4'h8) )  ustatus_valid_o_3 (.A(custatus_out_en), .B(
        ustatus_valid_lat_net_1), .Y(ustatus_valid_o_3_net_1));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIBCOG (.A(udata_r_sel1), 
        .B(cudata_r_o[27]), .Y(CORESYSSERVICES_0_SERV_DATA_R[27]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[2]  (.A(cudata_r_o[18]), .B(
        cudata_r_o[2]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[2]));
    SLE \ucnrbg_handle_o[2]  (.D(
        my_sysservice_state_0_SERV_NRBG_HANDLE[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ucnrbg_handle_o[2]));
    SLE \ucmdbyte_req_d1[0]  (.D(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        my_sysservice_state_0_SERV_ENABLE_REQ), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\ucmdbyte_req_d1[0]_net_1 )
        );
    SLE ustatus_valid_lat (.D(CORESYSSERVICES_0_SERV_BUSY), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_custatus_valid_i_net_1), 
        .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ustatus_valid_lat_net_1));
    SLE ureq_enable_d2 (.D(ureq_enable_d1_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ureq_enable_d2_net_1));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI99NG (.A(udata_r_sel1), 
        .B(cudata_r_o[16]), .Y(CORESYSSERVICES_0_SERV_DATA_R[16]));
    CFG3 #( .INIT(8'hAC) )  \udata_r_o[4]  (.A(cudata_r_o[20]), .B(
        cudata_r_o[4]), .C(udata_r_sel1), .Y(
        CORESYSSERVICES_0_SERV_DATA_R[4]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNIABOG (.A(udata_r_sel1), 
        .B(cudata_r_o[26]), .Y(CORESYSSERVICES_0_SERV_DATA_R[26]));
    CFG2 #( .INIT(4'h4) )  udata_r_sel1_0_a2_RNI55NG (.A(udata_r_sel1), 
        .B(cudata_r_o[12]), .Y(CORESYSSERVICES_0_SERV_DATA_R[12]));
    
endmodule


module syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8(
       syssvc_blk_0_AHBL_MASTER_HADDR,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       CoreAHBLite_0_AHBmslave16_HRDATA,
       my_sysservice_state_0_SERV_CMDBYTE_REQ,
       my_sysservice_state_0_SERV_NRBG_HANDLE,
       CORESYSSERVICES_0_SERV_STATUS_RESP,
       CORESYSSERVICES_0_SERV_DATA_R,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       cfdatain_d1_25,
       cfdatain_d1_26,
       cfdatain_d1_27,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       cfdatain_d1_20,
       cfdatain_d1_0,
       cfdatain_d1_2,
       cfdatain_d1_5,
       cfdatain_o_iv_0_7_0,
       req_dstreg_data_0_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_curr_state_RNI9FH21_0,
       memwr_desc_int_m_9,
       memwr_desc_int_m_15,
       memwr_desc_int_m_16,
       memwr_desc_int_m_19,
       memwr_desc_int_m_17,
       memwr_desc_int_m_14,
       memwr_desc_int_m_0,
       cfdatain_o_0_iv_0_0_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_1_0,
       masterDataInProg_0,
       CoreAHBLite_0_AHBmslave16_HWDATA_0,
       fmhwrite_d1,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       N_7894_i,
       RSTSYNC1,
       cfwr_req_o,
       cfrd_req_o,
       N_7928,
       un2_cudata_wrdy_int_1_0,
       mchready_i,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       cfdatain_o28,
       un2_cudata_wrdy_int_9,
       cfdatain_o27,
       N_5111_i,
       N_8225,
       N_12_1,
       g2_0_0_0,
       N_7903_0,
       N_10_0_0,
       g2,
       g0_0_2,
       g3,
       g0_0_1,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0,
       g2_0,
       idle_trigger,
       my_hpms_top_0_COMM_BLK_INT,
       N_7344,
       un1_cfdatain_o26_1_out,
       cfdatain_N_5,
       cfrd_resp_o,
       cfdatain_N_8_mux_i_0,
       CORESYSSERVICES_0_SERV_BUSY,
       my_hpms_top_0_HPMS_READY,
       my_hpms_top_0_FIC32_0_CLK,
       my_sysservice_state_0_SERV_ENABLE_REQ,
       CORESYSSERVICES_0_SERV_STATUS_VALID,
       CORESYSSERVICES_0_SERV_DATA_RVALID
    );
output [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
input  [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
input  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
input  [4:0] my_sysservice_state_0_SERV_CMDBYTE_REQ;
input  [7:0] my_sysservice_state_0_SERV_NRBG_HANDLE;
output [7:0] CORESYSSERVICES_0_SERV_STATUS_RESP;
output [31:0] CORESYSSERVICES_0_SERV_DATA_R;
output syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output syssvc_blk_0_AHBL_MASTER_HWDATA_15;
output syssvc_blk_0_AHBL_MASTER_HWDATA_16;
output syssvc_blk_0_AHBL_MASTER_HWDATA_23;
output syssvc_blk_0_AHBL_MASTER_HWDATA_0;
output syssvc_blk_0_AHBL_MASTER_HWDATA_1;
output syssvc_blk_0_AHBL_MASTER_HWDATA_2;
output syssvc_blk_0_AHBL_MASTER_HWDATA_7;
output syssvc_blk_0_AHBL_MASTER_HWDATA_8;
output syssvc_blk_0_AHBL_MASTER_HWDATA_9;
output syssvc_blk_0_AHBL_MASTER_HWDATA_10;
output syssvc_blk_0_AHBL_MASTER_HWDATA_11;
output syssvc_blk_0_AHBL_MASTER_HWDATA_13;
output syssvc_blk_0_AHBL_MASTER_HWDATA_14;
output cfdatain_d1_25;
output cfdatain_d1_26;
output cfdatain_d1_27;
output cfdatain_d1_28;
output cfdatain_d1_30;
output cfdatain_d1_11;
output cfdatain_d1_20;
output cfdatain_d1_0;
output cfdatain_d1_2;
output cfdatain_d1_5;
output cfdatain_o_iv_0_7_0;
output req_dstreg_data_0_0;
output cfdatain_o_0_iv_0_a2_3_0_0;
output req_curr_state_RNI9FH21_0;
output memwr_desc_int_m_9;
output memwr_desc_int_m_15;
output memwr_desc_int_m_16;
output memwr_desc_int_m_19;
output memwr_desc_int_m_17;
output memwr_desc_int_m_14;
output memwr_desc_int_m_0;
output cfdatain_o_0_iv_0_0_0;
output cfdatain_o_iv_0_4_0;
output cfdatain_o_0_iv_0_1_0;
input  masterDataInProg_0;
output CoreAHBLite_0_AHBmslave16_HWDATA_0;
output fmhwrite_d1;
output syssvc_blk_0_AHBL_MASTER_HWRITE;
output N_7894_i;
output RSTSYNC1;
output cfwr_req_o;
output cfrd_req_o;
output N_7928;
output un2_cudata_wrdy_int_1_0;
input  mchready_i;
input  syssvc_blk_0_AHBL_MASTER_HRESP_0;
output cfdatain_o28;
output un2_cudata_wrdy_int_9;
output cfdatain_o27;
output N_5111_i;
output N_8225;
output N_12_1;
output g2_0_0_0;
output N_7903_0;
output N_10_0_0;
output g2;
output g0_0_2;
output g3;
output g0_0_1;
output cfdatain_o_iv_0_N_5_3_0;
output g0_0_0;
output cfdatain_o_iv_N_5_3_0;
output g0_0;
output g2_0;
output idle_trigger;
input  my_hpms_top_0_COMM_BLK_INT;
output N_7344;
output un1_cfdatain_o26_1_out;
output cfdatain_N_5;
output cfrd_resp_o;
output cfdatain_N_8_mux_i_0;
output CORESYSSERVICES_0_SERV_BUSY;
input  my_hpms_top_0_HPMS_READY;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_sysservice_state_0_SERV_ENABLE_REQ;
output CORESYSSERVICES_0_SERV_STATUS_VALID;
output CORESYSSERVICES_0_SERV_DATA_RVALID;

    wire \cudata_r_o[0] , \cudata_r_o[1] , \cudata_r_o[2] , 
        \cudata_r_o[3] , \cudata_r_o[4] , \cudata_r_o[5] , 
        \cudata_r_o[6] , \cudata_r_o[7] , \cudata_r_o[8] , 
        \cudata_r_o[9] , \cudata_r_o[10] , \cudata_r_o[11] , 
        \cudata_r_o[12] , \cudata_r_o[13] , \cudata_r_o[14] , 
        \cudata_r_o[15] , \cudata_r_o[16] , \cudata_r_o[17] , 
        \cudata_r_o[18] , \cudata_r_o[19] , \cudata_r_o[20] , 
        \cudata_r_o[21] , \cudata_r_o[22] , \cudata_r_o[23] , 
        \cudata_r_o[24] , \cudata_r_o[25] , \cudata_r_o[26] , 
        \cudata_r_o[27] , \cudata_r_o[28] , \cudata_r_o[29] , 
        \cudata_r_o[30] , \cudata_r_o[31] , \uclatchcmd_o[0] , 
        \uclatchcmd_o[1] , \uclatchcmd_o[2] , \uclatchcmd_o[3] , 
        \uclatchcmd_o[4] , \ucnrbg_handle_o[0] , \ucnrbg_handle_o[1] , 
        \ucnrbg_handle_o[2] , \ucnrbg_handle_o[3] , 
        \ucnrbg_handle_o[4] , \ucnrbg_handle_o[5] , 
        \ucnrbg_handle_o[6] , \ucnrbg_handle_o[7] , 
        \ucnrbg_length_o[2] , main_curr_state_5371_d, N_7670, uctrig_o, 
        ucvalid_cmd_o, custatus_out_en, custatus_valid_o, 
        \cfdst_addr_o_iv[13] , \cfdst_addr_o_iv[14] , \curr_state[2] , 
        \curr_state[4] , \cfdst_addr_o_0_iv[30] , 
        \cfburst_len_wr_o_1_2_x[0] , \resp_curr_state[6] , 
        \resp_curr_state[0] , \resp_curr_state[5] , 
        \req_curr_state[0] , \cfburst_len_rd_o[0] , 
        \cfburst_len_rd_o[1] , \cfburst_len_rd_o[2] , 
        \cfburst_len_rd_o[3] , \cfburst_len_rd_o[6] , 
        \cfburst_len_rd_o[7] , \cfburst_len_rd_o[8] , 
        \cfburst_len_rd_o[9] , \cfburst_len_rd_o[10] , 
        \cfburst_len_rd_o[11] , \cfburst_len_rd_o[12] , 
        \cfburst_len_rd_o[13] , \cfburst_len_rd_o[14] , 
        \cfburst_len_rd_o[15] , \cfburst_len_wr_o[1] , 
        \cfburst_len_wr_o[2] , \cfburst_len_wr_o[3] , 
        \cfburst_len_wr_o[4] , \cfburst_len_wr_o[5] , 
        \cfburst_len_wr_o[6] , \cfsrc_addr_o[12] , \cfsrc_addr_o[13] , 
        \cfsrc_addr_o[14] , \cfsrc_addr_o[16] , \cfsrc_addr_o[29] , 
        \cfsrc_addr_o[2] , \cfsrc_addr_o[3] , \cfdst_addr_o[2] , 
        \cfdst_addr_o[3] , \cfdst_addr_o[4] , \cfdst_addr_o[12] , 
        \cfdst_addr_o[16] , \cfdst_addr_o[29] , N_7929, N_7931, 
        cfgrant_o, N_7888, cfburst_len_rd_o_1_sn_N_2, N_7876, N_7920, 
        N_7556_i, fctrans_done_o, fcbusreq_o, N_7540_i, N_7352_i, 
        GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CoreSysServices_FSMCtrl U_fsm_ctrl (.cfburst_len_rd_o({
        \cfburst_len_rd_o[15] , \cfburst_len_rd_o[14] , 
        \cfburst_len_rd_o[13] , \cfburst_len_rd_o[12] , 
        \cfburst_len_rd_o[11] , \cfburst_len_rd_o[10] , 
        \cfburst_len_rd_o[9] , \cfburst_len_rd_o[8] , 
        \cfburst_len_rd_o[7] , \cfburst_len_rd_o[6] , nc0, nc1, 
        \cfburst_len_rd_o[3] , \cfburst_len_rd_o[2] , 
        \cfburst_len_rd_o[1] , \cfburst_len_rd_o[0] }), 
        .cfburst_len_wr_o({\cfburst_len_wr_o[6] , 
        \cfburst_len_wr_o[5] , \cfburst_len_wr_o[4] , 
        \cfburst_len_wr_o[3] , \cfburst_len_wr_o[2] , 
        \cfburst_len_wr_o[1] }), .cfdst_addr_o_iv({
        \cfdst_addr_o_iv[14] , \cfdst_addr_o_iv[13] }), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), .cfdst_addr_o_0_iv_0(
        \cfdst_addr_o_0_iv[30] ), .cfsrc_addr_o_27(\cfsrc_addr_o[29] ), 
        .cfsrc_addr_o_11(\cfsrc_addr_o[13] ), .cfsrc_addr_o_12(
        \cfsrc_addr_o[14] ), .cfsrc_addr_o_10(\cfsrc_addr_o[12] ), 
        .cfsrc_addr_o_0(\cfsrc_addr_o[2] ), .cfsrc_addr_o_14(
        \cfsrc_addr_o[16] ), .cfsrc_addr_o_1(\cfsrc_addr_o[3] ), 
        .cfdst_addr_o_27(\cfdst_addr_o[29] ), .cfdst_addr_o_10(
        \cfdst_addr_o[12] ), .cfdst_addr_o_0(\cfdst_addr_o[2] ), 
        .cfdst_addr_o_2(\cfdst_addr_o[4] ), .cfdst_addr_o_14(
        \cfdst_addr_o[16] ), .cfdst_addr_o_1(\cfdst_addr_o[3] ), 
        .cfburst_len_wr_o_1_2_x_0(\cfburst_len_wr_o_1_2_x[0] ), 
        .resp_curr_state_5(\resp_curr_state[5] ), .resp_curr_state_6(
        \resp_curr_state[6] ), .resp_curr_state_0(\resp_curr_state[0] )
        , .req_curr_state_0(\req_curr_state[0] ), .curr_state_2(
        \curr_state[4] ), .curr_state_0(\curr_state[2] ), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), .N_7556_i(N_7556_i), 
        .N_7888(N_7888), .N_7876(N_7876), .cfrd_resp_o(cfrd_resp_o), 
        .cfgrant_o(cfgrant_o), .cfwr_req_o(cfwr_req_o), .cfrd_req_o(
        cfrd_req_o), .fctrans_done_o(fctrans_done_o), .N_7540_i(
        N_7540_i), .N_7929(N_7929), .cfburst_len_rd_o_1_sn_N_2(
        cfburst_len_rd_o_1_sn_N_2), .N_7931(N_7931), .N_7352_i(
        N_7352_i), .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .N_7920(N_7920), 
        .fcbusreq_o(fcbusreq_o), .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .fmhwrite_d1(fmhwrite_d1), 
        .idle_trigger(idle_trigger), .mchready_i(mchready_i), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY));
    GND GND (.Y(GND_net_1));
    CoreSysServices_CmdDec_Z7 U_CmdDec (.cfdst_addr_o_iv({
        \cfdst_addr_o_iv[14] , \cfdst_addr_o_iv[13] }), 
        .ucnrbg_handle_o({\ucnrbg_handle_o[7] , \ucnrbg_handle_o[6] , 
        \ucnrbg_handle_o[5] , \ucnrbg_handle_o[4] , 
        \ucnrbg_handle_o[3] , \ucnrbg_handle_o[2] , 
        \ucnrbg_handle_o[1] , \ucnrbg_handle_o[0] }), 
        .CoreAHBLite_0_AHBmslave16_HRDATA({
        CoreAHBLite_0_AHBmslave16_HRDATA[31], 
        CoreAHBLite_0_AHBmslave16_HRDATA[30], 
        CoreAHBLite_0_AHBmslave16_HRDATA[29], 
        CoreAHBLite_0_AHBmslave16_HRDATA[28], 
        CoreAHBLite_0_AHBmslave16_HRDATA[27], 
        CoreAHBLite_0_AHBmslave16_HRDATA[26], 
        CoreAHBLite_0_AHBmslave16_HRDATA[25], 
        CoreAHBLite_0_AHBmslave16_HRDATA[24], 
        CoreAHBLite_0_AHBmslave16_HRDATA[23], 
        CoreAHBLite_0_AHBmslave16_HRDATA[22], 
        CoreAHBLite_0_AHBmslave16_HRDATA[21], 
        CoreAHBLite_0_AHBmslave16_HRDATA[20], 
        CoreAHBLite_0_AHBmslave16_HRDATA[19], 
        CoreAHBLite_0_AHBmslave16_HRDATA[18], 
        CoreAHBLite_0_AHBmslave16_HRDATA[17], 
        CoreAHBLite_0_AHBmslave16_HRDATA[16], 
        CoreAHBLite_0_AHBmslave16_HRDATA[15], 
        CoreAHBLite_0_AHBmslave16_HRDATA[14], 
        CoreAHBLite_0_AHBmslave16_HRDATA[13], 
        CoreAHBLite_0_AHBmslave16_HRDATA[12], 
        CoreAHBLite_0_AHBmslave16_HRDATA[11], 
        CoreAHBLite_0_AHBmslave16_HRDATA[10], 
        CoreAHBLite_0_AHBmslave16_HRDATA[9], 
        CoreAHBLite_0_AHBmslave16_HRDATA[8], nc2, 
        CoreAHBLite_0_AHBmslave16_HRDATA[6], 
        CoreAHBLite_0_AHBmslave16_HRDATA[5], 
        CoreAHBLite_0_AHBmslave16_HRDATA[4], 
        CoreAHBLite_0_AHBmslave16_HRDATA[3], 
        CoreAHBLite_0_AHBmslave16_HRDATA[2], nc3, 
        CoreAHBLite_0_AHBmslave16_HRDATA[0]}), .uclatchcmd_o({
        \uclatchcmd_o[4] , \uclatchcmd_o[3] , \uclatchcmd_o[2] , 
        \uclatchcmd_o[1] , \uclatchcmd_o[0] }), .cfburst_len_rd_o({
        \cfburst_len_rd_o[15] , \cfburst_len_rd_o[14] , 
        \cfburst_len_rd_o[13] , \cfburst_len_rd_o[12] , 
        \cfburst_len_rd_o[11] , \cfburst_len_rd_o[10] , 
        \cfburst_len_rd_o[9] , \cfburst_len_rd_o[8] , 
        \cfburst_len_rd_o[7] , \cfburst_len_rd_o[6] , nc4, nc5, 
        \cfburst_len_rd_o[3] , \cfburst_len_rd_o[2] , 
        \cfburst_len_rd_o[1] , \cfburst_len_rd_o[0] }), 
        .cfburst_len_wr_o({\cfburst_len_wr_o[6] , 
        \cfburst_len_wr_o[5] , \cfburst_len_wr_o[4] , 
        \cfburst_len_wr_o[3] , \cfburst_len_wr_o[2] , 
        \cfburst_len_wr_o[1] }), .syssvc_blk_0_AHBL_MASTER_HRDATA({
        syssvc_blk_0_AHBL_MASTER_HRDATA[31], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[30], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[29], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[28], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[27], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[26], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[25], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[24], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[23], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[22], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[21], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[20], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[19], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[18], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[17], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[16], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[15], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[14], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[13], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[12], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[11], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[10], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[9], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[8], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[7], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[6], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[5], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[4], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[3], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[2], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[1], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]}), .cudata_r_o({
        \cudata_r_o[31] , \cudata_r_o[30] , \cudata_r_o[29] , 
        \cudata_r_o[28] , \cudata_r_o[27] , \cudata_r_o[26] , 
        \cudata_r_o[25] , \cudata_r_o[24] , \cudata_r_o[23] , 
        \cudata_r_o[22] , \cudata_r_o[21] , \cudata_r_o[20] , 
        \cudata_r_o[19] , \cudata_r_o[18] , \cudata_r_o[17] , 
        \cudata_r_o[16] , \cudata_r_o[15] , \cudata_r_o[14] , 
        \cudata_r_o[13] , \cudata_r_o[12] , \cudata_r_o[11] , 
        \cudata_r_o[10] , \cudata_r_o[9] , \cudata_r_o[8] , 
        \cudata_r_o[7] , \cudata_r_o[6] , \cudata_r_o[5] , 
        \cudata_r_o[4] , \cudata_r_o[3] , \cudata_r_o[2] , 
        \cudata_r_o[1] , \cudata_r_o[0] }), 
        .CoreAHBLite_0_AHBmslave16_HWDATA_0(
        CoreAHBLite_0_AHBmslave16_HWDATA_0), .masterDataInProg_0(
        masterDataInProg_0), .cfdatain_o_0_iv_0_1_0(
        cfdatain_o_0_iv_0_1_0), .cfdatain_o_iv_0_4_0(
        cfdatain_o_iv_0_4_0), .cfdatain_o_0_iv_0_0_0(
        cfdatain_o_0_iv_0_0_0), .memwr_desc_int_m_9(memwr_desc_int_m_9)
        , .memwr_desc_int_m_15(memwr_desc_int_m_15), 
        .memwr_desc_int_m_16(memwr_desc_int_m_16), 
        .memwr_desc_int_m_19(memwr_desc_int_m_19), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .curr_state_0(\curr_state[2] ), 
        .curr_state_2(\curr_state[4] ), .req_curr_state_RNI9FH21_0(
        req_curr_state_RNI9FH21_0), .cfdst_addr_o_0_iv_0(
        \cfdst_addr_o_0_iv[30] ), .cfdatain_o_0_iv_0_a2_3_0_0(
        cfdatain_o_0_iv_0_a2_3_0_0), .req_dstreg_data_0_0(
        req_dstreg_data_0_0), .ucnrbg_length_o_0(\ucnrbg_length_o[2] ), 
        .cfburst_len_wr_o_1_2_x_0(\cfburst_len_wr_o_1_2_x[0] ), 
        .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0), .resp_curr_state_6(
        \resp_curr_state[6] ), .resp_curr_state_0(\resp_curr_state[0] )
        , .resp_curr_state_5(\resp_curr_state[5] ), .req_curr_state_0(
        \req_curr_state[0] ), .cfsrc_addr_o_10(\cfsrc_addr_o[12] ), 
        .cfsrc_addr_o_11(\cfsrc_addr_o[13] ), .cfsrc_addr_o_12(
        \cfsrc_addr_o[14] ), .cfsrc_addr_o_14(\cfsrc_addr_o[16] ), 
        .cfsrc_addr_o_27(\cfsrc_addr_o[29] ), .cfsrc_addr_o_0(
        \cfsrc_addr_o[2] ), .cfsrc_addr_o_1(\cfsrc_addr_o[3] ), 
        .cfdst_addr_o_0(\cfdst_addr_o[2] ), .cfdst_addr_o_1(
        \cfdst_addr_o[3] ), .cfdst_addr_o_2(\cfdst_addr_o[4] ), 
        .cfdst_addr_o_10(\cfdst_addr_o[12] ), .cfdst_addr_o_14(
        \cfdst_addr_o[16] ), .cfdst_addr_o_27(\cfdst_addr_o[29] ), 
        .cfdatain_d1_25(cfdatain_d1_25), .cfdatain_d1_26(
        cfdatain_d1_26), .cfdatain_d1_27(cfdatain_d1_27), 
        .cfdatain_d1_28(cfdatain_d1_28), .cfdatain_d1_30(
        cfdatain_d1_30), .cfdatain_d1_11(cfdatain_d1_11), 
        .cfdatain_d1_20(cfdatain_d1_20), .cfdatain_d1_0(cfdatain_d1_0), 
        .cfdatain_d1_2(cfdatain_d1_2), .cfdatain_d1_5(cfdatain_d1_5), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), .cfdatain_N_8_mux_i_0(
        cfdatain_N_8_mux_i_0), .cfrd_resp_o(cfrd_resp_o), .N_7929(
        N_7929), .N_7931(N_7931), .cfgrant_o(cfgrant_o), .cfdatain_N_5(
        cfdatain_N_5), .uctrig_o(uctrig_o), .N_7888(N_7888), 
        .cfburst_len_rd_o_1_sn_N_2(cfburst_len_rd_o_1_sn_N_2), .N_7876(
        N_7876), .un1_cfdatain_o26_1_out(un1_cfdatain_o26_1_out), 
        .N_7344(N_7344), .N_7920(N_7920), .my_hpms_top_0_COMM_BLK_INT(
        my_hpms_top_0_COMM_BLK_INT), .idle_trigger(idle_trigger), 
        .custatus_out_en(custatus_out_en), .g2_0(g2_0), .g0_0(g0_0), 
        .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), .g0_0_0(g0_0_0), 
        .cfdatain_o_iv_0_N_5_3_0(cfdatain_o_iv_0_N_5_3_0), .g0_0_1(
        g0_0_1), .g3(g3), .g0_0_2(g0_0_2), .g2(g2), .N_10_0_0(N_10_0_0)
        , .N_7903_0(N_7903_0), .g2_0_0_0(g2_0_0_0), .N_12_1(N_12_1), 
        .N_8225(N_8225), .N_5111_i(N_5111_i), .N_7670(N_7670), 
        .cfdatain_o27(cfdatain_o27), .un2_cudata_wrdy_int_9(
        un2_cudata_wrdy_int_9), .N_7556_i(N_7556_i), .cfdatain_o28(
        cfdatain_o28), .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .mchready_i(mchready_i), 
        .un2_cudata_wrdy_int_1_0(un2_cudata_wrdy_int_1_0), .N_7928(
        N_7928), .ucvalid_cmd_o(ucvalid_cmd_o), .cfrd_req_o(cfrd_req_o)
        , .fctrans_done_o(fctrans_done_o), .fcbusreq_o(fcbusreq_o), 
        .CORESYSSERVICES_0_SERV_DATA_RVALID(
        CORESYSSERVICES_0_SERV_DATA_RVALID), .cfwr_req_o(cfwr_req_o), 
        .custatus_valid_o(custatus_valid_o), .RSTSYNC1(RSTSYNC1), 
        .main_curr_state_5371_d(main_curr_state_5371_d), .N_7894_i(
        N_7894_i), .N_7540_i(N_7540_i), .N_7352_i(N_7352_i), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY));
    CoreSysServices_UserIF_Z6 U_UserIF (.CORESYSSERVICES_0_SERV_DATA_R({
        CORESYSSERVICES_0_SERV_DATA_R[31], 
        CORESYSSERVICES_0_SERV_DATA_R[30], 
        CORESYSSERVICES_0_SERV_DATA_R[29], 
        CORESYSSERVICES_0_SERV_DATA_R[28], 
        CORESYSSERVICES_0_SERV_DATA_R[27], 
        CORESYSSERVICES_0_SERV_DATA_R[26], 
        CORESYSSERVICES_0_SERV_DATA_R[25], 
        CORESYSSERVICES_0_SERV_DATA_R[24], 
        CORESYSSERVICES_0_SERV_DATA_R[23], 
        CORESYSSERVICES_0_SERV_DATA_R[22], 
        CORESYSSERVICES_0_SERV_DATA_R[21], 
        CORESYSSERVICES_0_SERV_DATA_R[20], 
        CORESYSSERVICES_0_SERV_DATA_R[19], 
        CORESYSSERVICES_0_SERV_DATA_R[18], 
        CORESYSSERVICES_0_SERV_DATA_R[17], 
        CORESYSSERVICES_0_SERV_DATA_R[16], 
        CORESYSSERVICES_0_SERV_DATA_R[15], 
        CORESYSSERVICES_0_SERV_DATA_R[14], 
        CORESYSSERVICES_0_SERV_DATA_R[13], 
        CORESYSSERVICES_0_SERV_DATA_R[12], 
        CORESYSSERVICES_0_SERV_DATA_R[11], 
        CORESYSSERVICES_0_SERV_DATA_R[10], 
        CORESYSSERVICES_0_SERV_DATA_R[9], 
        CORESYSSERVICES_0_SERV_DATA_R[8], 
        CORESYSSERVICES_0_SERV_DATA_R[7], 
        CORESYSSERVICES_0_SERV_DATA_R[6], 
        CORESYSSERVICES_0_SERV_DATA_R[5], 
        CORESYSSERVICES_0_SERV_DATA_R[4], 
        CORESYSSERVICES_0_SERV_DATA_R[3], 
        CORESYSSERVICES_0_SERV_DATA_R[2], 
        CORESYSSERVICES_0_SERV_DATA_R[1], 
        CORESYSSERVICES_0_SERV_DATA_R[0]}), .cudata_r_o({
        \cudata_r_o[31] , \cudata_r_o[30] , \cudata_r_o[29] , 
        \cudata_r_o[28] , \cudata_r_o[27] , \cudata_r_o[26] , 
        \cudata_r_o[25] , \cudata_r_o[24] , \cudata_r_o[23] , 
        \cudata_r_o[22] , \cudata_r_o[21] , \cudata_r_o[20] , 
        \cudata_r_o[19] , \cudata_r_o[18] , \cudata_r_o[17] , 
        \cudata_r_o[16] , \cudata_r_o[15] , \cudata_r_o[14] , 
        \cudata_r_o[13] , \cudata_r_o[12] , \cudata_r_o[11] , 
        \cudata_r_o[10] , \cudata_r_o[9] , \cudata_r_o[8] , 
        \cudata_r_o[7] , \cudata_r_o[6] , \cudata_r_o[5] , 
        \cudata_r_o[4] , \cudata_r_o[3] , \cudata_r_o[2] , 
        \cudata_r_o[1] , \cudata_r_o[0] }), 
        .CORESYSSERVICES_0_SERV_STATUS_RESP({
        CORESYSSERVICES_0_SERV_STATUS_RESP[7], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[6], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[5], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[4], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[3], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[2], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[1], 
        CORESYSSERVICES_0_SERV_STATUS_RESP[0]}), .uclatchcmd_o({
        \uclatchcmd_o[4] , \uclatchcmd_o[3] , \uclatchcmd_o[2] , 
        \uclatchcmd_o[1] , \uclatchcmd_o[0] }), 
        .my_sysservice_state_0_SERV_NRBG_HANDLE({
        my_sysservice_state_0_SERV_NRBG_HANDLE[7], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[6], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[5], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[4], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[3], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[2], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[1], 
        my_sysservice_state_0_SERV_NRBG_HANDLE[0]}), .ucnrbg_handle_o({
        \ucnrbg_handle_o[7] , \ucnrbg_handle_o[6] , 
        \ucnrbg_handle_o[5] , \ucnrbg_handle_o[4] , 
        \ucnrbg_handle_o[3] , \ucnrbg_handle_o[2] , 
        \ucnrbg_handle_o[1] , \ucnrbg_handle_o[0] }), 
        .my_sysservice_state_0_SERV_CMDBYTE_REQ({
        my_sysservice_state_0_SERV_CMDBYTE_REQ[4], nc6, 
        my_sysservice_state_0_SERV_CMDBYTE_REQ[2], 
        my_sysservice_state_0_SERV_CMDBYTE_REQ[1], 
        my_sysservice_state_0_SERV_CMDBYTE_REQ[0]}), 
        .ucnrbg_length_o_0(\ucnrbg_length_o[2] ), 
        .main_curr_state_5371_d(main_curr_state_5371_d), 
        .CORESYSSERVICES_0_SERV_DATA_RVALID(
        CORESYSSERVICES_0_SERV_DATA_RVALID), .N_7670(N_7670), 
        .uctrig_o(uctrig_o), .CORESYSSERVICES_0_SERV_STATUS_VALID(
        CORESYSSERVICES_0_SERV_STATUS_VALID), .ucvalid_cmd_o(
        ucvalid_cmd_o), .custatus_out_en(custatus_out_en), 
        .my_sysservice_state_0_SERV_ENABLE_REQ(
        my_sysservice_state_0_SERV_ENABLE_REQ), .custatus_valid_o(
        custatus_valid_o), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .CORESYSSERVICES_0_SERV_BUSY(
        CORESYSSERVICES_0_SERV_BUSY));
    
endmodule


module my_sysservice_state(
       CORESYSSERVICES_0_SERV_STATUS_RESP,
       my_sysservice_state_0_SERV_CMDBYTE_REQ,
       my_sysservice_state_0_SERV_NRBG_HANDLE,
       syssvc_blk_0_NRBG_DATA,
       CORESYSSERVICES_0_SERV_DATA_R,
       syssvc_blk_0_NRBG_HANDLE,
       N_179_i,
       N_181_i,
       N_180_i,
       N_182_i,
       UART_top_0_START_sysservice,
       UART_top_0_SELF_TEST_SERVICE,
       UART_top_0_INSTANTIATE_SERVICE,
       UART_top_0_GENERATE_SERVICE,
       CORESYSSERVICES_0_SERV_STATUS_VALID,
       CORESYSSERVICES_0_SERV_DATA_RVALID,
       CORESYSSERVICES_0_SERV_BUSY,
       syssvc_blk_0_NRBG_SVC_DONE,
       my_sysservice_state_0_SERV_ENABLE_REQ,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY
    );
input  [7:0] CORESYSSERVICES_0_SERV_STATUS_RESP;
output [4:0] my_sysservice_state_0_SERV_CMDBYTE_REQ;
output [7:0] my_sysservice_state_0_SERV_NRBG_HANDLE;
output [31:0] syssvc_blk_0_NRBG_DATA;
input  [31:0] CORESYSSERVICES_0_SERV_DATA_R;
output [7:0] syssvc_blk_0_NRBG_HANDLE;
output N_179_i;
output N_181_i;
output N_180_i;
output N_182_i;
input  UART_top_0_START_sysservice;
input  UART_top_0_SELF_TEST_SERVICE;
input  UART_top_0_INSTANTIATE_SERVICE;
input  UART_top_0_GENERATE_SERVICE;
input  CORESYSSERVICES_0_SERV_STATUS_VALID;
input  CORESYSSERVICES_0_SERV_DATA_RVALID;
input  CORESYSSERVICES_0_SERV_BUSY;
output syssvc_blk_0_NRBG_SVC_DONE;
output my_sysservice_state_0_SERV_ENABLE_REQ;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;

    wire VCC_net_1, NRBG_HANDLE_0_sqmuxa, GND_net_1, 
        NRBG_DATA_0_sqmuxa, N_185_i, un1_fsm_6_0_net_1, 
        \NRBG_HANDLE_VAL[0]_net_1 , \NRBG_HANDLE_VAL_5[0]_net_1 , 
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1, \NRBG_HANDLE_VAL[1]_net_1 , 
        \NRBG_HANDLE_VAL_5[1]_net_1 , \NRBG_HANDLE_VAL[2]_net_1 , 
        \NRBG_HANDLE_VAL_5[2]_net_1 , \NRBG_HANDLE_VAL[3]_net_1 , 
        \NRBG_HANDLE_VAL_5[3]_net_1 , \NRBG_HANDLE_VAL[4]_net_1 , 
        \NRBG_HANDLE_VAL_5[4]_net_1 , \NRBG_HANDLE_VAL[5]_net_1 , 
        \NRBG_HANDLE_VAL_5[5]_net_1 , \NRBG_HANDLE_VAL[6]_net_1 , 
        \NRBG_HANDLE_VAL_5[6]_net_1 , \NRBG_HANDLE_VAL[7]_net_1 , 
        \NRBG_HANDLE_VAL_5[7]_net_1 , \SERV_NRBG_HANDLE_5[0]_net_1 , 
        un1_fsm_12_0_0, \SERV_NRBG_HANDLE_5[1]_net_1 , 
        \SERV_NRBG_HANDLE_5[2]_net_1 , \SERV_NRBG_HANDLE_5[3]_net_1 , 
        \SERV_NRBG_HANDLE_5[4]_net_1 , \SERV_NRBG_HANDLE_5[5]_net_1 , 
        \SERV_NRBG_HANDLE_5[6]_net_1 , \SERV_NRBG_HANDLE_5[7]_net_1 , 
        \SERV_CMDBYTE_REQ_6[0]_net_1 , N_184_i, un1_fsm_12_0_net_1, 
        NRBG_SVC_DONE_0_sqmuxa, un1_NRBG_HANDLE_VAL_1_sqmuxa_0_net_1, 
        un1_fsm_0_o4_net_1, \fsm_1[1]_net_1 , \fsm_1_ns[1] , 
        \fsm_1[2]_net_1 , \fsm_1[3]_net_1 , \fsm_1_ns[3]_net_1 , 
        \fsm_1[4]_net_1 , \fsm_1_ns[4] , \fsm_1[5]_net_1 , 
        \fsm_1[6]_net_1 , \fsm_1_ns[6]_net_1 , \fsm_1[7]_net_1 , 
        \fsm_1_ns[7]_net_1 , \fsm_1[8]_net_1 , \fsm_1_ns[8]_net_1 , 
        \fsm_1[9]_net_1 , \fsm_1_ns[9] , \fsm_1[10]_net_1 , 
        \fsm_1_ns[10]_net_1 , \fsm_1[11]_net_1 , \fsm_1_ns[11]_net_1 , 
        \fsm_1[12]_net_1 , \fsm_1_ns[12]_net_1 , \fsm_1[13]_net_1 , 
        \fsm_1_ns[13] , \fsm_1[14]_net_1 , \fsm_1_ns[14]_net_1 , 
        \fsm_1[15]_net_1 , \fsm_1_ns[15]_net_1 , \fsm_1[0]_net_1 , 
        \fsm_1_ns[0]_net_1 , N_206, \un1_fsm_3_i_a4_3[2]_net_1 , N_208, 
        \un1_fsm_3_i_a4_1[3]_net_1 , fsm16_5_net_1, fsm16_4_net_1, 
        \un1_fsm_3_i_a4_3[1]_net_1 , \un1_fsm_3_i_a4_4[2]_net_1 , 
        N_173, N_207, \fsm_1_ns_0[0]_net_1 , 
        \un1_fsm_3_i_a4_0[0]_net_1 , fsm16_net_1;
    
    CFG3 #( .INIT(8'hF2) )  \fsm_1_ns[3]  (.A(\fsm_1[3]_net_1 ), .B(
        fsm16_net_1), .C(\fsm_1[2]_net_1 ), .Y(\fsm_1_ns[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[1]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[1]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[1]_net_1 ));
    CFG4 #( .INIT(16'h0200) )  \fsm_1_ns_a4[4]  (.A(
        UART_top_0_GENERATE_SERVICE), .B(
        UART_top_0_INSTANTIATE_SERVICE), .C(
        UART_top_0_SELF_TEST_SERVICE), .D(N_207), .Y(\fsm_1_ns[4] ));
    CFG3 #( .INIT(8'hFE) )  un1_fsm_6_0_o3_0 (.A(
        UART_top_0_GENERATE_SERVICE), .B(
        UART_top_0_INSTANTIATE_SERVICE), .C(
        UART_top_0_SELF_TEST_SERVICE), .Y(N_173));
    SLE \NRBG_DATA[28]  (.D(CORESYSSERVICES_0_SERV_DATA_R[28]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[28])
        );
    SLE \NRBG_DATA[0]  (.D(CORESYSSERVICES_0_SERV_DATA_R[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[0]));
    SLE \NRBG_DATA[14]  (.D(CORESYSSERVICES_0_SERV_DATA_R[14]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[14])
        );
    SLE \NRBG_DATA[6]  (.D(CORESYSSERVICES_0_SERV_DATA_R[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[6]));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[6]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[6]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[6]_net_1 ));
    SLE \fsm_1[14]  (.D(\fsm_1_ns[14]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[14]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  un1_fsm_12_0 (.A(un1_fsm_0_o4_net_1), 
        .B(N_206), .C(\fsm_1[1]_net_1 ), .D(\fsm_1[4]_net_1 ), .Y(
        un1_fsm_12_0_net_1));
    SLE \NRBG_DATA[7]  (.D(CORESYSSERVICES_0_SERV_DATA_R[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[7]));
    SLE \SERV_NRBG_HANDLE[6]  (.D(\SERV_NRBG_HANDLE_5[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[6]));
    CFG2 #( .INIT(4'h8) )  NRBG_DATA_0_sqmuxa_0_a4 (.A(
        CORESYSSERVICES_0_SERV_DATA_RVALID), .B(\fsm_1[10]_net_1 ), .Y(
        NRBG_DATA_0_sqmuxa));
    SLE \NRBG_DATA[9]  (.D(CORESYSSERVICES_0_SERV_DATA_R[9]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[9]));
    CFG4 #( .INIT(16'h1000) )  fsm16 (.A(
        CORESYSSERVICES_0_SERV_STATUS_RESP[0]), .B(
        CORESYSSERVICES_0_SERV_STATUS_RESP[7]), .C(fsm16_5_net_1), .D(
        fsm16_4_net_1), .Y(fsm16_net_1));
    SLE \NRBG_DATA[29]  (.D(CORESYSSERVICES_0_SERV_DATA_R[29]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[29])
        );
    SLE \SERV_NRBG_HANDLE[0]  (.D(\SERV_NRBG_HANDLE_5[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[0]));
    SLE \NRBG_HANDLE[6]  (.D(CORESYSSERVICES_0_SERV_DATA_R[6]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[6]));
    SLE \NRBG_DATA[1]  (.D(CORESYSSERVICES_0_SERV_DATA_R[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[1]));
    CFG4 #( .INIT(16'h0001) )  \un1_fsm_3_i_a4_0[0]  (.A(
        \fsm_1[13]_net_1 ), .B(\fsm_1[9]_net_1 ), .C(\fsm_1[5]_net_1 ), 
        .D(\fsm_1[3]_net_1 ), .Y(\un1_fsm_3_i_a4_0[0]_net_1 ));
    SLE \NRBG_HANDLE[7]  (.D(CORESYSSERVICES_0_SERV_DATA_R[7]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[7]));
    CFG3 #( .INIT(8'hF4) )  \fsm_1_ns[11]  (.A(fsm16_net_1), .B(
        \fsm_1[11]_net_1 ), .C(NRBG_DATA_0_sqmuxa), .Y(
        \fsm_1_ns[11]_net_1 ));
    SLE \NRBG_DATA[31]  (.D(CORESYSSERVICES_0_SERV_DATA_R[31]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[31])
        );
    CFG2 #( .INIT(4'hE) )  \SERV_CMDBYTE_REQ_1_RNO[1]  (.A(
        un1_fsm_0_o4_net_1), .B(\fsm_1[8]_net_1 ), .Y(N_184_i));
    SLE \NRBG_DATA[26]  (.D(CORESYSSERVICES_0_SERV_DATA_R[26]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[26])
        );
    SLE \fsm_1[0]  (.D(\fsm_1_ns[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[0]_net_1 ));
    SLE \NRBG_DATA[27]  (.D(CORESYSSERVICES_0_SERV_DATA_R[27]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[27])
        );
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[0]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[0]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[0]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \fsm_1[11]  (.D(\fsm_1_ns[11]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[11]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[0]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[0]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[0]_net_1 ));
    CFG4 #( .INIT(16'hFFF7) )  \un1_fsm_3_i_a4[3]  (.A(N_208), .B(
        \un1_fsm_3_i_a4_1[3]_net_1 ), .C(\fsm_1[8]_net_1 ), .D(
        \fsm_1[12]_net_1 ), .Y(N_182_i));
    CFG2 #( .INIT(4'h1) )  \un1_fsm_3_i_a4_3[2]  (.A(\fsm_1[6]_net_1 ), 
        .B(\fsm_1[7]_net_1 ), .Y(\un1_fsm_3_i_a4_3[2]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \fsm_1_ns_a4[13]  (.A(
        CORESYSSERVICES_0_SERV_BUSY), .B(\fsm_1[12]_net_1 ), .Y(
        \fsm_1_ns[13] ));
    SLE \NRBG_DATA[30]  (.D(CORESYSSERVICES_0_SERV_DATA_R[30]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[30])
        );
    SLE \NRBG_HANDLE_VAL[6]  (.D(\NRBG_HANDLE_VAL_5[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[6]_net_1 )
        );
    SLE SERV_ENABLE_REQ (.D(un1_fsm_12_0_0), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_ENABLE_REQ));
    SLE \NRBG_HANDLE_VAL[7]  (.D(\NRBG_HANDLE_VAL_5[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[7]_net_1 )
        );
    CFG4 #( .INIT(16'hBA32) )  \fsm_1_ns_0[0]  (.A(\fsm_1[0]_net_1 ), 
        .B(UART_top_0_START_sysservice), .C(\fsm_1[15]_net_1 ), .D(
        CORESYSSERVICES_0_SERV_BUSY), .Y(\fsm_1_ns_0[0]_net_1 ));
    CFG2 #( .INIT(4'h8) )  NRBG_HANDLE_0_sqmuxa_0_a4 (.A(
        \fsm_1[6]_net_1 ), .B(CORESYSSERVICES_0_SERV_DATA_RVALID), .Y(
        NRBG_HANDLE_0_sqmuxa));
    SLE \NRBG_DATA[18]  (.D(CORESYSSERVICES_0_SERV_DATA_R[18]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[18])
        );
    SLE \NRBG_DATA[21]  (.D(CORESYSSERVICES_0_SERV_DATA_R[21]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[21])
        );
    CFG4 #( .INIT(16'hEAC0) )  \fsm_1_ns[8]  (.A(\fsm_1[7]_net_1 ), .B(
        \fsm_1[8]_net_1 ), .C(CORESYSSERVICES_0_SERV_BUSY), .D(
        fsm16_net_1), .Y(\fsm_1_ns[8]_net_1 ));
    CFG3 #( .INIT(8'hEA) )  \fsm_1_ns[15]  (.A(NRBG_SVC_DONE_0_sqmuxa), 
        .B(UART_top_0_START_sysservice), .C(\fsm_1[15]_net_1 ), .Y(
        \fsm_1_ns[15]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[2]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[2]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[2]_net_1 ));
    SLE \NRBG_DATA[19]  (.D(CORESYSSERVICES_0_SERV_DATA_R[19]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[19])
        );
    SLE \SERV_NRBG_HANDLE[4]  (.D(\SERV_NRBG_HANDLE_5[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[4]));
    SLE \NRBG_DATA[5]  (.D(CORESYSSERVICES_0_SERV_DATA_R[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[5]));
    CFG3 #( .INIT(8'h32) )  un1_fsm_6_0_a4_0 (.A(\fsm_1[12]_net_1 ), 
        .B(CORESYSSERVICES_0_SERV_BUSY), .C(\fsm_1[8]_net_1 ), .Y(
        N_206));
    CFG3 #( .INIT(8'hBA) )  un1_NRBG_HANDLE_VAL_1_sqmuxa_0 (.A(
        NRBG_SVC_DONE_0_sqmuxa), .B(UART_top_0_START_sysservice), .C(
        \fsm_1[15]_net_1 ), .Y(un1_NRBG_HANDLE_VAL_1_sqmuxa_0_net_1));
    SLE \NRBG_HANDLE[4]  (.D(CORESYSSERVICES_0_SERV_DATA_R[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[4]));
    VCC VCC (.Y(VCC_net_1));
    SLE \NRBG_DATA[20]  (.D(CORESYSSERVICES_0_SERV_DATA_R[20]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[20])
        );
    CFG4 #( .INIT(16'hFDFF) )  \un1_fsm_3_i_a4_0_RNINN6J[0]  (.A(
        \un1_fsm_3_i_a4_0[0]_net_1 ), .B(\fsm_1[7]_net_1 ), .C(
        \fsm_1[1]_net_1 ), .D(N_208), .Y(N_179_i));
    CFG3 #( .INIT(8'hBA) )  un1_NRBG_HANDLE_0_sqmuxa_0 (.A(
        NRBG_HANDLE_0_sqmuxa), .B(UART_top_0_START_sysservice), .C(
        \fsm_1[15]_net_1 ), .Y(un1_NRBG_HANDLE_0_sqmuxa_0_net_1));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[5]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[5]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[5]_net_1 ));
    SLE \NRBG_DATA[16]  (.D(CORESYSSERVICES_0_SERV_DATA_R[16]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[16])
        );
    SLE \NRBG_DATA[17]  (.D(CORESYSSERVICES_0_SERV_DATA_R[17]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[17])
        );
    SLE \fsm_1[9]  (.D(\fsm_1_ns[9] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \fsm_1[9]_net_1 ));
    SLE \SERV_CMDBYTE_REQ_1[2]  (.D(N_185_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_6_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[2]));
    CFG3 #( .INIT(8'h02) )  fsm16_4 (.A(
        CORESYSSERVICES_0_SERV_STATUS_VALID), .B(
        CORESYSSERVICES_0_SERV_STATUS_RESP[2]), .C(
        CORESYSSERVICES_0_SERV_STATUS_RESP[1]), .Y(fsm16_4_net_1));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[7]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[7]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[7]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[1]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[1]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[1]_net_1 ));
    SLE \fsm_1[4]  (.D(\fsm_1_ns[4] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \fsm_1[4]_net_1 ));
    SLE \SERV_NRBG_HANDLE[2]  (.D(\SERV_NRBG_HANDLE_5[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[2]));
    SLE \fsm_1[10]  (.D(\fsm_1_ns[10]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[10]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[3]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[3]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[3]_net_1 ));
    CFG3 #( .INIT(8'hF4) )  \fsm_1_ns[7]  (.A(fsm16_net_1), .B(
        \fsm_1[7]_net_1 ), .C(NRBG_HANDLE_0_sqmuxa), .Y(
        \fsm_1_ns[7]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \un1_fsm_3_i_a2[0]  (.A(\fsm_1[15]_net_1 ), 
        .B(\fsm_1[11]_net_1 ), .Y(N_208));
    SLE \NRBG_DATA[11]  (.D(CORESYSSERVICES_0_SERV_DATA_R[11]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[11])
        );
    SLE \SERV_NRBG_HANDLE[7]  (.D(\SERV_NRBG_HANDLE_5[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[7]));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[3]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[3]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[3]_net_1 ));
    SLE \NRBG_HANDLE_VAL[1]  (.D(\NRBG_HANDLE_VAL_5[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[1]_net_1 )
        );
    SLE \SERV_CMDBYTE_REQ_1[0]  (.D(\SERV_CMDBYTE_REQ_6[0]_net_1 ), 
        .CLK(my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_6_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[0]));
    SLE \NRBG_DATA[23]  (.D(CORESYSSERVICES_0_SERV_DATA_R[23]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[23])
        );
    SLE \fsm_1[7]  (.D(\fsm_1_ns[7]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[7]_net_1 ));
    SLE \fsm_1[5]  (.D(\fsm_1[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[5]_net_1 ));
    CFG3 #( .INIT(8'hF4) )  \fsm_1_ns[6]  (.A(
        CORESYSSERVICES_0_SERV_DATA_RVALID), .B(\fsm_1[6]_net_1 ), .C(
        \fsm_1[5]_net_1 ), .Y(\fsm_1_ns[6]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[2]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[2]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[2]_net_1 ));
    SLE \NRBG_HANDLE_VAL[2]  (.D(\NRBG_HANDLE_VAL_5[2]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[2]_net_1 )
        );
    SLE \NRBG_DATA[10]  (.D(CORESYSSERVICES_0_SERV_DATA_R[10]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[10])
        );
    SLE \NRBG_HANDLE[0]  (.D(CORESYSSERVICES_0_SERV_DATA_R[0]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[0]));
    SLE \fsm_1[6]  (.D(\fsm_1_ns[6]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[6]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \un1_fsm_3_i_a4_1[3]  (.A(
        \fsm_1[10]_net_1 ), .B(\fsm_1[9]_net_1 ), .C(\fsm_1[14]_net_1 )
        , .D(\fsm_1[13]_net_1 ), .Y(\un1_fsm_3_i_a4_1[3]_net_1 ));
    SLE \NRBG_DATA[3]  (.D(CORESYSSERVICES_0_SERV_DATA_R[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[3]));
    CFG4 #( .INIT(16'hF0F1) )  \SERV_CMDBYTE_REQ_6[0]  (.A(
        \fsm_1[8]_net_1 ), .B(UART_top_0_SELF_TEST_SERVICE), .C(
        un1_fsm_0_o4_net_1), .D(\fsm_1[12]_net_1 ), .Y(
        \SERV_CMDBYTE_REQ_6[0]_net_1 ));
    CFG3 #( .INIT(8'hC8) )  \fsm_1_ns_a4[15]  (.A(\fsm_1[14]_net_1 ), 
        .B(fsm16_net_1), .C(\fsm_1[3]_net_1 ), .Y(
        NRBG_SVC_DONE_0_sqmuxa));
    SLE \SERV_CMDBYTE_REQ_1[1]  (.D(N_184_i), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_6_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[1]));
    SLE \NRBG_DATA[4]  (.D(CORESYSSERVICES_0_SERV_DATA_R[4]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[4]));
    CFG3 #( .INIT(8'hCE) )  \fsm_1_ns[14]  (.A(\fsm_1[14]_net_1 ), .B(
        \fsm_1[13]_net_1 ), .C(fsm16_net_1), .Y(\fsm_1_ns[14]_net_1 ));
    SLE \NRBG_HANDLE[5]  (.D(CORESYSSERVICES_0_SERV_DATA_R[5]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[5]));
    CFG3 #( .INIT(8'hDC) )  \fsm_1_ns[0]  (.A(N_173), .B(
        \fsm_1_ns_0[0]_net_1 ), .C(\fsm_1[0]_net_1 ), .Y(
        \fsm_1_ns[0]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \fsm_1_ns_a2[1]  (.A(
        CORESYSSERVICES_0_SERV_BUSY), .B(\fsm_1[0]_net_1 ), .C(
        UART_top_0_START_sysservice), .Y(N_207));
    SLE \SERV_NRBG_HANDLE[1]  (.D(\SERV_NRBG_HANDLE_5[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[1]));
    SLE \NRBG_DATA[22]  (.D(CORESYSSERVICES_0_SERV_DATA_R[22]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[22])
        );
    SLE \fsm_1[12]  (.D(\fsm_1_ns[12]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[5]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[5]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[5]_net_1 ));
    CFG4 #( .INIT(16'hFFF7) )  \un1_fsm_3_i_a4_3_RNIKQR7[2]  (.A(
        \un1_fsm_3_i_a4_4[2]_net_1 ), .B(\un1_fsm_3_i_a4_3[2]_net_1 ), 
        .C(\fsm_1[5]_net_1 ), .D(\fsm_1[4]_net_1 ), .Y(N_181_i));
    SLE \NRBG_DATA[25]  (.D(CORESYSSERVICES_0_SERV_DATA_R[25]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[25])
        );
    SLE \NRBG_DATA[2]  (.D(CORESYSSERVICES_0_SERV_DATA_R[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[2]));
    SLE \fsm_1[13]  (.D(\fsm_1_ns[13] ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[13]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[7]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[7]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[7]_net_1 ));
    SLE \fsm_1[3]  (.D(\fsm_1_ns[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[3]_net_1 ));
    SLE \SERV_CMDBYTE_REQ_1[4]  (.D(un1_fsm_0_o4_net_1), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_6_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_CMDBYTE_REQ[4]));
    SLE \SERV_NRBG_HANDLE[5]  (.D(\SERV_NRBG_HANDLE_5[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[5]));
    CFG3 #( .INIT(8'hE0) )  \fsm_1_ns_a4[1]  (.A(
        UART_top_0_INSTANTIATE_SERVICE), .B(
        UART_top_0_SELF_TEST_SERVICE), .C(N_207), .Y(\fsm_1_ns[1] ));
    SLE \fsm_1[15]  (.D(\fsm_1_ns[15]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[15]_net_1 ));
    SLE \NRBG_HANDLE_VAL[5]  (.D(\NRBG_HANDLE_VAL_5[5]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[5]_net_1 )
        );
    SLE \fsm_1[1]  (.D(\fsm_1_ns[1] ), .CLK(my_hpms_top_0_FIC32_0_CLK), 
        .EN(VCC_net_1), .ALn(my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \fsm_1[1]_net_1 ));
    SLE \NRBG_DATA[13]  (.D(CORESYSSERVICES_0_SERV_DATA_R[13]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[13])
        );
    CFG4 #( .INIT(16'hFDFF) )  \un1_fsm_3_i_a4_3_RNIB79J[1]  (.A(
        \un1_fsm_3_i_a4_3[1]_net_1 ), .B(\fsm_1[14]_net_1 ), .C(
        \fsm_1[3]_net_1 ), .D(N_208), .Y(N_180_i));
    SLE \fsm_1[2]  (.D(\fsm_1[1]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[2]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \un1_fsm_3_i_a4_3[1]  (.A(
        \fsm_1[10]_net_1 ), .B(\fsm_1[7]_net_1 ), .C(\fsm_1[6]_net_1 ), 
        .D(\fsm_1[2]_net_1 ), .Y(\un1_fsm_3_i_a4_3[1]_net_1 ));
    SLE \NRBG_HANDLE[1]  (.D(CORESYSSERVICES_0_SERV_DATA_R[1]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[1]));
    CFG3 #( .INIT(8'hCE) )  \fsm_1_ns[10]  (.A(\fsm_1[10]_net_1 ), .B(
        \fsm_1[9]_net_1 ), .C(CORESYSSERVICES_0_SERV_DATA_RVALID), .Y(
        \fsm_1_ns[10]_net_1 ));
    SLE \NRBG_HANDLE_VAL[3]  (.D(\NRBG_HANDLE_VAL_5[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[3]_net_1 )
        );
    SLE \NRBG_HANDLE_VAL[4]  (.D(\NRBG_HANDLE_VAL_5[4]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[4]_net_1 )
        );
    CFG2 #( .INIT(4'hE) )  \SERV_CMDBYTE_REQ_1_RNO[2]  (.A(
        un1_fsm_0_o4_net_1), .B(\fsm_1[12]_net_1 ), .Y(N_185_i));
    SLE \NRBG_DATA[24]  (.D(CORESYSSERVICES_0_SERV_DATA_R[24]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[24])
        );
    CFG4 #( .INIT(16'hEAC0) )  \fsm_1_ns[12]  (.A(\fsm_1[11]_net_1 ), 
        .B(\fsm_1[12]_net_1 ), .C(CORESYSSERVICES_0_SERV_BUSY), .D(
        fsm16_net_1), .Y(\fsm_1_ns[12]_net_1 ));
    CFG4 #( .INIT(16'hFFEC) )  un1_fsm_6_0 (.A(N_173), .B(
        un1_fsm_0_o4_net_1), .C(N_207), .D(N_206), .Y(
        un1_fsm_6_0_net_1));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[4]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[4]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \NRBG_HANDLE_VAL_5[6]  (.A(
        CORESYSSERVICES_0_SERV_DATA_R[6]), .B(\fsm_1[6]_net_1 ), .Y(
        \NRBG_HANDLE_VAL_5[6]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  un1_fsm_0_o4 (.A(\fsm_1[2]_net_1 ), .B(
        \fsm_1[9]_net_1 ), .C(\fsm_1[5]_net_1 ), .D(\fsm_1[13]_net_1 ), 
        .Y(un1_fsm_0_o4_net_1));
    CFG3 #( .INIT(8'hFE) )  un1_fsm_10_0 (.A(\fsm_1[4]_net_1 ), .B(
        \fsm_1[1]_net_1 ), .C(N_206), .Y(un1_fsm_12_0_0));
    SLE \SERV_NRBG_HANDLE[3]  (.D(\SERV_NRBG_HANDLE_5[3]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(un1_fsm_12_0_0), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        my_sysservice_state_0_SERV_NRBG_HANDLE[3]));
    SLE \NRBG_DATA[12]  (.D(CORESYSSERVICES_0_SERV_DATA_R[12]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[12])
        );
    SLE \NRBG_HANDLE_VAL[0]  (.D(\NRBG_HANDLE_VAL_5[0]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_0_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\NRBG_HANDLE_VAL[0]_net_1 )
        );
    CFG2 #( .INIT(4'h8) )  \SERV_NRBG_HANDLE_5[4]  (.A(N_182_i), .B(
        \NRBG_HANDLE_VAL[4]_net_1 ), .Y(\SERV_NRBG_HANDLE_5[4]_net_1 ));
    SLE \NRBG_DATA[8]  (.D(CORESYSSERVICES_0_SERV_DATA_R[8]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[8]));
    SLE \NRBG_DATA[15]  (.D(CORESYSSERVICES_0_SERV_DATA_R[15]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_DATA_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_DATA[15])
        );
    CFG4 #( .INIT(16'h0001) )  \un1_fsm_3_i_a4_4[2]  (.A(
        \fsm_1[15]_net_1 ), .B(\fsm_1[14]_net_1 ), .C(
        \fsm_1[13]_net_1 ), .D(\fsm_1[12]_net_1 ), .Y(
        \un1_fsm_3_i_a4_4[2]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \fsm_1_ns_a4[9]  (.A(
        CORESYSSERVICES_0_SERV_BUSY), .B(\fsm_1[8]_net_1 ), .Y(
        \fsm_1_ns[9] ));
    SLE \NRBG_HANDLE[2]  (.D(CORESYSSERVICES_0_SERV_DATA_R[2]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[2]));
    SLE \NRBG_HANDLE[3]  (.D(CORESYSSERVICES_0_SERV_DATA_R[3]), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(NRBG_HANDLE_0_sqmuxa), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        syssvc_blk_0_NRBG_HANDLE[3]));
    SLE \fsm_1[8]  (.D(\fsm_1_ns[8]_net_1 ), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(VCC_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\fsm_1[8]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  fsm16_5 (.A(
        CORESYSSERVICES_0_SERV_STATUS_RESP[6]), .B(
        CORESYSSERVICES_0_SERV_STATUS_RESP[5]), .C(
        CORESYSSERVICES_0_SERV_STATUS_RESP[4]), .D(
        CORESYSSERVICES_0_SERV_STATUS_RESP[3]), .Y(fsm16_5_net_1));
    SLE NRBG_SVC_DONE (.D(NRBG_SVC_DONE_0_sqmuxa), .CLK(
        my_hpms_top_0_FIC32_0_CLK), .EN(
        un1_NRBG_HANDLE_VAL_1_sqmuxa_0_net_1), .ALn(
        my_hpms_top_0_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(syssvc_blk_0_NRBG_SVC_DONE)
        );
    
endmodule


module syssvc_blk(
       syssvc_blk_0_NRBG_HANDLE,
       syssvc_blk_0_NRBG_DATA,
       CoreAHBLite_0_AHBmslave16_HRDATA,
       syssvc_blk_0_AHBL_MASTER_HRDATA,
       syssvc_blk_0_AHBL_MASTER_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA_0,
       masterDataInProg_0,
       cfdatain_o_0_iv_0_1_0,
       cfdatain_o_iv_0_4_0,
       cfdatain_o_0_iv_0_0_0,
       memwr_desc_int_m_9,
       memwr_desc_int_m_15,
       memwr_desc_int_m_16,
       memwr_desc_int_m_19,
       memwr_desc_int_m_17,
       memwr_desc_int_m_14,
       memwr_desc_int_m_0,
       req_curr_state_RNI9FH21_0,
       cfdatain_o_0_iv_0_a2_3_0_0,
       req_dstreg_data_0_0,
       cfdatain_o_iv_0_7_0,
       cfdatain_d1_25,
       cfdatain_d1_26,
       cfdatain_d1_27,
       cfdatain_d1_28,
       cfdatain_d1_30,
       cfdatain_d1_11,
       cfdatain_d1_20,
       cfdatain_d1_0,
       cfdatain_d1_2,
       cfdatain_d1_5,
       syssvc_blk_0_AHBL_MASTER_HWDATA_15,
       syssvc_blk_0_AHBL_MASTER_HWDATA_16,
       syssvc_blk_0_AHBL_MASTER_HWDATA_23,
       syssvc_blk_0_AHBL_MASTER_HWDATA_0,
       syssvc_blk_0_AHBL_MASTER_HWDATA_1,
       syssvc_blk_0_AHBL_MASTER_HWDATA_2,
       syssvc_blk_0_AHBL_MASTER_HWDATA_7,
       syssvc_blk_0_AHBL_MASTER_HWDATA_8,
       syssvc_blk_0_AHBL_MASTER_HWDATA_9,
       syssvc_blk_0_AHBL_MASTER_HWDATA_10,
       syssvc_blk_0_AHBL_MASTER_HWDATA_11,
       syssvc_blk_0_AHBL_MASTER_HWDATA_13,
       syssvc_blk_0_AHBL_MASTER_HWDATA_14,
       syssvc_blk_0_AHBL_MASTER_HTRANS_0,
       syssvc_blk_0_NRBG_SVC_DONE,
       UART_top_0_GENERATE_SERVICE,
       UART_top_0_INSTANTIATE_SERVICE,
       UART_top_0_SELF_TEST_SERVICE,
       UART_top_0_START_sysservice,
       N_182_i,
       N_180_i,
       N_181_i,
       N_179_i,
       my_hpms_top_0_FIC32_0_CLK,
       my_hpms_top_0_HPMS_READY,
       cfdatain_N_8_mux_i_0,
       cfrd_resp_o,
       cfdatain_N_5,
       un1_cfdatain_o26_1_out,
       N_7344,
       my_hpms_top_0_COMM_BLK_INT,
       idle_trigger,
       g2_0,
       g0_0,
       cfdatain_o_iv_N_5_3_0,
       g0_0_0,
       cfdatain_o_iv_0_N_5_3_0,
       g0_0_1,
       g3,
       g0_0_2,
       g2,
       N_10_0_0,
       N_7903_0,
       g2_0_0_0,
       N_12_1,
       N_8225,
       N_5111_i,
       cfdatain_o27,
       un2_cudata_wrdy_int_9,
       cfdatain_o28,
       syssvc_blk_0_AHBL_MASTER_HRESP_0,
       mchready_i,
       un2_cudata_wrdy_int_1_0,
       N_7928,
       cfrd_req_o,
       cfwr_req_o,
       RSTSYNC1,
       N_7894_i,
       syssvc_blk_0_AHBL_MASTER_HWRITE,
       fmhwrite_d1
    );
output [7:0] syssvc_blk_0_NRBG_HANDLE;
output [31:0] syssvc_blk_0_NRBG_DATA;
input  [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
input  [31:0] syssvc_blk_0_AHBL_MASTER_HRDATA;
output [31:2] syssvc_blk_0_AHBL_MASTER_HADDR;
output CoreAHBLite_0_AHBmslave16_HWDATA_0;
input  masterDataInProg_0;
output cfdatain_o_0_iv_0_1_0;
output cfdatain_o_iv_0_4_0;
output cfdatain_o_0_iv_0_0_0;
output memwr_desc_int_m_9;
output memwr_desc_int_m_15;
output memwr_desc_int_m_16;
output memwr_desc_int_m_19;
output memwr_desc_int_m_17;
output memwr_desc_int_m_14;
output memwr_desc_int_m_0;
output req_curr_state_RNI9FH21_0;
output cfdatain_o_0_iv_0_a2_3_0_0;
output req_dstreg_data_0_0;
output cfdatain_o_iv_0_7_0;
output cfdatain_d1_25;
output cfdatain_d1_26;
output cfdatain_d1_27;
output cfdatain_d1_28;
output cfdatain_d1_30;
output cfdatain_d1_11;
output cfdatain_d1_20;
output cfdatain_d1_0;
output cfdatain_d1_2;
output cfdatain_d1_5;
output syssvc_blk_0_AHBL_MASTER_HWDATA_15;
output syssvc_blk_0_AHBL_MASTER_HWDATA_16;
output syssvc_blk_0_AHBL_MASTER_HWDATA_23;
output syssvc_blk_0_AHBL_MASTER_HWDATA_0;
output syssvc_blk_0_AHBL_MASTER_HWDATA_1;
output syssvc_blk_0_AHBL_MASTER_HWDATA_2;
output syssvc_blk_0_AHBL_MASTER_HWDATA_7;
output syssvc_blk_0_AHBL_MASTER_HWDATA_8;
output syssvc_blk_0_AHBL_MASTER_HWDATA_9;
output syssvc_blk_0_AHBL_MASTER_HWDATA_10;
output syssvc_blk_0_AHBL_MASTER_HWDATA_11;
output syssvc_blk_0_AHBL_MASTER_HWDATA_13;
output syssvc_blk_0_AHBL_MASTER_HWDATA_14;
output syssvc_blk_0_AHBL_MASTER_HTRANS_0;
output syssvc_blk_0_NRBG_SVC_DONE;
input  UART_top_0_GENERATE_SERVICE;
input  UART_top_0_INSTANTIATE_SERVICE;
input  UART_top_0_SELF_TEST_SERVICE;
input  UART_top_0_START_sysservice;
output N_182_i;
output N_180_i;
output N_181_i;
output N_179_i;
input  my_hpms_top_0_FIC32_0_CLK;
input  my_hpms_top_0_HPMS_READY;
output cfdatain_N_8_mux_i_0;
output cfrd_resp_o;
output cfdatain_N_5;
output un1_cfdatain_o26_1_out;
output N_7344;
input  my_hpms_top_0_COMM_BLK_INT;
output idle_trigger;
output g2_0;
output g0_0;
output cfdatain_o_iv_N_5_3_0;
output g0_0_0;
output cfdatain_o_iv_0_N_5_3_0;
output g0_0_1;
output g3;
output g0_0_2;
output g2;
output N_10_0_0;
output N_7903_0;
output g2_0_0_0;
output N_12_1;
output N_8225;
output N_5111_i;
output cfdatain_o27;
output un2_cudata_wrdy_int_9;
output cfdatain_o28;
input  syssvc_blk_0_AHBL_MASTER_HRESP_0;
input  mchready_i;
output un2_cudata_wrdy_int_1_0;
output N_7928;
output cfrd_req_o;
output cfwr_req_o;
output RSTSYNC1;
output N_7894_i;
output syssvc_blk_0_AHBL_MASTER_HWRITE;
output fmhwrite_d1;

    wire \my_sysservice_state_0_SERV_CMDBYTE_REQ[0] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[1] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[2] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[4] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[0] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[1] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[2] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[3] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[4] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[5] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[6] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[7] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[0] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[1] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[2] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[3] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[4] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[5] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[6] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[7] , 
        \CORESYSSERVICES_0_SERV_DATA_R[0] , 
        \CORESYSSERVICES_0_SERV_DATA_R[1] , 
        \CORESYSSERVICES_0_SERV_DATA_R[2] , 
        \CORESYSSERVICES_0_SERV_DATA_R[3] , 
        \CORESYSSERVICES_0_SERV_DATA_R[4] , 
        \CORESYSSERVICES_0_SERV_DATA_R[5] , 
        \CORESYSSERVICES_0_SERV_DATA_R[6] , 
        \CORESYSSERVICES_0_SERV_DATA_R[7] , 
        \CORESYSSERVICES_0_SERV_DATA_R[8] , 
        \CORESYSSERVICES_0_SERV_DATA_R[9] , 
        \CORESYSSERVICES_0_SERV_DATA_R[10] , 
        \CORESYSSERVICES_0_SERV_DATA_R[11] , 
        \CORESYSSERVICES_0_SERV_DATA_R[12] , 
        \CORESYSSERVICES_0_SERV_DATA_R[13] , 
        \CORESYSSERVICES_0_SERV_DATA_R[14] , 
        \CORESYSSERVICES_0_SERV_DATA_R[15] , 
        \CORESYSSERVICES_0_SERV_DATA_R[16] , 
        \CORESYSSERVICES_0_SERV_DATA_R[17] , 
        \CORESYSSERVICES_0_SERV_DATA_R[18] , 
        \CORESYSSERVICES_0_SERV_DATA_R[19] , 
        \CORESYSSERVICES_0_SERV_DATA_R[20] , 
        \CORESYSSERVICES_0_SERV_DATA_R[21] , 
        \CORESYSSERVICES_0_SERV_DATA_R[22] , 
        \CORESYSSERVICES_0_SERV_DATA_R[23] , 
        \CORESYSSERVICES_0_SERV_DATA_R[24] , 
        \CORESYSSERVICES_0_SERV_DATA_R[25] , 
        \CORESYSSERVICES_0_SERV_DATA_R[26] , 
        \CORESYSSERVICES_0_SERV_DATA_R[27] , 
        \CORESYSSERVICES_0_SERV_DATA_R[28] , 
        \CORESYSSERVICES_0_SERV_DATA_R[29] , 
        \CORESYSSERVICES_0_SERV_DATA_R[30] , 
        \CORESYSSERVICES_0_SERV_DATA_R[31] , 
        CORESYSSERVICES_0_SERV_BUSY, 
        my_sysservice_state_0_SERV_ENABLE_REQ, 
        CORESYSSERVICES_0_SERV_STATUS_VALID, 
        CORESYSSERVICES_0_SERV_DATA_RVALID, GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8 CORESYSSERVICES_0 
        (.syssvc_blk_0_AHBL_MASTER_HADDR({
        syssvc_blk_0_AHBL_MASTER_HADDR[31], 
        syssvc_blk_0_AHBL_MASTER_HADDR[30], 
        syssvc_blk_0_AHBL_MASTER_HADDR[29], 
        syssvc_blk_0_AHBL_MASTER_HADDR[28], 
        syssvc_blk_0_AHBL_MASTER_HADDR[27], 
        syssvc_blk_0_AHBL_MASTER_HADDR[26], 
        syssvc_blk_0_AHBL_MASTER_HADDR[25], 
        syssvc_blk_0_AHBL_MASTER_HADDR[24], 
        syssvc_blk_0_AHBL_MASTER_HADDR[23], 
        syssvc_blk_0_AHBL_MASTER_HADDR[22], 
        syssvc_blk_0_AHBL_MASTER_HADDR[21], 
        syssvc_blk_0_AHBL_MASTER_HADDR[20], 
        syssvc_blk_0_AHBL_MASTER_HADDR[19], 
        syssvc_blk_0_AHBL_MASTER_HADDR[18], 
        syssvc_blk_0_AHBL_MASTER_HADDR[17], 
        syssvc_blk_0_AHBL_MASTER_HADDR[16], 
        syssvc_blk_0_AHBL_MASTER_HADDR[15], 
        syssvc_blk_0_AHBL_MASTER_HADDR[14], 
        syssvc_blk_0_AHBL_MASTER_HADDR[13], 
        syssvc_blk_0_AHBL_MASTER_HADDR[12], 
        syssvc_blk_0_AHBL_MASTER_HADDR[11], 
        syssvc_blk_0_AHBL_MASTER_HADDR[10], 
        syssvc_blk_0_AHBL_MASTER_HADDR[9], 
        syssvc_blk_0_AHBL_MASTER_HADDR[8], 
        syssvc_blk_0_AHBL_MASTER_HADDR[7], 
        syssvc_blk_0_AHBL_MASTER_HADDR[6], 
        syssvc_blk_0_AHBL_MASTER_HADDR[5], 
        syssvc_blk_0_AHBL_MASTER_HADDR[4], 
        syssvc_blk_0_AHBL_MASTER_HADDR[3], 
        syssvc_blk_0_AHBL_MASTER_HADDR[2]}), 
        .syssvc_blk_0_AHBL_MASTER_HRDATA({
        syssvc_blk_0_AHBL_MASTER_HRDATA[31], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[30], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[29], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[28], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[27], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[26], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[25], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[24], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[23], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[22], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[21], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[20], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[19], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[18], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[17], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[16], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[15], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[14], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[13], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[12], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[11], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[10], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[9], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[8], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[7], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[6], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[5], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[4], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[3], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[2], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[1], 
        syssvc_blk_0_AHBL_MASTER_HRDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HRDATA({
        CoreAHBLite_0_AHBmslave16_HRDATA[31], 
        CoreAHBLite_0_AHBmslave16_HRDATA[30], 
        CoreAHBLite_0_AHBmslave16_HRDATA[29], 
        CoreAHBLite_0_AHBmslave16_HRDATA[28], 
        CoreAHBLite_0_AHBmslave16_HRDATA[27], 
        CoreAHBLite_0_AHBmslave16_HRDATA[26], 
        CoreAHBLite_0_AHBmslave16_HRDATA[25], 
        CoreAHBLite_0_AHBmslave16_HRDATA[24], 
        CoreAHBLite_0_AHBmslave16_HRDATA[23], 
        CoreAHBLite_0_AHBmslave16_HRDATA[22], 
        CoreAHBLite_0_AHBmslave16_HRDATA[21], 
        CoreAHBLite_0_AHBmslave16_HRDATA[20], 
        CoreAHBLite_0_AHBmslave16_HRDATA[19], 
        CoreAHBLite_0_AHBmslave16_HRDATA[18], 
        CoreAHBLite_0_AHBmslave16_HRDATA[17], 
        CoreAHBLite_0_AHBmslave16_HRDATA[16], 
        CoreAHBLite_0_AHBmslave16_HRDATA[15], 
        CoreAHBLite_0_AHBmslave16_HRDATA[14], 
        CoreAHBLite_0_AHBmslave16_HRDATA[13], 
        CoreAHBLite_0_AHBmslave16_HRDATA[12], 
        CoreAHBLite_0_AHBmslave16_HRDATA[11], 
        CoreAHBLite_0_AHBmslave16_HRDATA[10], 
        CoreAHBLite_0_AHBmslave16_HRDATA[9], 
        CoreAHBLite_0_AHBmslave16_HRDATA[8], nc0, 
        CoreAHBLite_0_AHBmslave16_HRDATA[6], 
        CoreAHBLite_0_AHBmslave16_HRDATA[5], 
        CoreAHBLite_0_AHBmslave16_HRDATA[4], 
        CoreAHBLite_0_AHBmslave16_HRDATA[3], 
        CoreAHBLite_0_AHBmslave16_HRDATA[2], nc1, 
        CoreAHBLite_0_AHBmslave16_HRDATA[0]}), 
        .my_sysservice_state_0_SERV_CMDBYTE_REQ({
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[4] , nc2, 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[2] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[1] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[0] }), 
        .my_sysservice_state_0_SERV_NRBG_HANDLE({
        \my_sysservice_state_0_SERV_NRBG_HANDLE[7] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[6] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[5] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[4] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[3] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[2] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[1] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[0] }), 
        .CORESYSSERVICES_0_SERV_STATUS_RESP({
        \CORESYSSERVICES_0_SERV_STATUS_RESP[7] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[6] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[5] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[4] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[3] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[2] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[1] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[0] }), 
        .CORESYSSERVICES_0_SERV_DATA_R({
        \CORESYSSERVICES_0_SERV_DATA_R[31] , 
        \CORESYSSERVICES_0_SERV_DATA_R[30] , 
        \CORESYSSERVICES_0_SERV_DATA_R[29] , 
        \CORESYSSERVICES_0_SERV_DATA_R[28] , 
        \CORESYSSERVICES_0_SERV_DATA_R[27] , 
        \CORESYSSERVICES_0_SERV_DATA_R[26] , 
        \CORESYSSERVICES_0_SERV_DATA_R[25] , 
        \CORESYSSERVICES_0_SERV_DATA_R[24] , 
        \CORESYSSERVICES_0_SERV_DATA_R[23] , 
        \CORESYSSERVICES_0_SERV_DATA_R[22] , 
        \CORESYSSERVICES_0_SERV_DATA_R[21] , 
        \CORESYSSERVICES_0_SERV_DATA_R[20] , 
        \CORESYSSERVICES_0_SERV_DATA_R[19] , 
        \CORESYSSERVICES_0_SERV_DATA_R[18] , 
        \CORESYSSERVICES_0_SERV_DATA_R[17] , 
        \CORESYSSERVICES_0_SERV_DATA_R[16] , 
        \CORESYSSERVICES_0_SERV_DATA_R[15] , 
        \CORESYSSERVICES_0_SERV_DATA_R[14] , 
        \CORESYSSERVICES_0_SERV_DATA_R[13] , 
        \CORESYSSERVICES_0_SERV_DATA_R[12] , 
        \CORESYSSERVICES_0_SERV_DATA_R[11] , 
        \CORESYSSERVICES_0_SERV_DATA_R[10] , 
        \CORESYSSERVICES_0_SERV_DATA_R[9] , 
        \CORESYSSERVICES_0_SERV_DATA_R[8] , 
        \CORESYSSERVICES_0_SERV_DATA_R[7] , 
        \CORESYSSERVICES_0_SERV_DATA_R[6] , 
        \CORESYSSERVICES_0_SERV_DATA_R[5] , 
        \CORESYSSERVICES_0_SERV_DATA_R[4] , 
        \CORESYSSERVICES_0_SERV_DATA_R[3] , 
        \CORESYSSERVICES_0_SERV_DATA_R[2] , 
        \CORESYSSERVICES_0_SERV_DATA_R[1] , 
        \CORESYSSERVICES_0_SERV_DATA_R[0] }), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        syssvc_blk_0_AHBL_MASTER_HTRANS_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        syssvc_blk_0_AHBL_MASTER_HWDATA_15), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        syssvc_blk_0_AHBL_MASTER_HWDATA_16), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        syssvc_blk_0_AHBL_MASTER_HWDATA_23), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        syssvc_blk_0_AHBL_MASTER_HWDATA_0), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        syssvc_blk_0_AHBL_MASTER_HWDATA_1), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        syssvc_blk_0_AHBL_MASTER_HWDATA_2), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        syssvc_blk_0_AHBL_MASTER_HWDATA_7), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        syssvc_blk_0_AHBL_MASTER_HWDATA_8), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        syssvc_blk_0_AHBL_MASTER_HWDATA_9), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        syssvc_blk_0_AHBL_MASTER_HWDATA_10), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        syssvc_blk_0_AHBL_MASTER_HWDATA_11), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        syssvc_blk_0_AHBL_MASTER_HWDATA_13), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        syssvc_blk_0_AHBL_MASTER_HWDATA_14), .cfdatain_d1_25(
        cfdatain_d1_25), .cfdatain_d1_26(cfdatain_d1_26), 
        .cfdatain_d1_27(cfdatain_d1_27), .cfdatain_d1_28(
        cfdatain_d1_28), .cfdatain_d1_30(cfdatain_d1_30), 
        .cfdatain_d1_11(cfdatain_d1_11), .cfdatain_d1_20(
        cfdatain_d1_20), .cfdatain_d1_0(cfdatain_d1_0), .cfdatain_d1_2(
        cfdatain_d1_2), .cfdatain_d1_5(cfdatain_d1_5), 
        .cfdatain_o_iv_0_7_0(cfdatain_o_iv_0_7_0), 
        .req_dstreg_data_0_0(req_dstreg_data_0_0), 
        .cfdatain_o_0_iv_0_a2_3_0_0(cfdatain_o_0_iv_0_a2_3_0_0), 
        .req_curr_state_RNI9FH21_0(req_curr_state_RNI9FH21_0), 
        .memwr_desc_int_m_9(memwr_desc_int_m_9), .memwr_desc_int_m_15(
        memwr_desc_int_m_15), .memwr_desc_int_m_16(memwr_desc_int_m_16)
        , .memwr_desc_int_m_19(memwr_desc_int_m_19), 
        .memwr_desc_int_m_17(memwr_desc_int_m_17), 
        .memwr_desc_int_m_14(memwr_desc_int_m_14), .memwr_desc_int_m_0(
        memwr_desc_int_m_0), .cfdatain_o_0_iv_0_0_0(
        cfdatain_o_0_iv_0_0_0), .cfdatain_o_iv_0_4_0(
        cfdatain_o_iv_0_4_0), .cfdatain_o_0_iv_0_1_0(
        cfdatain_o_0_iv_0_1_0), .masterDataInProg_0(masterDataInProg_0)
        , .CoreAHBLite_0_AHBmslave16_HWDATA_0(
        CoreAHBLite_0_AHBmslave16_HWDATA_0), .fmhwrite_d1(fmhwrite_d1), 
        .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .N_7894_i(N_7894_i), 
        .RSTSYNC1(RSTSYNC1), .cfwr_req_o(cfwr_req_o), .cfrd_req_o(
        cfrd_req_o), .N_7928(N_7928), .un2_cudata_wrdy_int_1_0(
        un2_cudata_wrdy_int_1_0), .mchready_i(mchready_i), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .cfdatain_o28(cfdatain_o28), 
        .un2_cudata_wrdy_int_9(un2_cudata_wrdy_int_9), .cfdatain_o27(
        cfdatain_o27), .N_5111_i(N_5111_i), .N_8225(N_8225), .N_12_1(
        N_12_1), .g2_0_0_0(g2_0_0_0), .N_7903_0(N_7903_0), .N_10_0_0(
        N_10_0_0), .g2(g2), .g0_0_2(g0_0_2), .g3(g3), .g0_0_1(g0_0_1), 
        .cfdatain_o_iv_0_N_5_3_0(cfdatain_o_iv_0_N_5_3_0), .g0_0_0(
        g0_0_0), .cfdatain_o_iv_N_5_3_0(cfdatain_o_iv_N_5_3_0), .g0_0(
        g0_0), .g2_0(g2_0), .idle_trigger(idle_trigger), 
        .my_hpms_top_0_COMM_BLK_INT(my_hpms_top_0_COMM_BLK_INT), 
        .N_7344(N_7344), .un1_cfdatain_o26_1_out(
        un1_cfdatain_o26_1_out), .cfdatain_N_5(cfdatain_N_5), 
        .cfrd_resp_o(cfrd_resp_o), .cfdatain_N_8_mux_i_0(
        cfdatain_N_8_mux_i_0), .CORESYSSERVICES_0_SERV_BUSY(
        CORESYSSERVICES_0_SERV_BUSY), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), 
        .my_sysservice_state_0_SERV_ENABLE_REQ(
        my_sysservice_state_0_SERV_ENABLE_REQ), 
        .CORESYSSERVICES_0_SERV_STATUS_VALID(
        CORESYSSERVICES_0_SERV_STATUS_VALID), 
        .CORESYSSERVICES_0_SERV_DATA_RVALID(
        CORESYSSERVICES_0_SERV_DATA_RVALID));
    my_sysservice_state my_sysservice_state_0 (
        .CORESYSSERVICES_0_SERV_STATUS_RESP({
        \CORESYSSERVICES_0_SERV_STATUS_RESP[7] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[6] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[5] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[4] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[3] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[2] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[1] , 
        \CORESYSSERVICES_0_SERV_STATUS_RESP[0] }), 
        .my_sysservice_state_0_SERV_CMDBYTE_REQ({
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[4] , nc3, 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[2] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[1] , 
        \my_sysservice_state_0_SERV_CMDBYTE_REQ[0] }), 
        .my_sysservice_state_0_SERV_NRBG_HANDLE({
        \my_sysservice_state_0_SERV_NRBG_HANDLE[7] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[6] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[5] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[4] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[3] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[2] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[1] , 
        \my_sysservice_state_0_SERV_NRBG_HANDLE[0] }), 
        .syssvc_blk_0_NRBG_DATA({syssvc_blk_0_NRBG_DATA[31], 
        syssvc_blk_0_NRBG_DATA[30], syssvc_blk_0_NRBG_DATA[29], 
        syssvc_blk_0_NRBG_DATA[28], syssvc_blk_0_NRBG_DATA[27], 
        syssvc_blk_0_NRBG_DATA[26], syssvc_blk_0_NRBG_DATA[25], 
        syssvc_blk_0_NRBG_DATA[24], syssvc_blk_0_NRBG_DATA[23], 
        syssvc_blk_0_NRBG_DATA[22], syssvc_blk_0_NRBG_DATA[21], 
        syssvc_blk_0_NRBG_DATA[20], syssvc_blk_0_NRBG_DATA[19], 
        syssvc_blk_0_NRBG_DATA[18], syssvc_blk_0_NRBG_DATA[17], 
        syssvc_blk_0_NRBG_DATA[16], syssvc_blk_0_NRBG_DATA[15], 
        syssvc_blk_0_NRBG_DATA[14], syssvc_blk_0_NRBG_DATA[13], 
        syssvc_blk_0_NRBG_DATA[12], syssvc_blk_0_NRBG_DATA[11], 
        syssvc_blk_0_NRBG_DATA[10], syssvc_blk_0_NRBG_DATA[9], 
        syssvc_blk_0_NRBG_DATA[8], syssvc_blk_0_NRBG_DATA[7], 
        syssvc_blk_0_NRBG_DATA[6], syssvc_blk_0_NRBG_DATA[5], 
        syssvc_blk_0_NRBG_DATA[4], syssvc_blk_0_NRBG_DATA[3], 
        syssvc_blk_0_NRBG_DATA[2], syssvc_blk_0_NRBG_DATA[1], 
        syssvc_blk_0_NRBG_DATA[0]}), .CORESYSSERVICES_0_SERV_DATA_R({
        \CORESYSSERVICES_0_SERV_DATA_R[31] , 
        \CORESYSSERVICES_0_SERV_DATA_R[30] , 
        \CORESYSSERVICES_0_SERV_DATA_R[29] , 
        \CORESYSSERVICES_0_SERV_DATA_R[28] , 
        \CORESYSSERVICES_0_SERV_DATA_R[27] , 
        \CORESYSSERVICES_0_SERV_DATA_R[26] , 
        \CORESYSSERVICES_0_SERV_DATA_R[25] , 
        \CORESYSSERVICES_0_SERV_DATA_R[24] , 
        \CORESYSSERVICES_0_SERV_DATA_R[23] , 
        \CORESYSSERVICES_0_SERV_DATA_R[22] , 
        \CORESYSSERVICES_0_SERV_DATA_R[21] , 
        \CORESYSSERVICES_0_SERV_DATA_R[20] , 
        \CORESYSSERVICES_0_SERV_DATA_R[19] , 
        \CORESYSSERVICES_0_SERV_DATA_R[18] , 
        \CORESYSSERVICES_0_SERV_DATA_R[17] , 
        \CORESYSSERVICES_0_SERV_DATA_R[16] , 
        \CORESYSSERVICES_0_SERV_DATA_R[15] , 
        \CORESYSSERVICES_0_SERV_DATA_R[14] , 
        \CORESYSSERVICES_0_SERV_DATA_R[13] , 
        \CORESYSSERVICES_0_SERV_DATA_R[12] , 
        \CORESYSSERVICES_0_SERV_DATA_R[11] , 
        \CORESYSSERVICES_0_SERV_DATA_R[10] , 
        \CORESYSSERVICES_0_SERV_DATA_R[9] , 
        \CORESYSSERVICES_0_SERV_DATA_R[8] , 
        \CORESYSSERVICES_0_SERV_DATA_R[7] , 
        \CORESYSSERVICES_0_SERV_DATA_R[6] , 
        \CORESYSSERVICES_0_SERV_DATA_R[5] , 
        \CORESYSSERVICES_0_SERV_DATA_R[4] , 
        \CORESYSSERVICES_0_SERV_DATA_R[3] , 
        \CORESYSSERVICES_0_SERV_DATA_R[2] , 
        \CORESYSSERVICES_0_SERV_DATA_R[1] , 
        \CORESYSSERVICES_0_SERV_DATA_R[0] }), 
        .syssvc_blk_0_NRBG_HANDLE({syssvc_blk_0_NRBG_HANDLE[7], 
        syssvc_blk_0_NRBG_HANDLE[6], syssvc_blk_0_NRBG_HANDLE[5], 
        syssvc_blk_0_NRBG_HANDLE[4], syssvc_blk_0_NRBG_HANDLE[3], 
        syssvc_blk_0_NRBG_HANDLE[2], syssvc_blk_0_NRBG_HANDLE[1], 
        syssvc_blk_0_NRBG_HANDLE[0]}), .N_179_i(N_179_i), .N_181_i(
        N_181_i), .N_180_i(N_180_i), .N_182_i(N_182_i), 
        .UART_top_0_START_sysservice(UART_top_0_START_sysservice), 
        .UART_top_0_SELF_TEST_SERVICE(UART_top_0_SELF_TEST_SERVICE), 
        .UART_top_0_INSTANTIATE_SERVICE(UART_top_0_INSTANTIATE_SERVICE)
        , .UART_top_0_GENERATE_SERVICE(UART_top_0_GENERATE_SERVICE), 
        .CORESYSSERVICES_0_SERV_STATUS_VALID(
        CORESYSSERVICES_0_SERV_STATUS_VALID), 
        .CORESYSSERVICES_0_SERV_DATA_RVALID(
        CORESYSSERVICES_0_SERV_DATA_RVALID), 
        .CORESYSSERVICES_0_SERV_BUSY(CORESYSSERVICES_0_SERV_BUSY), 
        .syssvc_blk_0_NRBG_SVC_DONE(syssvc_blk_0_NRBG_SVC_DONE), 
        .my_sysservice_state_0_SERV_ENABLE_REQ(
        my_sysservice_state_0_SERV_ENABLE_REQ), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY));
    
endmodule


module Top(
       cntout,
       fsm,
       DEVRST_N,
       RX,
       TX
    );
output [27:24] cntout;
output [3:0] fsm;
input  DEVRST_N;
input  RX;
output TX;

    wire my_hpms_top_0_FIC32_0_CLK, my_hpms_top_0_HPMS_READY, 
        \syssvc_blk_0_AHBL_MASTER_HADDR[2] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[3] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[4] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[5] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[6] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[7] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[8] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[9] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[10] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[11] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[12] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[13] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[14] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[15] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[16] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[17] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[18] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[19] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[20] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[21] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[22] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[23] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[24] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[25] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[26] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[27] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[28] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[29] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[30] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[31] , GND_net_1, 
        \syssvc_blk_0_AHBL_MASTER_HTRANS[1] , 
        syssvc_blk_0_AHBL_MASTER_HWRITE, my_hpms_top_0_COMM_BLK_INT, 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[0] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[1] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[2] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[3] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[4] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[5] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[6] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[7] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[8] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[9] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[10] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[11] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[12] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[13] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[14] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[15] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[16] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[17] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[18] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[19] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[20] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[21] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[22] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[23] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[24] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[25] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[26] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[27] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[28] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[29] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[30] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[31] , 
        syssvc_blk_0_AHBL_MASTER_HRESP_0, UART_top_0_GENERATE_SERVICE, 
        UART_top_0_INSTANTIATE_SERVICE, UART_top_0_SELF_TEST_SERVICE, 
        UART_top_0_START_sysservice, \syssvc_blk_0_NRBG_DATA[0] , 
        \syssvc_blk_0_NRBG_DATA[1] , \syssvc_blk_0_NRBG_DATA[2] , 
        \syssvc_blk_0_NRBG_DATA[3] , \syssvc_blk_0_NRBG_DATA[4] , 
        \syssvc_blk_0_NRBG_DATA[5] , \syssvc_blk_0_NRBG_DATA[6] , 
        \syssvc_blk_0_NRBG_DATA[7] , \syssvc_blk_0_NRBG_DATA[8] , 
        \syssvc_blk_0_NRBG_DATA[9] , \syssvc_blk_0_NRBG_DATA[10] , 
        \syssvc_blk_0_NRBG_DATA[11] , \syssvc_blk_0_NRBG_DATA[12] , 
        \syssvc_blk_0_NRBG_DATA[13] , \syssvc_blk_0_NRBG_DATA[14] , 
        \syssvc_blk_0_NRBG_DATA[15] , \syssvc_blk_0_NRBG_DATA[16] , 
        \syssvc_blk_0_NRBG_DATA[17] , \syssvc_blk_0_NRBG_DATA[18] , 
        \syssvc_blk_0_NRBG_DATA[19] , \syssvc_blk_0_NRBG_DATA[20] , 
        \syssvc_blk_0_NRBG_DATA[21] , \syssvc_blk_0_NRBG_DATA[22] , 
        \syssvc_blk_0_NRBG_DATA[23] , \syssvc_blk_0_NRBG_DATA[24] , 
        \syssvc_blk_0_NRBG_DATA[25] , \syssvc_blk_0_NRBG_DATA[26] , 
        \syssvc_blk_0_NRBG_DATA[27] , \syssvc_blk_0_NRBG_DATA[28] , 
        \syssvc_blk_0_NRBG_DATA[29] , \syssvc_blk_0_NRBG_DATA[30] , 
        \syssvc_blk_0_NRBG_DATA[31] , \syssvc_blk_0_NRBG_HANDLE[0] , 
        \syssvc_blk_0_NRBG_HANDLE[1] , \syssvc_blk_0_NRBG_HANDLE[2] , 
        \syssvc_blk_0_NRBG_HANDLE[3] , \syssvc_blk_0_NRBG_HANDLE[4] , 
        \syssvc_blk_0_NRBG_HANDLE[5] , \syssvc_blk_0_NRBG_HANDLE[6] , 
        \syssvc_blk_0_NRBG_HANDLE[7] , syssvc_blk_0_NRBG_SVC_DONE, 
        VCC_net_1, \syssvc_blk_0.CORESYSSERVICES_0.cfwr_req_o , 
        \syssvc_blk_0.CORESYSSERVICES_0.cfrd_req_o , 
        \syssvc_blk_0.CORESYSSERVICES_0.cfrd_resp_o , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[8] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[9] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[10] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[15] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[16] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[17] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[18] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[19] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[21] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[22] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[23] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[24] , 
        \syssvc_blk_0_AHBL_MASTER_HWDATA[31] , 
        \syssvc_blk_0.my_sysservice_state_0.N_182_i , 
        \syssvc_blk_0.CORESYSSERVICES_0.idle_trigger , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhwrite_d1 , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[0] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[0] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[0] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[2] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[11] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[20] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[25] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[26] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[27] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[28] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[30] , 
        \UART_top_0.COREABC_0.genblk2.RSTSYNC1 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o27 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o28 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_5111_i , RX_c, TX_c, 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_8225 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_9 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[20] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[25] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[28] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[30] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7344 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7928 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[11] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_1_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[26] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[27] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_0[12] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_1[14] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26_1_out , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_5 , 
        \req_curr_state_RNI9FH21[10] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.mchready_i , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_8_mux_i_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_a2_3_0[0] , 
        \UART_top_0.COREABC_0.SMADDR_i[1] , 
        \UART_top_0.COREABC_0.SMADDR_i[2] , 
        \UART_top_0.COREABC_0.SMADDR_i[5] , m10, \cntout_c[24] , 
        \cntout_c[25] , \cntout_c[26] , \cntout_c[27] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_4[29] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_7[29] , 
        G_622_net_1, \syssvc_blk_0.my_sysservice_state_0.N_181_i , 
        \syssvc_blk_0.my_sysservice_state_0.N_180_i , 
        \syssvc_blk_0.my_sysservice_state_0.N_179_i , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7894_i , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_N_5_3_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_N_5_3_0 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_1 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g3 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_2 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.req_dstreg_data_0[6] , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2 , 
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7903_0 , N_10_0_0, 
        N_12_1, \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0_0_0 ;
    
    OUTBUF \fsm_obuf[1]  (.D(
        \syssvc_blk_0.my_sysservice_state_0.N_180_i ), .PAD(fsm[1]));
    OUTBUF \cntout_obuf[27]  (.D(\cntout_c[27] ), .PAD(cntout[27]));
    OUTBUF \cntout_obuf[25]  (.D(\cntout_c[25] ), .PAD(cntout[25]));
    counter28 counter28_0 (.cntout_c({\cntout_c[27] , \cntout_c[26] , 
        \cntout_c[25] , \cntout_c[24] }), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK));
    OUTBUF \cntout_obuf[24]  (.D(\cntout_c[24] ), .PAD(cntout[24]));
    OUTBUF TX_obuf (.D(TX_c), .PAD(TX));
    GND GND (.Y(GND_net_1));
    UART_top UART_top_0 (.syssvc_blk_0_NRBG_HANDLE({
        \syssvc_blk_0_NRBG_HANDLE[7] , \syssvc_blk_0_NRBG_HANDLE[6] , 
        \syssvc_blk_0_NRBG_HANDLE[5] , \syssvc_blk_0_NRBG_HANDLE[4] , 
        \syssvc_blk_0_NRBG_HANDLE[3] , \syssvc_blk_0_NRBG_HANDLE[2] , 
        \syssvc_blk_0_NRBG_HANDLE[1] , \syssvc_blk_0_NRBG_HANDLE[0] }), 
        .syssvc_blk_0_NRBG_DATA({\syssvc_blk_0_NRBG_DATA[31] , 
        \syssvc_blk_0_NRBG_DATA[30] , \syssvc_blk_0_NRBG_DATA[29] , 
        \syssvc_blk_0_NRBG_DATA[28] , \syssvc_blk_0_NRBG_DATA[27] , 
        \syssvc_blk_0_NRBG_DATA[26] , \syssvc_blk_0_NRBG_DATA[25] , 
        \syssvc_blk_0_NRBG_DATA[24] , \syssvc_blk_0_NRBG_DATA[23] , 
        \syssvc_blk_0_NRBG_DATA[22] , \syssvc_blk_0_NRBG_DATA[21] , 
        \syssvc_blk_0_NRBG_DATA[20] , \syssvc_blk_0_NRBG_DATA[19] , 
        \syssvc_blk_0_NRBG_DATA[18] , \syssvc_blk_0_NRBG_DATA[17] , 
        \syssvc_blk_0_NRBG_DATA[16] , \syssvc_blk_0_NRBG_DATA[15] , 
        \syssvc_blk_0_NRBG_DATA[14] , \syssvc_blk_0_NRBG_DATA[13] , 
        \syssvc_blk_0_NRBG_DATA[12] , \syssvc_blk_0_NRBG_DATA[11] , 
        \syssvc_blk_0_NRBG_DATA[10] , \syssvc_blk_0_NRBG_DATA[9] , 
        \syssvc_blk_0_NRBG_DATA[8] , \syssvc_blk_0_NRBG_DATA[7] , 
        \syssvc_blk_0_NRBG_DATA[6] , \syssvc_blk_0_NRBG_DATA[5] , 
        \syssvc_blk_0_NRBG_DATA[4] , \syssvc_blk_0_NRBG_DATA[3] , 
        \syssvc_blk_0_NRBG_DATA[2] , \syssvc_blk_0_NRBG_DATA[1] , 
        \syssvc_blk_0_NRBG_DATA[0] }), .SMADDR_i_4(
        \UART_top_0.COREABC_0.SMADDR_i[5] ), .SMADDR_i_1(
        \UART_top_0.COREABC_0.SMADDR_i[2] ), .SMADDR_i_0(
        \UART_top_0.COREABC_0.SMADDR_i[1] ), .RX_c(RX_c), .TX_c(TX_c), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY), .RSTSYNC1(
        \UART_top_0.COREABC_0.genblk2.RSTSYNC1 ), 
        .syssvc_blk_0_NRBG_SVC_DONE(syssvc_blk_0_NRBG_SVC_DONE), .m10(
        m10), .G_622(G_622_net_1), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .UART_top_0_GENERATE_SERVICE(
        UART_top_0_GENERATE_SERVICE), .UART_top_0_START_sysservice(
        UART_top_0_START_sysservice), .UART_top_0_SELF_TEST_SERVICE(
        UART_top_0_SELF_TEST_SERVICE), .UART_top_0_INSTANTIATE_SERVICE(
        UART_top_0_INSTANTIATE_SERVICE));
    OUTBUF \fsm_obuf[3]  (.D(
        \syssvc_blk_0.my_sysservice_state_0.N_182_i ), .PAD(fsm[3]));
    OUTBUF \fsm_obuf[2]  (.D(
        \syssvc_blk_0.my_sysservice_state_0.N_181_i ), .PAD(fsm[2]));
    INBUF RX_ibuf (.PAD(RX), .Y(RX_c));
    OUTBUF \fsm_obuf[0]  (.D(
        \syssvc_blk_0.my_sysservice_state_0.N_179_i ), .PAD(fsm[0]));
    VCC VCC (.Y(VCC_net_1));
    my_hpms_top my_hpms_top_0 (.syssvc_blk_0_AHBL_MASTER_HADDR({
        \syssvc_blk_0_AHBL_MASTER_HADDR[31] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[30] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[29] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[28] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[27] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[26] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[25] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[24] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[23] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[22] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[21] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[20] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[19] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[18] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[17] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[16] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[15] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[14] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[13] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[12] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[11] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[10] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[9] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[8] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[7] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[6] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[5] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[4] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[3] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[2] }), 
        .syssvc_blk_0_AHBL_MASTER_HRDATA({
        \syssvc_blk_0_AHBL_MASTER_HRDATA[31] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[30] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[29] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[28] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[27] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[26] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[25] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[24] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[23] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[22] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[21] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[20] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[19] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[18] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[17] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[16] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[15] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[14] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[13] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[12] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[11] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[10] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[9] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[8] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[7] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[6] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[5] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[4] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[3] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[2] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[1] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HRDATA({
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        nc0, 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        nc1, 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[0] })
        , .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        \syssvc_blk_0_AHBL_MASTER_HTRANS[1] ), .masterDataInProg_0(
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[0] )
        , .cfdatain_o_iv_0_7_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_7[29] )
        , .cfdatain_o_iv_0_4_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_4[29] )
        , .cfdatain_o_0_iv_0_1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_1[14] )
        , .cfdatain_o_0_iv_0_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_0[12] )
        , .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[23] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[21] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[19] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[16] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[17] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[18] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[22] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[24] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[31] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[8] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[9] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[10] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[15] ), .memwr_desc_int_m_9(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[20] )
        , .memwr_desc_int_m_16(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[27] )
        , .memwr_desc_int_m_15(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[26] )
        , .memwr_desc_int_m_14(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[25] )
        , .memwr_desc_int_m_17(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[28] )
        , .memwr_desc_int_m_19(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[30] )
        , .memwr_desc_int_m_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[11] )
        , .cfdatain_d1_5(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] ), 
        .cfdatain_d1_2(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[2] ), 
        .cfdatain_d1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[0] ), 
        .cfdatain_d1_20(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[20] ), 
        .cfdatain_d1_27(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[27] ), 
        .cfdatain_d1_26(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[26] ), 
        .cfdatain_d1_25(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[25] ), 
        .cfdatain_d1_28(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[28] ), 
        .cfdatain_d1_30(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[30] ), 
        .cfdatain_d1_11(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[11] ), 
        .cfdatain_o_0_iv_0_a2_3_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_a2_3_0[0] )
        , .req_curr_state_RNI9FH21_0(\req_curr_state_RNI9FH21[10] ), 
        .req_dstreg_data_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.req_dstreg_data_0[6] )
        , .CoreAHBLite_0_AHBmslave16_HWDATA_0(
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HWDATA[13] )
        , .DEVRST_N(DEVRST_N), .my_hpms_top_0_FIC32_0_CLK(
        my_hpms_top_0_FIC32_0_CLK), .mchready_i(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.mchready_i ), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), 
        .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .my_hpms_top_0_HPMS_READY(
        my_hpms_top_0_HPMS_READY), .cfdatain_N_8_mux_i_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_8_mux_i_0 )
        , .cfdatain_o27(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o27 ), 
        .un1_cfdatain_o26_1_out(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26_1_out )
        , .cfdatain_o28(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o28 ), 
        .N_7928(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7928 ), 
        .N_7344(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7344 ), 
        .cfrd_resp_o(\syssvc_blk_0.CORESYSSERVICES_0.cfrd_resp_o ), 
        .N_5111_i(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_5111_i ), 
        .cfwr_req_o(\syssvc_blk_0.CORESYSSERVICES_0.cfwr_req_o ), 
        .idle_trigger(\syssvc_blk_0.CORESYSSERVICES_0.idle_trigger ), 
        .fmhwrite_d1(
        \syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhwrite_d1 ), 
        .cfrd_req_o(\syssvc_blk_0.CORESYSSERVICES_0.cfrd_req_o ), 
        .g0_0(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0 ), .g2_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0 ), .g0_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_0 ), 
        .cfdatain_o_iv_N_5_3_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_N_5_3_0 )
        , .g0_0_1(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_1 ), 
        .cfdatain_o_iv_0_N_5_3_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_N_5_3_0 )
        , .g0_0_2(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_2 ), 
        .g3(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g3 ), 
        .un2_cudata_wrdy_int_9(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_9 )
        , .g2(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2 ), .N_10_0_0(
        N_10_0_0), .N_12_1(N_12_1), .g2_0_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0_0_0 ), .N_7903_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7903_0 ), 
        .cfdatain_N_5(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_5 ), 
        .un2_cudata_wrdy_int_1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_1_0 )
        , .N_8225(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_8225 ), 
        .N_7894_i(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7894_i ), 
        .my_hpms_top_0_COMM_BLK_INT(my_hpms_top_0_COMM_BLK_INT));
    CFG4 #( .INIT(16'h0048) )  G_622 (.A(
        \UART_top_0.COREABC_0.SMADDR_i[1] ), .B(m10), .C(
        \UART_top_0.COREABC_0.SMADDR_i[2] ), .D(
        \UART_top_0.COREABC_0.SMADDR_i[5] ), .Y(G_622_net_1));
    syssvc_blk syssvc_blk_0 (.syssvc_blk_0_NRBG_HANDLE({
        \syssvc_blk_0_NRBG_HANDLE[7] , \syssvc_blk_0_NRBG_HANDLE[6] , 
        \syssvc_blk_0_NRBG_HANDLE[5] , \syssvc_blk_0_NRBG_HANDLE[4] , 
        \syssvc_blk_0_NRBG_HANDLE[3] , \syssvc_blk_0_NRBG_HANDLE[2] , 
        \syssvc_blk_0_NRBG_HANDLE[1] , \syssvc_blk_0_NRBG_HANDLE[0] }), 
        .syssvc_blk_0_NRBG_DATA({\syssvc_blk_0_NRBG_DATA[31] , 
        \syssvc_blk_0_NRBG_DATA[30] , \syssvc_blk_0_NRBG_DATA[29] , 
        \syssvc_blk_0_NRBG_DATA[28] , \syssvc_blk_0_NRBG_DATA[27] , 
        \syssvc_blk_0_NRBG_DATA[26] , \syssvc_blk_0_NRBG_DATA[25] , 
        \syssvc_blk_0_NRBG_DATA[24] , \syssvc_blk_0_NRBG_DATA[23] , 
        \syssvc_blk_0_NRBG_DATA[22] , \syssvc_blk_0_NRBG_DATA[21] , 
        \syssvc_blk_0_NRBG_DATA[20] , \syssvc_blk_0_NRBG_DATA[19] , 
        \syssvc_blk_0_NRBG_DATA[18] , \syssvc_blk_0_NRBG_DATA[17] , 
        \syssvc_blk_0_NRBG_DATA[16] , \syssvc_blk_0_NRBG_DATA[15] , 
        \syssvc_blk_0_NRBG_DATA[14] , \syssvc_blk_0_NRBG_DATA[13] , 
        \syssvc_blk_0_NRBG_DATA[12] , \syssvc_blk_0_NRBG_DATA[11] , 
        \syssvc_blk_0_NRBG_DATA[10] , \syssvc_blk_0_NRBG_DATA[9] , 
        \syssvc_blk_0_NRBG_DATA[8] , \syssvc_blk_0_NRBG_DATA[7] , 
        \syssvc_blk_0_NRBG_DATA[6] , \syssvc_blk_0_NRBG_DATA[5] , 
        \syssvc_blk_0_NRBG_DATA[4] , \syssvc_blk_0_NRBG_DATA[3] , 
        \syssvc_blk_0_NRBG_DATA[2] , \syssvc_blk_0_NRBG_DATA[1] , 
        \syssvc_blk_0_NRBG_DATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HRDATA({
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        nc2, 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        nc3, 
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HRDATA[0] })
        , .syssvc_blk_0_AHBL_MASTER_HRDATA({
        \syssvc_blk_0_AHBL_MASTER_HRDATA[31] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[30] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[29] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[28] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[27] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[26] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[25] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[24] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[23] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[22] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[21] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[20] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[19] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[18] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[17] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[16] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[15] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[14] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[13] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[12] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[11] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[10] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[9] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[8] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[7] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[6] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[5] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[4] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[3] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[2] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[1] , 
        \syssvc_blk_0_AHBL_MASTER_HRDATA[0] }), 
        .syssvc_blk_0_AHBL_MASTER_HADDR({
        \syssvc_blk_0_AHBL_MASTER_HADDR[31] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[30] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[29] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[28] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[27] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[26] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[25] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[24] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[23] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[22] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[21] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[20] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[19] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[18] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[17] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[16] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[15] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[14] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[13] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[12] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[11] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[10] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[9] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[8] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[7] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[6] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[5] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[4] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[3] , 
        \syssvc_blk_0_AHBL_MASTER_HADDR[2] }), 
        .CoreAHBLite_0_AHBmslave16_HWDATA_0(
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0_AHBmslave16_HWDATA[13] )
        , .masterDataInProg_0(
        \my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[0] )
        , .cfdatain_o_0_iv_0_1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_1[14] )
        , .cfdatain_o_iv_0_4_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_4[29] )
        , .cfdatain_o_0_iv_0_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_0[12] )
        , .memwr_desc_int_m_9(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[20] )
        , .memwr_desc_int_m_15(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[26] )
        , .memwr_desc_int_m_16(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[27] )
        , .memwr_desc_int_m_19(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[30] )
        , .memwr_desc_int_m_17(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[28] )
        , .memwr_desc_int_m_14(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[25] )
        , .memwr_desc_int_m_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_desc_int_m[11] )
        , .req_curr_state_RNI9FH21_0(\req_curr_state_RNI9FH21[10] ), 
        .cfdatain_o_0_iv_0_a2_3_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv_0_a2_3_0[0] )
        , .req_dstreg_data_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.req_dstreg_data_0[6] )
        , .cfdatain_o_iv_0_7_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_7[29] )
        , .cfdatain_d1_25(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[25] ), 
        .cfdatain_d1_26(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[26] ), 
        .cfdatain_d1_27(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[27] ), 
        .cfdatain_d1_28(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[28] ), 
        .cfdatain_d1_30(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[30] ), 
        .cfdatain_d1_11(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[11] ), 
        .cfdatain_d1_20(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[20] ), 
        .cfdatain_d1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[0] ), 
        .cfdatain_d1_2(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[2] ), 
        .cfdatain_d1_5(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_15(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[23] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_16(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[24] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_23(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[31] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_0(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[8] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_1(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[9] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_2(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[10] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_7(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[15] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_8(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[16] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_9(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[17] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_10(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[18] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_11(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[19] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_13(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[21] ), 
        .syssvc_blk_0_AHBL_MASTER_HWDATA_14(
        \syssvc_blk_0_AHBL_MASTER_HWDATA[22] ), 
        .syssvc_blk_0_AHBL_MASTER_HTRANS_0(
        \syssvc_blk_0_AHBL_MASTER_HTRANS[1] ), 
        .syssvc_blk_0_NRBG_SVC_DONE(syssvc_blk_0_NRBG_SVC_DONE), 
        .UART_top_0_GENERATE_SERVICE(UART_top_0_GENERATE_SERVICE), 
        .UART_top_0_INSTANTIATE_SERVICE(UART_top_0_INSTANTIATE_SERVICE)
        , .UART_top_0_SELF_TEST_SERVICE(UART_top_0_SELF_TEST_SERVICE), 
        .UART_top_0_START_sysservice(UART_top_0_START_sysservice), 
        .N_182_i(\syssvc_blk_0.my_sysservice_state_0.N_182_i ), 
        .N_180_i(\syssvc_blk_0.my_sysservice_state_0.N_180_i ), 
        .N_181_i(\syssvc_blk_0.my_sysservice_state_0.N_181_i ), 
        .N_179_i(\syssvc_blk_0.my_sysservice_state_0.N_179_i ), 
        .my_hpms_top_0_FIC32_0_CLK(my_hpms_top_0_FIC32_0_CLK), 
        .my_hpms_top_0_HPMS_READY(my_hpms_top_0_HPMS_READY), 
        .cfdatain_N_8_mux_i_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_8_mux_i_0 )
        , .cfrd_resp_o(\syssvc_blk_0.CORESYSSERVICES_0.cfrd_resp_o ), 
        .cfdatain_N_5(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_N_5 ), 
        .un1_cfdatain_o26_1_out(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26_1_out )
        , .N_7344(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7344 ), 
        .my_hpms_top_0_COMM_BLK_INT(my_hpms_top_0_COMM_BLK_INT), 
        .idle_trigger(\syssvc_blk_0.CORESYSSERVICES_0.idle_trigger ), 
        .g2_0(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0 ), .g0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0 ), 
        .cfdatain_o_iv_N_5_3_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_N_5_3_0 )
        , .g0_0_0(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_0 ), 
        .cfdatain_o_iv_0_N_5_3_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_N_5_3_0 )
        , .g0_0_1(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_1 ), 
        .g3(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g3 ), .g0_0_2(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g0_0_2 ), .g2(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2 ), .N_10_0_0(
        N_10_0_0), .N_7903_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7903_0 ), .g2_0_0_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.g2_0_0_0 ), .N_12_1(
        N_12_1), .N_8225(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_8225 ), .N_5111_i(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_5111_i ), 
        .cfdatain_o27(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o27 ), 
        .un2_cudata_wrdy_int_9(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_9 )
        , .cfdatain_o28(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o28 ), 
        .syssvc_blk_0_AHBL_MASTER_HRESP_0(
        syssvc_blk_0_AHBL_MASTER_HRESP_0), .mchready_i(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.mchready_i ), 
        .un2_cudata_wrdy_int_1_0(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_1_0 )
        , .N_7928(\syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7928 ), 
        .cfrd_req_o(\syssvc_blk_0.CORESYSSERVICES_0.cfrd_req_o ), 
        .cfwr_req_o(\syssvc_blk_0.CORESYSSERVICES_0.cfwr_req_o ), 
        .RSTSYNC1(\UART_top_0.COREABC_0.genblk2.RSTSYNC1 ), .N_7894_i(
        \syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.N_7894_i ), 
        .syssvc_blk_0_AHBL_MASTER_HWRITE(
        syssvc_blk_0_AHBL_MASTER_HWRITE), .fmhwrite_d1(
        \syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhwrite_d1 ));
    OUTBUF \cntout_obuf[26]  (.D(\cntout_c[26] ), .PAD(cntout[26]));
    
endmodule
