library verilog;
use verilog.vl_types.all;
entity AHBLMasterIF is
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        HSEL            : out    vl_logic;
        HADDR           : out    vl_logic_vector(31 downto 0);
        HWRITE          : out    vl_logic;
        HWDATA          : out    vl_logic_vector(31 downto 0);
        HTRANS          : out    vl_logic_vector(1 downto 0);
        HBURST          : out    vl_logic_vector(2 downto 0);
        HSIZE           : out    vl_logic_vector(2 downto 0);
        HRESP           : in     vl_logic;
        HREADY          : in     vl_logic;
        HRDATA          : in     vl_logic_vector(31 downto 0);
        fmhsel_i        : in     vl_logic;
        fmhtrans_i      : in     vl_logic_vector(1 downto 0);
        fmhwrite_i      : in     vl_logic;
        fmhsize_i       : in     vl_logic_vector(2 downto 0);
        fmhburst_i      : in     vl_logic_vector(2 downto 0);
        fmhaddr_i       : in     vl_logic_vector(31 downto 0);
        fmhwdata_i      : in     vl_logic_vector(31 downto 0);
        mfhready_o      : out    vl_logic;
        mfhresp_o       : out    vl_logic;
        mfhrdata_o      : out    vl_logic_vector(31 downto 0)
    );
end AHBLMasterIF;
