library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_INSTRUCTIONS is
    generic(
        AWIDTH          : integer := 0;
        DWIDTH          : integer := 0;
        SWIDTH          : integer := 0;
        ICWIDTH         : integer := 0;
        IIWIDTH         : integer := 0;
        IFWIDTH         : integer := 0;
        IWWIDTH         : integer := 0;
        EN_MULT         : integer := 0;
        EN_INC          : integer := 0;
        TESTMODE        : integer := 0;
        Label_WelcomeMessage: integer := 3;
        Label_Pattern1  : integer := 125;
        Label_Pattern2  : integer := 267
    );
    port(
        ADDRESS         : in     vl_logic_vector;
        INSTRUCTION     : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of AWIDTH : constant is 1;
    attribute mti_svvh_generic_type of DWIDTH : constant is 1;
    attribute mti_svvh_generic_type of SWIDTH : constant is 1;
    attribute mti_svvh_generic_type of ICWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IIWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IFWIDTH : constant is 1;
    attribute mti_svvh_generic_type of IWWIDTH : constant is 1;
    attribute mti_svvh_generic_type of EN_MULT : constant is 1;
    attribute mti_svvh_generic_type of EN_INC : constant is 1;
    attribute mti_svvh_generic_type of TESTMODE : constant is 1;
    attribute mti_svvh_generic_type of Label_WelcomeMessage : constant is 1;
    attribute mti_svvh_generic_type of Label_Pattern1 : constant is 1;
    attribute mti_svvh_generic_type of Label_Pattern2 : constant is 1;
end UART_top_COREABC_0_INSTRUCTIONS;
