library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_RAM256X16 is
    port(
        RWCLK           : in     vl_logic;
        RESET           : in     vl_logic;
        WEN             : in     vl_logic;
        REN             : in     vl_logic;
        WADDR           : in     vl_logic_vector(7 downto 0);
        RADDR           : in     vl_logic_vector(7 downto 0);
        WD              : in     vl_logic_vector(15 downto 0);
        RD              : out    vl_logic_vector(15 downto 0)
    );
end UART_top_COREABC_0_RAM256X16;
