library verilog;
use verilog.vl_types.all;
entity fsm_ctrl is
    port(
        hclk            : in     vl_logic;
        hresetn         : in     vl_logic;
        mfhready_i      : in     vl_logic;
        mfhresp_i       : in     vl_logic;
        mfhrdata_i      : in     vl_logic_vector(31 downto 0);
        cfgrant_i       : in     vl_logic;
        cfsrc_addr_i    : in     vl_logic_vector(31 downto 0);
        cfdst_addr_i    : in     vl_logic_vector(31 downto 0);
        cfburst_len_wr_i: in     vl_logic_vector(31 downto 0);
        cfburst_len_rd_i: in     vl_logic_vector(31 downto 0);
        cfrd_resp_i     : in     vl_logic;
        cfwr_req_i      : in     vl_logic;
        cfrd_req_i      : in     vl_logic;
        cfwr_req_d      : in     vl_logic;
        cfrd_req_d      : in     vl_logic;
        cfdatain_i      : in     vl_logic_vector(31 downto 0);
        cfcommaccess_active: in     vl_logic;
        cfcommaccess_resp_active: in     vl_logic;
        fmhtrans_o      : out    vl_logic_vector(1 downto 0);
        fmhwrite_o      : out    vl_logic;
        fmhsize_o       : out    vl_logic_vector(2 downto 0);
        fmhburst_o      : out    vl_logic_vector(2 downto 0);
        fmhsel_o        : out    vl_logic;
        fmhaddr_o       : out    vl_logic_vector(31 downto 0);
        fmhwdata_o      : out    vl_logic_vector(31 downto 0);
        fcbusreq_o      : out    vl_logic;
        fctrans_done_o  : out    vl_logic;
        fcdataout_o     : out    vl_logic_vector(31 downto 0);
        idle_trigger    : out    vl_logic;
        rvalid_out_en   : out    vl_logic;
        clr_req         : out    vl_logic;
        push            : out    vl_logic;
        pop             : out    vl_logic
    );
end fsm_ctrl;
