library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_ram16x8 is
    generic(
        RAM_WIDTH       : integer := 8;
        RAM_DEPTH       : integer := 16;
        ADDR_SZ         : integer := 4
    );
    port(
        clk             : in     vl_logic;
        data_in         : in     vl_logic_vector;
        read_address    : in     vl_logic_vector;
        write_address   : in     vl_logic_vector;
        write_n         : in     vl_logic;
        read_n          : in     vl_logic;
        data_out        : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of RAM_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of RAM_DEPTH : constant is 1;
    attribute mti_svvh_generic_type of ADDR_SZ : constant is 1;
end UART_top_CoreUARTapb_0_ram16x8;
