library verilog;
use verilog.vl_types.all;
entity my_hpms_CCC_0_FCCC is
    port(
        RCOSC_25_50MHZ  : in     vl_logic;
        LOCK            : out    vl_logic;
        GL0             : out    vl_logic
    );
end my_hpms_CCC_0_FCCC;
