library verilog;
use verilog.vl_types.all;
entity APB_register_blk is
    port(
        PCLK            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PRESETN         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PADDR           : in     vl_logic_vector(31 downto 0);
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        START_sysservice: out    vl_logic;
        NRBG_DATA       : in     vl_logic_vector(31 downto 0);
        NRBG_HANDLE     : in     vl_logic_vector(7 downto 0);
        SELF_TEST_SERVICE: out    vl_logic;
        INSTANTIATE_SERVICE: out    vl_logic;
        GENERATE_SERVICE: out    vl_logic
    );
end APB_register_blk;
