library verilog;
use verilog.vl_types.all;
entity CoreAHBLite is
    generic(
        FAMILY          : vl_logic_vector(5 downto 0) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi1);
        MEMSPACE        : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
        HADDR_SHG_CFG   : vl_logic_vector(0 downto 0) := (others => Hi1);
        SC_0            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_1            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_2            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_3            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_4            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_5            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_6            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_7            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_8            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_9            : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_10           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_11           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_12           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_13           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_14           : vl_logic_vector(0 downto 0) := (others => Hi0);
        SC_15           : vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT0ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT1ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT2ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT3ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT4ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT5ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT6ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT7ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT8ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT9ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT10ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT11ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT12ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT13ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT14ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT15ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M0_AHBSLOT16ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT0ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT1ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT2ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT3ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT4ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT5ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT6ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT7ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT8ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT9ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT10ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT11ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT12ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT13ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT14ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT15ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0);
        M1_AHBSLOT16ENABLE: vl_logic_vector(0 downto 0) := (others => Hi0)
    );
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        REMAP_M0        : in     vl_logic;
        HADDR_M0        : in     vl_logic_vector(31 downto 0);
        HMASTLOCK_M0    : in     vl_logic;
        HSIZE_M0        : in     vl_logic_vector(2 downto 0);
        HTRANS_M0       : in     vl_logic_vector(1 downto 0);
        HWRITE_M0       : in     vl_logic;
        HWDATA_M0       : in     vl_logic_vector(31 downto 0);
        HBURST_M0       : in     vl_logic_vector(2 downto 0);
        HPROT_M0        : in     vl_logic_vector(3 downto 0);
        HRESP_M0        : out    vl_logic_vector(1 downto 0);
        HRDATA_M0       : out    vl_logic_vector(31 downto 0);
        HREADY_M0       : out    vl_logic;
        HADDR_M1        : in     vl_logic_vector(31 downto 0);
        HMASTLOCK_M1    : in     vl_logic;
        HSIZE_M1        : in     vl_logic_vector(2 downto 0);
        HTRANS_M1       : in     vl_logic_vector(1 downto 0);
        HWRITE_M1       : in     vl_logic;
        HWDATA_M1       : in     vl_logic_vector(31 downto 0);
        HBURST_M1       : in     vl_logic_vector(2 downto 0);
        HPROT_M1        : in     vl_logic_vector(3 downto 0);
        HRESP_M1        : out    vl_logic_vector(1 downto 0);
        HRDATA_M1       : out    vl_logic_vector(31 downto 0);
        HREADY_M1       : out    vl_logic;
        HRDATA_S0       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S0    : in     vl_logic;
        HRESP_S0        : in     vl_logic_vector(1 downto 0);
        HSEL_S0         : out    vl_logic;
        HADDR_S0        : out    vl_logic_vector(31 downto 0);
        HSIZE_S0        : out    vl_logic_vector(2 downto 0);
        HTRANS_S0       : out    vl_logic_vector(1 downto 0);
        HWRITE_S0       : out    vl_logic;
        HWDATA_S0       : out    vl_logic_vector(31 downto 0);
        HREADY_S0       : out    vl_logic;
        HMASTLOCK_S0    : out    vl_logic;
        HBURST_S0       : out    vl_logic_vector(2 downto 0);
        HPROT_S0        : out    vl_logic_vector(3 downto 0);
        HRDATA_S1       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S1    : in     vl_logic;
        HRESP_S1        : in     vl_logic_vector(1 downto 0);
        HSEL_S1         : out    vl_logic;
        HADDR_S1        : out    vl_logic_vector(31 downto 0);
        HSIZE_S1        : out    vl_logic_vector(2 downto 0);
        HTRANS_S1       : out    vl_logic_vector(1 downto 0);
        HWRITE_S1       : out    vl_logic;
        HWDATA_S1       : out    vl_logic_vector(31 downto 0);
        HREADY_S1       : out    vl_logic;
        HMASTLOCK_S1    : out    vl_logic;
        HBURST_S1       : out    vl_logic_vector(2 downto 0);
        HPROT_S1        : out    vl_logic_vector(3 downto 0);
        HRDATA_S2       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S2    : in     vl_logic;
        HRESP_S2        : in     vl_logic_vector(1 downto 0);
        HSEL_S2         : out    vl_logic;
        HADDR_S2        : out    vl_logic_vector(31 downto 0);
        HSIZE_S2        : out    vl_logic_vector(2 downto 0);
        HTRANS_S2       : out    vl_logic_vector(1 downto 0);
        HWRITE_S2       : out    vl_logic;
        HWDATA_S2       : out    vl_logic_vector(31 downto 0);
        HREADY_S2       : out    vl_logic;
        HMASTLOCK_S2    : out    vl_logic;
        HBURST_S2       : out    vl_logic_vector(2 downto 0);
        HPROT_S2        : out    vl_logic_vector(3 downto 0);
        HRDATA_S3       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S3    : in     vl_logic;
        HRESP_S3        : in     vl_logic_vector(1 downto 0);
        HSEL_S3         : out    vl_logic;
        HADDR_S3        : out    vl_logic_vector(31 downto 0);
        HSIZE_S3        : out    vl_logic_vector(2 downto 0);
        HTRANS_S3       : out    vl_logic_vector(1 downto 0);
        HWRITE_S3       : out    vl_logic;
        HWDATA_S3       : out    vl_logic_vector(31 downto 0);
        HREADY_S3       : out    vl_logic;
        HMASTLOCK_S3    : out    vl_logic;
        HBURST_S3       : out    vl_logic_vector(2 downto 0);
        HPROT_S3        : out    vl_logic_vector(3 downto 0);
        HRDATA_S4       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S4    : in     vl_logic;
        HRESP_S4        : in     vl_logic_vector(1 downto 0);
        HSEL_S4         : out    vl_logic;
        HADDR_S4        : out    vl_logic_vector(31 downto 0);
        HSIZE_S4        : out    vl_logic_vector(2 downto 0);
        HTRANS_S4       : out    vl_logic_vector(1 downto 0);
        HWRITE_S4       : out    vl_logic;
        HWDATA_S4       : out    vl_logic_vector(31 downto 0);
        HREADY_S4       : out    vl_logic;
        HMASTLOCK_S4    : out    vl_logic;
        HBURST_S4       : out    vl_logic_vector(2 downto 0);
        HPROT_S4        : out    vl_logic_vector(3 downto 0);
        HRDATA_S5       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S5    : in     vl_logic;
        HRESP_S5        : in     vl_logic_vector(1 downto 0);
        HSEL_S5         : out    vl_logic;
        HADDR_S5        : out    vl_logic_vector(31 downto 0);
        HSIZE_S5        : out    vl_logic_vector(2 downto 0);
        HTRANS_S5       : out    vl_logic_vector(1 downto 0);
        HWRITE_S5       : out    vl_logic;
        HWDATA_S5       : out    vl_logic_vector(31 downto 0);
        HREADY_S5       : out    vl_logic;
        HMASTLOCK_S5    : out    vl_logic;
        HBURST_S5       : out    vl_logic_vector(2 downto 0);
        HPROT_S5        : out    vl_logic_vector(3 downto 0);
        HRDATA_S6       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S6    : in     vl_logic;
        HRESP_S6        : in     vl_logic_vector(1 downto 0);
        HSEL_S6         : out    vl_logic;
        HADDR_S6        : out    vl_logic_vector(31 downto 0);
        HSIZE_S6        : out    vl_logic_vector(2 downto 0);
        HTRANS_S6       : out    vl_logic_vector(1 downto 0);
        HWRITE_S6       : out    vl_logic;
        HWDATA_S6       : out    vl_logic_vector(31 downto 0);
        HREADY_S6       : out    vl_logic;
        HMASTLOCK_S6    : out    vl_logic;
        HBURST_S6       : out    vl_logic_vector(2 downto 0);
        HPROT_S6        : out    vl_logic_vector(3 downto 0);
        HRDATA_S7       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S7    : in     vl_logic;
        HRESP_S7        : in     vl_logic_vector(1 downto 0);
        HSEL_S7         : out    vl_logic;
        HADDR_S7        : out    vl_logic_vector(31 downto 0);
        HSIZE_S7        : out    vl_logic_vector(2 downto 0);
        HTRANS_S7       : out    vl_logic_vector(1 downto 0);
        HWRITE_S7       : out    vl_logic;
        HWDATA_S7       : out    vl_logic_vector(31 downto 0);
        HREADY_S7       : out    vl_logic;
        HMASTLOCK_S7    : out    vl_logic;
        HBURST_S7       : out    vl_logic_vector(2 downto 0);
        HPROT_S7        : out    vl_logic_vector(3 downto 0);
        HRDATA_S8       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S8    : in     vl_logic;
        HRESP_S8        : in     vl_logic_vector(1 downto 0);
        HSEL_S8         : out    vl_logic;
        HADDR_S8        : out    vl_logic_vector(31 downto 0);
        HSIZE_S8        : out    vl_logic_vector(2 downto 0);
        HTRANS_S8       : out    vl_logic_vector(1 downto 0);
        HWRITE_S8       : out    vl_logic;
        HWDATA_S8       : out    vl_logic_vector(31 downto 0);
        HREADY_S8       : out    vl_logic;
        HMASTLOCK_S8    : out    vl_logic;
        HBURST_S8       : out    vl_logic_vector(2 downto 0);
        HPROT_S8        : out    vl_logic_vector(3 downto 0);
        HRDATA_S9       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S9    : in     vl_logic;
        HRESP_S9        : in     vl_logic_vector(1 downto 0);
        HSEL_S9         : out    vl_logic;
        HADDR_S9        : out    vl_logic_vector(31 downto 0);
        HSIZE_S9        : out    vl_logic_vector(2 downto 0);
        HTRANS_S9       : out    vl_logic_vector(1 downto 0);
        HWRITE_S9       : out    vl_logic;
        HWDATA_S9       : out    vl_logic_vector(31 downto 0);
        HREADY_S9       : out    vl_logic;
        HMASTLOCK_S9    : out    vl_logic;
        HBURST_S9       : out    vl_logic_vector(2 downto 0);
        HPROT_S9        : out    vl_logic_vector(3 downto 0);
        HRDATA_S10      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S10   : in     vl_logic;
        HRESP_S10       : in     vl_logic_vector(1 downto 0);
        HSEL_S10        : out    vl_logic;
        HADDR_S10       : out    vl_logic_vector(31 downto 0);
        HSIZE_S10       : out    vl_logic_vector(2 downto 0);
        HTRANS_S10      : out    vl_logic_vector(1 downto 0);
        HWRITE_S10      : out    vl_logic;
        HWDATA_S10      : out    vl_logic_vector(31 downto 0);
        HREADY_S10      : out    vl_logic;
        HMASTLOCK_S10   : out    vl_logic;
        HBURST_S10      : out    vl_logic_vector(2 downto 0);
        HPROT_S10       : out    vl_logic_vector(3 downto 0);
        HRDATA_S11      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S11   : in     vl_logic;
        HRESP_S11       : in     vl_logic_vector(1 downto 0);
        HSEL_S11        : out    vl_logic;
        HADDR_S11       : out    vl_logic_vector(31 downto 0);
        HSIZE_S11       : out    vl_logic_vector(2 downto 0);
        HTRANS_S11      : out    vl_logic_vector(1 downto 0);
        HWRITE_S11      : out    vl_logic;
        HWDATA_S11      : out    vl_logic_vector(31 downto 0);
        HREADY_S11      : out    vl_logic;
        HMASTLOCK_S11   : out    vl_logic;
        HBURST_S11      : out    vl_logic_vector(2 downto 0);
        HPROT_S11       : out    vl_logic_vector(3 downto 0);
        HRDATA_S12      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S12   : in     vl_logic;
        HRESP_S12       : in     vl_logic_vector(1 downto 0);
        HSEL_S12        : out    vl_logic;
        HADDR_S12       : out    vl_logic_vector(31 downto 0);
        HSIZE_S12       : out    vl_logic_vector(2 downto 0);
        HTRANS_S12      : out    vl_logic_vector(1 downto 0);
        HWRITE_S12      : out    vl_logic;
        HWDATA_S12      : out    vl_logic_vector(31 downto 0);
        HREADY_S12      : out    vl_logic;
        HMASTLOCK_S12   : out    vl_logic;
        HBURST_S12      : out    vl_logic_vector(2 downto 0);
        HPROT_S12       : out    vl_logic_vector(3 downto 0);
        HRDATA_S13      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S13   : in     vl_logic;
        HRESP_S13       : in     vl_logic_vector(1 downto 0);
        HSEL_S13        : out    vl_logic;
        HADDR_S13       : out    vl_logic_vector(31 downto 0);
        HSIZE_S13       : out    vl_logic_vector(2 downto 0);
        HTRANS_S13      : out    vl_logic_vector(1 downto 0);
        HWRITE_S13      : out    vl_logic;
        HWDATA_S13      : out    vl_logic_vector(31 downto 0);
        HREADY_S13      : out    vl_logic;
        HMASTLOCK_S13   : out    vl_logic;
        HBURST_S13      : out    vl_logic_vector(2 downto 0);
        HPROT_S13       : out    vl_logic_vector(3 downto 0);
        HRDATA_S14      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S14   : in     vl_logic;
        HRESP_S14       : in     vl_logic_vector(1 downto 0);
        HSEL_S14        : out    vl_logic;
        HADDR_S14       : out    vl_logic_vector(31 downto 0);
        HSIZE_S14       : out    vl_logic_vector(2 downto 0);
        HTRANS_S14      : out    vl_logic_vector(1 downto 0);
        HWRITE_S14      : out    vl_logic;
        HWDATA_S14      : out    vl_logic_vector(31 downto 0);
        HREADY_S14      : out    vl_logic;
        HMASTLOCK_S14   : out    vl_logic;
        HBURST_S14      : out    vl_logic_vector(2 downto 0);
        HPROT_S14       : out    vl_logic_vector(3 downto 0);
        HRDATA_S15      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S15   : in     vl_logic;
        HRESP_S15       : in     vl_logic_vector(1 downto 0);
        HSEL_S15        : out    vl_logic;
        HADDR_S15       : out    vl_logic_vector(31 downto 0);
        HSIZE_S15       : out    vl_logic_vector(2 downto 0);
        HTRANS_S15      : out    vl_logic_vector(1 downto 0);
        HWRITE_S15      : out    vl_logic;
        HWDATA_S15      : out    vl_logic_vector(31 downto 0);
        HREADY_S15      : out    vl_logic;
        HMASTLOCK_S15   : out    vl_logic;
        HBURST_S15      : out    vl_logic_vector(2 downto 0);
        HPROT_S15       : out    vl_logic_vector(3 downto 0);
        HRDATA_S16      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S16   : in     vl_logic;
        HRESP_S16       : in     vl_logic_vector(1 downto 0);
        HSEL_S16        : out    vl_logic;
        HADDR_S16       : out    vl_logic_vector(31 downto 0);
        HSIZE_S16       : out    vl_logic_vector(2 downto 0);
        HTRANS_S16      : out    vl_logic_vector(1 downto 0);
        HWRITE_S16      : out    vl_logic;
        HWDATA_S16      : out    vl_logic_vector(31 downto 0);
        HREADY_S16      : out    vl_logic;
        HMASTLOCK_S16   : out    vl_logic;
        HBURST_S16      : out    vl_logic_vector(2 downto 0);
        HPROT_S16       : out    vl_logic_vector(3 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FAMILY : constant is 2;
    attribute mti_svvh_generic_type of MEMSPACE : constant is 2;
    attribute mti_svvh_generic_type of HADDR_SHG_CFG : constant is 2;
    attribute mti_svvh_generic_type of SC_0 : constant is 2;
    attribute mti_svvh_generic_type of SC_1 : constant is 2;
    attribute mti_svvh_generic_type of SC_2 : constant is 2;
    attribute mti_svvh_generic_type of SC_3 : constant is 2;
    attribute mti_svvh_generic_type of SC_4 : constant is 2;
    attribute mti_svvh_generic_type of SC_5 : constant is 2;
    attribute mti_svvh_generic_type of SC_6 : constant is 2;
    attribute mti_svvh_generic_type of SC_7 : constant is 2;
    attribute mti_svvh_generic_type of SC_8 : constant is 2;
    attribute mti_svvh_generic_type of SC_9 : constant is 2;
    attribute mti_svvh_generic_type of SC_10 : constant is 2;
    attribute mti_svvh_generic_type of SC_11 : constant is 2;
    attribute mti_svvh_generic_type of SC_12 : constant is 2;
    attribute mti_svvh_generic_type of SC_13 : constant is 2;
    attribute mti_svvh_generic_type of SC_14 : constant is 2;
    attribute mti_svvh_generic_type of SC_15 : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT0ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT1ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT2ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT3ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT4ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT5ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT6ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT7ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT8ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT9ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT10ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT11ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT12ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT13ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT14ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT15ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M0_AHBSLOT16ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT0ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT1ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT2ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT3ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT4ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT5ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT6ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT7ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT8ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT9ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT10ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT11ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT12ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT13ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT14ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT15ENABLE : constant is 2;
    attribute mti_svvh_generic_type of M1_AHBSLOT16ENABLE : constant is 2;
end CoreAHBLite;
