library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_COREUART is
    generic(
        TX_FIFO         : integer := 0;
        RX_FIFO         : integer := 0;
        RX_LEGACY_MODE  : integer := 0;
        FAMILY          : integer := 15;
        BAUD_VAL_FRCTN_EN: integer := 0
    );
    port(
        RESET_N         : in     vl_logic;
        CLK             : in     vl_logic;
        WEN             : in     vl_logic;
        OEN             : in     vl_logic;
        CSN             : in     vl_logic;
        DATA_IN         : in     vl_logic_vector(7 downto 0);
        RX              : in     vl_logic;
        BAUD_VAL        : in     vl_logic_vector(12 downto 0);
        BIT8            : in     vl_logic;
        PARITY_EN       : in     vl_logic;
        ODD_N_EVEN      : in     vl_logic;
        PARITY_ERR      : out    vl_logic;
        OVERFLOW        : out    vl_logic;
        TXRDY           : out    vl_logic;
        RXRDY           : out    vl_logic;
        DATA_OUT        : out    vl_logic_vector(7 downto 0);
        TX              : out    vl_logic;
        FRAMING_ERR     : out    vl_logic;
        BAUD_VAL_FRACTION: in     vl_logic_vector(2 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of TX_FIFO : constant is 1;
    attribute mti_svvh_generic_type of RX_FIFO : constant is 1;
    attribute mti_svvh_generic_type of RX_LEGACY_MODE : constant is 1;
    attribute mti_svvh_generic_type of FAMILY : constant is 1;
    attribute mti_svvh_generic_type of BAUD_VAL_FRCTN_EN : constant is 1;
end UART_top_CoreUARTapb_0_COREUART;
