library verilog;
use verilog.vl_types.all;
entity COREAHBLITE_ADDRDEC is
    generic(
        MEMSPACE        : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
        HADDR_SHG_CFG   : vl_logic_vector(0 downto 0) := (others => Hi1);
        SC              : vl_logic_vector(15 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        M_AHBSLOTENABLE : vl_logic_vector(16 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1)
    );
    port(
        ADDR            : in     vl_logic_vector(31 downto 0);
        REMAP           : in     vl_logic;
        ADDRDEC         : out    vl_logic_vector(16 downto 0);
        ABSOLUTEADDR    : out    vl_logic_vector(31 downto 0);
        RESERVEDDEC     : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MEMSPACE : constant is 2;
    attribute mti_svvh_generic_type of HADDR_SHG_CFG : constant is 2;
    attribute mti_svvh_generic_type of SC : constant is 2;
    attribute mti_svvh_generic_type of M_AHBSLOTENABLE : constant is 2;
end COREAHBLITE_ADDRDEC;
