library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_IRAM512X9 is
    generic(
        CID             : integer := 0;
        RID             : integer := 0;
        UNIQ_STRING_LENGTH: integer := 10
    );
    port(
        RWCLK           : in     vl_logic;
        RESET           : in     vl_logic;
        RENABLE         : in     vl_logic;
        RADDR           : in     vl_logic_vector(8 downto 0);
        RD              : out    vl_logic_vector(8 downto 0);
        INITADDR        : in     vl_logic_vector(8 downto 0);
        WENABLE         : in     vl_logic;
        INITDATA        : in     vl_logic_vector(8 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of CID : constant is 1;
    attribute mti_svvh_generic_type of RID : constant is 1;
    attribute mti_svvh_generic_type of UNIQ_STRING_LENGTH : constant is 1;
end UART_top_COREABC_0_IRAM512X9;
