library verilog;
use verilog.vl_types.all;
entity my_hpms is
    port(
        DEVRST_N        : in     vl_logic;
        EXT_RESET_IN_N  : in     vl_logic;
        FIC32_0_RESET_IN_N: in     vl_logic;
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HADDR_M0: in     vl_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HBURST_M0: in     vl_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HMASTLOCK_M0: in     vl_logic;
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HPROT_M0: in     vl_logic_vector(3 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HSIZE_M0: in     vl_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HTRANS_M0: in     vl_logic_vector(1 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HWDATA_M0: in     vl_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HWRITE_M0: in     vl_logic;
        USER_FAB_RESET_IN_N: in     vl_logic;
        COMM_BLK_INT    : out    vl_logic;
        FIC32_0_CLK     : out    vl_logic;
        FIC32_0_LOCK    : out    vl_logic;
        HPMS_FAB_RESET_N: out    vl_logic;
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HRDATA_M0: out    vl_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HREADY_M0: out    vl_logic;
        HPMS_FIC_0_USER_MASTER_M1_AHBmmaster_HRESP_M0: out    vl_logic_vector(1 downto 0);
        HPMS_INT_M2F    : out    vl_logic_vector(15 downto 0);
        USER_FAB_RESET_N: out    vl_logic
    );
end my_hpms;
