library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_RAMBLOCKS is
    generic(
        DWIDTH          : integer := 0;
        FAMILY          : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RESETN          : in     vl_logic;
        WEN             : in     vl_logic;
        ADDR            : in     vl_logic_vector(7 downto 0);
        WD              : in     vl_logic_vector;
        RD              : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DWIDTH : constant is 1;
    attribute mti_svvh_generic_type of FAMILY : constant is 1;
end UART_top_COREABC_0_RAMBLOCKS;
