library verilog;
use verilog.vl_types.all;
entity UART_top is
    port(
        NRBG_DATA       : in     vl_logic_vector(31 downto 0);
        NRBG_HANDLE     : in     vl_logic_vector(7 downto 0);
        NRBG_SVC_DONE   : in     vl_logic;
        NSYSRESET       : in     vl_logic;
        PCLK            : in     vl_logic;
        RX              : in     vl_logic;
        GENERATE_SERVICE: out    vl_logic;
        INSTANTIATE_SERVICE: out    vl_logic;
        SELF_TEST_SERVICE: out    vl_logic;
        START_sysservice: out    vl_logic;
        TX              : out    vl_logic
    );
end UART_top;
