library verilog;
use verilog.vl_types.all;
entity Top is
    port(
        DEVRST_N        : in     vl_logic;
        RX              : in     vl_logic;
        TX              : out    vl_logic;
        cntout          : out    vl_logic_vector(27 downto 24);
        fsm             : out    vl_logic_vector(3 downto 0)
    );
end Top;
