library verilog;
use verilog.vl_types.all;
entity UART_top_CoreUARTapb_0_Clock_gen is
    generic(
        BAUD_VAL_FRCTN_EN: integer := 0
    );
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        baud_val        : in     vl_logic_vector(12 downto 0);
        baud_clock      : out    vl_logic;
        xmit_pulse      : out    vl_logic;
        BAUD_VAL_FRACTION: in     vl_logic_vector(2 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of BAUD_VAL_FRCTN_EN : constant is 1;
end UART_top_CoreUARTapb_0_Clock_gen;
