library verilog;
use verilog.vl_types.all;
entity my_hpms_HPMS is
    port(
        FIC_0_AHB_S_HADDR: in     vl_logic_vector(31 downto 0);
        FIC_0_AHB_S_HMASTLOCK: in     vl_logic;
        FIC_0_AHB_S_HREADY: in     vl_logic;
        FIC_0_AHB_S_HSEL: in     vl_logic;
        FIC_0_AHB_S_HSIZE: in     vl_logic_vector(1 downto 0);
        FIC_0_AHB_S_HTRANS: in     vl_logic_vector(1 downto 0);
        FIC_0_AHB_S_HWDATA: in     vl_logic_vector(31 downto 0);
        FIC_0_AHB_S_HWRITE: in     vl_logic;
        FIC_2_APB_M_PRDATA: in     vl_logic_vector(31 downto 0);
        FIC_2_APB_M_PREADY: in     vl_logic;
        FIC_2_APB_M_PSLVERR: in     vl_logic;
        M3_RESET_N      : in     vl_logic;
        MCCC_CLK_BASE   : in     vl_logic;
        MCCC_CLK_BASE_PLL_LOCK: in     vl_logic;
        MSS_RESET_N_F2M : in     vl_logic;
        COMM_BLK_INT    : out    vl_logic;
        FIC_0_AHB_S_HRDATA: out    vl_logic_vector(31 downto 0);
        FIC_0_AHB_S_HREADYOUT: out    vl_logic;
        FIC_0_AHB_S_HRESP: out    vl_logic;
        FIC_2_APB_M_PADDR: out    vl_logic_vector(15 downto 2);
        FIC_2_APB_M_PCLK: out    vl_logic;
        FIC_2_APB_M_PENABLE: out    vl_logic;
        FIC_2_APB_M_PRESET_N: out    vl_logic;
        FIC_2_APB_M_PSEL: out    vl_logic;
        FIC_2_APB_M_PWDATA: out    vl_logic_vector(31 downto 0);
        FIC_2_APB_M_PWRITE: out    vl_logic;
        M3_NMI          : out    vl_logic;
        MSS_INT_M2F     : out    vl_logic_vector(15 downto 0);
        MSS_RESET_N_M2F : out    vl_logic
    );
end my_hpms_HPMS;
