library verilog;
use verilog.vl_types.all;
entity CoreResetP is
    generic(
        FAMILY          : integer := 19;
        EXT_RESET_CFG   : integer := 3;
        DEVICE_VOLTAGE  : integer := 2;
        MDDR_IN_USE     : integer := 1;
        FDDR_IN_USE     : integer := 1;
        SDIF0_IN_USE    : integer := 1;
        SDIF1_IN_USE    : integer := 1;
        SDIF2_IN_USE    : integer := 1;
        SDIF3_IN_USE    : integer := 1;
        DDR_WAIT        : integer := 200
    );
    port(
        RCOSC_25_50MHZ  : in     vl_logic;
        CLK_BASE        : in     vl_logic;
        POWER_ON_RESET_N: in     vl_logic;
        EXT_RESET_IN_N  : in     vl_logic;
        EXT_RESET_OUT   : out    vl_logic;
        MSS_RESET_N_F2M : out    vl_logic;
        M3_RESET_N      : out    vl_logic;
        MSS_RESET_N_M2F : in     vl_logic;
        FIC_2_APB_M_PRESET_N: in     vl_logic;
        MDDR_DDR_AXI_S_CORE_RESET_N: out    vl_logic;
        MSS_FAB_RESET_N : out    vl_logic;
        INIT_DONE       : out    vl_logic;
        CLR_INIT_DONE   : in     vl_logic;
        CONFIG_DONE     : in     vl_logic;
        USER_FAB_RESET_IN_N: in     vl_logic;
        USER_FAB_RESET_N: out    vl_logic;
        FPLL_LOCK       : in     vl_logic;
        FDDR_CORE_RESET_N: out    vl_logic;
        SDIF0_SPLL_LOCK : in     vl_logic;
        SDIF0_PHY_RESET_N: out    vl_logic;
        SDIF0_CORE_RESET_N: out    vl_logic;
        SDIF1_SPLL_LOCK : in     vl_logic;
        SDIF1_PHY_RESET_N: out    vl_logic;
        SDIF1_CORE_RESET_N: out    vl_logic;
        SDIF2_SPLL_LOCK : in     vl_logic;
        SDIF2_PHY_RESET_N: out    vl_logic;
        SDIF2_CORE_RESET_N: out    vl_logic;
        SDIF3_SPLL_LOCK : in     vl_logic;
        SDIF3_PHY_RESET_N: out    vl_logic;
        SDIF3_CORE_RESET_N: out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FAMILY : constant is 1;
    attribute mti_svvh_generic_type of EXT_RESET_CFG : constant is 1;
    attribute mti_svvh_generic_type of DEVICE_VOLTAGE : constant is 1;
    attribute mti_svvh_generic_type of MDDR_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of FDDR_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of SDIF0_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of SDIF1_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of SDIF2_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of SDIF3_IN_USE : constant is 1;
    attribute mti_svvh_generic_type of DDR_WAIT : constant is 1;
end CoreResetP;
