library verilog;
use verilog.vl_types.all;
entity Nibble2Ascii is
    generic(
        LO              : vl_logic := Hi0;
        HI              : vl_logic := Hi1
    );
    port(
        ascii           : out    vl_logic_vector(7 downto 0);
        nibble          : in     vl_logic_vector(3 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of LO : constant is 1;
    attribute mti_svvh_generic_type of HI : constant is 1;
end Nibble2Ascii;
