//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sun Apr 24 20:21:51 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// my_hpms_top
module my_hpms_top(
    // Inputs
    DEVRST_N,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0,
    // Outputs
    COMM_BLK_INT,
    FIC_0_CLK,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0,
    HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0,
    HPMS_INT_M2F,
    HPMS_READY
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input  [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0;
input  [2:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0;
input         HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0;
input  [3:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0;
input  [2:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0;
input  [1:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0;
input  [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0;
input         HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        COMM_BLK_INT;
output        FIC_0_CLK;
output [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0;
output        HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0;
output [1:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0;
output [15:0] HPMS_INT_M2F;
output        HPMS_READY;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          COMM_BLK_INT_net_0;
wire          DEVRST_N;
wire          FIC_0_CLK_net_0;
wire   [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0;
wire   [2:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0;
wire          HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0;
wire   [3:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0;
wire   [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA;
wire          HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY;
wire   [1:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP;
wire   [2:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0;
wire   [1:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0;
wire   [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0;
wire          HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0;
wire   [15:0] HPMS_INT_M2F_net_0;
wire          HPMS_READY_net_0;
wire          COMM_BLK_INT_net_1;
wire          FIC_0_CLK_net_1;
wire          HPMS_READY_net_1;
wire          HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_net_0;
wire   [15:0] HPMS_INT_M2F_net_1;
wire   [31:0] HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_net_0;
wire   [1:0]  HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net = 1'b1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign COMM_BLK_INT_net_1                             = COMM_BLK_INT_net_0;
assign COMM_BLK_INT                                   = COMM_BLK_INT_net_1;
assign FIC_0_CLK_net_1                                = FIC_0_CLK_net_0;
assign FIC_0_CLK                                      = FIC_0_CLK_net_1;
assign HPMS_READY_net_1                               = HPMS_READY_net_0;
assign HPMS_READY                                     = HPMS_READY_net_1;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_net_0    = HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0       = HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_net_0;
assign HPMS_INT_M2F_net_1                             = HPMS_INT_M2F_net_0;
assign HPMS_INT_M2F[15:0]                             = HPMS_INT_M2F_net_1;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_net_0    = HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0[31:0] = HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_net_0;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_net_0     = HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0[1:0]   = HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------my_hpms
my_hpms my_hpms_0(
        // Inputs
        .FAB_RESET_N                                 ( VCC_net ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0 ( HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0 ),
        .DEVRST_N                                    ( DEVRST_N ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0 ),
        // Outputs
        .POWER_ON_RESET_N                            (  ),
        .HPMS_READY                                  ( HPMS_READY_net_0 ),
        .INIT_DONE                                   (  ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY ),
        .FIC_0_CLK                                   ( FIC_0_CLK_net_0 ),
        .FIC_0_LOCK                                  (  ),
        .COMM_BLK_INT                                ( COMM_BLK_INT_net_0 ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0    ( HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP ),
        .HPMS_INT_M2F                                ( HPMS_INT_M2F_net_0 ) 
        );


endmodule
