library verilog;
use verilog.vl_types.all;
entity UART_top_COREABC_0_RAM128X8 is
    port(
        WD              : in     vl_logic_vector(7 downto 0);
        RD              : out    vl_logic_vector(7 downto 0);
        WADDR           : in     vl_logic_vector(6 downto 0);
        RADDR           : in     vl_logic_vector(6 downto 0);
        WEN             : in     vl_logic;
        WCLK            : in     vl_logic;
        RCLK            : in     vl_logic;
        RESETN          : in     vl_logic
    );
end UART_top_COREABC_0_RAM128X8;
