
#####  START OF RAM REPORT  #####

#####  LSRAM REPORT  #####

INSTANTIATED     RTL_INSTANCE                                               PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE                                              DEPTH_X_WIDTH(A/B)     LOW-POWER_MODE     ECC     A_DOUT_PIPE_REG(EN/ARST/SRST)     B_DOUT_PIPE_REG(EN/ARST/SRST)     WRITE_MODE(A/B)          
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO               UART_top_0.COREABC_0.URAM\.UR.UG3\.UR32\.UR0.RAM[15:0]     RAM                DEFAULT            UART_top_0.COREABC_0.URAM\.UR.UG3\.UR32\.UR0.RAM_RAM_0_0     1KX18_1KX18            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                  UART_top_0.COREABC_0.URAM\.UR.UG3\.UR32\.UR0.RAM_RAM_0_1     1KX18_1KX18            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
==============================================================================================================================================================================================================================================================================================================================

#####  URAM REPORT  #####

INSTANTIATED     RTL_INSTANCE                                                                                 PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE                                                                                       DEPTH_X_WIDTH     LOW-POWER_MODE     ECC     A_ADDR_REG(EN/ARST/SRST)     B_ADDR_REG(EN/ARST/SRST)     A_DATA_PIPE_REG(EN/ARST/SRST)     B_DATA_PIPE_REG(EN/ARST/SRST)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO               UART_top_0.CoreUARTapb_0.CUARTlOlI.genblk2\.CUARTl11.CUARTIIlI.CUARTII0I.CUARTI00I[7:0]      RAM                DEFAULT            UART_top_0.CoreUARTapb_0.CUARTlOlI.genblk2\.CUARTl11.CUARTIIlI.CUARTII0I.CUARTI00I_CUARTI00I_0_0      128X9             0                  0       0(0/0/0)                     0(0/0/0)                     1(1/0/0)                          0(0/0/0)                     
                                                                                                                                                                                                                                                                                                                                                                                                                                
NO               UART_top_0.CoreUARTapb_0.CUARTlOlI.genblk3\.CUARTIIOI.CUARTIIlI.CUARTII0I.CUARTI00I[7:0]     RAM                DEFAULT            UART_top_0.CoreUARTapb_0.CUARTlOlI.genblk3\.CUARTIIOI.CUARTIIlI.CUARTII0I.CUARTI00I_CUARTI00I_0_0     128X9             0                  0       0(0/0/0)                     0(0/0/0)                     1(1/0/0)                          0(0/0/0)                     
================================================================================================================================================================================================================================================================================================================================================================================================================================

#####  END OF RAM REPORT  #####

